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| Rev | Author | Line No. | Line |
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| 1120 | serge | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | */ |
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| 26 | /* |
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| 27 | * Authors: |
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| 28 | * Jerome Glisse |
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| 29 | * Thomas Hellstrom |
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| 30 | * Dave Airlie |
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| 31 | */ |
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| 1125 | serge | 32 | #include |
| 33 | #include |
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| 1120 | serge | 34 | |
| 35 | #include "radeon_drm.h" |
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| 36 | #include "radeon.h" |
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| 37 | #include |
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| 1126 | serge | 38 | #include "radeon_object.h" |
| 1120 | serge | 39 | |
| 40 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
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| 41 | int pages, u32_t *pagelist); |
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| 42 | |||
| 43 | |||
| 44 | |||
| 45 | |||
| 46 | static struct drm_mm mm_gtt; |
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| 47 | static struct drm_mm mm_vram; |
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| 48 | |||
| 49 | |||
| 50 | int radeon_object_init(struct radeon_device *rdev) |
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| 51 | { |
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| 52 | int r = 0; |
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| 53 | |||
| 1125 | serge | 54 | dbgprintf("%s\n",__FUNCTION__); |
| 55 | |||
| 1120 | serge | 56 | r = drm_mm_init(&mm_vram, 0x800000 >> PAGE_SHIFT, |
| 57 | ((rdev->mc.aper_size - 0x800000) >> PAGE_SHIFT)); |
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| 58 | if (r) { |
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| 59 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
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| 60 | return r; |
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| 61 | }; |
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| 62 | |||
| 63 | r = drm_mm_init(&mm_gtt, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT)); |
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| 64 | if (r) { |
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| 65 | DRM_ERROR("Failed initializing GTT heap.\n"); |
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| 66 | return r; |
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| 67 | } |
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| 68 | |||
| 69 | return r; |
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| 70 | // return radeon_ttm_init(rdev); |
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| 71 | } |
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| 72 | |||
| 73 | static inline uint32_t radeon_object_flags_from_domain(uint32_t domain) |
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| 74 | { |
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| 75 | uint32_t flags = 0; |
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| 76 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
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| 77 | flags |= TTM_PL_FLAG_VRAM; |
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| 78 | } |
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| 79 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
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| 80 | flags |= TTM_PL_FLAG_TT; |
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| 81 | } |
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| 82 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
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| 83 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 84 | } |
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| 85 | if (!flags) { |
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| 86 | flags |= TTM_PL_FLAG_SYSTEM; |
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| 87 | } |
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| 88 | return flags; |
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| 89 | } |
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| 90 | |||
| 91 | |||
| 92 | int radeon_object_create(struct radeon_device *rdev, |
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| 93 | struct drm_gem_object *gobj, |
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| 94 | unsigned long size, |
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| 95 | bool kernel, |
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| 96 | uint32_t domain, |
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| 97 | bool interruptible, |
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| 98 | struct radeon_object **robj_ptr) |
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| 99 | { |
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| 100 | struct radeon_object *robj; |
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| 101 | enum ttm_bo_type type; |
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| 102 | uint32_t flags; |
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| 103 | int r; |
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| 104 | |||
| 105 | dbgprintf("%s\n",__FUNCTION__); |
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| 106 | |||
| 107 | if (kernel) { |
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| 108 | type = ttm_bo_type_kernel; |
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| 109 | } else { |
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| 110 | type = ttm_bo_type_device; |
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| 111 | } |
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| 112 | *robj_ptr = NULL; |
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| 113 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 114 | if (robj == NULL) { |
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| 115 | return -ENOMEM; |
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| 116 | } |
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| 117 | robj->rdev = rdev; |
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| 118 | // robj->gobj = gobj; |
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| 119 | INIT_LIST_HEAD(&robj->list); |
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| 120 | |||
| 121 | flags = radeon_object_flags_from_domain(domain); |
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| 122 | |||
| 123 | robj->flags = flags; |
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| 124 | |||
| 125 | dbgprintf("robj flags %x\n", robj->flags); |
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| 126 | |||
| 127 | if( flags & TTM_PL_FLAG_VRAM) |
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| 128 | { |
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| 129 | size_t num_pages; |
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| 130 | |||
| 131 | struct drm_mm_node *vm_node; |
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| 132 | |||
| 133 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 134 | |||
| 135 | if (num_pages == 0) { |
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| 136 | printk("Illegal buffer object size.\n"); |
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| 137 | return -EINVAL; |
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| 138 | } |
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| 139 | retry_pre_get: |
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| 140 | r = drm_mm_pre_get(&mm_vram); |
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| 141 | |||
| 142 | if (unlikely(r != 0)) |
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| 143 | return r; |
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| 144 | |||
| 145 | vm_node = drm_mm_search_free(&mm_vram, num_pages, 0, 0); |
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| 146 | |||
| 147 | if (unlikely(vm_node == NULL)) { |
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| 148 | r = -ENOMEM; |
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| 149 | return r; |
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| 150 | } |
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| 151 | |||
| 152 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 153 | |||
| 154 | if (unlikely(robj->mm_node == NULL)) { |
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| 155 | goto retry_pre_get; |
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| 156 | } |
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| 157 | |||
| 158 | robj->vm_addr = ((uint32_t)robj->mm_node->start); |
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| 159 | |||
| 160 | dbgprintf("alloc vram: base %x size %x\n", |
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| 161 | robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 162 | |||
| 163 | }; |
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| 164 | |||
| 165 | if( flags & TTM_PL_FLAG_TT) |
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| 166 | { |
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| 167 | size_t num_pages; |
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| 168 | |||
| 169 | struct drm_mm_node *vm_node; |
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| 170 | |||
| 171 | num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
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| 172 | |||
| 173 | if (num_pages == 0) { |
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| 174 | printk("Illegal buffer object size.\n"); |
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| 175 | return -EINVAL; |
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| 176 | } |
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| 177 | retry_pre_get1: |
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| 178 | r = drm_mm_pre_get(&mm_gtt); |
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| 179 | |||
| 180 | if (unlikely(r != 0)) |
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| 181 | return r; |
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| 182 | |||
| 183 | vm_node = drm_mm_search_free(&mm_gtt, num_pages, 0, 0); |
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| 184 | |||
| 185 | if (unlikely(vm_node == NULL)) { |
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| 186 | r = -ENOMEM; |
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| 187 | return r; |
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| 188 | } |
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| 189 | |||
| 190 | robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0); |
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| 191 | |||
| 192 | if (unlikely(robj->mm_node == NULL)) { |
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| 193 | goto retry_pre_get1; |
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| 194 | } |
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| 195 | |||
| 196 | robj->vm_addr = ((uint32_t)robj->mm_node->start) ; |
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| 197 | |||
| 198 | dbgprintf("alloc gtt: base %x size %x\n", |
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| 199 | robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT); |
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| 200 | }; |
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| 201 | |||
| 202 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 203 | // 0, 0, false, NULL, size, |
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| 204 | // &radeon_ttm_object_object_destroy); |
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| 205 | if (unlikely(r != 0)) { |
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| 206 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 207 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 208 | size, flags, 0); |
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| 209 | return r; |
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| 210 | } |
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| 211 | *robj_ptr = robj; |
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| 212 | // if (gobj) { |
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| 213 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 214 | // } |
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| 215 | return 0; |
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| 216 | } |
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| 217 | |||
| 218 | #define page_tabs 0xFDC00000 |
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| 219 | |||
| 220 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
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| 221 | uint64_t *gpu_addr) |
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| 222 | { |
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| 223 | uint32_t flags; |
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| 224 | uint32_t tmp; |
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| 225 | int r = 0; |
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| 226 | |||
| 227 | dbgprintf("%s\n",__FUNCTION__); |
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| 228 | |||
| 229 | // flags = radeon_object_flags_from_domain(domain); |
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| 230 | // spin_lock(&robj->tobj.lock); |
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| 231 | if (robj->pin_count) { |
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| 232 | robj->pin_count++; |
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| 233 | if (gpu_addr != NULL) { |
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| 234 | *gpu_addr = robj->gpu_addr; |
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| 235 | } |
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| 236 | // spin_unlock(&robj->tobj.lock); |
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| 237 | return 0; |
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| 238 | } |
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| 239 | // spin_unlock(&robj->tobj.lock); |
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| 240 | // r = radeon_object_reserve(robj, false); |
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| 241 | // if (unlikely(r != 0)) { |
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| 242 | // DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
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| 243 | // return r; |
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| 244 | // } |
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| 245 | // tmp = robj->tobj.mem.placement; |
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| 246 | // ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
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| 247 | // robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
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| 248 | // r = ttm_buffer_object_validate(&robj->tobj, |
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| 249 | // robj->tobj.proposed_placement, |
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| 250 | // false, false); |
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| 251 | |||
| 252 | robj->gpu_addr = ((u64)robj->vm_addr) << PAGE_SHIFT; |
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| 253 | |||
| 254 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 255 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 256 | else if (robj->flags & TTM_PL_FLAG_TT) |
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| 257 | { |
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| 258 | u32_t *pagelist; |
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| 259 | robj->kptr = KernelAlloc( robj->mm_node->size << PAGE_SHIFT ); |
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| 260 | dbgprintf("kernel alloc %x\n", robj->kptr ); |
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| 261 | |||
| 262 | pagelist = &((u32_t*)page_tabs)[(u32_t)robj->kptr >> 12]; |
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| 263 | dbgprintf("pagelist %x\n", pagelist); |
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| 264 | radeon_gart_bind(robj->rdev, robj->gpu_addr, |
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| 265 | robj->mm_node->size, pagelist); |
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| 266 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 267 | } |
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| 268 | else |
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| 269 | { |
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| 270 | DRM_ERROR("Unknown placement %d\n", robj->flags); |
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| 271 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 272 | r = -1; |
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| 273 | }; |
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| 274 | |||
| 275 | // flags & TTM_PL_FLAG_VRAM |
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| 276 | if (gpu_addr != NULL) { |
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| 277 | *gpu_addr = robj->gpu_addr; |
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| 278 | } |
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| 279 | robj->pin_count = 1; |
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| 280 | if (unlikely(r != 0)) { |
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| 281 | DRM_ERROR("radeon: failed to pin object.\n"); |
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| 282 | } |
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| 283 | |||
| 284 | dbgprintf("done %s\n",__FUNCTION__); |
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| 285 | |||
| 286 | return r; |
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| 287 | } |
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| 288 | |||
| 289 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 290 | { |
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| 291 | int r = 0; |
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| 292 | |||
| 293 | dbgprintf("%s\n",__FUNCTION__); |
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| 294 | |||
| 295 | // spin_lock(&robj->tobj.lock); |
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| 296 | if (robj->kptr) { |
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| 297 | if (ptr) { |
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| 298 | *ptr = robj->kptr; |
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| 299 | } |
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| 300 | // spin_unlock(&robj->tobj.lock); |
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| 301 | return 0; |
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| 302 | } |
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| 303 | // spin_unlock(&robj->tobj.lock); |
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| 304 | |||
| 305 | if(robj->flags & TTM_PL_FLAG_VRAM) |
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| 306 | { |
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| 307 | robj->cpu_addr = robj->rdev->mc.aper_base + |
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| 308 | (robj->vm_addr << PAGE_SHIFT); |
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| 309 | robj->kptr = (void*)MapIoMem(robj->cpu_addr, |
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| 310 | robj->mm_node->size << 12, PG_SW); |
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| 311 | dbgprintf("map io mem %x at %x\n", robj->cpu_addr, robj->kptr); |
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| 312 | |||
| 313 | } |
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| 314 | else |
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| 315 | { |
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| 316 | return -1; |
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| 317 | } |
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| 318 | |||
| 319 | if (ptr) { |
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| 320 | *ptr = robj->kptr; |
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| 321 | } |
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| 322 | |||
| 323 | dbgprintf("done %s\n",__FUNCTION__); |
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| 324 | |||
| 325 | return 0; |
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| 326 | } |
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| 327 | |||
| 328 | |||
| 329 | #if 0 |
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| 330 | |||
| 331 | void radeon_object_unpin(struct radeon_object *robj) |
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| 332 | { |
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| 333 | uint32_t flags; |
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| 334 | int r; |
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| 335 | |||
| 336 | // spin_lock(&robj->tobj.lock); |
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| 337 | if (!robj->pin_count) { |
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| 338 | // spin_unlock(&robj->tobj.lock); |
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| 339 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
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| 340 | return; |
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| 341 | } |
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| 342 | robj->pin_count--; |
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| 343 | if (robj->pin_count) { |
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| 344 | // spin_unlock(&robj->tobj.lock); |
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| 345 | return; |
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| 346 | } |
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| 347 | // spin_unlock(&robj->tobj.lock); |
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| 348 | r = radeon_object_reserve(robj, false); |
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| 349 | if (unlikely(r != 0)) { |
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| 350 | DRM_ERROR("radeon: failed to reserve object for unpinning it.\n"); |
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| 351 | return; |
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| 352 | } |
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| 353 | flags = robj->tobj.mem.placement; |
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| 354 | robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT; |
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| 355 | r = ttm_buffer_object_validate(&robj->tobj, |
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| 356 | robj->tobj.proposed_placement, |
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| 357 | false, false); |
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| 358 | if (unlikely(r != 0)) { |
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| 359 | DRM_ERROR("radeon: failed to unpin buffer.\n"); |
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| 360 | } |
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| 361 | radeon_object_unreserve(robj); |
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| 362 | } |
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| 363 | |||
| 364 | |||
| 365 | |||
| 366 | |||
| 367 | |||
| 368 | /* |
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| 369 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
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| 370 | * function are calling it. |
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| 371 | */ |
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| 372 | |||
| 373 | static int radeon_object_reserve(struct radeon_object *robj, bool interruptible) |
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| 374 | { |
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| 375 | return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0); |
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| 376 | } |
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| 377 | |||
| 378 | static void radeon_object_unreserve(struct radeon_object *robj) |
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| 379 | { |
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| 380 | ttm_bo_unreserve(&robj->tobj); |
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| 381 | } |
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| 382 | |||
| 383 | static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj) |
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| 384 | { |
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| 385 | struct radeon_object *robj; |
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| 386 | |||
| 387 | robj = container_of(tobj, struct radeon_object, tobj); |
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| 388 | // list_del_init(&robj->list); |
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| 389 | kfree(robj); |
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| 390 | } |
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| 391 | |||
| 392 | static inline void radeon_object_gpu_addr(struct radeon_object *robj) |
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| 393 | { |
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| 394 | /* Default gpu address */ |
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| 395 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 396 | if (robj->tobj.mem.mm_node == NULL) { |
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| 397 | return; |
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| 398 | } |
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| 399 | robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT; |
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| 400 | switch (robj->tobj.mem.mem_type) { |
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| 401 | case TTM_PL_VRAM: |
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| 402 | robj->gpu_addr += (u64)robj->rdev->mc.vram_location; |
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| 403 | break; |
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| 404 | case TTM_PL_TT: |
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| 405 | robj->gpu_addr += (u64)robj->rdev->mc.gtt_location; |
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| 406 | break; |
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| 407 | default: |
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| 408 | DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type); |
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| 409 | robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL; |
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| 410 | return; |
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| 411 | } |
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| 412 | } |
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| 413 | |||
| 414 | |||
| 415 | int radeon_object_create(struct radeon_device *rdev, |
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| 416 | struct drm_gem_object *gobj, |
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| 417 | unsigned long size, |
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| 418 | bool kernel, |
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| 419 | uint32_t domain, |
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| 420 | bool interruptible, |
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| 421 | struct radeon_object **robj_ptr) |
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| 422 | { |
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| 423 | struct radeon_object *robj; |
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| 424 | enum ttm_bo_type type; |
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| 425 | uint32_t flags; |
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| 426 | int r; |
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| 427 | |||
| 428 | // if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
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| 429 | // rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
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| 430 | // } |
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| 431 | if (kernel) { |
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| 432 | type = ttm_bo_type_kernel; |
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| 433 | } else { |
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| 434 | type = ttm_bo_type_device; |
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| 435 | } |
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| 436 | *robj_ptr = NULL; |
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| 437 | robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL); |
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| 438 | if (robj == NULL) { |
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| 439 | return -ENOMEM; |
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| 440 | } |
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| 441 | robj->rdev = rdev; |
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| 442 | robj->gobj = gobj; |
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| 443 | // INIT_LIST_HEAD(&robj->list); |
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| 444 | |||
| 445 | flags = radeon_object_flags_from_domain(domain); |
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| 446 | // r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags, |
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| 447 | // 0, 0, false, NULL, size, |
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| 448 | // &radeon_ttm_object_object_destroy); |
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| 449 | if (unlikely(r != 0)) { |
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| 450 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
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| 451 | DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n", |
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| 452 | size, flags, 0); |
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| 453 | return r; |
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| 454 | } |
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| 455 | *robj_ptr = robj; |
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| 456 | // if (gobj) { |
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| 457 | // list_add_tail(&robj->list, &rdev->gem.objects); |
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| 458 | // } |
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| 459 | return 0; |
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| 460 | } |
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| 461 | |||
| 462 | int radeon_object_kmap(struct radeon_object *robj, void **ptr) |
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| 463 | { |
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| 464 | int r; |
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| 465 | |||
| 466 | // spin_lock(&robj->tobj.lock); |
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| 467 | if (robj->kptr) { |
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| 468 | if (ptr) { |
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| 469 | *ptr = robj->kptr; |
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| 470 | } |
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| 471 | // spin_unlock(&robj->tobj.lock); |
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| 472 | return 0; |
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| 473 | } |
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| 474 | // spin_unlock(&robj->tobj.lock); |
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| 475 | r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap); |
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| 476 | if (r) { |
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| 477 | return r; |
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| 478 | } |
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| 479 | // spin_lock(&robj->tobj.lock); |
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| 480 | robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem); |
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| 481 | // spin_unlock(&robj->tobj.lock); |
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| 482 | if (ptr) { |
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| 483 | *ptr = robj->kptr; |
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| 484 | } |
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| 485 | return 0; |
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| 486 | } |
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| 487 | |||
| 488 | void radeon_object_kunmap(struct radeon_object *robj) |
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| 489 | { |
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| 490 | // spin_lock(&robj->tobj.lock); |
||
| 491 | if (robj->kptr == NULL) { |
||
| 492 | // spin_unlock(&robj->tobj.lock); |
||
| 493 | return; |
||
| 494 | } |
||
| 495 | robj->kptr = NULL; |
||
| 496 | // spin_unlock(&robj->tobj.lock); |
||
| 497 | ttm_bo_kunmap(&robj->kmap); |
||
| 498 | } |
||
| 499 | |||
| 500 | void radeon_object_unref(struct radeon_object **robj) |
||
| 501 | { |
||
| 502 | struct ttm_buffer_object *tobj; |
||
| 503 | |||
| 504 | if ((*robj) == NULL) { |
||
| 505 | return; |
||
| 506 | } |
||
| 507 | tobj = &((*robj)->tobj); |
||
| 508 | ttm_bo_unref(&tobj); |
||
| 509 | if (tobj == NULL) { |
||
| 510 | *robj = NULL; |
||
| 511 | } |
||
| 512 | } |
||
| 513 | |||
| 514 | int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset) |
||
| 515 | { |
||
| 516 | *offset = robj->tobj.addr_space_offset; |
||
| 517 | return 0; |
||
| 518 | } |
||
| 519 | |||
| 520 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, |
||
| 521 | uint64_t *gpu_addr) |
||
| 522 | { |
||
| 523 | uint32_t flags; |
||
| 524 | uint32_t tmp; |
||
| 525 | int r; |
||
| 526 | |||
| 527 | flags = radeon_object_flags_from_domain(domain); |
||
| 528 | // spin_lock(&robj->tobj.lock); |
||
| 529 | if (robj->pin_count) { |
||
| 530 | robj->pin_count++; |
||
| 531 | if (gpu_addr != NULL) { |
||
| 532 | *gpu_addr = robj->gpu_addr; |
||
| 533 | } |
||
| 534 | // spin_unlock(&robj->tobj.lock); |
||
| 535 | return 0; |
||
| 536 | } |
||
| 537 | // spin_unlock(&robj->tobj.lock); |
||
| 538 | r = radeon_object_reserve(robj, false); |
||
| 539 | if (unlikely(r != 0)) { |
||
| 540 | DRM_ERROR("radeon: failed to reserve object for pinning it.\n"); |
||
| 541 | return r; |
||
| 542 | } |
||
| 543 | tmp = robj->tobj.mem.placement; |
||
| 544 | ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
||
| 545 | robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING; |
||
| 546 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 547 | robj->tobj.proposed_placement, |
||
| 548 | false, false); |
||
| 549 | radeon_object_gpu_addr(robj); |
||
| 550 | if (gpu_addr != NULL) { |
||
| 551 | *gpu_addr = robj->gpu_addr; |
||
| 552 | } |
||
| 553 | robj->pin_count = 1; |
||
| 554 | if (unlikely(r != 0)) { |
||
| 555 | DRM_ERROR("radeon: failed to pin object.\n"); |
||
| 556 | } |
||
| 557 | radeon_object_unreserve(robj); |
||
| 558 | return r; |
||
| 559 | } |
||
| 560 | |||
| 561 | void radeon_object_unpin(struct radeon_object *robj) |
||
| 562 | { |
||
| 563 | uint32_t flags; |
||
| 564 | int r; |
||
| 565 | |||
| 566 | // spin_lock(&robj->tobj.lock); |
||
| 567 | if (!robj->pin_count) { |
||
| 568 | // spin_unlock(&robj->tobj.lock); |
||
| 569 | printk(KERN_WARNING "Unpin not necessary for %p !\n", robj); |
||
| 570 | return; |
||
| 571 | } |
||
| 572 | robj->pin_count--; |
||
| 573 | if (robj->pin_count) { |
||
| 574 | // spin_unlock(&robj->tobj.lock); |
||
| 575 | return; |
||
| 576 | } |
||
| 577 | // spin_unlock(&robj->tobj.lock); |
||
| 578 | r = radeon_object_reserve(robj, false); |
||
| 579 | if (unlikely(r != 0)) { |
||
| 580 | DRM_ERROR("radeon: failed to reserve object for unpinning it.\n"); |
||
| 581 | return; |
||
| 582 | } |
||
| 583 | flags = robj->tobj.mem.placement; |
||
| 584 | robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT; |
||
| 585 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 586 | robj->tobj.proposed_placement, |
||
| 587 | false, false); |
||
| 588 | if (unlikely(r != 0)) { |
||
| 589 | DRM_ERROR("radeon: failed to unpin buffer.\n"); |
||
| 590 | } |
||
| 591 | radeon_object_unreserve(robj); |
||
| 592 | } |
||
| 593 | |||
| 594 | int radeon_object_wait(struct radeon_object *robj) |
||
| 595 | { |
||
| 596 | int r = 0; |
||
| 597 | |||
| 598 | /* FIXME: should use block reservation instead */ |
||
| 599 | r = radeon_object_reserve(robj, true); |
||
| 600 | if (unlikely(r != 0)) { |
||
| 601 | DRM_ERROR("radeon: failed to reserve object for waiting.\n"); |
||
| 602 | return r; |
||
| 603 | } |
||
| 604 | // spin_lock(&robj->tobj.lock); |
||
| 605 | if (robj->tobj.sync_obj) { |
||
| 606 | r = ttm_bo_wait(&robj->tobj, true, false, false); |
||
| 607 | } |
||
| 608 | // spin_unlock(&robj->tobj.lock); |
||
| 609 | radeon_object_unreserve(robj); |
||
| 610 | return r; |
||
| 611 | } |
||
| 612 | |||
| 613 | int radeon_object_evict_vram(struct radeon_device *rdev) |
||
| 614 | { |
||
| 615 | if (rdev->flags & RADEON_IS_IGP) { |
||
| 616 | /* Useless to evict on IGP chips */ |
||
| 617 | return 0; |
||
| 618 | } |
||
| 619 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
||
| 620 | } |
||
| 621 | |||
| 622 | void radeon_object_force_delete(struct radeon_device *rdev) |
||
| 623 | { |
||
| 624 | struct radeon_object *robj, *n; |
||
| 625 | struct drm_gem_object *gobj; |
||
| 626 | |||
| 627 | if (list_empty(&rdev->gem.objects)) { |
||
| 628 | return; |
||
| 629 | } |
||
| 630 | DRM_ERROR("Userspace still has active objects !\n"); |
||
| 631 | list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) { |
||
| 632 | mutex_lock(&rdev->ddev->struct_mutex); |
||
| 633 | gobj = robj->gobj; |
||
| 634 | DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n", |
||
| 635 | gobj, robj, (unsigned long)gobj->size, |
||
| 636 | *((unsigned long *)&gobj->refcount)); |
||
| 637 | list_del_init(&robj->list); |
||
| 638 | radeon_object_unref(&robj); |
||
| 639 | gobj->driver_private = NULL; |
||
| 640 | drm_gem_object_unreference(gobj); |
||
| 641 | mutex_unlock(&rdev->ddev->struct_mutex); |
||
| 642 | } |
||
| 643 | } |
||
| 644 | |||
| 645 | void radeon_object_fini(struct radeon_device *rdev) |
||
| 646 | { |
||
| 647 | radeon_ttm_fini(rdev); |
||
| 648 | } |
||
| 649 | |||
| 650 | void radeon_object_list_add_object(struct radeon_object_list *lobj, |
||
| 651 | struct list_head *head) |
||
| 652 | { |
||
| 653 | if (lobj->wdomain) { |
||
| 654 | list_add(&lobj->list, head); |
||
| 655 | } else { |
||
| 656 | list_add_tail(&lobj->list, head); |
||
| 657 | } |
||
| 658 | } |
||
| 659 | |||
| 660 | int radeon_object_list_reserve(struct list_head *head) |
||
| 661 | { |
||
| 662 | struct radeon_object_list *lobj; |
||
| 663 | struct list_head *i; |
||
| 664 | int r; |
||
| 665 | |||
| 666 | list_for_each(i, head) { |
||
| 667 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 668 | if (!lobj->robj->pin_count) { |
||
| 669 | r = radeon_object_reserve(lobj->robj, true); |
||
| 670 | if (unlikely(r != 0)) { |
||
| 671 | DRM_ERROR("radeon: failed to reserve object.\n"); |
||
| 672 | return r; |
||
| 673 | } |
||
| 674 | } else { |
||
| 675 | } |
||
| 676 | } |
||
| 677 | return 0; |
||
| 678 | } |
||
| 679 | |||
| 680 | void radeon_object_list_unreserve(struct list_head *head) |
||
| 681 | { |
||
| 682 | struct radeon_object_list *lobj; |
||
| 683 | struct list_head *i; |
||
| 684 | |||
| 685 | list_for_each(i, head) { |
||
| 686 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 687 | if (!lobj->robj->pin_count) { |
||
| 688 | radeon_object_unreserve(lobj->robj); |
||
| 689 | } else { |
||
| 690 | } |
||
| 691 | } |
||
| 692 | } |
||
| 693 | |||
| 694 | int radeon_object_list_validate(struct list_head *head, void *fence) |
||
| 695 | { |
||
| 696 | struct radeon_object_list *lobj; |
||
| 697 | struct radeon_object *robj; |
||
| 698 | struct radeon_fence *old_fence = NULL; |
||
| 699 | struct list_head *i; |
||
| 700 | uint32_t flags; |
||
| 701 | int r; |
||
| 702 | |||
| 703 | r = radeon_object_list_reserve(head); |
||
| 704 | if (unlikely(r != 0)) { |
||
| 705 | radeon_object_list_unreserve(head); |
||
| 706 | return r; |
||
| 707 | } |
||
| 708 | list_for_each(i, head) { |
||
| 709 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 710 | robj = lobj->robj; |
||
| 711 | if (lobj->wdomain) { |
||
| 712 | flags = radeon_object_flags_from_domain(lobj->wdomain); |
||
| 713 | flags |= TTM_PL_FLAG_TT; |
||
| 714 | } else { |
||
| 715 | flags = radeon_object_flags_from_domain(lobj->rdomain); |
||
| 716 | flags |= TTM_PL_FLAG_TT; |
||
| 717 | flags |= TTM_PL_FLAG_VRAM; |
||
| 718 | } |
||
| 719 | if (!robj->pin_count) { |
||
| 720 | robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING; |
||
| 721 | r = ttm_buffer_object_validate(&robj->tobj, |
||
| 722 | robj->tobj.proposed_placement, |
||
| 723 | true, false); |
||
| 724 | if (unlikely(r)) { |
||
| 725 | radeon_object_list_unreserve(head); |
||
| 726 | DRM_ERROR("radeon: failed to validate.\n"); |
||
| 727 | return r; |
||
| 728 | } |
||
| 729 | radeon_object_gpu_addr(robj); |
||
| 730 | } |
||
| 731 | lobj->gpu_offset = robj->gpu_addr; |
||
| 732 | if (fence) { |
||
| 733 | old_fence = (struct radeon_fence *)robj->tobj.sync_obj; |
||
| 734 | robj->tobj.sync_obj = radeon_fence_ref(fence); |
||
| 735 | robj->tobj.sync_obj_arg = NULL; |
||
| 736 | } |
||
| 737 | if (old_fence) { |
||
| 738 | radeon_fence_unref(&old_fence); |
||
| 739 | } |
||
| 740 | } |
||
| 741 | return 0; |
||
| 742 | } |
||
| 743 | |||
| 744 | void radeon_object_list_unvalidate(struct list_head *head) |
||
| 745 | { |
||
| 746 | struct radeon_object_list *lobj; |
||
| 747 | struct radeon_fence *old_fence = NULL; |
||
| 748 | struct list_head *i; |
||
| 749 | |||
| 750 | list_for_each(i, head) { |
||
| 751 | lobj = list_entry(i, struct radeon_object_list, list); |
||
| 752 | old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj; |
||
| 753 | lobj->robj->tobj.sync_obj = NULL; |
||
| 754 | if (old_fence) { |
||
| 755 | radeon_fence_unref(&old_fence); |
||
| 756 | } |
||
| 757 | } |
||
| 758 | radeon_object_list_unreserve(head); |
||
| 759 | } |
||
| 760 | |||
| 761 | void radeon_object_list_clean(struct list_head *head) |
||
| 762 | { |
||
| 763 | radeon_object_list_unreserve(head); |
||
| 764 | } |
||
| 765 | |||
| 766 | int radeon_object_fbdev_mmap(struct radeon_object *robj, |
||
| 767 | struct vm_area_struct *vma) |
||
| 768 | { |
||
| 769 | return ttm_fbdev_mmap(vma, &robj->tobj); |
||
| 770 | } |
||
| 771 | |||
| 1128 | serge | 772 | #endif |
| 773 | |||
| 1120 | serge | 774 | unsigned long radeon_object_size(struct radeon_object *robj) |
| 775 | { |
||
| 776 | return robj->tobj.num_pages << PAGE_SHIFT; |
||
| 777 | } |
||
| 778 |