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1117 | serge | 1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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3 | * VA Linux Systems Inc., Fremont, California. |
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4 | * Copyright 2008 Red Hat Inc. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Original Authors: |
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25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
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26 | * |
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27 | * Kernel port Author: Dave Airlie |
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28 | */ |
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29 | |||
30 | #ifndef RADEON_MODE_H |
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31 | #define RADEON_MODE_H |
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32 | |||
2997 | Serge | 33 | #include |
34 | #include |
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35 | #include |
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6104 | serge | 36 | #include |
2997 | Serge | 37 | #include |
38 | #include |
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1125 | serge | 39 | #include |
40 | #include |
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1117 | serge | 41 | |
1963 | serge | 42 | struct radeon_bo; |
1179 | serge | 43 | struct radeon_device; |
44 | |||
1117 | serge | 45 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
46 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
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47 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
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48 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
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49 | |||
5078 | serge | 50 | #define RADEON_MAX_HPD_PINS 7 |
51 | #define RADEON_MAX_CRTCS 6 |
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52 | #define RADEON_MAX_AFMT_BLOCKS 7 |
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53 | |||
1117 | serge | 54 | enum radeon_rmx_type { |
55 | RMX_OFF, |
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56 | RMX_FULL, |
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57 | RMX_CENTER, |
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58 | RMX_ASPECT |
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59 | }; |
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60 | |||
61 | enum radeon_tv_std { |
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62 | TV_STD_NTSC, |
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63 | TV_STD_PAL, |
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64 | TV_STD_PAL_M, |
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65 | TV_STD_PAL_60, |
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66 | TV_STD_NTSC_J, |
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67 | TV_STD_SCART_PAL, |
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68 | TV_STD_SECAM, |
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69 | TV_STD_PAL_CN, |
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1404 | serge | 70 | TV_STD_PAL_N, |
1117 | serge | 71 | }; |
72 | |||
1963 | serge | 73 | enum radeon_underscan_type { |
74 | UNDERSCAN_OFF, |
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75 | UNDERSCAN_ON, |
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76 | UNDERSCAN_AUTO, |
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77 | }; |
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78 | |||
79 | enum radeon_hpd_id { |
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80 | RADEON_HPD_1 = 0, |
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81 | RADEON_HPD_2, |
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82 | RADEON_HPD_3, |
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83 | RADEON_HPD_4, |
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84 | RADEON_HPD_5, |
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85 | RADEON_HPD_6, |
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86 | RADEON_HPD_NONE = 0xff, |
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87 | }; |
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88 | |||
6104 | serge | 89 | enum radeon_output_csc { |
90 | RADEON_OUTPUT_CSC_BYPASS = 0, |
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91 | RADEON_OUTPUT_CSC_TVRGB = 1, |
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92 | RADEON_OUTPUT_CSC_YCBCR601 = 2, |
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93 | RADEON_OUTPUT_CSC_YCBCR709 = 3, |
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94 | }; |
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95 | |||
1963 | serge | 96 | #define RADEON_MAX_I2C_BUS 16 |
97 | |||
1321 | serge | 98 | /* radeon gpio-based i2c |
99 | * 1. "mask" reg and bits |
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100 | * grabs the gpio pins for software use |
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101 | * 0=not held 1=held |
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102 | * 2. "a" reg and bits |
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103 | * output pin value |
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104 | * 0=low 1=high |
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105 | * 3. "en" reg and bits |
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106 | * sets the pin direction |
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107 | * 0=input 1=output |
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108 | * 4. "y" reg and bits |
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109 | * input pin value |
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110 | * 0=low 1=high |
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111 | */ |
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1117 | serge | 112 | struct radeon_i2c_bus_rec { |
113 | bool valid; |
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1321 | serge | 114 | /* id used by atom */ |
115 | uint8_t i2c_id; |
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1430 | serge | 116 | /* id used by atom */ |
1963 | serge | 117 | enum radeon_hpd_id hpd; |
1321 | serge | 118 | /* can be used with hw i2c engine */ |
119 | bool hw_capable; |
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120 | /* uses multi-media i2c engine */ |
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121 | bool mm_i2c; |
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122 | /* regs and bits */ |
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1117 | serge | 123 | uint32_t mask_clk_reg; |
124 | uint32_t mask_data_reg; |
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125 | uint32_t a_clk_reg; |
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126 | uint32_t a_data_reg; |
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1321 | serge | 127 | uint32_t en_clk_reg; |
128 | uint32_t en_data_reg; |
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129 | uint32_t y_clk_reg; |
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130 | uint32_t y_data_reg; |
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1117 | serge | 131 | uint32_t mask_clk_mask; |
132 | uint32_t mask_data_mask; |
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133 | uint32_t a_clk_mask; |
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134 | uint32_t a_data_mask; |
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1321 | serge | 135 | uint32_t en_clk_mask; |
136 | uint32_t en_data_mask; |
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137 | uint32_t y_clk_mask; |
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138 | uint32_t y_data_mask; |
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1117 | serge | 139 | }; |
140 | |||
141 | struct radeon_tmds_pll { |
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142 | uint32_t freq; |
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143 | uint32_t value; |
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144 | }; |
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145 | |||
146 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
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147 | |||
1430 | serge | 148 | /* pll flags */ |
1117 | serge | 149 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
150 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
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151 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
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152 | #define RADEON_PLL_LEGACY (1 << 3) |
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153 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
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154 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
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155 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
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156 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
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157 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
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158 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
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159 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
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1179 | serge | 160 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
1404 | serge | 161 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
1963 | serge | 162 | #define RADEON_PLL_IS_LCD (1 << 13) |
163 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
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1117 | serge | 164 | |
165 | struct radeon_pll { |
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1404 | serge | 166 | /* reference frequency */ |
167 | uint32_t reference_freq; |
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168 | |||
169 | /* fixed dividers */ |
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170 | uint32_t reference_div; |
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171 | uint32_t post_div; |
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172 | |||
173 | /* pll in/out limits */ |
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1117 | serge | 174 | uint32_t pll_in_min; |
175 | uint32_t pll_in_max; |
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176 | uint32_t pll_out_min; |
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177 | uint32_t pll_out_max; |
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1963 | serge | 178 | uint32_t lcd_pll_out_min; |
179 | uint32_t lcd_pll_out_max; |
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1404 | serge | 180 | uint32_t best_vco; |
1117 | serge | 181 | |
1404 | serge | 182 | /* divider limits */ |
1117 | serge | 183 | uint32_t min_ref_div; |
184 | uint32_t max_ref_div; |
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185 | uint32_t min_post_div; |
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186 | uint32_t max_post_div; |
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187 | uint32_t min_feedback_div; |
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188 | uint32_t max_feedback_div; |
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189 | uint32_t min_frac_feedback_div; |
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190 | uint32_t max_frac_feedback_div; |
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1404 | serge | 191 | |
192 | /* flags for the current clock */ |
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193 | uint32_t flags; |
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194 | |||
195 | /* pll id */ |
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196 | uint32_t id; |
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1117 | serge | 197 | }; |
198 | |||
199 | struct radeon_i2c_chan { |
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1321 | serge | 200 | struct i2c_adapter adapter; |
1117 | serge | 201 | struct drm_device *dev; |
6104 | serge | 202 | struct i2c_algo_bit_data bit; |
1117 | serge | 203 | struct radeon_i2c_bus_rec rec; |
5078 | serge | 204 | struct drm_dp_aux aux; |
205 | bool has_aux; |
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206 | struct mutex mutex; |
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1117 | serge | 207 | }; |
208 | |||
209 | /* mostly for macs, but really any system without connector tables */ |
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210 | enum radeon_connector_table { |
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1963 | serge | 211 | CT_NONE = 0, |
1117 | serge | 212 | CT_GENERIC, |
213 | CT_IBOOK, |
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214 | CT_POWERBOOK_EXTERNAL, |
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215 | CT_POWERBOOK_INTERNAL, |
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216 | CT_POWERBOOK_VGA, |
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217 | CT_MINI_EXTERNAL, |
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218 | CT_MINI_INTERNAL, |
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219 | CT_IMAC_G5_ISIGHT, |
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220 | CT_EMAC, |
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1963 | serge | 221 | CT_RN50_POWER, |
222 | CT_MAC_X800, |
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223 | CT_MAC_G5_9600, |
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3192 | Serge | 224 | CT_SAM440EP, |
225 | CT_MAC_G4_SILVER |
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1117 | serge | 226 | }; |
227 | |||
1321 | serge | 228 | enum radeon_dvo_chip { |
229 | DVO_SIL164, |
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230 | DVO_SIL1178, |
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231 | }; |
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232 | |||
1963 | serge | 233 | struct radeon_fbdev; |
234 | |||
2997 | Serge | 235 | struct radeon_afmt { |
236 | bool enabled; |
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237 | int offset; |
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238 | bool last_buffer_filled_status; |
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239 | int id; |
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240 | }; |
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241 | |||
1117 | serge | 242 | struct radeon_mode_info { |
243 | struct atom_context *atom_context; |
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1268 | serge | 244 | struct card_info *atom_card_info; |
1117 | serge | 245 | enum radeon_connector_table connector_table; |
246 | bool mode_config_initialized; |
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5078 | serge | 247 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
248 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; |
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1179 | serge | 249 | /* DVI-I properties */ |
250 | struct drm_property *coherent_mode_property; |
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251 | /* DAC enable load detect */ |
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252 | struct drm_property *load_detect_property; |
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1963 | serge | 253 | /* TV standard */ |
1179 | serge | 254 | struct drm_property *tv_std_property; |
255 | /* legacy TMDS PLL detect */ |
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256 | struct drm_property *tmds_pll_property; |
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1963 | serge | 257 | /* underscan */ |
258 | struct drm_property *underscan_property; |
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259 | struct drm_property *underscan_hborder_property; |
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260 | struct drm_property *underscan_vborder_property; |
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5078 | serge | 261 | /* audio */ |
262 | struct drm_property *audio_property; |
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263 | /* FMT dithering */ |
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264 | struct drm_property *dither_property; |
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6104 | serge | 265 | /* Output CSC */ |
266 | struct drm_property *output_csc_property; |
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1430 | serge | 267 | /* hardcoded DFP edid from BIOS */ |
268 | struct edid *bios_hardcoded_edid; |
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1963 | serge | 269 | int bios_hardcoded_edid_size; |
270 | |||
271 | /* pointer to fbdev info structure */ |
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272 | struct radeon_fbdev *rfbdev; |
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2997 | Serge | 273 | /* firmware flags */ |
274 | u16 firmware_flags; |
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275 | /* pointer to backlight encoder */ |
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276 | struct radeon_encoder *bl_encoder; |
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6104 | serge | 277 | |
278 | /* bitmask for active encoder frontends */ |
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279 | uint32_t active_encoders; |
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1117 | serge | 280 | }; |
281 | |||
2997 | Serge | 282 | #define RADEON_MAX_BL_LEVEL 0xFF |
283 | |||
284 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
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285 | |||
286 | struct radeon_backlight_privdata { |
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287 | struct radeon_encoder *encoder; |
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288 | uint8_t negative; |
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289 | }; |
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290 | |||
291 | #endif |
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292 | |||
1179 | serge | 293 | #define MAX_H_CODE_TIMING_LEN 32 |
294 | #define MAX_V_CODE_TIMING_LEN 32 |
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295 | |||
296 | /* need to store these as reading |
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297 | back code tables is excessive */ |
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298 | struct radeon_tv_regs { |
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299 | uint32_t tv_uv_adr; |
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300 | uint32_t timing_cntl; |
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301 | uint32_t hrestart; |
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302 | uint32_t vrestart; |
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303 | uint32_t frestart; |
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304 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
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305 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
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306 | }; |
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307 | |||
2997 | Serge | 308 | struct radeon_atom_ss { |
309 | uint16_t percentage; |
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5078 | serge | 310 | uint16_t percentage_divider; |
2997 | Serge | 311 | uint8_t type; |
312 | uint16_t step; |
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313 | uint8_t delay; |
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314 | uint8_t range; |
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315 | uint8_t refdiv; |
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316 | /* asic_ss */ |
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317 | uint16_t rate; |
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318 | uint16_t amount; |
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319 | }; |
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320 | |||
5078 | serge | 321 | enum radeon_flip_status { |
322 | RADEON_FLIP_NONE, |
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323 | RADEON_FLIP_PENDING, |
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324 | RADEON_FLIP_SUBMITTED |
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325 | }; |
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326 | |||
1117 | serge | 327 | struct radeon_crtc { |
1123 | serge | 328 | struct drm_crtc base; |
1117 | serge | 329 | int crtc_id; |
1179 | serge | 330 | u16 lut_r[256], lut_g[256], lut_b[256]; |
1117 | serge | 331 | bool enabled; |
332 | bool can_tile; |
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333 | uint32_t crtc_offset; |
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1321 | serge | 334 | struct drm_gem_object *cursor_bo; |
1117 | serge | 335 | uint64_t cursor_addr; |
5271 | serge | 336 | int cursor_x; |
337 | int cursor_y; |
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338 | int cursor_hot_x; |
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339 | int cursor_hot_y; |
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1117 | serge | 340 | int cursor_width; |
341 | int cursor_height; |
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5078 | serge | 342 | int max_cursor_width; |
343 | int max_cursor_height; |
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1179 | serge | 344 | uint32_t legacy_display_base_addr; |
345 | enum radeon_rmx_type rmx_type; |
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1963 | serge | 346 | u8 h_border; |
347 | u8 v_border; |
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1179 | serge | 348 | fixed20_12 vsc; |
349 | fixed20_12 hsc; |
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1268 | serge | 350 | struct drm_display_mode native_mode; |
1430 | serge | 351 | int pll_id; |
5078 | serge | 352 | /* page flipping */ |
353 | struct workqueue_struct *flip_queue; |
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354 | struct radeon_flip_work *flip_work; |
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355 | enum radeon_flip_status flip_status; |
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2997 | Serge | 356 | /* pll sharing */ |
357 | struct radeon_atom_ss ss; |
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358 | bool ss_enabled; |
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359 | u32 adjusted_clock; |
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360 | int bpc; |
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361 | u32 pll_reference_div; |
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362 | u32 pll_post_div; |
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363 | u32 pll_flags; |
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364 | struct drm_encoder *encoder; |
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365 | struct drm_connector *connector; |
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5078 | serge | 366 | /* for dpm */ |
367 | u32 line_time; |
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368 | u32 wm_low; |
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369 | u32 wm_high; |
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6104 | serge | 370 | u32 lb_vblank_lead_lines; |
5078 | serge | 371 | struct drm_display_mode hw_mode; |
6104 | serge | 372 | enum radeon_output_csc output_csc; |
1117 | serge | 373 | }; |
374 | |||
375 | struct radeon_encoder_primary_dac { |
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376 | /* legacy primary dac */ |
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377 | uint32_t ps2_pdac_adj; |
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378 | }; |
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379 | |||
380 | struct radeon_encoder_lvds { |
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381 | /* legacy lvds */ |
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382 | uint16_t panel_vcc_delay; |
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383 | uint8_t panel_pwr_delay; |
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384 | uint8_t panel_digon_delay; |
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385 | uint8_t panel_blon_delay; |
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386 | uint16_t panel_ref_divider; |
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387 | uint8_t panel_post_divider; |
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388 | uint16_t panel_fb_divider; |
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389 | bool use_bios_dividers; |
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390 | uint32_t lvds_gen_cntl; |
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391 | /* panel mode */ |
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1268 | serge | 392 | struct drm_display_mode native_mode; |
1963 | serge | 393 | struct backlight_device *bl_dev; |
394 | int dpms_mode; |
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395 | uint8_t backlight_level; |
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1117 | serge | 396 | }; |
397 | |||
398 | struct radeon_encoder_tv_dac { |
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399 | /* legacy tv dac */ |
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400 | uint32_t ps2_tvdac_adj; |
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401 | uint32_t ntsc_tvdac_adj; |
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402 | uint32_t pal_tvdac_adj; |
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403 | |||
1179 | serge | 404 | int h_pos; |
405 | int v_pos; |
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406 | int h_size; |
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407 | int supported_tv_stds; |
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408 | bool tv_on; |
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1117 | serge | 409 | enum radeon_tv_std tv_std; |
1179 | serge | 410 | struct radeon_tv_regs tv; |
1117 | serge | 411 | }; |
412 | |||
413 | struct radeon_encoder_int_tmds { |
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414 | /* legacy int tmds */ |
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415 | struct radeon_tmds_pll tmds_pll[4]; |
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416 | }; |
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417 | |||
1321 | serge | 418 | struct radeon_encoder_ext_tmds { |
419 | /* tmds over dvo */ |
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420 | struct radeon_i2c_chan *i2c_bus; |
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421 | uint8_t slave_addr; |
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422 | enum radeon_dvo_chip dvo_chip; |
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423 | }; |
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424 | |||
1268 | serge | 425 | /* spread spectrum */ |
1117 | serge | 426 | struct radeon_encoder_atom_dig { |
1963 | serge | 427 | bool linkb; |
1117 | serge | 428 | /* atom dig */ |
429 | bool coherent_mode; |
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1963 | serge | 430 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
431 | /* atom lvds/edp */ |
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432 | uint32_t lcd_misc; |
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1117 | serge | 433 | uint16_t panel_pwr_delay; |
1963 | serge | 434 | uint32_t lcd_ss_id; |
1117 | serge | 435 | /* panel mode */ |
1268 | serge | 436 | struct drm_display_mode native_mode; |
1963 | serge | 437 | struct backlight_device *bl_dev; |
438 | int dpms_mode; |
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439 | uint8_t backlight_level; |
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2997 | Serge | 440 | int panel_mode; |
441 | struct radeon_afmt *afmt; |
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6104 | serge | 442 | struct r600_audio_pin *pin; |
443 | int active_mst_links; |
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1117 | serge | 444 | }; |
445 | |||
1179 | serge | 446 | struct radeon_encoder_atom_dac { |
447 | enum radeon_tv_std tv_std; |
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448 | }; |
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449 | |||
6104 | serge | 450 | struct radeon_encoder_mst { |
451 | int crtc; |
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452 | struct radeon_encoder *primary; |
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453 | struct radeon_connector *connector; |
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454 | struct drm_dp_mst_port *port; |
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455 | int pbn; |
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456 | int fe; |
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457 | bool fe_from_be; |
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458 | bool enc_active; |
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459 | }; |
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460 | |||
1117 | serge | 461 | struct radeon_encoder { |
6104 | serge | 462 | struct drm_encoder base; |
1963 | serge | 463 | uint32_t encoder_enum; |
1117 | serge | 464 | uint32_t encoder_id; |
465 | uint32_t devices; |
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1179 | serge | 466 | uint32_t active_device; |
1117 | serge | 467 | uint32_t flags; |
468 | uint32_t pixel_clock; |
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469 | enum radeon_rmx_type rmx_type; |
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1963 | serge | 470 | enum radeon_underscan_type underscan_type; |
471 | uint32_t underscan_hborder; |
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472 | uint32_t underscan_vborder; |
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1268 | serge | 473 | struct drm_display_mode native_mode; |
1117 | serge | 474 | void *enc_priv; |
1963 | serge | 475 | int audio_polling_active; |
476 | bool is_ext_encoder; |
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477 | u16 caps; |
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6104 | serge | 478 | struct radeon_audio_funcs *audio; |
479 | enum radeon_output_csc output_csc; |
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480 | bool can_mst; |
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481 | uint32_t offset; |
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482 | bool is_mst_encoder; |
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483 | /* front end for this mst encoder */ |
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1117 | serge | 484 | }; |
485 | |||
486 | struct radeon_connector_atom_dig { |
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487 | uint32_t igp_lane_info; |
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1321 | serge | 488 | /* displayport */ |
3192 | Serge | 489 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1321 | serge | 490 | u8 dp_sink_type; |
491 | int dp_clock; |
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492 | int dp_lane_count; |
||
1963 | serge | 493 | bool edp_on; |
6104 | serge | 494 | bool is_mst; |
1117 | serge | 495 | }; |
496 | |||
1321 | serge | 497 | struct radeon_gpio_rec { |
498 | bool valid; |
||
499 | u8 id; |
||
500 | u32 reg; |
||
501 | u32 mask; |
||
5271 | serge | 502 | u32 shift; |
1321 | serge | 503 | }; |
504 | |||
505 | struct radeon_hpd { |
||
506 | enum radeon_hpd_id hpd; |
||
507 | u8 plugged_state; |
||
508 | struct radeon_gpio_rec gpio; |
||
509 | }; |
||
510 | |||
1963 | serge | 511 | struct radeon_router { |
512 | u32 router_id; |
||
513 | struct radeon_i2c_bus_rec i2c_info; |
||
514 | u8 i2c_addr; |
||
515 | /* i2c mux */ |
||
516 | bool ddc_valid; |
||
517 | u8 ddc_mux_type; |
||
518 | u8 ddc_mux_control_pin; |
||
519 | u8 ddc_mux_state; |
||
520 | /* clock/data mux */ |
||
521 | bool cd_valid; |
||
522 | u8 cd_mux_type; |
||
523 | u8 cd_mux_control_pin; |
||
524 | u8 cd_mux_state; |
||
525 | }; |
||
526 | |||
5078 | serge | 527 | enum radeon_connector_audio { |
528 | RADEON_AUDIO_DISABLE = 0, |
||
529 | RADEON_AUDIO_ENABLE = 1, |
||
530 | RADEON_AUDIO_AUTO = 2 |
||
531 | }; |
||
532 | |||
533 | enum radeon_connector_dither { |
||
534 | RADEON_FMT_DITHER_DISABLE = 0, |
||
535 | RADEON_FMT_DITHER_ENABLE = 1, |
||
536 | }; |
||
537 | |||
6104 | serge | 538 | struct stream_attribs { |
539 | uint16_t fe; |
||
540 | uint16_t slots; |
||
541 | }; |
||
542 | |||
1117 | serge | 543 | struct radeon_connector { |
6104 | serge | 544 | struct drm_connector base; |
1117 | serge | 545 | uint32_t connector_id; |
546 | uint32_t devices; |
||
547 | struct radeon_i2c_chan *ddc_bus; |
||
1963 | serge | 548 | /* some systems have an hdmi and vga port with a shared ddc line */ |
1268 | serge | 549 | bool shared_ddc; |
1179 | serge | 550 | bool use_digital; |
551 | /* we need to mind the EDID between detect |
||
552 | and get modes due to analog/digital/tvencoder */ |
||
553 | struct edid *edid; |
||
1117 | serge | 554 | void *con_priv; |
1179 | serge | 555 | bool dac_load_detect; |
2997 | Serge | 556 | bool detected_by_load; /* if the connection status was determined by load */ |
6104 | serge | 557 | bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ |
1268 | serge | 558 | uint16_t connector_object_id; |
1321 | serge | 559 | struct radeon_hpd hpd; |
1963 | serge | 560 | struct radeon_router router; |
561 | struct radeon_i2c_chan *router_bus; |
||
5078 | serge | 562 | enum radeon_connector_audio audio; |
563 | enum radeon_connector_dither dither; |
||
564 | int pixelclock_for_modeset; |
||
6104 | serge | 565 | bool is_mst_connector; |
566 | struct radeon_connector *mst_port; |
||
567 | struct drm_dp_mst_port *port; |
||
568 | struct drm_dp_mst_topology_mgr mst_mgr; |
||
569 | |||
570 | struct radeon_encoder *mst_encoder; |
||
571 | struct stream_attribs cur_stream_attribs[6]; |
||
572 | int enabled_attribs; |
||
1117 | serge | 573 | }; |
574 | |||
575 | struct radeon_framebuffer { |
||
6104 | serge | 576 | struct drm_framebuffer base; |
577 | struct drm_gem_object *obj; |
||
1117 | serge | 578 | }; |
579 | |||
2997 | Serge | 580 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
581 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
||
1963 | serge | 582 | |
3764 | Serge | 583 | struct atom_clock_dividers { |
584 | u32 post_div; |
||
585 | union { |
||
586 | struct { |
||
587 | #ifdef __BIG_ENDIAN |
||
588 | u32 reserved : 6; |
||
589 | u32 whole_fb_div : 12; |
||
590 | u32 frac_fb_div : 14; |
||
591 | #else |
||
592 | u32 frac_fb_div : 14; |
||
593 | u32 whole_fb_div : 12; |
||
594 | u32 reserved : 6; |
||
595 | #endif |
||
596 | }; |
||
597 | u32 fb_div; |
||
598 | }; |
||
599 | u32 ref_div; |
||
600 | bool enable_post_div; |
||
601 | bool enable_dithen; |
||
602 | u32 vco_mode; |
||
603 | u32 real_clock; |
||
5078 | serge | 604 | /* added for CI */ |
605 | u32 post_divider; |
||
606 | u32 flags; |
||
3764 | Serge | 607 | }; |
608 | |||
5078 | serge | 609 | struct atom_mpll_param { |
610 | union { |
||
611 | struct { |
||
612 | #ifdef __BIG_ENDIAN |
||
613 | u32 reserved : 8; |
||
614 | u32 clkfrac : 12; |
||
615 | u32 clkf : 12; |
||
616 | #else |
||
617 | u32 clkf : 12; |
||
618 | u32 clkfrac : 12; |
||
619 | u32 reserved : 8; |
||
620 | #endif |
||
621 | }; |
||
622 | u32 fb_div; |
||
623 | }; |
||
624 | u32 post_div; |
||
625 | u32 bwcntl; |
||
626 | u32 dll_speed; |
||
627 | u32 vco_mode; |
||
628 | u32 yclk_sel; |
||
629 | u32 qdr; |
||
630 | u32 half_rate; |
||
631 | }; |
||
632 | |||
633 | #define MEM_TYPE_GDDR5 0x50 |
||
634 | #define MEM_TYPE_GDDR4 0x40 |
||
635 | #define MEM_TYPE_GDDR3 0x30 |
||
636 | #define MEM_TYPE_DDR2 0x20 |
||
637 | #define MEM_TYPE_GDDR1 0x10 |
||
638 | #define MEM_TYPE_DDR3 0xb0 |
||
639 | #define MEM_TYPE_MASK 0xf0 |
||
640 | |||
641 | struct atom_memory_info { |
||
642 | u8 mem_vendor; |
||
643 | u8 mem_type; |
||
644 | }; |
||
645 | |||
646 | #define MAX_AC_TIMING_ENTRIES 16 |
||
647 | |||
648 | struct atom_memory_clock_range_table |
||
649 | { |
||
650 | u8 num_entries; |
||
651 | u8 rsv[3]; |
||
652 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
||
653 | }; |
||
654 | |||
655 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
||
656 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
||
657 | |||
658 | struct atom_mc_reg_entry { |
||
659 | u32 mclk_max; |
||
660 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
||
661 | }; |
||
662 | |||
663 | struct atom_mc_register_address { |
||
664 | u16 s1; |
||
665 | u8 pre_reg_data; |
||
666 | }; |
||
667 | |||
668 | struct atom_mc_reg_table { |
||
669 | u8 last; |
||
670 | u8 num_entries; |
||
671 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
||
672 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
||
673 | }; |
||
674 | |||
675 | #define MAX_VOLTAGE_ENTRIES 32 |
||
676 | |||
677 | struct atom_voltage_table_entry |
||
678 | { |
||
679 | u16 value; |
||
680 | u32 smio_low; |
||
681 | }; |
||
682 | |||
683 | struct atom_voltage_table |
||
684 | { |
||
685 | u32 count; |
||
686 | u32 mask_low; |
||
687 | u32 phase_delay; |
||
688 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
||
689 | }; |
||
690 | |||
6104 | serge | 691 | /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ |
692 | #define USE_REAL_VBLANKSTART (1 << 30) |
||
693 | #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) |
||
5078 | serge | 694 | |
695 | extern void |
||
696 | radeon_add_atom_connector(struct drm_device *dev, |
||
697 | uint32_t connector_id, |
||
698 | uint32_t supported_device, |
||
699 | int connector_type, |
||
700 | struct radeon_i2c_bus_rec *i2c_bus, |
||
701 | uint32_t igp_lane_info, |
||
702 | uint16_t connector_object_id, |
||
703 | struct radeon_hpd *hpd, |
||
704 | struct radeon_router *router); |
||
705 | extern void |
||
706 | radeon_add_legacy_connector(struct drm_device *dev, |
||
707 | uint32_t connector_id, |
||
708 | uint32_t supported_device, |
||
709 | int connector_type, |
||
710 | struct radeon_i2c_bus_rec *i2c_bus, |
||
711 | uint16_t connector_object_id, |
||
712 | struct radeon_hpd *hpd); |
||
713 | extern uint32_t |
||
714 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
||
715 | uint8_t dac); |
||
716 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
||
717 | |||
1404 | serge | 718 | extern enum radeon_tv_std |
719 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
||
720 | extern enum radeon_tv_std |
||
721 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
||
5078 | serge | 722 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
723 | u16 *vddc, u16 *vddci, u16 *mvdd); |
||
1404 | serge | 724 | |
5078 | serge | 725 | extern void |
726 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
||
727 | struct drm_encoder *encoder, |
||
728 | bool connected); |
||
729 | extern void |
||
730 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
||
731 | struct drm_encoder *encoder, |
||
732 | bool connected); |
||
733 | |||
1963 | serge | 734 | extern struct drm_connector * |
735 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
||
2997 | Serge | 736 | extern struct drm_connector * |
737 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
||
738 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
||
739 | u32 pixel_clock); |
||
1963 | serge | 740 | |
2997 | Serge | 741 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
742 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
||
1963 | serge | 743 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
2997 | Serge | 744 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
1963 | serge | 745 | |
5078 | serge | 746 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
747 | |||
1321 | serge | 748 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
1963 | serge | 749 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1321 | serge | 750 | struct drm_display_mode *mode); |
751 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
||
2997 | Serge | 752 | const struct drm_display_mode *mode); |
1963 | serge | 753 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
6104 | serge | 754 | struct drm_connector *connector); |
2997 | Serge | 755 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
1321 | serge | 756 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
757 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
||
2997 | Serge | 758 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
759 | struct drm_connector *connector); |
||
6661 | serge | 760 | extern int radeon_dp_get_dp_link_config(struct drm_connector *connector, |
761 | const u8 *dpcd, |
||
762 | unsigned pix_clock, |
||
763 | unsigned *dp_lanes, unsigned *dp_rate); |
||
5078 | serge | 764 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
765 | u8 power_state); |
||
766 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
||
6104 | serge | 767 | extern ssize_t |
768 | radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); |
||
769 | |||
1963 | serge | 770 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
6104 | serge | 771 | extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); |
1963 | serge | 772 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
2997 | Serge | 773 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
1321 | serge | 774 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
775 | int action, uint8_t lane_num, |
||
776 | uint8_t lane_set); |
||
6104 | serge | 777 | extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, |
778 | int action, uint8_t lane_num, |
||
779 | uint8_t lane_set, int fe); |
||
780 | extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, |
||
781 | int fe); |
||
1986 | serge | 782 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
2997 | Serge | 783 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
5078 | serge | 784 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
1321 | serge | 785 | |
1963 | serge | 786 | extern void radeon_i2c_init(struct radeon_device *rdev); |
787 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
||
788 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
||
789 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
||
790 | extern void radeon_i2c_add(struct radeon_device *rdev, |
||
791 | struct radeon_i2c_bus_rec *rec, |
||
792 | const char *name); |
||
793 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
||
794 | struct radeon_i2c_bus_rec *i2c_bus); |
||
1117 | serge | 795 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
796 | struct radeon_i2c_bus_rec *rec, |
||
797 | const char *name); |
||
798 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
||
1430 | serge | 799 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
6104 | serge | 800 | u8 slave_addr, |
801 | u8 addr, |
||
802 | u8 *val); |
||
1430 | serge | 803 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
6104 | serge | 804 | u8 slave_addr, |
805 | u8 addr, |
||
806 | u8 val); |
||
1963 | serge | 807 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
808 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
||
3192 | Serge | 809 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
1117 | serge | 810 | |
1963 | serge | 811 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
812 | struct radeon_atom_ss *ss, |
||
813 | int id); |
||
814 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
||
815 | struct radeon_atom_ss *ss, |
||
816 | int id, u32 clock); |
||
5271 | serge | 817 | extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, |
818 | u8 id); |
||
1963 | serge | 819 | |
820 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
||
6104 | serge | 821 | uint64_t freq, |
822 | uint32_t *dot_clock_p, |
||
823 | uint32_t *fb_div_p, |
||
824 | uint32_t *frac_fb_div_p, |
||
825 | uint32_t *ref_div_p, |
||
826 | uint32_t *post_div_p); |
||
1117 | serge | 827 | |
1963 | serge | 828 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
829 | u32 freq, |
||
830 | u32 *dot_clock_p, |
||
831 | u32 *fb_div_p, |
||
832 | u32 *frac_fb_div_p, |
||
833 | u32 *ref_div_p, |
||
834 | u32 *post_div_p); |
||
835 | |||
1321 | serge | 836 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
837 | |||
1117 | serge | 838 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
839 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
||
840 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
||
841 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
||
842 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
||
1963 | serge | 843 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
1321 | serge | 844 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
1117 | serge | 845 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
1963 | serge | 846 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
1179 | serge | 847 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
5271 | serge | 848 | extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); |
1117 | serge | 849 | |
850 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
||
851 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
6104 | serge | 852 | struct drm_framebuffer *old_fb); |
1963 | serge | 853 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
854 | struct drm_framebuffer *fb, |
||
855 | int x, int y, |
||
856 | enum mode_set_atomic state); |
||
1117 | serge | 857 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
858 | struct drm_display_mode *mode, |
||
859 | struct drm_display_mode *adjusted_mode, |
||
860 | int x, int y, |
||
861 | struct drm_framebuffer *old_fb); |
||
862 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
||
863 | |||
864 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
865 | struct drm_framebuffer *old_fb); |
||
1963 | serge | 866 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
867 | struct drm_framebuffer *fb, |
||
868 | int x, int y, |
||
869 | enum mode_set_atomic state); |
||
870 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
||
871 | struct drm_framebuffer *fb, |
||
872 | int x, int y, int atomic); |
||
5271 | serge | 873 | extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, |
6104 | serge | 874 | struct drm_file *file_priv, |
875 | uint32_t handle, |
||
876 | uint32_t width, |
||
5271 | serge | 877 | uint32_t height, |
878 | int32_t hot_x, |
||
879 | int32_t hot_y); |
||
1117 | serge | 880 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
881 | int x, int y); |
||
5271 | serge | 882 | extern void radeon_cursor_reset(struct drm_crtc *crtc); |
1117 | serge | 883 | |
6104 | serge | 884 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
885 | unsigned int flags, int *vpos, int *hpos, |
||
886 | ktime_t *stime, ktime_t *etime, |
||
887 | const struct drm_display_mode *mode); |
||
1963 | serge | 888 | |
1430 | serge | 889 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
890 | extern struct edid * |
||
1963 | serge | 891 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
1117 | serge | 892 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
893 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
||
894 | extern struct radeon_encoder_atom_dig * |
||
895 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
||
1321 | serge | 896 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
6104 | serge | 897 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 898 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
6104 | serge | 899 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 900 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
6104 | serge | 901 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 902 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
903 | struct radeon_encoder_ext_tmds *tmds); |
||
904 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
||
905 | struct radeon_encoder_ext_tmds *tmds); |
||
1117 | serge | 906 | extern struct radeon_encoder_primary_dac * |
907 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
||
908 | extern struct radeon_encoder_tv_dac * |
||
909 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
||
910 | extern struct radeon_encoder_lvds * |
||
911 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
||
912 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
||
913 | extern struct radeon_encoder_tv_dac * |
||
914 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
||
915 | extern struct radeon_encoder_primary_dac * |
||
916 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
||
1321 | serge | 917 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
918 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
||
1117 | serge | 919 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
920 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
||
921 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
||
922 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
||
1179 | serge | 923 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
924 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
||
1117 | serge | 925 | extern void |
926 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
||
927 | extern void |
||
928 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
||
929 | extern void |
||
930 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
||
931 | extern void |
||
932 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
||
933 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
||
934 | u16 blue, int regno); |
||
1221 | serge | 935 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
936 | u16 *blue, int regno); |
||
2997 | Serge | 937 | int radeon_framebuffer_init(struct drm_device *dev, |
1963 | serge | 938 | struct radeon_framebuffer *rfb, |
6938 | serge | 939 | const struct drm_mode_fb_cmd2 *mode_cmd, |
6104 | serge | 940 | struct drm_gem_object *obj); |
1117 | serge | 941 | |
942 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
||
943 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
||
944 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
||
945 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
946 | struct radeon_crtc *radeon_crtc); |
||
947 | void radeon_legacy_init_crtc(struct drm_device *dev, |
||
948 | struct radeon_crtc *radeon_crtc); |
||
949 | |||
950 | void radeon_get_clock_info(struct drm_device *dev); |
||
951 | |||
952 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
||
953 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
||
954 | |||
955 | void radeon_enc_destroy(struct drm_encoder *encoder); |
||
956 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
||
957 | void radeon_combios_asic_init(struct drm_device *dev); |
||
1179 | serge | 958 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
2997 | Serge | 959 | const struct drm_display_mode *mode, |
1179 | serge | 960 | struct drm_display_mode *adjusted_mode); |
1963 | serge | 961 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
962 | struct drm_display_mode *adjusted_mode); |
||
1179 | serge | 963 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
1123 | serge | 964 | |
1179 | serge | 965 | /* legacy tv */ |
966 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
||
967 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
||
968 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
||
969 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
||
970 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
||
971 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
||
972 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
||
973 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
||
974 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
||
975 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
||
976 | struct drm_display_mode *mode, |
||
977 | struct drm_display_mode *adjusted_mode); |
||
1963 | serge | 978 | |
5078 | serge | 979 | /* fmt blocks */ |
980 | void avivo_program_fmt(struct drm_encoder *encoder); |
||
981 | void dce3_program_fmt(struct drm_encoder *encoder); |
||
982 | void dce4_program_fmt(struct drm_encoder *encoder); |
||
983 | void dce8_program_fmt(struct drm_encoder *encoder); |
||
984 | |||
1963 | serge | 985 | /* fbdev layer */ |
986 | int radeon_fbdev_init(struct radeon_device *rdev); |
||
987 | void radeon_fbdev_fini(struct radeon_device *rdev); |
||
988 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
||
989 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
||
6104 | serge | 990 | void radeon_fbdev_restore_mode(struct radeon_device *rdev); |
1963 | serge | 991 | |
992 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); |
||
993 | |||
5078 | serge | 994 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
6104 | serge | 995 | |
996 | void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); |
||
997 | void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); |
||
998 | |||
1963 | serge | 999 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
1000 | |||
1001 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
||
6104 | serge | 1002 | |
1003 | /* mst */ |
||
1004 | int radeon_dp_mst_init(struct radeon_connector *radeon_connector); |
||
1005 | int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); |
||
1006 | int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); |
||
1007 | int radeon_mst_debugfs_init(struct radeon_device *rdev); |
||
1008 | void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); |
||
1009 | |||
1010 | void radeon_setup_mst_connector(struct drm_device *dev); |
||
1011 | |||
1012 | int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); |
||
1013 | void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); |
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1117 | serge | 1014 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |