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1117 | serge | 1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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3 | * VA Linux Systems Inc., Fremont, California. |
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4 | * Copyright 2008 Red Hat Inc. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Original Authors: |
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25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
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26 | * |
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27 | * Kernel port Author: Dave Airlie |
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28 | */ |
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29 | |||
30 | #ifndef RADEON_MODE_H |
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31 | #define RADEON_MODE_H |
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32 | |||
1125 | serge | 33 | #include |
34 | #include |
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1123 | serge | 35 | #include |
1321 | serge | 36 | #include |
1125 | serge | 37 | #include |
1179 | serge | 38 | #include |
1125 | serge | 39 | #include |
1179 | serge | 40 | #include "radeon_fixed.h" |
1117 | serge | 41 | |
1179 | serge | 42 | struct radeon_device; |
43 | |||
1117 | serge | 44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
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46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
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47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
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48 | |||
49 | enum radeon_rmx_type { |
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50 | RMX_OFF, |
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51 | RMX_FULL, |
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52 | RMX_CENTER, |
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53 | RMX_ASPECT |
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54 | }; |
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55 | |||
56 | enum radeon_tv_std { |
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57 | TV_STD_NTSC, |
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58 | TV_STD_PAL, |
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59 | TV_STD_PAL_M, |
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60 | TV_STD_PAL_60, |
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61 | TV_STD_NTSC_J, |
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62 | TV_STD_SCART_PAL, |
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63 | TV_STD_SECAM, |
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64 | TV_STD_PAL_CN, |
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1404 | serge | 65 | TV_STD_PAL_N, |
1117 | serge | 66 | }; |
67 | |||
1321 | serge | 68 | /* radeon gpio-based i2c |
69 | * 1. "mask" reg and bits |
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70 | * grabs the gpio pins for software use |
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71 | * 0=not held 1=held |
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72 | * 2. "a" reg and bits |
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73 | * output pin value |
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74 | * 0=low 1=high |
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75 | * 3. "en" reg and bits |
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76 | * sets the pin direction |
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77 | * 0=input 1=output |
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78 | * 4. "y" reg and bits |
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79 | * input pin value |
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80 | * 0=low 1=high |
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81 | */ |
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1117 | serge | 82 | struct radeon_i2c_bus_rec { |
83 | bool valid; |
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1321 | serge | 84 | /* id used by atom */ |
85 | uint8_t i2c_id; |
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1430 | serge | 86 | /* id used by atom */ |
87 | uint8_t hpd_id; |
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1321 | serge | 88 | /* can be used with hw i2c engine */ |
89 | bool hw_capable; |
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90 | /* uses multi-media i2c engine */ |
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91 | bool mm_i2c; |
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92 | /* regs and bits */ |
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1117 | serge | 93 | uint32_t mask_clk_reg; |
94 | uint32_t mask_data_reg; |
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95 | uint32_t a_clk_reg; |
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96 | uint32_t a_data_reg; |
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1321 | serge | 97 | uint32_t en_clk_reg; |
98 | uint32_t en_data_reg; |
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99 | uint32_t y_clk_reg; |
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100 | uint32_t y_data_reg; |
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1117 | serge | 101 | uint32_t mask_clk_mask; |
102 | uint32_t mask_data_mask; |
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103 | uint32_t a_clk_mask; |
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104 | uint32_t a_data_mask; |
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1321 | serge | 105 | uint32_t en_clk_mask; |
106 | uint32_t en_data_mask; |
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107 | uint32_t y_clk_mask; |
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108 | uint32_t y_data_mask; |
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1117 | serge | 109 | }; |
110 | |||
111 | struct radeon_tmds_pll { |
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112 | uint32_t freq; |
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113 | uint32_t value; |
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114 | }; |
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115 | |||
116 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
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117 | |||
1430 | serge | 118 | /* pll flags */ |
1117 | serge | 119 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
120 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
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121 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
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122 | #define RADEON_PLL_LEGACY (1 << 3) |
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123 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
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124 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
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125 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
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126 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
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127 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
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128 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
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129 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
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1179 | serge | 130 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
1404 | serge | 131 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
1117 | serge | 132 | |
1430 | serge | 133 | /* pll algo */ |
134 | enum radeon_pll_algo { |
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135 | PLL_ALGO_LEGACY, |
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136 | PLL_ALGO_NEW |
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137 | }; |
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138 | |||
1117 | serge | 139 | struct radeon_pll { |
1404 | serge | 140 | /* reference frequency */ |
141 | uint32_t reference_freq; |
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142 | |||
143 | /* fixed dividers */ |
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144 | uint32_t reference_div; |
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145 | uint32_t post_div; |
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146 | |||
147 | /* pll in/out limits */ |
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1117 | serge | 148 | uint32_t pll_in_min; |
149 | uint32_t pll_in_max; |
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150 | uint32_t pll_out_min; |
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151 | uint32_t pll_out_max; |
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1404 | serge | 152 | uint32_t best_vco; |
1117 | serge | 153 | |
1404 | serge | 154 | /* divider limits */ |
1117 | serge | 155 | uint32_t min_ref_div; |
156 | uint32_t max_ref_div; |
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157 | uint32_t min_post_div; |
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158 | uint32_t max_post_div; |
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159 | uint32_t min_feedback_div; |
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160 | uint32_t max_feedback_div; |
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161 | uint32_t min_frac_feedback_div; |
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162 | uint32_t max_frac_feedback_div; |
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1404 | serge | 163 | |
164 | /* flags for the current clock */ |
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165 | uint32_t flags; |
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166 | |||
167 | /* pll id */ |
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168 | uint32_t id; |
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1430 | serge | 169 | /* pll algo */ |
170 | enum radeon_pll_algo algo; |
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1117 | serge | 171 | }; |
172 | |||
1430 | serge | 173 | struct i2c_algo_radeon_data { |
174 | struct i2c_adapter bit_adapter; |
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175 | struct i2c_algo_bit_data bit_data; |
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176 | }; |
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177 | |||
1117 | serge | 178 | struct radeon_i2c_chan { |
1321 | serge | 179 | struct i2c_adapter adapter; |
1117 | serge | 180 | struct drm_device *dev; |
1321 | serge | 181 | union { |
182 | struct i2c_algo_dp_aux_data dp; |
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1430 | serge | 183 | struct i2c_algo_radeon_data radeon; |
1321 | serge | 184 | } algo; |
1117 | serge | 185 | struct radeon_i2c_bus_rec rec; |
186 | }; |
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187 | |||
188 | /* mostly for macs, but really any system without connector tables */ |
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189 | enum radeon_connector_table { |
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190 | CT_NONE, |
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191 | CT_GENERIC, |
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192 | CT_IBOOK, |
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193 | CT_POWERBOOK_EXTERNAL, |
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194 | CT_POWERBOOK_INTERNAL, |
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195 | CT_POWERBOOK_VGA, |
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196 | CT_MINI_EXTERNAL, |
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197 | CT_MINI_INTERNAL, |
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198 | CT_IMAC_G5_ISIGHT, |
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199 | CT_EMAC, |
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200 | }; |
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201 | |||
1321 | serge | 202 | enum radeon_dvo_chip { |
203 | DVO_SIL164, |
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204 | DVO_SIL1178, |
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205 | }; |
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206 | |||
1117 | serge | 207 | struct radeon_mode_info { |
208 | struct atom_context *atom_context; |
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1268 | serge | 209 | struct card_info *atom_card_info; |
1117 | serge | 210 | enum radeon_connector_table connector_table; |
211 | bool mode_config_initialized; |
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1430 | serge | 212 | struct radeon_crtc *crtcs[6]; |
1179 | serge | 213 | /* DVI-I properties */ |
214 | struct drm_property *coherent_mode_property; |
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215 | /* DAC enable load detect */ |
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216 | struct drm_property *load_detect_property; |
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217 | /* TV standard load detect */ |
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218 | struct drm_property *tv_std_property; |
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219 | /* legacy TMDS PLL detect */ |
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220 | struct drm_property *tmds_pll_property; |
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1430 | serge | 221 | /* hardcoded DFP edid from BIOS */ |
222 | struct edid *bios_hardcoded_edid; |
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1117 | serge | 223 | }; |
224 | |||
1179 | serge | 225 | #define MAX_H_CODE_TIMING_LEN 32 |
226 | #define MAX_V_CODE_TIMING_LEN 32 |
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227 | |||
228 | /* need to store these as reading |
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229 | back code tables is excessive */ |
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230 | struct radeon_tv_regs { |
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231 | uint32_t tv_uv_adr; |
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232 | uint32_t timing_cntl; |
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233 | uint32_t hrestart; |
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234 | uint32_t vrestart; |
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235 | uint32_t frestart; |
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236 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
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237 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
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238 | }; |
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239 | |||
1117 | serge | 240 | struct radeon_crtc { |
1123 | serge | 241 | struct drm_crtc base; |
1117 | serge | 242 | int crtc_id; |
1179 | serge | 243 | u16 lut_r[256], lut_g[256], lut_b[256]; |
1117 | serge | 244 | bool enabled; |
245 | bool can_tile; |
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246 | uint32_t crtc_offset; |
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1321 | serge | 247 | struct drm_gem_object *cursor_bo; |
1117 | serge | 248 | uint64_t cursor_addr; |
249 | int cursor_width; |
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250 | int cursor_height; |
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1179 | serge | 251 | uint32_t legacy_display_base_addr; |
252 | uint32_t legacy_cursor_offset; |
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253 | enum radeon_rmx_type rmx_type; |
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254 | fixed20_12 vsc; |
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255 | fixed20_12 hsc; |
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1268 | serge | 256 | struct drm_display_mode native_mode; |
1430 | serge | 257 | int pll_id; |
1117 | serge | 258 | }; |
259 | |||
260 | struct radeon_encoder_primary_dac { |
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261 | /* legacy primary dac */ |
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262 | uint32_t ps2_pdac_adj; |
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263 | }; |
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264 | |||
265 | struct radeon_encoder_lvds { |
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266 | /* legacy lvds */ |
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267 | uint16_t panel_vcc_delay; |
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268 | uint8_t panel_pwr_delay; |
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269 | uint8_t panel_digon_delay; |
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270 | uint8_t panel_blon_delay; |
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271 | uint16_t panel_ref_divider; |
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272 | uint8_t panel_post_divider; |
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273 | uint16_t panel_fb_divider; |
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274 | bool use_bios_dividers; |
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275 | uint32_t lvds_gen_cntl; |
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276 | /* panel mode */ |
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1268 | serge | 277 | struct drm_display_mode native_mode; |
1117 | serge | 278 | }; |
279 | |||
280 | struct radeon_encoder_tv_dac { |
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281 | /* legacy tv dac */ |
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282 | uint32_t ps2_tvdac_adj; |
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283 | uint32_t ntsc_tvdac_adj; |
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284 | uint32_t pal_tvdac_adj; |
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285 | |||
1179 | serge | 286 | int h_pos; |
287 | int v_pos; |
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288 | int h_size; |
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289 | int supported_tv_stds; |
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290 | bool tv_on; |
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1117 | serge | 291 | enum radeon_tv_std tv_std; |
1179 | serge | 292 | struct radeon_tv_regs tv; |
1117 | serge | 293 | }; |
294 | |||
295 | struct radeon_encoder_int_tmds { |
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296 | /* legacy int tmds */ |
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297 | struct radeon_tmds_pll tmds_pll[4]; |
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298 | }; |
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299 | |||
1321 | serge | 300 | struct radeon_encoder_ext_tmds { |
301 | /* tmds over dvo */ |
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302 | struct radeon_i2c_chan *i2c_bus; |
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303 | uint8_t slave_addr; |
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304 | enum radeon_dvo_chip dvo_chip; |
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305 | }; |
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306 | |||
1268 | serge | 307 | /* spread spectrum */ |
308 | struct radeon_atom_ss { |
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309 | uint16_t percentage; |
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310 | uint8_t type; |
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311 | uint8_t step; |
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312 | uint8_t delay; |
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313 | uint8_t range; |
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314 | uint8_t refdiv; |
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315 | }; |
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316 | |||
1117 | serge | 317 | struct radeon_encoder_atom_dig { |
318 | /* atom dig */ |
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319 | bool coherent_mode; |
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1404 | serge | 320 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ |
1117 | serge | 321 | /* atom lvds */ |
322 | uint32_t lvds_misc; |
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323 | uint16_t panel_pwr_delay; |
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1430 | serge | 324 | enum radeon_pll_algo pll_algo; |
1268 | serge | 325 | struct radeon_atom_ss *ss; |
1117 | serge | 326 | /* panel mode */ |
1268 | serge | 327 | struct drm_display_mode native_mode; |
1117 | serge | 328 | }; |
329 | |||
1179 | serge | 330 | struct radeon_encoder_atom_dac { |
331 | enum radeon_tv_std tv_std; |
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332 | }; |
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333 | |||
1117 | serge | 334 | struct radeon_encoder { |
335 | struct drm_encoder base; |
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336 | uint32_t encoder_id; |
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337 | uint32_t devices; |
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1179 | serge | 338 | uint32_t active_device; |
1117 | serge | 339 | uint32_t flags; |
340 | uint32_t pixel_clock; |
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341 | enum radeon_rmx_type rmx_type; |
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1268 | serge | 342 | struct drm_display_mode native_mode; |
1117 | serge | 343 | void *enc_priv; |
1404 | serge | 344 | int hdmi_offset; |
345 | int hdmi_audio_workaround; |
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346 | int hdmi_buffer_status; |
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1117 | serge | 347 | }; |
348 | |||
349 | struct radeon_connector_atom_dig { |
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350 | uint32_t igp_lane_info; |
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351 | bool linkb; |
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1321 | serge | 352 | /* displayport */ |
353 | struct radeon_i2c_chan *dp_i2c_bus; |
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354 | u8 dpcd[8]; |
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355 | u8 dp_sink_type; |
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356 | int dp_clock; |
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357 | int dp_lane_count; |
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1117 | serge | 358 | }; |
359 | |||
1321 | serge | 360 | struct radeon_gpio_rec { |
361 | bool valid; |
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362 | u8 id; |
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363 | u32 reg; |
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364 | u32 mask; |
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365 | }; |
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366 | |||
367 | enum radeon_hpd_id { |
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368 | RADEON_HPD_NONE = 0, |
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369 | RADEON_HPD_1, |
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370 | RADEON_HPD_2, |
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371 | RADEON_HPD_3, |
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372 | RADEON_HPD_4, |
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373 | RADEON_HPD_5, |
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374 | RADEON_HPD_6, |
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375 | }; |
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376 | |||
377 | struct radeon_hpd { |
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378 | enum radeon_hpd_id hpd; |
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379 | u8 plugged_state; |
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380 | struct radeon_gpio_rec gpio; |
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381 | }; |
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382 | |||
1117 | serge | 383 | struct radeon_connector { |
384 | struct drm_connector base; |
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385 | uint32_t connector_id; |
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386 | uint32_t devices; |
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387 | struct radeon_i2c_chan *ddc_bus; |
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1268 | serge | 388 | /* some systems have a an hdmi and vga port with a shared ddc line */ |
389 | bool shared_ddc; |
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1179 | serge | 390 | bool use_digital; |
391 | /* we need to mind the EDID between detect |
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392 | and get modes due to analog/digital/tvencoder */ |
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393 | struct edid *edid; |
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1117 | serge | 394 | void *con_priv; |
1179 | serge | 395 | bool dac_load_detect; |
1268 | serge | 396 | uint16_t connector_object_id; |
1321 | serge | 397 | struct radeon_hpd hpd; |
1117 | serge | 398 | }; |
399 | |||
400 | struct radeon_framebuffer { |
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1123 | serge | 401 | struct drm_framebuffer base; |
402 | struct drm_gem_object *obj; |
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1117 | serge | 403 | }; |
404 | |||
1404 | serge | 405 | extern enum radeon_tv_std |
406 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
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407 | extern enum radeon_tv_std |
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408 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
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409 | |||
1321 | serge | 410 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
411 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
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412 | extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, |
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413 | struct drm_display_mode *mode); |
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414 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
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415 | struct drm_display_mode *mode); |
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416 | extern void dp_link_train(struct drm_encoder *encoder, |
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417 | struct drm_connector *connector); |
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418 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
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419 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
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1430 | serge | 420 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); |
1321 | serge | 421 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
422 | int action, uint8_t lane_num, |
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423 | uint8_t lane_set); |
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424 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
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425 | uint8_t write_byte, uint8_t *read_byte); |
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426 | |||
427 | extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
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428 | struct radeon_i2c_bus_rec *rec, |
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429 | const char *name); |
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1117 | serge | 430 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
431 | struct radeon_i2c_bus_rec *rec, |
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432 | const char *name); |
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433 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
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1430 | serge | 434 | extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c); |
435 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
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1321 | serge | 436 | u8 slave_addr, |
437 | u8 addr, |
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438 | u8 *val); |
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1430 | serge | 439 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
1321 | serge | 440 | u8 slave_addr, |
441 | u8 addr, |
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442 | u8 val); |
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1117 | serge | 443 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
444 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
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445 | |||
1123 | serge | 446 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
1117 | serge | 447 | |
448 | extern void radeon_compute_pll(struct radeon_pll *pll, |
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449 | uint64_t freq, |
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450 | uint32_t *dot_clock_p, |
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451 | uint32_t *fb_div_p, |
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452 | uint32_t *frac_fb_div_p, |
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453 | uint32_t *ref_div_p, |
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1404 | serge | 454 | uint32_t *post_div_p); |
1117 | serge | 455 | |
1321 | serge | 456 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
457 | |||
1117 | serge | 458 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
459 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
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460 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
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461 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
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462 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
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463 | extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); |
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1321 | serge | 464 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
1117 | serge | 465 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
1179 | serge | 466 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
1117 | serge | 467 | |
468 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
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469 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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470 | struct drm_framebuffer *old_fb); |
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471 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
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472 | struct drm_display_mode *mode, |
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473 | struct drm_display_mode *adjusted_mode, |
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474 | int x, int y, |
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475 | struct drm_framebuffer *old_fb); |
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476 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
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477 | |||
478 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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479 | struct drm_framebuffer *old_fb); |
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480 | |||
481 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
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482 | struct drm_file *file_priv, |
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483 | uint32_t handle, |
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484 | uint32_t width, |
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485 | uint32_t height); |
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486 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
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487 | int x, int y); |
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488 | |||
1430 | serge | 489 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
490 | extern struct edid * |
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491 | radeon_combios_get_hardcoded_edid(struct radeon_device *rdev); |
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1117 | serge | 492 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
493 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
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494 | extern struct radeon_encoder_atom_dig * |
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495 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
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1321 | serge | 496 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1179 | serge | 497 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 498 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1179 | serge | 499 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 500 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1179 | serge | 501 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 502 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
503 | struct radeon_encoder_ext_tmds *tmds); |
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504 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
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505 | struct radeon_encoder_ext_tmds *tmds); |
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1117 | serge | 506 | extern struct radeon_encoder_primary_dac * |
507 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
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508 | extern struct radeon_encoder_tv_dac * |
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509 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
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510 | extern struct radeon_encoder_lvds * |
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511 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
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512 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
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513 | extern struct radeon_encoder_tv_dac * |
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514 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
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515 | extern struct radeon_encoder_primary_dac * |
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516 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
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1321 | serge | 517 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
518 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
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1117 | serge | 519 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
520 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
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521 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
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522 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
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1179 | serge | 523 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
524 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
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1117 | serge | 525 | extern void |
526 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
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527 | extern void |
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528 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
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529 | extern void |
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530 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
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531 | extern void |
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532 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
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533 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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534 | u16 blue, int regno); |
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1221 | serge | 535 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
536 | u16 *blue, int regno); |
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1117 | serge | 537 | struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
538 | struct drm_mode_fb_cmd *mode_cmd, |
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539 | struct drm_gem_object *obj); |
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540 | |||
541 | int radeonfb_probe(struct drm_device *dev); |
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542 | |||
543 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
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544 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
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545 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
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546 | void radeon_atombios_init_crtc(struct drm_device *dev, |
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547 | struct radeon_crtc *radeon_crtc); |
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548 | void radeon_legacy_init_crtc(struct drm_device *dev, |
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549 | struct radeon_crtc *radeon_crtc); |
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550 | |||
551 | void radeon_get_clock_info(struct drm_device *dev); |
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552 | |||
553 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
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554 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
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555 | |||
556 | void radeon_enc_destroy(struct drm_encoder *encoder); |
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557 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
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558 | void radeon_combios_asic_init(struct drm_device *dev); |
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559 | extern int radeon_static_clocks_init(struct drm_device *dev); |
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1179 | serge | 560 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
561 | struct drm_display_mode *mode, |
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562 | struct drm_display_mode *adjusted_mode); |
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563 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
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1123 | serge | 564 | |
1179 | serge | 565 | /* legacy tv */ |
566 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
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567 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
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568 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
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569 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
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570 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
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571 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
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572 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
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573 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
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574 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
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575 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
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576 | struct drm_display_mode *mode, |
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577 | struct drm_display_mode *adjusted_mode); |
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1117 | serge | 578 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><> |