WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_legacy_encoders.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
		28	#include
1123	serge	29	#include "radeon.h"
		30	#include "atom.h"
2997	Serge	31	#include
		32	#ifdef CONFIG_PMAC_BACKLIGHT
		33	#include
		34	#endif
1123	serge	35
1179	serge	36	static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
1123	serge	37	{
		38	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	39	struct drm_encoder_helper_funcs *encoder_funcs;
1123	serge	40
1179	serge	41	encoder_funcs = encoder->helper_private;
		42	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
		43	radeon_encoder->active_device = 0;
1123	serge	44	}
		45
1963	serge	46	static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
1123	serge	47	{
		48	struct drm_device *dev = encoder->dev;
		49	struct radeon_device *rdev = dev->dev_private;
		50	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		51	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
		52	int panel_pwr_delay = 2000;
1403	serge	53	bool is_mac = false;
1963	serge	54	uint8_t backlight_level;
		55	DRM_DEBUG_KMS("\n");
1123	serge	56
1963	serge	57	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		58	backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
		59
1123	serge	60	if (radeon_encoder->enc_priv) {
		61	if (rdev->is_atom_bios) {
		62	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		63	panel_pwr_delay = lvds->panel_pwr_delay;
1963	serge	64	if (lvds->bl_dev)
		65	backlight_level = lvds->backlight_level;
1123	serge	66	} else {
		67	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		68	panel_pwr_delay = lvds->panel_pwr_delay;
1963	serge	69	if (lvds->bl_dev)
		70	backlight_level = lvds->backlight_level;
1123	serge	71	}
		72	}
		73
1403	serge	74	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
		75	* Taken from radeonfb.
		76	*/
		77	if ((rdev->mode_info.connector_table == CT_IBOOK) \|\|
		78	(rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) \|\|
		79	(rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) \|\|
		80	(rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
		81	is_mac = true;
		82
1123	serge	83	switch (mode) {
		84	case DRM_MODE_DPMS_ON:
		85	disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
		86	disp_pwr_man \|= RADEON_AUTO_PWRUP_EN;
		87	WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
		88	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		89	lvds_pll_cntl \|= RADEON_LVDS_PLL_EN;
		90	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
2997	Serge	91	mdelay(1);
1123	serge	92
		93	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		94	lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
		95	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		96
1963	serge	97	lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS \|
		98	RADEON_LVDS_BL_MOD_LEVEL_MASK);
		99	lvds_gen_cntl \|= (RADEON_LVDS_ON \| RADEON_LVDS_EN \|
		100	RADEON_LVDS_DIGON \| RADEON_LVDS_BLON \|
		101	(backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
1403	serge	102	if (is_mac)
		103	lvds_gen_cntl \|= RADEON_LVDS_BL_MOD_EN;
2997	Serge	104	mdelay(panel_pwr_delay);
1123	serge	105	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		106	break;
		107	case DRM_MODE_DPMS_STANDBY:
		108	case DRM_MODE_DPMS_SUSPEND:
		109	case DRM_MODE_DPMS_OFF:
		110	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		111	WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
		112	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
1403	serge	113	if (is_mac) {
		114	lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
		115	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		116	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_EN);
		117	} else {
		118	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
1123	serge	119	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_BLON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON);
1403	serge	120	}
2997	Serge	121	mdelay(panel_pwr_delay);
1123	serge	122	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		123	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
2997	Serge	124	mdelay(panel_pwr_delay);
1123	serge	125	break;
		126	}
		127
		128	if (rdev->is_atom_bios)
		129	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		130	else
		131	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	132
1123	serge	133	}
		134
1963	serge	135	static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
		136	{
		137	struct radeon_device *rdev = encoder->dev->dev_private;
		138	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		139	DRM_DEBUG("\n");
		140
		141	if (radeon_encoder->enc_priv) {
		142	if (rdev->is_atom_bios) {
		143	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		144	lvds->dpms_mode = mode;
		145	} else {
		146	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		147	lvds->dpms_mode = mode;
		148	}
		149	}
		150
		151	radeon_legacy_lvds_update(encoder, mode);
		152	}
		153
1123	serge	154	static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
		155	{
		156	struct radeon_device *rdev = encoder->dev->dev_private;
		157
		158	if (rdev->is_atom_bios)
		159	radeon_atom_output_lock(encoder, true);
		160	else
		161	radeon_combios_output_lock(encoder, true);
		162	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
		163	}
		164
		165	static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
		166	{
		167	struct radeon_device *rdev = encoder->dev->dev_private;
		168
		169	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
		170	if (rdev->is_atom_bios)
		171	radeon_atom_output_lock(encoder, false);
		172	else
		173	radeon_combios_output_lock(encoder, false);
		174	}
		175
		176	static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
		177	struct drm_display_mode *mode,
		178	struct drm_display_mode *adjusted_mode)
		179	{
		180	struct drm_device *dev = encoder->dev;
		181	struct radeon_device *rdev = dev->dev_private;
		182	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		183	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		184	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
		185
1963	serge	186	DRM_DEBUG_KMS("\n");
1123	serge	187
		188	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		189	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
		190
		191	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1321	serge	192	if (rdev->is_atom_bios) {
		193	/* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
		194	* need to call that on resume to set up the reg properly.
		195	*/
		196	radeon_encoder->pixel_clock = adjusted_mode->clock;
		197	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		198	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		199	} else {
1123	serge	200	struct radeon_encoder_lvds lvds = (struct radeon_encoder_lvds )radeon_encoder->enc_priv;
		201	if (lvds) {
1963	serge	202	DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
1123	serge	203	lvds_gen_cntl = lvds->lvds_gen_cntl;
		204	lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		205	(0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		206	lvds_ss_gen_cntl \|= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		207	(lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		208	} else
		209	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1321	serge	210	}
1123	serge	211	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		212	lvds_gen_cntl &= ~(RADEON_LVDS_ON \|
		213	RADEON_LVDS_BLON \|
		214	RADEON_LVDS_EN \|
		215	RADEON_LVDS_RST_FM);
		216
		217	if (ASIC_IS_R300(rdev))
		218	lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
		219
		220	if (radeon_crtc->crtc_id == 0) {
		221	if (ASIC_IS_R300(rdev)) {
1179	serge	222	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	223	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_RMX;
		224	} else
		225	lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
		226	} else {
		227	if (ASIC_IS_R300(rdev))
		228	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_CRTC2;
		229	else
		230	lvds_gen_cntl \|= RADEON_LVDS_SEL_CRTC2;
		231	}
		232
		233	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		234	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		235	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
		236
		237	if (rdev->family == CHIP_RV410)
		238	WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
		239
		240	if (rdev->is_atom_bios)
		241	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		242	else
		243	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		244	}
		245
1321	serge	246	static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
2997	Serge	247	const struct drm_display_mode *mode,
1123	serge	248	struct drm_display_mode *adjusted_mode)
		249	{
		250	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		251
1268	serge	252	/* set the active encoder to connector routing */
		253	radeon_encoder_set_active_device(encoder);
1123	serge	254	drm_mode_set_crtcinfo(adjusted_mode, 0);
		255
1321	serge	256	/* get the native mode for LVDS */
1963	serge	257	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
		258	radeon_panel_mode_fixup(encoder, adjusted_mode);
1123	serge	259
		260	return true;
		261	}
		262
		263	static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
		264	.dpms = radeon_legacy_lvds_dpms,
1321	serge	265	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	266	.prepare = radeon_legacy_lvds_prepare,
		267	.mode_set = radeon_legacy_lvds_mode_set,
		268	.commit = radeon_legacy_lvds_commit,
1179	serge	269	.disable = radeon_legacy_encoder_disable,
1123	serge	270	};
		271
2997	Serge	272	u8
		273	radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
		274	{
		275	struct drm_device *dev = radeon_encoder->base.dev;
		276	struct radeon_device *rdev = dev->dev_private;
		277	u8 backlight_level;
1123	serge	278
2997	Serge	279	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
		280	RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
1963	serge	281
2997	Serge	282	return backlight_level;
		283	}
1963	serge	284
2997	Serge	285	void
		286	radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
		287	{
		288	struct drm_device *dev = radeon_encoder->base.dev;
		289	struct radeon_device *rdev = dev->dev_private;
		290	int dpms_mode = DRM_MODE_DPMS_ON;
		291
		292	if (radeon_encoder->enc_priv) {
		293	if (rdev->is_atom_bios) {
		294	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		295	if (lvds->backlight_level > 0)
		296	dpms_mode = lvds->dpms_mode;
		297	else
		298	dpms_mode = DRM_MODE_DPMS_OFF;
		299	lvds->backlight_level = level;
		300	} else {
		301	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		302	if (lvds->backlight_level > 0)
		303	dpms_mode = lvds->dpms_mode;
		304	else
		305	dpms_mode = DRM_MODE_DPMS_OFF;
		306	lvds->backlight_level = level;
		307	}
		308	}
		309
		310	radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
		311	}
		312
		313	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
		314
1963	serge	315	static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
		316	{
		317	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		318	uint8_t level;
		319
		320	/* Convert brightness to hardware level */
		321	if (bd->props.brightness < 0)
		322	level = 0;
2997	Serge	323	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
		324	level = RADEON_MAX_BL_LEVEL;
1963	serge	325	else
		326	level = bd->props.brightness;
		327
		328	if (pdata->negative)
2997	Serge	329	level = RADEON_MAX_BL_LEVEL - level;
1963	serge	330
		331	return level;
		332	}
		333
		334	static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
		335	{
		336	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		337	struct radeon_encoder *radeon_encoder = pdata->encoder;
		338
2997	Serge	339	radeon_legacy_set_backlight_level(radeon_encoder,
		340	radeon_legacy_lvds_level(bd));
1963	serge	341
		342	return 0;
		343	}
		344
		345	static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
		346	{
		347	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		348	struct radeon_encoder *radeon_encoder = pdata->encoder;
		349	struct drm_device *dev = radeon_encoder->base.dev;
		350	struct radeon_device *rdev = dev->dev_private;
		351	uint8_t backlight_level;
		352
		353	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
		354	RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
		355
2997	Serge	356	return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
1963	serge	357	}
		358
		359	static const struct backlight_ops radeon_backlight_ops = {
		360	.get_brightness = radeon_legacy_backlight_get_brightness,
		361	.update_status = radeon_legacy_backlight_update_status,
		362	};
		363
		364	void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
		365	struct drm_connector *drm_connector)
		366	{
		367	struct drm_device *dev = radeon_encoder->base.dev;
		368	struct radeon_device *rdev = dev->dev_private;
		369	struct backlight_device *bd;
		370	struct backlight_properties props;
		371	struct radeon_backlight_privdata *pdata;
		372	uint8_t backlight_level;
2997	Serge	373	char bl_name[16];
1963	serge	374
		375	if (!radeon_encoder->enc_priv)
		376	return;
		377
		378	#ifdef CONFIG_PMAC_BACKLIGHT
		379	if (!pmac_has_backlight_type("ati") &&
		380	!pmac_has_backlight_type("mnca"))
		381	return;
		382	#endif
		383
		384	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
		385	if (!pdata) {
		386	DRM_ERROR("Memory allocation failed\n");
		387	goto error;
		388	}
		389
2997	Serge	390	memset(&props, 0, sizeof(props));
		391	props.max_brightness = RADEON_MAX_BL_LEVEL;
1963	serge	392	props.type = BACKLIGHT_RAW;
2997	Serge	393	snprintf(bl_name, sizeof(bl_name),
		394	"radeon_bl%d", dev->primary->index);
		395	bd = backlight_device_register(bl_name, &drm_connector->kdev,
1963	serge	396	pdata, &radeon_backlight_ops, &props);
		397	if (IS_ERR(bd)) {
		398	DRM_ERROR("Backlight registration failed\n");
		399	goto error;
		400	}
		401
		402	pdata->encoder = radeon_encoder;
		403
		404	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
		405	RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
		406
		407	/* First, try to detect backlight level sense based on the assumption
		408	* that firmware set it up at full brightness
		409	*/
		410	if (backlight_level == 0)
		411	pdata->negative = true;
		412	else if (backlight_level == 0xff)
		413	pdata->negative = false;
		414	else {
		415	/* XXX hack... maybe some day we can figure out in what direction
		416	* backlight should work on a given panel?
		417	*/
		418	pdata->negative = (rdev->family != CHIP_RV200 &&
		419	rdev->family != CHIP_RV250 &&
		420	rdev->family != CHIP_RV280 &&
		421	rdev->family != CHIP_RV350);
		422
		423	#ifdef CONFIG_PMAC_BACKLIGHT
		424	pdata->negative = (pdata->negative \|\|
		425	of_machine_is_compatible("PowerBook4,3") \|\|
		426	of_machine_is_compatible("PowerBook6,3") \|\|
		427	of_machine_is_compatible("PowerBook6,5"));
		428	#endif
		429	}
		430
		431	if (rdev->is_atom_bios) {
		432	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		433	lvds->bl_dev = bd;
		434	} else {
		435	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		436	lvds->bl_dev = bd;
		437	}
		438
		439	bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
		440	bd->props.power = FB_BLANK_UNBLANK;
		441	backlight_update_status(bd);
		442
		443	DRM_INFO("radeon legacy LVDS backlight initialized\n");
		444
		445	return;
		446
		447	error:
		448	kfree(pdata);
		449	return;
		450	}
		451
		452	static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
		453	{
		454	struct drm_device *dev = radeon_encoder->base.dev;
		455	struct radeon_device *rdev = dev->dev_private;
		456	struct backlight_device *bd = NULL;
		457
		458	if (!radeon_encoder->enc_priv)
		459	return;
		460
		461	if (rdev->is_atom_bios) {
		462	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		463	bd = lvds->bl_dev;
		464	lvds->bl_dev = NULL;
		465	} else {
		466	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		467	bd = lvds->bl_dev;
		468	lvds->bl_dev = NULL;
		469	}
		470
		471	if (bd) {
2997	Serge	472	struct radeon_backlight_privdata *pdata;
1963	serge	473
		474	pdata = bl_get_data(bd);
		475	backlight_device_unregister(bd);
		476	kfree(pdata);
		477
		478	DRM_INFO("radeon legacy LVDS backlight unloaded\n");
		479	}
		480	}
		481
		482	#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
		483
		484	void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
		485	{
		486	}
		487
		488	static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
		489	{
		490	}
		491
		492	#endif
		493
		494
		495	static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
		496	{
		497	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		498
		499	if (radeon_encoder->enc_priv) {
		500	radeon_legacy_backlight_exit(radeon_encoder);
		501	kfree(radeon_encoder->enc_priv);
		502	}
		503	drm_encoder_cleanup(encoder);
		504	kfree(radeon_encoder);
		505	}
		506
1123	serge	507	static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
1963	serge	508	.destroy = radeon_lvds_enc_destroy,
1123	serge	509	};
		510
		511	static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
		512	{
		513	struct drm_device *dev = encoder->dev;
		514	struct radeon_device *rdev = dev->dev_private;
		515	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		516	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
		517	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		518
1963	serge	519	DRM_DEBUG_KMS("\n");
1123	serge	520
		521	switch (mode) {
		522	case DRM_MODE_DPMS_ON:
		523	crtc_ext_cntl \|= RADEON_CRTC_CRT_ON;
		524	dac_cntl &= ~RADEON_DAC_PDWN;
		525	dac_macro_cntl &= ~(RADEON_DAC_PDWN_R \|
		526	RADEON_DAC_PDWN_G \|
		527	RADEON_DAC_PDWN_B);
		528	break;
		529	case DRM_MODE_DPMS_STANDBY:
		530	case DRM_MODE_DPMS_SUSPEND:
		531	case DRM_MODE_DPMS_OFF:
		532	crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
		533	dac_cntl \|= RADEON_DAC_PDWN;
		534	dac_macro_cntl \|= (RADEON_DAC_PDWN_R \|
		535	RADEON_DAC_PDWN_G \|
		536	RADEON_DAC_PDWN_B);
		537	break;
		538	}
		539
		540	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		541	WREG32(RADEON_DAC_CNTL, dac_cntl);
		542	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		543
		544	if (rdev->is_atom_bios)
		545	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		546	else
		547	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	548
1123	serge	549	}
		550
		551	static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
		552	{
		553	struct radeon_device *rdev = encoder->dev->dev_private;
		554
		555	if (rdev->is_atom_bios)
		556	radeon_atom_output_lock(encoder, true);
		557	else
		558	radeon_combios_output_lock(encoder, true);
		559	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		560	}
		561
		562	static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
		563	{
		564	struct radeon_device *rdev = encoder->dev->dev_private;
		565
		566	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		567
		568	if (rdev->is_atom_bios)
		569	radeon_atom_output_lock(encoder, false);
		570	else
		571	radeon_combios_output_lock(encoder, false);
		572	}
		573
		574	static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
		575	struct drm_display_mode *mode,
		576	struct drm_display_mode *adjusted_mode)
		577	{
		578	struct drm_device *dev = encoder->dev;
		579	struct radeon_device *rdev = dev->dev_private;
		580	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		581	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		582	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
		583
1963	serge	584	DRM_DEBUG_KMS("\n");
1123	serge	585
		586	if (radeon_crtc->crtc_id == 0) {
		587	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		588	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		589	~(RADEON_DISP_DAC_SOURCE_MASK);
		590	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		591	} else {
		592	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
		593	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		594	}
		595	} else {
		596	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		597	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		598	~(RADEON_DISP_DAC_SOURCE_MASK);
		599	disp_output_cntl \|= RADEON_DISP_DAC_SOURCE_CRTC2;
		600	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		601	} else {
		602	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC_CLK_SEL;
		603	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		604	}
		605	}
		606
		607	dac_cntl = (RADEON_DAC_MASK_ALL \|
		608	RADEON_DAC_VGA_ADR_EN \|
		609	/* TODO 6-bits */
		610	RADEON_DAC_8BIT_EN);
		611
		612	WREG32_P(RADEON_DAC_CNTL,
		613	dac_cntl,
		614	RADEON_DAC_RANGE_CNTL \|
		615	RADEON_DAC_BLANKING);
		616
		617	if (radeon_encoder->enc_priv) {
		618	struct radeon_encoder_primary_dac p_dac = (struct radeon_encoder_primary_dac )radeon_encoder->enc_priv;
		619	dac_macro_cntl = p_dac->ps2_pdac_adj;
		620	} else
		621	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		622	dac_macro_cntl \|= RADEON_DAC_PDWN_R \| RADEON_DAC_PDWN_G \| RADEON_DAC_PDWN_B;
		623	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		624
		625	if (rdev->is_atom_bios)
		626	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		627	else
		628	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		629	}
		630
		631	static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
		632	struct drm_connector *connector)
		633	{
		634	struct drm_device *dev = encoder->dev;
		635	struct radeon_device *rdev = dev->dev_private;
		636	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
		637	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
		638	enum drm_connector_status found = connector_status_disconnected;
		639	bool color = true;
		640
		641	/* save the regs we need */
		642	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
		643	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		644	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		645	dac_cntl = RREG32(RADEON_DAC_CNTL);
		646	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		647
		648	tmp = vclk_ecp_cntl &
		649	~(RADEON_PIXCLK_ALWAYS_ONb \| RADEON_PIXCLK_DAC_ALWAYS_ONb);
		650	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
		651
		652	tmp = crtc_ext_cntl \| RADEON_CRTC_CRT_ON;
		653	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
		654
		655	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN \|
		656	RADEON_DAC_FORCE_DATA_EN;
		657
		658	if (color)
		659	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		660	else
		661	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		662
		663	if (ASIC_IS_R300(rdev))
		664	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		665	else
		666	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		667
		668	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		669
		670	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK \| RADEON_DAC_PDWN);
		671	tmp \|= RADEON_DAC_RANGE_CNTL_PS2 \| RADEON_DAC_CMP_EN;
		672	WREG32(RADEON_DAC_CNTL, tmp);
		673
		674	tmp &= ~(RADEON_DAC_PDWN_R \|
		675	RADEON_DAC_PDWN_G \|
		676	RADEON_DAC_PDWN_B);
		677
		678	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
		679
2997	Serge	680	mdelay(2);
1123	serge	681
		682	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
		683	found = connector_status_connected;
		684
		685	/* restore the regs we used */
		686	WREG32(RADEON_DAC_CNTL, dac_cntl);
		687	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		688	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		689	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		690	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
		691
		692	return found;
		693	}
		694
		695	static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
		696	.dpms = radeon_legacy_primary_dac_dpms,
1321	serge	697	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	698	.prepare = radeon_legacy_primary_dac_prepare,
		699	.mode_set = radeon_legacy_primary_dac_mode_set,
		700	.commit = radeon_legacy_primary_dac_commit,
		701	.detect = radeon_legacy_primary_dac_detect,
1179	serge	702	.disable = radeon_legacy_encoder_disable,
1123	serge	703	};
		704
		705
		706	static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
		707	.destroy = radeon_enc_destroy,
		708	};
		709
		710	static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
		711	{
		712	struct drm_device *dev = encoder->dev;
		713	struct radeon_device *rdev = dev->dev_private;
		714	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
1963	serge	715	DRM_DEBUG_KMS("\n");
1123	serge	716
		717	switch (mode) {
		718	case DRM_MODE_DPMS_ON:
		719	fp_gen_cntl \|= (RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		720	break;
		721	case DRM_MODE_DPMS_STANDBY:
		722	case DRM_MODE_DPMS_SUSPEND:
		723	case DRM_MODE_DPMS_OFF:
		724	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		725	break;
		726	}
		727
		728	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		729
		730	if (rdev->is_atom_bios)
		731	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		732	else
		733	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	734
1123	serge	735	}
		736
		737	static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
		738	{
		739	struct radeon_device *rdev = encoder->dev->dev_private;
		740
		741	if (rdev->is_atom_bios)
		742	radeon_atom_output_lock(encoder, true);
		743	else
		744	radeon_combios_output_lock(encoder, true);
		745	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
		746	}
		747
		748	static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
		749	{
		750	struct radeon_device *rdev = encoder->dev->dev_private;
		751
		752	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
		753
		754	if (rdev->is_atom_bios)
		755	radeon_atom_output_lock(encoder, true);
		756	else
		757	radeon_combios_output_lock(encoder, true);
		758	}
		759
		760	static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
		761	struct drm_display_mode *mode,
		762	struct drm_display_mode *adjusted_mode)
		763	{
		764	struct drm_device *dev = encoder->dev;
		765	struct radeon_device *rdev = dev->dev_private;
		766	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		767	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		768	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
		769	int i;
		770
1963	serge	771	DRM_DEBUG_KMS("\n");
1123	serge	772
		773	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
		774	tmp &= 0xfffff;
		775	if (rdev->family == CHIP_RV280) {
		776	/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
		777	tmp ^= (1 << 22);
		778	tmds_pll_cntl ^= (1 << 22);
		779	}
		780
		781	if (radeon_encoder->enc_priv) {
		782	struct radeon_encoder_int_tmds tmds = (struct radeon_encoder_int_tmds )radeon_encoder->enc_priv;
		783
		784	for (i = 0; i < 4; i++) {
		785	if (tmds->tmds_pll[i].freq == 0)
		786	break;
		787	if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
		788	tmp = tmds->tmds_pll[i].value ;
		789	break;
		790	}
		791	}
		792	}
		793
		794	if (ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV280)) {
		795	if (tmp & 0xfff00000)
		796	tmds_pll_cntl = tmp;
		797	else {
		798	tmds_pll_cntl &= 0xfff00000;
		799	tmds_pll_cntl \|= tmp;
		800	}
		801	} else
		802	tmds_pll_cntl = tmp;
		803
		804	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
		805	~(RADEON_TMDS_TRANSMITTER_PLLRST);
		806
		807	if (rdev->family == CHIP_R200 \|\|
		808	rdev->family == CHIP_R100 \|\|
		809	ASIC_IS_R300(rdev))
		810	tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
		811	else /* RV chips got this bit reversed */
		812	tmds_transmitter_cntl \|= RADEON_TMDS_TRANSMITTER_PLLEN;
		813
		814	fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) \|
		815	(RADEON_FP_CRTC_DONT_SHADOW_VPAR \|
		816	RADEON_FP_CRTC_DONT_SHADOW_HEND));
		817
		818	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		819
1268	serge	820	fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN \|
		821	RADEON_FP_DFP_SYNC_SEL \|
		822	RADEON_FP_CRT_SYNC_SEL \|
		823	RADEON_FP_CRTC_LOCK_8DOT \|
		824	RADEON_FP_USE_SHADOW_EN \|
		825	RADEON_FP_CRTC_USE_SHADOW_VEND \|
		826	RADEON_FP_CRT_SYNC_ALT);
		827
1123	serge	828	if (1) /* FIXME rgbBits == 8 */
		829	fp_gen_cntl \|= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
		830	else
		831	fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
		832
		833	if (radeon_crtc->crtc_id == 0) {
		834	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		835	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1179	serge	836	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	837	fp_gen_cntl \|= R200_FP_SOURCE_SEL_RMX;
		838	else
		839	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC1;
		840	} else
1268	serge	841	fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
1123	serge	842	} else {
		843	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		844	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
		845	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC2;
		846	} else
		847	fp_gen_cntl \|= RADEON_FP_SEL_CRTC2;
		848	}
		849
		850	WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
		851	WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
		852	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		853
		854	if (rdev->is_atom_bios)
		855	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		856	else
		857	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		858	}
		859
		860	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
		861	.dpms = radeon_legacy_tmds_int_dpms,
1321	serge	862	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	863	.prepare = radeon_legacy_tmds_int_prepare,
		864	.mode_set = radeon_legacy_tmds_int_mode_set,
		865	.commit = radeon_legacy_tmds_int_commit,
1179	serge	866	.disable = radeon_legacy_encoder_disable,
1123	serge	867	};
		868
		869
		870	static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
		871	.destroy = radeon_enc_destroy,
		872	};
		873
		874	static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
		875	{
		876	struct drm_device *dev = encoder->dev;
		877	struct radeon_device *rdev = dev->dev_private;
		878	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1963	serge	879	DRM_DEBUG_KMS("\n");
1123	serge	880
		881	switch (mode) {
		882	case DRM_MODE_DPMS_ON:
		883	fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
		884	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		885	break;
		886	case DRM_MODE_DPMS_STANDBY:
		887	case DRM_MODE_DPMS_SUSPEND:
		888	case DRM_MODE_DPMS_OFF:
		889	fp2_gen_cntl \|= RADEON_FP2_BLANK_EN;
		890	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		891	break;
		892	}
		893
		894	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		895
		896	if (rdev->is_atom_bios)
		897	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		898	else
		899	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	900
1123	serge	901	}
		902
		903	static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
		904	{
		905	struct radeon_device *rdev = encoder->dev->dev_private;
		906
		907	if (rdev->is_atom_bios)
		908	radeon_atom_output_lock(encoder, true);
		909	else
		910	radeon_combios_output_lock(encoder, true);
		911	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
		912	}
		913
		914	static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
		915	{
		916	struct radeon_device *rdev = encoder->dev->dev_private;
		917	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
		918
		919	if (rdev->is_atom_bios)
		920	radeon_atom_output_lock(encoder, false);
		921	else
		922	radeon_combios_output_lock(encoder, false);
		923	}
		924
		925	static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
		926	struct drm_display_mode *mode,
		927	struct drm_display_mode *adjusted_mode)
		928	{
		929	struct drm_device *dev = encoder->dev;
		930	struct radeon_device *rdev = dev->dev_private;
		931	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		932	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		933	uint32_t fp2_gen_cntl;
		934
1963	serge	935	DRM_DEBUG_KMS("\n");
1123	serge	936
		937	if (rdev->is_atom_bios) {
		938	radeon_encoder->pixel_clock = adjusted_mode->clock;
1963	serge	939	atombios_dvo_setup(encoder, ATOM_ENABLE);
1123	serge	940	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		941	} else {
		942	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		943
		944	if (1) /* FIXME rgbBits == 8 */
		945	fp2_gen_cntl \|= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
		946	else
		947	fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
		948
		949	fp2_gen_cntl &= ~(RADEON_FP2_ON \|
		950	RADEON_FP2_DVO_EN \|
		951	RADEON_FP2_DVO_RATE_SEL_SDR);
		952
		953	/* XXX: these are oem specific */
		954	if (ASIC_IS_R300(rdev)) {
		955	if ((dev->pdev->device == 0x4850) &&
		956	(dev->pdev->subsystem_vendor == 0x1028) &&
		957	(dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
		958	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
		959	else
		960	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;
		961
		962	/*if (mode->clock > 165000)
		963	fp2_gen_cntl \|= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
		964	}
1321	serge	965	if (!radeon_combios_external_tmds_setup(encoder))
		966	radeon_external_tmds_setup(encoder);
1123	serge	967	}
		968
		969	if (radeon_crtc->crtc_id == 0) {
		970	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		971	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1179	serge	972	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	973	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_RMX;
		974	else
		975	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC1;
		976	} else
		977	fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
		978	} else {
		979	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		980	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
		981	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		982	} else
		983	fp2_gen_cntl \|= RADEON_FP2_SRC_SEL_CRTC2;
		984	}
		985
		986	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		987
		988	if (rdev->is_atom_bios)
		989	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		990	else
		991	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		992	}
		993
1321	serge	994	static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
		995	{
		996	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2997	Serge	997	/* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1321	serge	998	kfree(radeon_encoder->enc_priv);
		999	drm_encoder_cleanup(encoder);
		1000	kfree(radeon_encoder);
		1001	}
		1002
1123	serge	1003	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
		1004	.dpms = radeon_legacy_tmds_ext_dpms,
1321	serge	1005	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	1006	.prepare = radeon_legacy_tmds_ext_prepare,
		1007	.mode_set = radeon_legacy_tmds_ext_mode_set,
		1008	.commit = radeon_legacy_tmds_ext_commit,
1179	serge	1009	.disable = radeon_legacy_encoder_disable,
1123	serge	1010	};
		1011
		1012
		1013	static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1321	serge	1014	.destroy = radeon_ext_tmds_enc_destroy,
1123	serge	1015	};
		1016
		1017	static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
		1018	{
		1019	struct drm_device *dev = encoder->dev;
		1020	struct radeon_device *rdev = dev->dev_private;
1179	serge	1021	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1123	serge	1022	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1179	serge	1023	uint32_t tv_master_cntl = 0;
		1024	bool is_tv;
1963	serge	1025	DRM_DEBUG_KMS("\n");
1123	serge	1026
1179	serge	1027	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
		1028
1123	serge	1029	if (rdev->family == CHIP_R200)
		1030	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		1031	else {
1179	serge	1032	if (is_tv)
		1033	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		1034	else
1123	serge	1035	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1036	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1037	}
		1038
		1039	switch (mode) {
		1040	case DRM_MODE_DPMS_ON:
		1041	if (rdev->family == CHIP_R200) {
		1042	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		1043	} else {
1179	serge	1044	if (is_tv)
		1045	tv_master_cntl \|= RADEON_TV_ON;
		1046	else
1123	serge	1047	crtc2_gen_cntl \|= RADEON_CRTC2_CRT2_ON;
1179	serge	1048
1123	serge	1049	if (rdev->family == CHIP_R420 \|\|
		1050	rdev->family == CHIP_R423 \|\|
		1051	rdev->family == CHIP_RV410)
		1052	tv_dac_cntl &= ~(R420_TV_DAC_RDACPD \|
		1053	R420_TV_DAC_GDACPD \|
		1054	R420_TV_DAC_BDACPD \|
		1055	RADEON_TV_DAC_BGSLEEP);
		1056	else
		1057	tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD \|
		1058	RADEON_TV_DAC_GDACPD \|
		1059	RADEON_TV_DAC_BDACPD \|
		1060	RADEON_TV_DAC_BGSLEEP);
		1061	}
		1062	break;
		1063	case DRM_MODE_DPMS_STANDBY:
		1064	case DRM_MODE_DPMS_SUSPEND:
		1065	case DRM_MODE_DPMS_OFF:
		1066	if (rdev->family == CHIP_R200)
		1067	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		1068	else {
1179	serge	1069	if (is_tv)
		1070	tv_master_cntl &= ~RADEON_TV_ON;
		1071	else
1123	serge	1072	crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1179	serge	1073
1123	serge	1074	if (rdev->family == CHIP_R420 \|\|
		1075	rdev->family == CHIP_R423 \|\|
		1076	rdev->family == CHIP_RV410)
		1077	tv_dac_cntl \|= (R420_TV_DAC_RDACPD \|
		1078	R420_TV_DAC_GDACPD \|
		1079	R420_TV_DAC_BDACPD \|
		1080	RADEON_TV_DAC_BGSLEEP);
		1081	else
		1082	tv_dac_cntl \|= (RADEON_TV_DAC_RDACPD \|
		1083	RADEON_TV_DAC_GDACPD \|
		1084	RADEON_TV_DAC_BDACPD \|
		1085	RADEON_TV_DAC_BGSLEEP);
		1086	}
		1087	break;
		1088	}
		1089
		1090	if (rdev->family == CHIP_R200) {
		1091	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		1092	} else {
1179	serge	1093	if (is_tv)
		1094	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		1095	else
1123	serge	1096	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1097	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1098	}
		1099
		1100	if (rdev->is_atom_bios)
		1101	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		1102	else
		1103	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	1104
1123	serge	1105	}
		1106
		1107	static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
		1108	{
		1109	struct radeon_device *rdev = encoder->dev->dev_private;
		1110
		1111	if (rdev->is_atom_bios)
		1112	radeon_atom_output_lock(encoder, true);
		1113	else
		1114	radeon_combios_output_lock(encoder, true);
		1115	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		1116	}
		1117
		1118	static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
		1119	{
		1120	struct radeon_device *rdev = encoder->dev->dev_private;
		1121
		1122	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		1123
		1124	if (rdev->is_atom_bios)
		1125	radeon_atom_output_lock(encoder, true);
		1126	else
		1127	radeon_combios_output_lock(encoder, true);
		1128	}
		1129
		1130	static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
		1131	struct drm_display_mode *mode,
		1132	struct drm_display_mode *adjusted_mode)
		1133	{
		1134	struct drm_device *dev = encoder->dev;
		1135	struct radeon_device *rdev = dev->dev_private;
		1136	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1137	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	1138	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	1139	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1179	serge	1140	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
		1141	bool is_tv = false;
1123	serge	1142
1963	serge	1143	DRM_DEBUG_KMS("\n");
1123	serge	1144
1179	serge	1145	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1123	serge	1146
		1147	if (rdev->family != CHIP_R200) {
		1148	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1149	if (rdev->family == CHIP_R420 \|\|
		1150	rdev->family == CHIP_R423 \|\|
		1151	rdev->family == CHIP_RV410) {
		1152	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		1153	RADEON_TV_DAC_BGADJ_MASK \|
		1154	R420_TV_DAC_DACADJ_MASK \|
		1155	R420_TV_DAC_RDACPD \|
		1156	R420_TV_DAC_GDACPD \|
1221	serge	1157	R420_TV_DAC_BDACPD \|
1123	serge	1158	R420_TV_DAC_TVENABLE);
		1159	} else {
		1160	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		1161	RADEON_TV_DAC_BGADJ_MASK \|
		1162	RADEON_TV_DAC_DACADJ_MASK \|
		1163	RADEON_TV_DAC_RDACPD \|
		1164	RADEON_TV_DAC_GDACPD \|
1221	serge	1165	RADEON_TV_DAC_BDACPD);
1123	serge	1166	}
		1167
1963	serge	1168	tv_dac_cntl \|= RADEON_TV_DAC_NBLANK \| RADEON_TV_DAC_NHOLD;
		1169
		1170	if (is_tv) {
		1171	if (tv_dac->tv_std == TV_STD_NTSC \|\|
		1172	tv_dac->tv_std == TV_STD_NTSC_J \|\|
		1173	tv_dac->tv_std == TV_STD_PAL_M \|\|
		1174	tv_dac->tv_std == TV_STD_PAL_60)
		1175	tv_dac_cntl \|= tv_dac->ntsc_tvdac_adj;
		1176	else
		1177	tv_dac_cntl \|= tv_dac->pal_tvdac_adj;
		1178
		1179	if (tv_dac->tv_std == TV_STD_NTSC \|\|
		1180	tv_dac->tv_std == TV_STD_NTSC_J)
		1181	tv_dac_cntl \|= RADEON_TV_DAC_STD_NTSC;
		1182	else
		1183	tv_dac_cntl \|= RADEON_TV_DAC_STD_PAL;
		1184	} else
		1185	tv_dac_cntl \|= (RADEON_TV_DAC_STD_PS2 \|
1123	serge	1186	tv_dac->ps2_tvdac_adj);
		1187
		1188	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1189	}
		1190
		1191	if (ASIC_IS_R300(rdev)) {
		1192	gpiopad_a = RREG32(RADEON_GPIOPAD_A) \| 1;
		1193	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1963	serge	1194	} else if (rdev->family != CHIP_R200)
		1195	disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1196	else if (rdev->family == CHIP_R200)
		1197	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1179	serge	1198
1963	serge	1199	if (rdev->family >= CHIP_R200)
1179	serge	1200	disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1123	serge	1201
1179	serge	1202	if (is_tv) {
		1203	uint32_t dac_cntl;
		1204
		1205	dac_cntl = RREG32(RADEON_DAC_CNTL);
		1206	dac_cntl &= ~RADEON_DAC_TVO_EN;
		1207	WREG32(RADEON_DAC_CNTL, dac_cntl);
		1208
		1209	if (ASIC_IS_R300(rdev))
		1210	gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
		1211
		1212	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
		1213	if (radeon_crtc->crtc_id == 0) {
		1214	if (ASIC_IS_R300(rdev)) {
		1215	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1216	disp_output_cntl \|= (RADEON_DISP_TVDAC_SOURCE_CRTC \|
		1217	RADEON_DISP_TV_SOURCE_CRTC);
		1218	}
		1219	if (rdev->family >= CHIP_R200) {
		1220	disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
		1221	} else {
		1222	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1223	}
		1224	} else {
		1225	if (ASIC_IS_R300(rdev)) {
		1226	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1227	disp_output_cntl \|= RADEON_DISP_TV_SOURCE_CRTC;
		1228	}
		1229	if (rdev->family >= CHIP_R200) {
		1230	disp_tv_out_cntl \|= RADEON_DISP_TV_PATH_SRC_CRTC2;
		1231	} else {
		1232	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		1233	}
		1234	}
		1235	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		1236	} else {
		1237
1123	serge	1238	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC2_CLK_SEL;
		1239
		1240	if (radeon_crtc->crtc_id == 0) {
		1241	if (ASIC_IS_R300(rdev)) {
		1242	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1243	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC;
		1244	} else if (rdev->family == CHIP_R200) {
		1245	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		1246	RADEON_FP2_DVO_RATE_SEL_SDR);
		1247	} else
		1248	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1249	} else {
		1250	if (ASIC_IS_R300(rdev)) {
		1251	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1252	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1253	} else if (rdev->family == CHIP_R200) {
		1254	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		1255	RADEON_FP2_DVO_RATE_SEL_SDR);
		1256	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		1257	} else
		1258	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		1259	}
		1260	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1179	serge	1261	}
1123	serge	1262
		1263	if (ASIC_IS_R300(rdev)) {
		1264	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1179	serge	1265	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1963	serge	1266	} else if (rdev->family != CHIP_R200)
		1267	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1268	else if (rdev->family == CHIP_R200)
		1269	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1179	serge	1270
		1271	if (rdev->family >= CHIP_R200)
		1272	WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1123	serge	1273
1179	serge	1274	if (is_tv)
		1275	radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
		1276
1123	serge	1277	if (rdev->is_atom_bios)
		1278	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1279	else
		1280	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1281
		1282	}
		1283
1179	serge	1284	static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
		1285	struct drm_connector *connector)
		1286	{
		1287	struct drm_device *dev = encoder->dev;
		1288	struct radeon_device *rdev = dev->dev_private;
		1289	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1290	uint32_t disp_output_cntl, gpiopad_a, tmp;
		1291	bool found = false;
		1292
		1293	/* save regs needed */
		1294	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
		1295	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1296	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1297	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1298	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1299	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1300
		1301	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
		1302
		1303	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
		1304
		1305	WREG32(RADEON_CRTC2_GEN_CNTL,
		1306	RADEON_CRTC2_CRT2_ON \| RADEON_CRTC2_VSYNC_TRISTAT);
		1307
		1308	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1309	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1310	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1311
		1312	WREG32(RADEON_DAC_EXT_CNTL,
		1313	RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1314	RADEON_DAC2_FORCE_DATA_EN \|
		1315	RADEON_DAC_FORCE_DATA_SEL_RGB \|
		1316	(0xec << RADEON_DAC_FORCE_DATA_SHIFT));
		1317
		1318	WREG32(RADEON_TV_DAC_CNTL,
		1319	RADEON_TV_DAC_STD_NTSC \|
		1320	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1321	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1322
		1323	RREG32(RADEON_TV_DAC_CNTL);
		1324	mdelay(4);
		1325
		1326	WREG32(RADEON_TV_DAC_CNTL,
		1327	RADEON_TV_DAC_NBLANK \|
		1328	RADEON_TV_DAC_NHOLD \|
		1329	RADEON_TV_MONITOR_DETECT_EN \|
		1330	RADEON_TV_DAC_STD_NTSC \|
		1331	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1332	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1333
		1334	RREG32(RADEON_TV_DAC_CNTL);
		1335	mdelay(6);
		1336
		1337	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1338	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
		1339	found = true;
1963	serge	1340	DRM_DEBUG_KMS("S-video TV connection detected\n");
1179	serge	1341	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1342	found = true;
1963	serge	1343	DRM_DEBUG_KMS("Composite TV connection detected\n");
1179	serge	1344	}
		1345
		1346	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1347	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1348	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1349	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1350	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1351	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1352	return found;
		1353	}
		1354
		1355	static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
		1356	struct drm_connector *connector)
		1357	{
		1358	struct drm_device *dev = encoder->dev;
		1359	struct radeon_device *rdev = dev->dev_private;
		1360	uint32_t tv_dac_cntl, dac_cntl2;
		1361	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
		1362	bool found = false;
		1363
		1364	if (ASIC_IS_R300(rdev))
		1365	return r300_legacy_tv_detect(encoder, connector);
		1366
		1367	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1368	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		1369	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1370	config_cntl = RREG32(RADEON_CONFIG_CNTL);
		1371	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
		1372
		1373	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
		1374	WREG32(RADEON_DAC_CNTL2, tmp);
		1375
		1376	tmp = tv_master_cntl \| RADEON_TV_ON;
		1377	tmp &= ~(RADEON_TV_ASYNC_RST \|
		1378	RADEON_RESTART_PHASE_FIX \|
		1379	RADEON_CRT_FIFO_CE_EN \|
		1380	RADEON_TV_FIFO_CE_EN \|
		1381	RADEON_RE_SYNC_NOW_SEL_MASK);
		1382	tmp \|= RADEON_TV_FIFO_ASYNC_RST \| RADEON_CRT_ASYNC_RST;
		1383	WREG32(RADEON_TV_MASTER_CNTL, tmp);
		1384
		1385	tmp = RADEON_TV_DAC_NBLANK \| RADEON_TV_DAC_NHOLD \|
		1386	RADEON_TV_MONITOR_DETECT_EN \| RADEON_TV_DAC_STD_NTSC \|
		1387	(8 << RADEON_TV_DAC_BGADJ_SHIFT);
		1388
		1389	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
		1390	tmp \|= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
		1391	else
		1392	tmp \|= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
		1393	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1394
		1395	tmp = RADEON_C_GRN_EN \| RADEON_CMP_BLU_EN \|
		1396	RADEON_RED_MX_FORCE_DAC_DATA \|
		1397	RADEON_GRN_MX_FORCE_DAC_DATA \|
		1398	RADEON_BLU_MX_FORCE_DAC_DATA \|
		1399	(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
		1400	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
		1401
		1402	mdelay(3);
		1403	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1404	if (tmp & RADEON_TV_DAC_GDACDET) {
		1405	found = true;
1963	serge	1406	DRM_DEBUG_KMS("S-video TV connection detected\n");
1179	serge	1407	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1408	found = true;
1963	serge	1409	DRM_DEBUG_KMS("Composite TV connection detected\n");
1179	serge	1410	}
		1411
		1412	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
		1413	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1414	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		1415	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1416	return found;
		1417	}
		1418
1123	serge	1419	static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
		1420	struct drm_connector *connector)
		1421	{
		1422	struct drm_device *dev = encoder->dev;
		1423	struct radeon_device *rdev = dev->dev_private;
		1424	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1425	uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
		1426	enum drm_connector_status found = connector_status_disconnected;
1179	serge	1427	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1428	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	1429	bool color = true;
1963	serge	1430	struct drm_crtc *crtc;
1123	serge	1431
1963	serge	1432	/* find out if crtc2 is in use or if this encoder is using it */
		1433	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		1434	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1435	if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
		1436	if (encoder->crtc != crtc) {
		1437	return connector_status_disconnected;
		1438	}
		1439	}
		1440	}
		1441
1179	serge	1442	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO \|\|
		1443	connector->connector_type == DRM_MODE_CONNECTOR_Composite \|\|
		1444	connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
		1445	bool tv_detect;
1123	serge	1446
1179	serge	1447	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
		1448	return connector_status_disconnected;
		1449
		1450	tv_detect = radeon_legacy_tv_detect(encoder, connector);
		1451	if (tv_detect && tv_dac)
		1452	found = connector_status_connected;
		1453	return found;
		1454	}
		1455
		1456	/* don't probe if the encoder is being used for something else not CRT related */
		1457	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
		1458	DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
		1459	return connector_status_disconnected;
		1460	}
		1461
1123	serge	1462	/* save the regs we need */
		1463	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		1464	gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
		1465	disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
		1466	disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
		1467	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1468	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1469	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1470	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1471
		1472	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
		1473	\| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
		1474	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
		1475
		1476	if (ASIC_IS_R300(rdev))
		1477	WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
		1478
		1479	tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
		1480	tmp \|= RADEON_CRTC2_CRT2_ON \|
		1481	(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
		1482
		1483	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		1484
		1485	if (ASIC_IS_R300(rdev)) {
		1486	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1487	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1488	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1489	} else {
		1490	tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
		1491	WREG32(RADEON_DISP_HW_DEBUG, tmp);
		1492	}
		1493
		1494	tmp = RADEON_TV_DAC_NBLANK \|
		1495	RADEON_TV_DAC_NHOLD \|
		1496	RADEON_TV_MONITOR_DETECT_EN \|
		1497	RADEON_TV_DAC_STD_PS2;
		1498
		1499	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1500
		1501	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1502	RADEON_DAC2_FORCE_DATA_EN;
		1503
		1504	if (color)
		1505	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		1506	else
		1507	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		1508
		1509	if (ASIC_IS_R300(rdev))
		1510	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		1511	else
		1512	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		1513
		1514	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		1515
		1516	tmp = dac_cntl2 \| RADEON_DAC2_DAC2_CLK_SEL \| RADEON_DAC2_CMP_EN;
		1517	WREG32(RADEON_DAC_CNTL2, tmp);
		1518
2997	Serge	1519	mdelay(10);
1123	serge	1520
		1521	if (ASIC_IS_R300(rdev)) {
		1522	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
		1523	found = connector_status_connected;
		1524	} else {
		1525	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
		1526	found = connector_status_connected;
		1527	}
		1528
		1529	/* restore regs we used */
		1530	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1531	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1532	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1533	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1534
		1535	if (ASIC_IS_R300(rdev)) {
		1536	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1537	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1538	} else {
		1539	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1540	}
		1541	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		1542
1179	serge	1543	return found;
1123	serge	1544
		1545	}
		1546
		1547	static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
		1548	.dpms = radeon_legacy_tv_dac_dpms,
1321	serge	1549	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	1550	.prepare = radeon_legacy_tv_dac_prepare,
		1551	.mode_set = radeon_legacy_tv_dac_mode_set,
		1552	.commit = radeon_legacy_tv_dac_commit,
		1553	.detect = radeon_legacy_tv_dac_detect,
1179	serge	1554	.disable = radeon_legacy_encoder_disable,
1123	serge	1555	};
		1556
		1557
		1558	static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
		1559	.destroy = radeon_enc_destroy,
		1560	};
		1561
1179	serge	1562
		1563	static struct radeon_encoder_int_tmds radeon_legacy_get_tmds_info(struct radeon_encoder encoder)
		1564	{
		1565	struct drm_device *dev = encoder->base.dev;
		1566	struct radeon_device *rdev = dev->dev_private;
		1567	struct radeon_encoder_int_tmds *tmds = NULL;
		1568	bool ret;
		1569
		1570	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
		1571
		1572	if (!tmds)
		1573	return NULL;
		1574
		1575	if (rdev->is_atom_bios)
		1576	ret = radeon_atombios_get_tmds_info(encoder, tmds);
		1577	else
		1578	ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
		1579
		1580	if (ret == false)
		1581	radeon_legacy_get_tmds_info_from_table(encoder, tmds);
		1582
		1583	return tmds;
		1584	}
		1585
1321	serge	1586	static struct radeon_encoder_ext_tmds radeon_legacy_get_ext_tmds_info(struct radeon_encoder encoder)
		1587	{
		1588	struct drm_device *dev = encoder->base.dev;
		1589	struct radeon_device *rdev = dev->dev_private;
		1590	struct radeon_encoder_ext_tmds *tmds = NULL;
		1591	bool ret;
		1592
		1593	if (rdev->is_atom_bios)
		1594	return NULL;
		1595
		1596	tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
		1597
		1598	if (!tmds)
		1599	return NULL;
		1600
		1601	ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
		1602
		1603	if (ret == false)
		1604	radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
		1605
		1606	return tmds;
		1607	}
		1608
1123	serge	1609	void
1963	serge	1610	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1123	serge	1611	{
		1612	struct radeon_device *rdev = dev->dev_private;
		1613	struct drm_encoder *encoder;
		1614	struct radeon_encoder *radeon_encoder;
		1615
		1616	/* see if we already added it */
		1617	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1618	radeon_encoder = to_radeon_encoder(encoder);
1963	serge	1619	if (radeon_encoder->encoder_enum == encoder_enum) {
1123	serge	1620	radeon_encoder->devices \|= supported_device;
		1621	return;
		1622	}
		1623
		1624	}
		1625
		1626	/* add a new one */
		1627	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1628	if (!radeon_encoder)
		1629	return;
		1630
		1631	encoder = &radeon_encoder->base;
1221	serge	1632	if (rdev->flags & RADEON_SINGLE_CRTC)
		1633	encoder->possible_crtcs = 0x1;
		1634	else
1123	serge	1635	encoder->possible_crtcs = 0x3;
		1636
		1637	radeon_encoder->enc_priv = NULL;
		1638
1963	serge	1639	radeon_encoder->encoder_enum = encoder_enum;
		1640	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1123	serge	1641	radeon_encoder->devices = supported_device;
1179	serge	1642	radeon_encoder->rmx_type = RMX_OFF;
1123	serge	1643
		1644	switch (radeon_encoder->encoder_id) {
		1645	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1179	serge	1646	encoder->possible_crtcs = 0x1;
1123	serge	1647	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1648	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
		1649	if (rdev->is_atom_bios)
		1650	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1651	else
		1652	radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
		1653	radeon_encoder->rmx_type = RMX_FULL;
		1654	break;
		1655	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1656	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1657	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1179	serge	1658	radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1123	serge	1659	break;
		1660	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1661	drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
		1662	drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
		1663	if (rdev->is_atom_bios)
		1664	radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
		1665	else
		1666	radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
		1667	break;
		1668	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1669	drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		1670	drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
		1671	if (rdev->is_atom_bios)
		1672	radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
		1673	else
		1674	radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
		1675	break;
		1676	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1677	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1678	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
		1679	if (!rdev->is_atom_bios)
1321	serge	1680	radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1123	serge	1681	break;
		1682	}
		1683	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_encoders.c – Rev 2997