Rev 1403 | Rev 1963 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * |
||
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
6 | * copy of this software and associated documentation files (the "Software"), |
||
7 | * to deal in the Software without restriction, including without limitation |
||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
9 | * and/or sell copies of the Software, and to permit persons to whom the |
||
10 | * Software is furnished to do so, subject to the following conditions: |
||
11 | * |
||
12 | * The above copyright notice and this permission notice shall be included in |
||
13 | * all copies or substantial portions of the Software. |
||
14 | * |
||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
21 | * OTHER DEALINGS IN THE SOFTWARE. |
||
22 | * |
||
23 | * Authors: Dave Airlie |
||
24 | * Alex Deucher |
||
25 | */ |
||
26 | #include "drmP.h" |
||
27 | #include "drm_crtc_helper.h" |
||
28 | #include "radeon_drm.h" |
||
29 | #include "radeon.h" |
||
30 | #include "atom.h" |
||
31 | |||
1179 | serge | 32 | static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) |
1123 | serge | 33 | { |
34 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1179 | serge | 35 | struct drm_encoder_helper_funcs *encoder_funcs; |
1123 | serge | 36 | |
1179 | serge | 37 | encoder_funcs = encoder->helper_private; |
38 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
||
39 | radeon_encoder->active_device = 0; |
||
1123 | serge | 40 | } |
41 | |||
42 | static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) |
||
43 | { |
||
44 | struct drm_device *dev = encoder->dev; |
||
45 | struct radeon_device *rdev = dev->dev_private; |
||
46 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
47 | uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; |
||
48 | int panel_pwr_delay = 2000; |
||
1403 | serge | 49 | bool is_mac = false; |
1123 | serge | 50 | DRM_DEBUG("\n"); |
51 | |||
52 | if (radeon_encoder->enc_priv) { |
||
53 | if (rdev->is_atom_bios) { |
||
54 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
||
55 | panel_pwr_delay = lvds->panel_pwr_delay; |
||
56 | } else { |
||
57 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
||
58 | panel_pwr_delay = lvds->panel_pwr_delay; |
||
59 | } |
||
60 | } |
||
61 | |||
1403 | serge | 62 | /* macs (and possibly some x86 oem systems?) wire up LVDS strangely |
63 | * Taken from radeonfb. |
||
64 | */ |
||
65 | if ((rdev->mode_info.connector_table == CT_IBOOK) || |
||
66 | (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || |
||
67 | (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || |
||
68 | (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) |
||
69 | is_mac = true; |
||
70 | |||
1123 | serge | 71 | switch (mode) { |
72 | case DRM_MODE_DPMS_ON: |
||
73 | disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); |
||
74 | disp_pwr_man |= RADEON_AUTO_PWRUP_EN; |
||
75 | WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); |
||
76 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
||
77 | lvds_pll_cntl |= RADEON_LVDS_PLL_EN; |
||
78 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
||
79 | udelay(1000); |
||
80 | |||
81 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
||
82 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; |
||
83 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
||
84 | |||
85 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
||
86 | lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); |
||
1403 | serge | 87 | if (is_mac) |
88 | lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; |
||
1123 | serge | 89 | lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); |
90 | udelay(panel_pwr_delay * 1000); |
||
91 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
||
92 | break; |
||
93 | case DRM_MODE_DPMS_STANDBY: |
||
94 | case DRM_MODE_DPMS_SUSPEND: |
||
95 | case DRM_MODE_DPMS_OFF: |
||
96 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
97 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); |
||
98 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
||
99 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
||
1403 | serge | 100 | if (is_mac) { |
101 | lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; |
||
102 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
||
103 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); |
||
104 | } else { |
||
105 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
||
1123 | serge | 106 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); |
1403 | serge | 107 | } |
1123 | serge | 108 | udelay(panel_pwr_delay * 1000); |
109 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
||
110 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
111 | break; |
||
112 | } |
||
113 | |||
114 | if (rdev->is_atom_bios) |
||
115 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
116 | else |
||
117 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 118 | |
119 | /* adjust pm to dpms change */ |
||
120 | radeon_pm_compute_clocks(rdev); |
||
1123 | serge | 121 | } |
122 | |||
123 | static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) |
||
124 | { |
||
125 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
126 | |||
127 | if (rdev->is_atom_bios) |
||
128 | radeon_atom_output_lock(encoder, true); |
||
129 | else |
||
130 | radeon_combios_output_lock(encoder, true); |
||
131 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
132 | } |
||
133 | |||
134 | static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) |
||
135 | { |
||
136 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
137 | |||
138 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); |
||
139 | if (rdev->is_atom_bios) |
||
140 | radeon_atom_output_lock(encoder, false); |
||
141 | else |
||
142 | radeon_combios_output_lock(encoder, false); |
||
143 | } |
||
144 | |||
145 | static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, |
||
146 | struct drm_display_mode *mode, |
||
147 | struct drm_display_mode *adjusted_mode) |
||
148 | { |
||
149 | struct drm_device *dev = encoder->dev; |
||
150 | struct radeon_device *rdev = dev->dev_private; |
||
151 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
152 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
153 | uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; |
||
154 | |||
155 | DRM_DEBUG("\n"); |
||
156 | |||
157 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
||
158 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; |
||
159 | |||
160 | lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
||
1321 | serge | 161 | if (rdev->is_atom_bios) { |
162 | /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl |
||
163 | * need to call that on resume to set up the reg properly. |
||
164 | */ |
||
165 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
||
166 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
||
167 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
||
168 | } else { |
||
1123 | serge | 169 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
170 | if (lvds) { |
||
171 | DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); |
||
172 | lvds_gen_cntl = lvds->lvds_gen_cntl; |
||
173 | lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
||
174 | (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
||
175 | lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
||
176 | (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
||
177 | } else |
||
178 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
||
1321 | serge | 179 | } |
1123 | serge | 180 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
181 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | |
||
182 | RADEON_LVDS_BLON | |
||
183 | RADEON_LVDS_EN | |
||
184 | RADEON_LVDS_RST_FM); |
||
185 | |||
186 | if (ASIC_IS_R300(rdev)) |
||
187 | lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); |
||
188 | |||
189 | if (radeon_crtc->crtc_id == 0) { |
||
190 | if (ASIC_IS_R300(rdev)) { |
||
1179 | serge | 191 | if (radeon_encoder->rmx_type != RMX_OFF) |
1123 | serge | 192 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; |
193 | } else |
||
194 | lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; |
||
195 | } else { |
||
196 | if (ASIC_IS_R300(rdev)) |
||
197 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; |
||
198 | else |
||
199 | lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; |
||
200 | } |
||
201 | |||
202 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
||
203 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
||
204 | WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); |
||
205 | |||
206 | if (rdev->family == CHIP_RV410) |
||
207 | WREG32(RADEON_CLOCK_CNTL_INDEX, 0); |
||
208 | |||
209 | if (rdev->is_atom_bios) |
||
210 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
211 | else |
||
212 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
213 | } |
||
214 | |||
1321 | serge | 215 | static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, |
1123 | serge | 216 | struct drm_display_mode *mode, |
217 | struct drm_display_mode *adjusted_mode) |
||
218 | { |
||
219 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1430 | serge | 220 | struct drm_device *dev = encoder->dev; |
221 | struct radeon_device *rdev = dev->dev_private; |
||
1123 | serge | 222 | |
1430 | serge | 223 | /* adjust pm to upcoming mode change */ |
224 | radeon_pm_compute_clocks(rdev); |
||
225 | |||
1268 | serge | 226 | /* set the active encoder to connector routing */ |
227 | radeon_encoder_set_active_device(encoder); |
||
1123 | serge | 228 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
229 | |||
1321 | serge | 230 | /* get the native mode for LVDS */ |
231 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { |
||
232 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
||
233 | int mode_id = adjusted_mode->base.id; |
||
234 | *adjusted_mode = *native_mode; |
||
235 | adjusted_mode->hdisplay = mode->hdisplay; |
||
236 | adjusted_mode->vdisplay = mode->vdisplay; |
||
1403 | serge | 237 | adjusted_mode->crtc_hdisplay = mode->hdisplay; |
238 | adjusted_mode->crtc_vdisplay = mode->vdisplay; |
||
1321 | serge | 239 | adjusted_mode->base.id = mode_id; |
240 | } |
||
1123 | serge | 241 | |
242 | return true; |
||
243 | } |
||
244 | |||
245 | static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { |
||
246 | .dpms = radeon_legacy_lvds_dpms, |
||
1321 | serge | 247 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 248 | .prepare = radeon_legacy_lvds_prepare, |
249 | .mode_set = radeon_legacy_lvds_mode_set, |
||
250 | .commit = radeon_legacy_lvds_commit, |
||
1179 | serge | 251 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 252 | }; |
253 | |||
254 | |||
255 | static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { |
||
256 | .destroy = radeon_enc_destroy, |
||
257 | }; |
||
258 | |||
259 | static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) |
||
260 | { |
||
261 | struct drm_device *dev = encoder->dev; |
||
262 | struct radeon_device *rdev = dev->dev_private; |
||
263 | uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
264 | uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); |
||
265 | uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
||
266 | |||
267 | DRM_DEBUG("\n"); |
||
268 | |||
269 | switch (mode) { |
||
270 | case DRM_MODE_DPMS_ON: |
||
271 | crtc_ext_cntl |= RADEON_CRTC_CRT_ON; |
||
272 | dac_cntl &= ~RADEON_DAC_PDWN; |
||
273 | dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | |
||
274 | RADEON_DAC_PDWN_G | |
||
275 | RADEON_DAC_PDWN_B); |
||
276 | break; |
||
277 | case DRM_MODE_DPMS_STANDBY: |
||
278 | case DRM_MODE_DPMS_SUSPEND: |
||
279 | case DRM_MODE_DPMS_OFF: |
||
280 | crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; |
||
281 | dac_cntl |= RADEON_DAC_PDWN; |
||
282 | dac_macro_cntl |= (RADEON_DAC_PDWN_R | |
||
283 | RADEON_DAC_PDWN_G | |
||
284 | RADEON_DAC_PDWN_B); |
||
285 | break; |
||
286 | } |
||
287 | |||
288 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
289 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
||
290 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
||
291 | |||
292 | if (rdev->is_atom_bios) |
||
293 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
294 | else |
||
295 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 296 | |
297 | /* adjust pm to dpms change */ |
||
298 | radeon_pm_compute_clocks(rdev); |
||
1123 | serge | 299 | } |
300 | |||
301 | static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) |
||
302 | { |
||
303 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
304 | |||
305 | if (rdev->is_atom_bios) |
||
306 | radeon_atom_output_lock(encoder, true); |
||
307 | else |
||
308 | radeon_combios_output_lock(encoder, true); |
||
309 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
310 | } |
||
311 | |||
312 | static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) |
||
313 | { |
||
314 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
315 | |||
316 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
||
317 | |||
318 | if (rdev->is_atom_bios) |
||
319 | radeon_atom_output_lock(encoder, false); |
||
320 | else |
||
321 | radeon_combios_output_lock(encoder, false); |
||
322 | } |
||
323 | |||
324 | static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, |
||
325 | struct drm_display_mode *mode, |
||
326 | struct drm_display_mode *adjusted_mode) |
||
327 | { |
||
328 | struct drm_device *dev = encoder->dev; |
||
329 | struct radeon_device *rdev = dev->dev_private; |
||
330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
331 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
332 | uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; |
||
333 | |||
334 | DRM_DEBUG("\n"); |
||
335 | |||
336 | if (radeon_crtc->crtc_id == 0) { |
||
337 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
||
338 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
||
339 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
||
340 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
341 | } else { |
||
342 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); |
||
343 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
344 | } |
||
345 | } else { |
||
346 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
||
347 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
||
348 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
||
349 | disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; |
||
350 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
351 | } else { |
||
352 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; |
||
353 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
354 | } |
||
355 | } |
||
356 | |||
357 | dac_cntl = (RADEON_DAC_MASK_ALL | |
||
358 | RADEON_DAC_VGA_ADR_EN | |
||
359 | /* TODO 6-bits */ |
||
360 | RADEON_DAC_8BIT_EN); |
||
361 | |||
362 | WREG32_P(RADEON_DAC_CNTL, |
||
363 | dac_cntl, |
||
364 | RADEON_DAC_RANGE_CNTL | |
||
365 | RADEON_DAC_BLANKING); |
||
366 | |||
367 | if (radeon_encoder->enc_priv) { |
||
368 | struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; |
||
369 | dac_macro_cntl = p_dac->ps2_pdac_adj; |
||
370 | } else |
||
371 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
||
372 | dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; |
||
373 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
||
374 | |||
375 | if (rdev->is_atom_bios) |
||
376 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
377 | else |
||
378 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
379 | } |
||
380 | |||
381 | static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, |
||
382 | struct drm_connector *connector) |
||
383 | { |
||
384 | struct drm_device *dev = encoder->dev; |
||
385 | struct radeon_device *rdev = dev->dev_private; |
||
386 | uint32_t vclk_ecp_cntl, crtc_ext_cntl; |
||
387 | uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; |
||
388 | enum drm_connector_status found = connector_status_disconnected; |
||
389 | bool color = true; |
||
390 | |||
391 | /* save the regs we need */ |
||
392 | vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
393 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
394 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
||
395 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
||
396 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
||
397 | |||
398 | tmp = vclk_ecp_cntl & |
||
399 | ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
400 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
401 | |||
402 | tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; |
||
403 | WREG32(RADEON_CRTC_EXT_CNTL, tmp); |
||
404 | |||
405 | tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | |
||
406 | RADEON_DAC_FORCE_DATA_EN; |
||
407 | |||
408 | if (color) |
||
409 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
||
410 | else |
||
411 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
||
412 | |||
413 | if (ASIC_IS_R300(rdev)) |
||
414 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
415 | else |
||
416 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
417 | |||
418 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
||
419 | |||
420 | tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); |
||
421 | tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; |
||
422 | WREG32(RADEON_DAC_CNTL, tmp); |
||
423 | |||
424 | tmp &= ~(RADEON_DAC_PDWN_R | |
||
425 | RADEON_DAC_PDWN_G | |
||
426 | RADEON_DAC_PDWN_B); |
||
427 | |||
428 | WREG32(RADEON_DAC_MACRO_CNTL, tmp); |
||
429 | |||
430 | udelay(2000); |
||
431 | |||
432 | if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) |
||
433 | found = connector_status_connected; |
||
434 | |||
435 | /* restore the regs we used */ |
||
436 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
||
437 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
||
438 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
||
439 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
440 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); |
||
441 | |||
442 | return found; |
||
443 | } |
||
444 | |||
445 | static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { |
||
446 | .dpms = radeon_legacy_primary_dac_dpms, |
||
1321 | serge | 447 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 448 | .prepare = radeon_legacy_primary_dac_prepare, |
449 | .mode_set = radeon_legacy_primary_dac_mode_set, |
||
450 | .commit = radeon_legacy_primary_dac_commit, |
||
451 | .detect = radeon_legacy_primary_dac_detect, |
||
1179 | serge | 452 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 453 | }; |
454 | |||
455 | |||
456 | static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { |
||
457 | .destroy = radeon_enc_destroy, |
||
458 | }; |
||
459 | |||
460 | static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) |
||
461 | { |
||
462 | struct drm_device *dev = encoder->dev; |
||
463 | struct radeon_device *rdev = dev->dev_private; |
||
464 | uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); |
||
465 | DRM_DEBUG("\n"); |
||
466 | |||
467 | switch (mode) { |
||
468 | case DRM_MODE_DPMS_ON: |
||
469 | fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
||
470 | break; |
||
471 | case DRM_MODE_DPMS_STANDBY: |
||
472 | case DRM_MODE_DPMS_SUSPEND: |
||
473 | case DRM_MODE_DPMS_OFF: |
||
474 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
||
475 | break; |
||
476 | } |
||
477 | |||
478 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
||
479 | |||
480 | if (rdev->is_atom_bios) |
||
481 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
482 | else |
||
483 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 484 | |
485 | /* adjust pm to dpms change */ |
||
486 | radeon_pm_compute_clocks(rdev); |
||
1123 | serge | 487 | } |
488 | |||
489 | static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) |
||
490 | { |
||
491 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
492 | |||
493 | if (rdev->is_atom_bios) |
||
494 | radeon_atom_output_lock(encoder, true); |
||
495 | else |
||
496 | radeon_combios_output_lock(encoder, true); |
||
497 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
498 | } |
||
499 | |||
500 | static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) |
||
501 | { |
||
502 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
503 | |||
504 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); |
||
505 | |||
506 | if (rdev->is_atom_bios) |
||
507 | radeon_atom_output_lock(encoder, true); |
||
508 | else |
||
509 | radeon_combios_output_lock(encoder, true); |
||
510 | } |
||
511 | |||
512 | static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, |
||
513 | struct drm_display_mode *mode, |
||
514 | struct drm_display_mode *adjusted_mode) |
||
515 | { |
||
516 | struct drm_device *dev = encoder->dev; |
||
517 | struct radeon_device *rdev = dev->dev_private; |
||
518 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
519 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
520 | uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; |
||
521 | int i; |
||
522 | |||
523 | DRM_DEBUG("\n"); |
||
524 | |||
525 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); |
||
526 | tmp &= 0xfffff; |
||
527 | if (rdev->family == CHIP_RV280) { |
||
528 | /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ |
||
529 | tmp ^= (1 << 22); |
||
530 | tmds_pll_cntl ^= (1 << 22); |
||
531 | } |
||
532 | |||
533 | if (radeon_encoder->enc_priv) { |
||
534 | struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; |
||
535 | |||
536 | for (i = 0; i < 4; i++) { |
||
537 | if (tmds->tmds_pll[i].freq == 0) |
||
538 | break; |
||
539 | if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { |
||
540 | tmp = tmds->tmds_pll[i].value ; |
||
541 | break; |
||
542 | } |
||
543 | } |
||
544 | } |
||
545 | |||
546 | if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { |
||
547 | if (tmp & 0xfff00000) |
||
548 | tmds_pll_cntl = tmp; |
||
549 | else { |
||
550 | tmds_pll_cntl &= 0xfff00000; |
||
551 | tmds_pll_cntl |= tmp; |
||
552 | } |
||
553 | } else |
||
554 | tmds_pll_cntl = tmp; |
||
555 | |||
556 | tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & |
||
557 | ~(RADEON_TMDS_TRANSMITTER_PLLRST); |
||
558 | |||
559 | if (rdev->family == CHIP_R200 || |
||
560 | rdev->family == CHIP_R100 || |
||
561 | ASIC_IS_R300(rdev)) |
||
562 | tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); |
||
563 | else /* RV chips got this bit reversed */ |
||
564 | tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; |
||
565 | |||
566 | fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | |
||
567 | (RADEON_FP_CRTC_DONT_SHADOW_VPAR | |
||
568 | RADEON_FP_CRTC_DONT_SHADOW_HEND)); |
||
569 | |||
570 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
||
571 | |||
1268 | serge | 572 | fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | |
573 | RADEON_FP_DFP_SYNC_SEL | |
||
574 | RADEON_FP_CRT_SYNC_SEL | |
||
575 | RADEON_FP_CRTC_LOCK_8DOT | |
||
576 | RADEON_FP_USE_SHADOW_EN | |
||
577 | RADEON_FP_CRTC_USE_SHADOW_VEND | |
||
578 | RADEON_FP_CRT_SYNC_ALT); |
||
579 | |||
1123 | serge | 580 | if (1) /* FIXME rgbBits == 8 */ |
581 | fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ |
||
582 | else |
||
583 | fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ |
||
584 | |||
585 | if (radeon_crtc->crtc_id == 0) { |
||
586 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
||
587 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
||
1179 | serge | 588 | if (radeon_encoder->rmx_type != RMX_OFF) |
1123 | serge | 589 | fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; |
590 | else |
||
591 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; |
||
592 | } else |
||
1268 | serge | 593 | fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; |
1123 | serge | 594 | } else { |
595 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
||
596 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
||
597 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; |
||
598 | } else |
||
599 | fp_gen_cntl |= RADEON_FP_SEL_CRTC2; |
||
600 | } |
||
601 | |||
602 | WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); |
||
603 | WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); |
||
604 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
||
605 | |||
606 | if (rdev->is_atom_bios) |
||
607 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
608 | else |
||
609 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
610 | } |
||
611 | |||
612 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { |
||
613 | .dpms = radeon_legacy_tmds_int_dpms, |
||
1321 | serge | 614 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 615 | .prepare = radeon_legacy_tmds_int_prepare, |
616 | .mode_set = radeon_legacy_tmds_int_mode_set, |
||
617 | .commit = radeon_legacy_tmds_int_commit, |
||
1179 | serge | 618 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 619 | }; |
620 | |||
621 | |||
622 | static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { |
||
623 | .destroy = radeon_enc_destroy, |
||
624 | }; |
||
625 | |||
626 | static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) |
||
627 | { |
||
628 | struct drm_device *dev = encoder->dev; |
||
629 | struct radeon_device *rdev = dev->dev_private; |
||
630 | uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
631 | DRM_DEBUG("\n"); |
||
632 | |||
633 | switch (mode) { |
||
634 | case DRM_MODE_DPMS_ON: |
||
635 | fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; |
||
636 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
637 | break; |
||
638 | case DRM_MODE_DPMS_STANDBY: |
||
639 | case DRM_MODE_DPMS_SUSPEND: |
||
640 | case DRM_MODE_DPMS_OFF: |
||
641 | fp2_gen_cntl |= RADEON_FP2_BLANK_EN; |
||
642 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
643 | break; |
||
644 | } |
||
645 | |||
646 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
647 | |||
648 | if (rdev->is_atom_bios) |
||
649 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
650 | else |
||
651 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 652 | |
653 | /* adjust pm to dpms change */ |
||
654 | radeon_pm_compute_clocks(rdev); |
||
1123 | serge | 655 | } |
656 | |||
657 | static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) |
||
658 | { |
||
659 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
660 | |||
661 | if (rdev->is_atom_bios) |
||
662 | radeon_atom_output_lock(encoder, true); |
||
663 | else |
||
664 | radeon_combios_output_lock(encoder, true); |
||
665 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
666 | } |
||
667 | |||
668 | static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) |
||
669 | { |
||
670 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
671 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); |
||
672 | |||
673 | if (rdev->is_atom_bios) |
||
674 | radeon_atom_output_lock(encoder, false); |
||
675 | else |
||
676 | radeon_combios_output_lock(encoder, false); |
||
677 | } |
||
678 | |||
679 | static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, |
||
680 | struct drm_display_mode *mode, |
||
681 | struct drm_display_mode *adjusted_mode) |
||
682 | { |
||
683 | struct drm_device *dev = encoder->dev; |
||
684 | struct radeon_device *rdev = dev->dev_private; |
||
685 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
686 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
687 | uint32_t fp2_gen_cntl; |
||
688 | |||
689 | DRM_DEBUG("\n"); |
||
690 | |||
691 | if (rdev->is_atom_bios) { |
||
692 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
||
693 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
||
694 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
695 | } else { |
||
696 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
697 | |||
698 | if (1) /* FIXME rgbBits == 8 */ |
||
699 | fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ |
||
700 | else |
||
701 | fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ |
||
702 | |||
703 | fp2_gen_cntl &= ~(RADEON_FP2_ON | |
||
704 | RADEON_FP2_DVO_EN | |
||
705 | RADEON_FP2_DVO_RATE_SEL_SDR); |
||
706 | |||
707 | /* XXX: these are oem specific */ |
||
708 | if (ASIC_IS_R300(rdev)) { |
||
709 | if ((dev->pdev->device == 0x4850) && |
||
710 | (dev->pdev->subsystem_vendor == 0x1028) && |
||
711 | (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ |
||
712 | fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; |
||
713 | else |
||
714 | fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; |
||
715 | |||
716 | /*if (mode->clock > 165000) |
||
717 | fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ |
||
718 | } |
||
1321 | serge | 719 | if (!radeon_combios_external_tmds_setup(encoder)) |
720 | radeon_external_tmds_setup(encoder); |
||
1123 | serge | 721 | } |
722 | |||
723 | if (radeon_crtc->crtc_id == 0) { |
||
724 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
||
725 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
||
1179 | serge | 726 | if (radeon_encoder->rmx_type != RMX_OFF) |
1123 | serge | 727 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; |
728 | else |
||
729 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; |
||
730 | } else |
||
731 | fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; |
||
732 | } else { |
||
733 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
||
734 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
||
735 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
||
736 | } else |
||
737 | fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; |
||
738 | } |
||
739 | |||
740 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
741 | |||
742 | if (rdev->is_atom_bios) |
||
743 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
744 | else |
||
745 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
746 | } |
||
747 | |||
1321 | serge | 748 | static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) |
749 | { |
||
750 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
751 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
||
752 | if (tmds) { |
||
753 | if (tmds->i2c_bus) |
||
754 | radeon_i2c_destroy(tmds->i2c_bus); |
||
755 | } |
||
756 | kfree(radeon_encoder->enc_priv); |
||
757 | drm_encoder_cleanup(encoder); |
||
758 | kfree(radeon_encoder); |
||
759 | } |
||
760 | |||
1123 | serge | 761 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { |
762 | .dpms = radeon_legacy_tmds_ext_dpms, |
||
1321 | serge | 763 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 764 | .prepare = radeon_legacy_tmds_ext_prepare, |
765 | .mode_set = radeon_legacy_tmds_ext_mode_set, |
||
766 | .commit = radeon_legacy_tmds_ext_commit, |
||
1179 | serge | 767 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 768 | }; |
769 | |||
770 | |||
771 | static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { |
||
1321 | serge | 772 | .destroy = radeon_ext_tmds_enc_destroy, |
1123 | serge | 773 | }; |
774 | |||
775 | static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) |
||
776 | { |
||
777 | struct drm_device *dev = encoder->dev; |
||
778 | struct radeon_device *rdev = dev->dev_private; |
||
1179 | serge | 779 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1123 | serge | 780 | uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; |
1179 | serge | 781 | uint32_t tv_master_cntl = 0; |
782 | bool is_tv; |
||
1123 | serge | 783 | DRM_DEBUG("\n"); |
784 | |||
1179 | serge | 785 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
786 | |||
1123 | serge | 787 | if (rdev->family == CHIP_R200) |
788 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
789 | else { |
||
1179 | serge | 790 | if (is_tv) |
791 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
||
792 | else |
||
1123 | serge | 793 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
794 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
795 | } |
||
796 | |||
797 | switch (mode) { |
||
798 | case DRM_MODE_DPMS_ON: |
||
799 | if (rdev->family == CHIP_R200) { |
||
800 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
801 | } else { |
||
1179 | serge | 802 | if (is_tv) |
803 | tv_master_cntl |= RADEON_TV_ON; |
||
804 | else |
||
1123 | serge | 805 | crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; |
1179 | serge | 806 | |
1123 | serge | 807 | if (rdev->family == CHIP_R420 || |
808 | rdev->family == CHIP_R423 || |
||
809 | rdev->family == CHIP_RV410) |
||
810 | tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | |
||
811 | R420_TV_DAC_GDACPD | |
||
812 | R420_TV_DAC_BDACPD | |
||
813 | RADEON_TV_DAC_BGSLEEP); |
||
814 | else |
||
815 | tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | |
||
816 | RADEON_TV_DAC_GDACPD | |
||
817 | RADEON_TV_DAC_BDACPD | |
||
818 | RADEON_TV_DAC_BGSLEEP); |
||
819 | } |
||
820 | break; |
||
821 | case DRM_MODE_DPMS_STANDBY: |
||
822 | case DRM_MODE_DPMS_SUSPEND: |
||
823 | case DRM_MODE_DPMS_OFF: |
||
824 | if (rdev->family == CHIP_R200) |
||
825 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
826 | else { |
||
1179 | serge | 827 | if (is_tv) |
828 | tv_master_cntl &= ~RADEON_TV_ON; |
||
829 | else |
||
1123 | serge | 830 | crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; |
1179 | serge | 831 | |
1123 | serge | 832 | if (rdev->family == CHIP_R420 || |
833 | rdev->family == CHIP_R423 || |
||
834 | rdev->family == CHIP_RV410) |
||
835 | tv_dac_cntl |= (R420_TV_DAC_RDACPD | |
||
836 | R420_TV_DAC_GDACPD | |
||
837 | R420_TV_DAC_BDACPD | |
||
838 | RADEON_TV_DAC_BGSLEEP); |
||
839 | else |
||
840 | tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | |
||
841 | RADEON_TV_DAC_GDACPD | |
||
842 | RADEON_TV_DAC_BDACPD | |
||
843 | RADEON_TV_DAC_BGSLEEP); |
||
844 | } |
||
845 | break; |
||
846 | } |
||
847 | |||
848 | if (rdev->family == CHIP_R200) { |
||
849 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
850 | } else { |
||
1179 | serge | 851 | if (is_tv) |
852 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
||
853 | else |
||
1123 | serge | 854 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
855 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
856 | } |
||
857 | |||
858 | if (rdev->is_atom_bios) |
||
859 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
860 | else |
||
861 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 862 | |
863 | /* adjust pm to dpms change */ |
||
864 | radeon_pm_compute_clocks(rdev); |
||
1123 | serge | 865 | } |
866 | |||
867 | static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) |
||
868 | { |
||
869 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
870 | |||
871 | if (rdev->is_atom_bios) |
||
872 | radeon_atom_output_lock(encoder, true); |
||
873 | else |
||
874 | radeon_combios_output_lock(encoder, true); |
||
875 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
876 | } |
||
877 | |||
878 | static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) |
||
879 | { |
||
880 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
881 | |||
882 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
||
883 | |||
884 | if (rdev->is_atom_bios) |
||
885 | radeon_atom_output_lock(encoder, true); |
||
886 | else |
||
887 | radeon_combios_output_lock(encoder, true); |
||
888 | } |
||
889 | |||
890 | static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, |
||
891 | struct drm_display_mode *mode, |
||
892 | struct drm_display_mode *adjusted_mode) |
||
893 | { |
||
894 | struct drm_device *dev = encoder->dev; |
||
895 | struct radeon_device *rdev = dev->dev_private; |
||
896 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
897 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1179 | serge | 898 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
1123 | serge | 899 | uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; |
1179 | serge | 900 | uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; |
901 | bool is_tv = false; |
||
1123 | serge | 902 | |
903 | DRM_DEBUG("\n"); |
||
904 | |||
1179 | serge | 905 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
1123 | serge | 906 | |
907 | if (rdev->family != CHIP_R200) { |
||
908 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
909 | if (rdev->family == CHIP_R420 || |
||
910 | rdev->family == CHIP_R423 || |
||
911 | rdev->family == CHIP_RV410) { |
||
912 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
||
913 | RADEON_TV_DAC_BGADJ_MASK | |
||
914 | R420_TV_DAC_DACADJ_MASK | |
||
915 | R420_TV_DAC_RDACPD | |
||
916 | R420_TV_DAC_GDACPD | |
||
1221 | serge | 917 | R420_TV_DAC_BDACPD | |
1123 | serge | 918 | R420_TV_DAC_TVENABLE); |
919 | } else { |
||
920 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
||
921 | RADEON_TV_DAC_BGADJ_MASK | |
||
922 | RADEON_TV_DAC_DACADJ_MASK | |
||
923 | RADEON_TV_DAC_RDACPD | |
||
924 | RADEON_TV_DAC_GDACPD | |
||
1221 | serge | 925 | RADEON_TV_DAC_BDACPD); |
1123 | serge | 926 | } |
927 | |||
928 | /* FIXME TV */ |
||
1179 | serge | 929 | if (tv_dac) { |
1123 | serge | 930 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
931 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
||
932 | RADEON_TV_DAC_NHOLD | |
||
933 | RADEON_TV_DAC_STD_PS2 | |
||
934 | tv_dac->ps2_tvdac_adj); |
||
935 | } else |
||
936 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
||
937 | RADEON_TV_DAC_NHOLD | |
||
938 | RADEON_TV_DAC_STD_PS2); |
||
939 | |||
940 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
941 | } |
||
942 | |||
943 | if (ASIC_IS_R300(rdev)) { |
||
944 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; |
||
945 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
||
1179 | serge | 946 | } |
947 | |||
948 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) |
||
949 | disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); |
||
1123 | serge | 950 | else |
951 | disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
||
952 | |||
1179 | serge | 953 | if (rdev->family == CHIP_R200) |
954 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
955 | |||
956 | if (is_tv) { |
||
957 | uint32_t dac_cntl; |
||
958 | |||
959 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
||
960 | dac_cntl &= ~RADEON_DAC_TVO_EN; |
||
961 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
||
962 | |||
963 | if (ASIC_IS_R300(rdev)) |
||
964 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; |
||
965 | |||
966 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; |
||
967 | if (radeon_crtc->crtc_id == 0) { |
||
968 | if (ASIC_IS_R300(rdev)) { |
||
969 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
970 | disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | |
||
971 | RADEON_DISP_TV_SOURCE_CRTC); |
||
972 | } |
||
973 | if (rdev->family >= CHIP_R200) { |
||
974 | disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; |
||
975 | } else { |
||
976 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
||
977 | } |
||
978 | } else { |
||
979 | if (ASIC_IS_R300(rdev)) { |
||
980 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
981 | disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; |
||
982 | } |
||
983 | if (rdev->family >= CHIP_R200) { |
||
984 | disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; |
||
985 | } else { |
||
986 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
||
987 | } |
||
988 | } |
||
989 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
990 | } else { |
||
991 | |||
1123 | serge | 992 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; |
993 | |||
994 | if (radeon_crtc->crtc_id == 0) { |
||
995 | if (ASIC_IS_R300(rdev)) { |
||
996 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
997 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; |
||
998 | } else if (rdev->family == CHIP_R200) { |
||
999 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
||
1000 | RADEON_FP2_DVO_RATE_SEL_SDR); |
||
1001 | } else |
||
1002 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
||
1003 | } else { |
||
1004 | if (ASIC_IS_R300(rdev)) { |
||
1005 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1006 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
||
1007 | } else if (rdev->family == CHIP_R200) { |
||
1008 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
||
1009 | RADEON_FP2_DVO_RATE_SEL_SDR); |
||
1010 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
||
1011 | } else |
||
1012 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
||
1013 | } |
||
1014 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
1179 | serge | 1015 | } |
1123 | serge | 1016 | |
1017 | if (ASIC_IS_R300(rdev)) { |
||
1018 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
||
1179 | serge | 1019 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
1020 | } |
||
1021 | |||
1022 | if (rdev->family >= CHIP_R200) |
||
1023 | WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); |
||
1123 | serge | 1024 | else |
1025 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
||
1026 | |||
1179 | serge | 1027 | if (rdev->family == CHIP_R200) |
1028 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
1029 | |||
1030 | if (is_tv) |
||
1031 | radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); |
||
1032 | |||
1123 | serge | 1033 | if (rdev->is_atom_bios) |
1034 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
1035 | else |
||
1036 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
1037 | |||
1038 | } |
||
1039 | |||
1179 | serge | 1040 | static bool r300_legacy_tv_detect(struct drm_encoder *encoder, |
1041 | struct drm_connector *connector) |
||
1042 | { |
||
1043 | struct drm_device *dev = encoder->dev; |
||
1044 | struct radeon_device *rdev = dev->dev_private; |
||
1045 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
||
1046 | uint32_t disp_output_cntl, gpiopad_a, tmp; |
||
1047 | bool found = false; |
||
1048 | |||
1049 | /* save regs needed */ |
||
1050 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
||
1051 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
||
1052 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
1053 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
||
1054 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
1055 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
||
1056 | |||
1057 | WREG32_P(RADEON_GPIOPAD_A, 0, ~1); |
||
1058 | |||
1059 | WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); |
||
1060 | |||
1061 | WREG32(RADEON_CRTC2_GEN_CNTL, |
||
1062 | RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); |
||
1063 | |||
1064 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1065 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
||
1066 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
||
1067 | |||
1068 | WREG32(RADEON_DAC_EXT_CNTL, |
||
1069 | RADEON_DAC2_FORCE_BLANK_OFF_EN | |
||
1070 | RADEON_DAC2_FORCE_DATA_EN | |
||
1071 | RADEON_DAC_FORCE_DATA_SEL_RGB | |
||
1072 | (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); |
||
1073 | |||
1074 | WREG32(RADEON_TV_DAC_CNTL, |
||
1075 | RADEON_TV_DAC_STD_NTSC | |
||
1076 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
||
1077 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
||
1078 | |||
1079 | RREG32(RADEON_TV_DAC_CNTL); |
||
1080 | mdelay(4); |
||
1081 | |||
1082 | WREG32(RADEON_TV_DAC_CNTL, |
||
1083 | RADEON_TV_DAC_NBLANK | |
||
1084 | RADEON_TV_DAC_NHOLD | |
||
1085 | RADEON_TV_MONITOR_DETECT_EN | |
||
1086 | RADEON_TV_DAC_STD_NTSC | |
||
1087 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
||
1088 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
||
1089 | |||
1090 | RREG32(RADEON_TV_DAC_CNTL); |
||
1091 | mdelay(6); |
||
1092 | |||
1093 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
||
1094 | if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { |
||
1095 | found = true; |
||
1096 | DRM_DEBUG("S-video TV connection detected\n"); |
||
1097 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
||
1098 | found = true; |
||
1099 | DRM_DEBUG("Composite TV connection detected\n"); |
||
1100 | } |
||
1101 | |||
1102 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
1103 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
||
1104 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
1105 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
1106 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
||
1107 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
||
1108 | return found; |
||
1109 | } |
||
1110 | |||
1111 | static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, |
||
1112 | struct drm_connector *connector) |
||
1113 | { |
||
1114 | struct drm_device *dev = encoder->dev; |
||
1115 | struct radeon_device *rdev = dev->dev_private; |
||
1116 | uint32_t tv_dac_cntl, dac_cntl2; |
||
1117 | uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; |
||
1118 | bool found = false; |
||
1119 | |||
1120 | if (ASIC_IS_R300(rdev)) |
||
1121 | return r300_legacy_tv_detect(encoder, connector); |
||
1122 | |||
1123 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
||
1124 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
||
1125 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
1126 | config_cntl = RREG32(RADEON_CONFIG_CNTL); |
||
1127 | tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); |
||
1128 | |||
1129 | tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; |
||
1130 | WREG32(RADEON_DAC_CNTL2, tmp); |
||
1131 | |||
1132 | tmp = tv_master_cntl | RADEON_TV_ON; |
||
1133 | tmp &= ~(RADEON_TV_ASYNC_RST | |
||
1134 | RADEON_RESTART_PHASE_FIX | |
||
1135 | RADEON_CRT_FIFO_CE_EN | |
||
1136 | RADEON_TV_FIFO_CE_EN | |
||
1137 | RADEON_RE_SYNC_NOW_SEL_MASK); |
||
1138 | tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; |
||
1139 | WREG32(RADEON_TV_MASTER_CNTL, tmp); |
||
1140 | |||
1141 | tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | |
||
1142 | RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | |
||
1143 | (8 << RADEON_TV_DAC_BGADJ_SHIFT); |
||
1144 | |||
1145 | if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) |
||
1146 | tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); |
||
1147 | else |
||
1148 | tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); |
||
1149 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
||
1150 | |||
1151 | tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | |
||
1152 | RADEON_RED_MX_FORCE_DAC_DATA | |
||
1153 | RADEON_GRN_MX_FORCE_DAC_DATA | |
||
1154 | RADEON_BLU_MX_FORCE_DAC_DATA | |
||
1155 | (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); |
||
1156 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); |
||
1157 | |||
1158 | mdelay(3); |
||
1159 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
||
1160 | if (tmp & RADEON_TV_DAC_GDACDET) { |
||
1161 | found = true; |
||
1162 | DRM_DEBUG("S-video TV connection detected\n"); |
||
1163 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
||
1164 | found = true; |
||
1165 | DRM_DEBUG("Composite TV connection detected\n"); |
||
1166 | } |
||
1167 | |||
1168 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); |
||
1169 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
1170 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
||
1171 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
||
1172 | return found; |
||
1173 | } |
||
1174 | |||
1123 | serge | 1175 | static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, |
1176 | struct drm_connector *connector) |
||
1177 | { |
||
1178 | struct drm_device *dev = encoder->dev; |
||
1179 | struct radeon_device *rdev = dev->dev_private; |
||
1180 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
||
1181 | uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; |
||
1182 | enum drm_connector_status found = connector_status_disconnected; |
||
1179 | serge | 1183 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1184 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
||
1123 | serge | 1185 | bool color = true; |
1186 | |||
1179 | serge | 1187 | if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || |
1188 | connector->connector_type == DRM_MODE_CONNECTOR_Composite || |
||
1189 | connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { |
||
1190 | bool tv_detect; |
||
1123 | serge | 1191 | |
1179 | serge | 1192 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) |
1193 | return connector_status_disconnected; |
||
1194 | |||
1195 | tv_detect = radeon_legacy_tv_detect(encoder, connector); |
||
1196 | if (tv_detect && tv_dac) |
||
1197 | found = connector_status_connected; |
||
1198 | return found; |
||
1199 | } |
||
1200 | |||
1201 | /* don't probe if the encoder is being used for something else not CRT related */ |
||
1202 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { |
||
1203 | DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); |
||
1204 | return connector_status_disconnected; |
||
1205 | } |
||
1206 | |||
1123 | serge | 1207 | /* save the regs we need */ |
1208 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
1209 | gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0; |
||
1210 | disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0; |
||
1211 | disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG); |
||
1212 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
1213 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
1214 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
||
1215 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
||
1216 | |||
1217 | tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb |
||
1218 | | RADEON_PIX2CLK_DAC_ALWAYS_ONb); |
||
1219 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
1220 | |||
1221 | if (ASIC_IS_R300(rdev)) |
||
1222 | WREG32_P(RADEON_GPIOPAD_A, 1, ~1); |
||
1223 | |||
1224 | tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; |
||
1225 | tmp |= RADEON_CRTC2_CRT2_ON | |
||
1226 | (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); |
||
1227 | |||
1228 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
||
1229 | |||
1230 | if (ASIC_IS_R300(rdev)) { |
||
1231 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1232 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
||
1233 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
||
1234 | } else { |
||
1235 | tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; |
||
1236 | WREG32(RADEON_DISP_HW_DEBUG, tmp); |
||
1237 | } |
||
1238 | |||
1239 | tmp = RADEON_TV_DAC_NBLANK | |
||
1240 | RADEON_TV_DAC_NHOLD | |
||
1241 | RADEON_TV_MONITOR_DETECT_EN | |
||
1242 | RADEON_TV_DAC_STD_PS2; |
||
1243 | |||
1244 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
||
1245 | |||
1246 | tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | |
||
1247 | RADEON_DAC2_FORCE_DATA_EN; |
||
1248 | |||
1249 | if (color) |
||
1250 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
||
1251 | else |
||
1252 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
||
1253 | |||
1254 | if (ASIC_IS_R300(rdev)) |
||
1255 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
1256 | else |
||
1257 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
1258 | |||
1259 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
||
1260 | |||
1261 | tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; |
||
1262 | WREG32(RADEON_DAC_CNTL2, tmp); |
||
1263 | |||
1264 | udelay(10000); |
||
1265 | |||
1266 | if (ASIC_IS_R300(rdev)) { |
||
1267 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) |
||
1268 | found = connector_status_connected; |
||
1269 | } else { |
||
1270 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) |
||
1271 | found = connector_status_connected; |
||
1272 | } |
||
1273 | |||
1274 | /* restore regs we used */ |
||
1275 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
||
1276 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
||
1277 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
1278 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
1279 | |||
1280 | if (ASIC_IS_R300(rdev)) { |
||
1281 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
1282 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
||
1283 | } else { |
||
1284 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
||
1285 | } |
||
1286 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
1287 | |||
1179 | serge | 1288 | return found; |
1123 | serge | 1289 | |
1290 | } |
||
1291 | |||
1292 | static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { |
||
1293 | .dpms = radeon_legacy_tv_dac_dpms, |
||
1321 | serge | 1294 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 1295 | .prepare = radeon_legacy_tv_dac_prepare, |
1296 | .mode_set = radeon_legacy_tv_dac_mode_set, |
||
1297 | .commit = radeon_legacy_tv_dac_commit, |
||
1298 | .detect = radeon_legacy_tv_dac_detect, |
||
1179 | serge | 1299 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 1300 | }; |
1301 | |||
1302 | |||
1303 | static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { |
||
1304 | .destroy = radeon_enc_destroy, |
||
1305 | }; |
||
1306 | |||
1179 | serge | 1307 | |
1308 | static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) |
||
1309 | { |
||
1310 | struct drm_device *dev = encoder->base.dev; |
||
1311 | struct radeon_device *rdev = dev->dev_private; |
||
1312 | struct radeon_encoder_int_tmds *tmds = NULL; |
||
1313 | bool ret; |
||
1314 | |||
1315 | tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
||
1316 | |||
1317 | if (!tmds) |
||
1318 | return NULL; |
||
1319 | |||
1320 | if (rdev->is_atom_bios) |
||
1321 | ret = radeon_atombios_get_tmds_info(encoder, tmds); |
||
1322 | else |
||
1323 | ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); |
||
1324 | |||
1325 | if (ret == false) |
||
1326 | radeon_legacy_get_tmds_info_from_table(encoder, tmds); |
||
1327 | |||
1328 | return tmds; |
||
1329 | } |
||
1330 | |||
1321 | serge | 1331 | static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) |
1332 | { |
||
1333 | struct drm_device *dev = encoder->base.dev; |
||
1334 | struct radeon_device *rdev = dev->dev_private; |
||
1335 | struct radeon_encoder_ext_tmds *tmds = NULL; |
||
1336 | bool ret; |
||
1337 | |||
1338 | if (rdev->is_atom_bios) |
||
1339 | return NULL; |
||
1340 | |||
1341 | tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); |
||
1342 | |||
1343 | if (!tmds) |
||
1344 | return NULL; |
||
1345 | |||
1346 | ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); |
||
1347 | |||
1348 | if (ret == false) |
||
1349 | radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); |
||
1350 | |||
1351 | return tmds; |
||
1352 | } |
||
1353 | |||
1123 | serge | 1354 | void |
1355 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
||
1356 | { |
||
1357 | struct radeon_device *rdev = dev->dev_private; |
||
1358 | struct drm_encoder *encoder; |
||
1359 | struct radeon_encoder *radeon_encoder; |
||
1360 | |||
1361 | /* see if we already added it */ |
||
1362 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
1363 | radeon_encoder = to_radeon_encoder(encoder); |
||
1364 | if (radeon_encoder->encoder_id == encoder_id) { |
||
1365 | radeon_encoder->devices |= supported_device; |
||
1366 | return; |
||
1367 | } |
||
1368 | |||
1369 | } |
||
1370 | |||
1371 | /* add a new one */ |
||
1372 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
||
1373 | if (!radeon_encoder) |
||
1374 | return; |
||
1375 | |||
1376 | encoder = &radeon_encoder->base; |
||
1221 | serge | 1377 | if (rdev->flags & RADEON_SINGLE_CRTC) |
1378 | encoder->possible_crtcs = 0x1; |
||
1379 | else |
||
1123 | serge | 1380 | encoder->possible_crtcs = 0x3; |
1381 | |||
1382 | radeon_encoder->enc_priv = NULL; |
||
1383 | |||
1384 | radeon_encoder->encoder_id = encoder_id; |
||
1385 | radeon_encoder->devices = supported_device; |
||
1179 | serge | 1386 | radeon_encoder->rmx_type = RMX_OFF; |
1123 | serge | 1387 | |
1388 | switch (radeon_encoder->encoder_id) { |
||
1389 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
||
1179 | serge | 1390 | encoder->possible_crtcs = 0x1; |
1123 | serge | 1391 | drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); |
1392 | drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); |
||
1393 | if (rdev->is_atom_bios) |
||
1394 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
||
1395 | else |
||
1396 | radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); |
||
1397 | radeon_encoder->rmx_type = RMX_FULL; |
||
1398 | break; |
||
1399 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
||
1400 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); |
||
1401 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); |
||
1179 | serge | 1402 | radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); |
1123 | serge | 1403 | break; |
1404 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
||
1405 | drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); |
||
1406 | drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); |
||
1407 | if (rdev->is_atom_bios) |
||
1408 | radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); |
||
1409 | else |
||
1410 | radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); |
||
1411 | break; |
||
1412 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
||
1413 | drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
||
1414 | drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); |
||
1415 | if (rdev->is_atom_bios) |
||
1416 | radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); |
||
1417 | else |
||
1418 | radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); |
||
1419 | break; |
||
1420 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
||
1421 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS); |
||
1422 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); |
||
1423 | if (!rdev->is_atom_bios) |
||
1321 | serge | 1424 | radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); |
1123 | serge | 1425 | break; |
1426 | } |
||
1427 | }><>><>><>><>><>><>><>><>><>><>><>><>>>><>><>><>><>><>><>><>><> |