WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_legacy_encoders.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "drm_crtc_helper.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
1179	serge	32	static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
1123	serge	33	{
		34	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	35	struct drm_encoder_helper_funcs *encoder_funcs;
1123	serge	36
1179	serge	37	encoder_funcs = encoder->helper_private;
		38	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
		39	radeon_encoder->active_device = 0;
1123	serge	40	}
		41
		42	static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
		43	{
		44	struct drm_device *dev = encoder->dev;
		45	struct radeon_device *rdev = dev->dev_private;
		46	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		47	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
		48	int panel_pwr_delay = 2000;
1403	serge	49	bool is_mac = false;
1123	serge	50	DRM_DEBUG("\n");
		51
		52	if (radeon_encoder->enc_priv) {
		53	if (rdev->is_atom_bios) {
		54	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		55	panel_pwr_delay = lvds->panel_pwr_delay;
		56	} else {
		57	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		58	panel_pwr_delay = lvds->panel_pwr_delay;
		59	}
		60	}
		61
1403	serge	62	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
		63	* Taken from radeonfb.
		64	*/
		65	if ((rdev->mode_info.connector_table == CT_IBOOK) \|\|
		66	(rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) \|\|
		67	(rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) \|\|
		68	(rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
		69	is_mac = true;
		70
1123	serge	71	switch (mode) {
		72	case DRM_MODE_DPMS_ON:
		73	disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
		74	disp_pwr_man \|= RADEON_AUTO_PWRUP_EN;
		75	WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
		76	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		77	lvds_pll_cntl \|= RADEON_LVDS_PLL_EN;
		78	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		79	udelay(1000);
		80
		81	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		82	lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
		83	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		84
		85	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		86	lvds_gen_cntl \|= (RADEON_LVDS_ON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON \| RADEON_LVDS_BLON);
1403	serge	87	if (is_mac)
		88	lvds_gen_cntl \|= RADEON_LVDS_BL_MOD_EN;
1123	serge	89	lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
		90	udelay(panel_pwr_delay * 1000);
		91	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		92	break;
		93	case DRM_MODE_DPMS_STANDBY:
		94	case DRM_MODE_DPMS_SUSPEND:
		95	case DRM_MODE_DPMS_OFF:
		96	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		97	WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
		98	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		99	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
1403	serge	100	if (is_mac) {
		101	lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
		102	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		103	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_EN);
		104	} else {
		105	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
1123	serge	106	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_BLON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON);
1403	serge	107	}
1123	serge	108	udelay(panel_pwr_delay * 1000);
		109	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		110	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		111	break;
		112	}
		113
		114	if (rdev->is_atom_bios)
		115	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		116	else
		117	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		118	}
		119
		120	static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
		121	{
		122	struct radeon_device *rdev = encoder->dev->dev_private;
		123
		124	if (rdev->is_atom_bios)
		125	radeon_atom_output_lock(encoder, true);
		126	else
		127	radeon_combios_output_lock(encoder, true);
		128	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
		129	}
		130
		131	static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
		132	{
		133	struct radeon_device *rdev = encoder->dev->dev_private;
		134
		135	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
		136	if (rdev->is_atom_bios)
		137	radeon_atom_output_lock(encoder, false);
		138	else
		139	radeon_combios_output_lock(encoder, false);
		140	}
		141
		142	static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
		143	struct drm_display_mode *mode,
		144	struct drm_display_mode *adjusted_mode)
		145	{
		146	struct drm_device *dev = encoder->dev;
		147	struct radeon_device *rdev = dev->dev_private;
		148	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		149	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		150	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
		151
		152	DRM_DEBUG("\n");
		153
		154	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		155	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
		156
		157	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1321	serge	158	if (rdev->is_atom_bios) {
		159	/* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
		160	* need to call that on resume to set up the reg properly.
		161	*/
		162	radeon_encoder->pixel_clock = adjusted_mode->clock;
		163	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		164	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		165	} else {
1123	serge	166	struct radeon_encoder_lvds lvds = (struct radeon_encoder_lvds )radeon_encoder->enc_priv;
		167	if (lvds) {
		168	DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
		169	lvds_gen_cntl = lvds->lvds_gen_cntl;
		170	lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		171	(0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		172	lvds_ss_gen_cntl \|= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		173	(lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		174	} else
		175	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1321	serge	176	}
1123	serge	177	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		178	lvds_gen_cntl &= ~(RADEON_LVDS_ON \|
		179	RADEON_LVDS_BLON \|
		180	RADEON_LVDS_EN \|
		181	RADEON_LVDS_RST_FM);
		182
		183	if (ASIC_IS_R300(rdev))
		184	lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
		185
		186	if (radeon_crtc->crtc_id == 0) {
		187	if (ASIC_IS_R300(rdev)) {
1179	serge	188	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	189	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_RMX;
		190	} else
		191	lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
		192	} else {
		193	if (ASIC_IS_R300(rdev))
		194	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_CRTC2;
		195	else
		196	lvds_gen_cntl \|= RADEON_LVDS_SEL_CRTC2;
		197	}
		198
		199	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		200	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		201	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
		202
		203	if (rdev->family == CHIP_RV410)
		204	WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
		205
		206	if (rdev->is_atom_bios)
		207	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		208	else
		209	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		210	}
		211
1321	serge	212	static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
1123	serge	213	struct drm_display_mode *mode,
		214	struct drm_display_mode *adjusted_mode)
		215	{
		216	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		217
1268	serge	218	/* set the active encoder to connector routing */
		219	radeon_encoder_set_active_device(encoder);
1123	serge	220	drm_mode_set_crtcinfo(adjusted_mode, 0);
		221
1321	serge	222	/* get the native mode for LVDS */
		223	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
		224	struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
		225	int mode_id = adjusted_mode->base.id;
		226	adjusted_mode = native_mode;
		227	adjusted_mode->hdisplay = mode->hdisplay;
		228	adjusted_mode->vdisplay = mode->vdisplay;
1403	serge	229	adjusted_mode->crtc_hdisplay = mode->hdisplay;
		230	adjusted_mode->crtc_vdisplay = mode->vdisplay;
1321	serge	231	adjusted_mode->base.id = mode_id;
		232	}
1123	serge	233
		234	return true;
		235	}
		236
		237	static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
		238	.dpms = radeon_legacy_lvds_dpms,
1321	serge	239	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	240	.prepare = radeon_legacy_lvds_prepare,
		241	.mode_set = radeon_legacy_lvds_mode_set,
		242	.commit = radeon_legacy_lvds_commit,
1179	serge	243	.disable = radeon_legacy_encoder_disable,
1123	serge	244	};
		245
		246
		247	static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
		248	.destroy = radeon_enc_destroy,
		249	};
		250
		251	static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
		252	{
		253	struct drm_device *dev = encoder->dev;
		254	struct radeon_device *rdev = dev->dev_private;
		255	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		256	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
		257	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		258
		259	DRM_DEBUG("\n");
		260
		261	switch (mode) {
		262	case DRM_MODE_DPMS_ON:
		263	crtc_ext_cntl \|= RADEON_CRTC_CRT_ON;
		264	dac_cntl &= ~RADEON_DAC_PDWN;
		265	dac_macro_cntl &= ~(RADEON_DAC_PDWN_R \|
		266	RADEON_DAC_PDWN_G \|
		267	RADEON_DAC_PDWN_B);
		268	break;
		269	case DRM_MODE_DPMS_STANDBY:
		270	case DRM_MODE_DPMS_SUSPEND:
		271	case DRM_MODE_DPMS_OFF:
		272	crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
		273	dac_cntl \|= RADEON_DAC_PDWN;
		274	dac_macro_cntl \|= (RADEON_DAC_PDWN_R \|
		275	RADEON_DAC_PDWN_G \|
		276	RADEON_DAC_PDWN_B);
		277	break;
		278	}
		279
		280	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		281	WREG32(RADEON_DAC_CNTL, dac_cntl);
		282	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		283
		284	if (rdev->is_atom_bios)
		285	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		286	else
		287	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		288	}
		289
		290	static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
		291	{
		292	struct radeon_device *rdev = encoder->dev->dev_private;
		293
		294	if (rdev->is_atom_bios)
		295	radeon_atom_output_lock(encoder, true);
		296	else
		297	radeon_combios_output_lock(encoder, true);
		298	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		299	}
		300
		301	static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
		302	{
		303	struct radeon_device *rdev = encoder->dev->dev_private;
		304
		305	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		306
		307	if (rdev->is_atom_bios)
		308	radeon_atom_output_lock(encoder, false);
		309	else
		310	radeon_combios_output_lock(encoder, false);
		311	}
		312
		313	static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
		314	struct drm_display_mode *mode,
		315	struct drm_display_mode *adjusted_mode)
		316	{
		317	struct drm_device *dev = encoder->dev;
		318	struct radeon_device *rdev = dev->dev_private;
		319	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		320	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		321	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
		322
		323	DRM_DEBUG("\n");
		324
		325	if (radeon_crtc->crtc_id == 0) {
		326	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		327	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		328	~(RADEON_DISP_DAC_SOURCE_MASK);
		329	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		330	} else {
		331	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
		332	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		333	}
		334	} else {
		335	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		336	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		337	~(RADEON_DISP_DAC_SOURCE_MASK);
		338	disp_output_cntl \|= RADEON_DISP_DAC_SOURCE_CRTC2;
		339	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		340	} else {
		341	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC_CLK_SEL;
		342	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		343	}
		344	}
		345
		346	dac_cntl = (RADEON_DAC_MASK_ALL \|
		347	RADEON_DAC_VGA_ADR_EN \|
		348	/* TODO 6-bits */
		349	RADEON_DAC_8BIT_EN);
		350
		351	WREG32_P(RADEON_DAC_CNTL,
		352	dac_cntl,
		353	RADEON_DAC_RANGE_CNTL \|
		354	RADEON_DAC_BLANKING);
		355
		356	if (radeon_encoder->enc_priv) {
		357	struct radeon_encoder_primary_dac p_dac = (struct radeon_encoder_primary_dac )radeon_encoder->enc_priv;
		358	dac_macro_cntl = p_dac->ps2_pdac_adj;
		359	} else
		360	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		361	dac_macro_cntl \|= RADEON_DAC_PDWN_R \| RADEON_DAC_PDWN_G \| RADEON_DAC_PDWN_B;
		362	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		363
		364	if (rdev->is_atom_bios)
		365	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		366	else
		367	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		368	}
		369
		370	static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
		371	struct drm_connector *connector)
		372	{
		373	struct drm_device *dev = encoder->dev;
		374	struct radeon_device *rdev = dev->dev_private;
		375	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
		376	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
		377	enum drm_connector_status found = connector_status_disconnected;
		378	bool color = true;
		379
		380	/* save the regs we need */
		381	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
		382	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		383	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		384	dac_cntl = RREG32(RADEON_DAC_CNTL);
		385	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		386
		387	tmp = vclk_ecp_cntl &
		388	~(RADEON_PIXCLK_ALWAYS_ONb \| RADEON_PIXCLK_DAC_ALWAYS_ONb);
		389	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
		390
		391	tmp = crtc_ext_cntl \| RADEON_CRTC_CRT_ON;
		392	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
		393
		394	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN \|
		395	RADEON_DAC_FORCE_DATA_EN;
		396
		397	if (color)
		398	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		399	else
		400	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		401
		402	if (ASIC_IS_R300(rdev))
		403	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		404	else
		405	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		406
		407	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		408
		409	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK \| RADEON_DAC_PDWN);
		410	tmp \|= RADEON_DAC_RANGE_CNTL_PS2 \| RADEON_DAC_CMP_EN;
		411	WREG32(RADEON_DAC_CNTL, tmp);
		412
		413	tmp &= ~(RADEON_DAC_PDWN_R \|
		414	RADEON_DAC_PDWN_G \|
		415	RADEON_DAC_PDWN_B);
		416
		417	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
		418
		419	udelay(2000);
		420
		421	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
		422	found = connector_status_connected;
		423
		424	/* restore the regs we used */
		425	WREG32(RADEON_DAC_CNTL, dac_cntl);
		426	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		427	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		428	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		429	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
		430
		431	return found;
		432	}
		433
		434	static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
		435	.dpms = radeon_legacy_primary_dac_dpms,
1321	serge	436	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	437	.prepare = radeon_legacy_primary_dac_prepare,
		438	.mode_set = radeon_legacy_primary_dac_mode_set,
		439	.commit = radeon_legacy_primary_dac_commit,
		440	.detect = radeon_legacy_primary_dac_detect,
1179	serge	441	.disable = radeon_legacy_encoder_disable,
1123	serge	442	};
		443
		444
		445	static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
		446	.destroy = radeon_enc_destroy,
		447	};
		448
		449	static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
		450	{
		451	struct drm_device *dev = encoder->dev;
		452	struct radeon_device *rdev = dev->dev_private;
		453	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
		454	DRM_DEBUG("\n");
		455
		456	switch (mode) {
		457	case DRM_MODE_DPMS_ON:
		458	fp_gen_cntl \|= (RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		459	break;
		460	case DRM_MODE_DPMS_STANDBY:
		461	case DRM_MODE_DPMS_SUSPEND:
		462	case DRM_MODE_DPMS_OFF:
		463	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		464	break;
		465	}
		466
		467	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		468
		469	if (rdev->is_atom_bios)
		470	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		471	else
		472	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		473	}
		474
		475	static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
		476	{
		477	struct radeon_device *rdev = encoder->dev->dev_private;
		478
		479	if (rdev->is_atom_bios)
		480	radeon_atom_output_lock(encoder, true);
		481	else
		482	radeon_combios_output_lock(encoder, true);
		483	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
		484	}
		485
		486	static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
		487	{
		488	struct radeon_device *rdev = encoder->dev->dev_private;
		489
		490	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
		491
		492	if (rdev->is_atom_bios)
		493	radeon_atom_output_lock(encoder, true);
		494	else
		495	radeon_combios_output_lock(encoder, true);
		496	}
		497
		498	static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
		499	struct drm_display_mode *mode,
		500	struct drm_display_mode *adjusted_mode)
		501	{
		502	struct drm_device *dev = encoder->dev;
		503	struct radeon_device *rdev = dev->dev_private;
		504	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		505	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		506	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
		507	int i;
		508
		509	DRM_DEBUG("\n");
		510
		511	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
		512	tmp &= 0xfffff;
		513	if (rdev->family == CHIP_RV280) {
		514	/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
		515	tmp ^= (1 << 22);
		516	tmds_pll_cntl ^= (1 << 22);
		517	}
		518
		519	if (radeon_encoder->enc_priv) {
		520	struct radeon_encoder_int_tmds tmds = (struct radeon_encoder_int_tmds )radeon_encoder->enc_priv;
		521
		522	for (i = 0; i < 4; i++) {
		523	if (tmds->tmds_pll[i].freq == 0)
		524	break;
		525	if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
		526	tmp = tmds->tmds_pll[i].value ;
		527	break;
		528	}
		529	}
		530	}
		531
		532	if (ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV280)) {
		533	if (tmp & 0xfff00000)
		534	tmds_pll_cntl = tmp;
		535	else {
		536	tmds_pll_cntl &= 0xfff00000;
		537	tmds_pll_cntl \|= tmp;
		538	}
		539	} else
		540	tmds_pll_cntl = tmp;
		541
		542	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
		543	~(RADEON_TMDS_TRANSMITTER_PLLRST);
		544
		545	if (rdev->family == CHIP_R200 \|\|
		546	rdev->family == CHIP_R100 \|\|
		547	ASIC_IS_R300(rdev))
		548	tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
		549	else /* RV chips got this bit reversed */
		550	tmds_transmitter_cntl \|= RADEON_TMDS_TRANSMITTER_PLLEN;
		551
		552	fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) \|
		553	(RADEON_FP_CRTC_DONT_SHADOW_VPAR \|
		554	RADEON_FP_CRTC_DONT_SHADOW_HEND));
		555
		556	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		557
1268	serge	558	fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN \|
		559	RADEON_FP_DFP_SYNC_SEL \|
		560	RADEON_FP_CRT_SYNC_SEL \|
		561	RADEON_FP_CRTC_LOCK_8DOT \|
		562	RADEON_FP_USE_SHADOW_EN \|
		563	RADEON_FP_CRTC_USE_SHADOW_VEND \|
		564	RADEON_FP_CRT_SYNC_ALT);
		565
1123	serge	566	if (1) /* FIXME rgbBits == 8 */
		567	fp_gen_cntl \|= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
		568	else
		569	fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
		570
		571	if (radeon_crtc->crtc_id == 0) {
		572	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		573	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1179	serge	574	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	575	fp_gen_cntl \|= R200_FP_SOURCE_SEL_RMX;
		576	else
		577	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC1;
		578	} else
1268	serge	579	fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
1123	serge	580	} else {
		581	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		582	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
		583	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC2;
		584	} else
		585	fp_gen_cntl \|= RADEON_FP_SEL_CRTC2;
		586	}
		587
		588	WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
		589	WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
		590	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		591
		592	if (rdev->is_atom_bios)
		593	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		594	else
		595	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		596	}
		597
		598	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
		599	.dpms = radeon_legacy_tmds_int_dpms,
1321	serge	600	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	601	.prepare = radeon_legacy_tmds_int_prepare,
		602	.mode_set = radeon_legacy_tmds_int_mode_set,
		603	.commit = radeon_legacy_tmds_int_commit,
1179	serge	604	.disable = radeon_legacy_encoder_disable,
1123	serge	605	};
		606
		607
		608	static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
		609	.destroy = radeon_enc_destroy,
		610	};
		611
		612	static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
		613	{
		614	struct drm_device *dev = encoder->dev;
		615	struct radeon_device *rdev = dev->dev_private;
		616	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		617	DRM_DEBUG("\n");
		618
		619	switch (mode) {
		620	case DRM_MODE_DPMS_ON:
		621	fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
		622	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		623	break;
		624	case DRM_MODE_DPMS_STANDBY:
		625	case DRM_MODE_DPMS_SUSPEND:
		626	case DRM_MODE_DPMS_OFF:
		627	fp2_gen_cntl \|= RADEON_FP2_BLANK_EN;
		628	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		629	break;
		630	}
		631
		632	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		633
		634	if (rdev->is_atom_bios)
		635	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		636	else
		637	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		638	}
		639
		640	static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
		641	{
		642	struct radeon_device *rdev = encoder->dev->dev_private;
		643
		644	if (rdev->is_atom_bios)
		645	radeon_atom_output_lock(encoder, true);
		646	else
		647	radeon_combios_output_lock(encoder, true);
		648	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
		649	}
		650
		651	static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
		652	{
		653	struct radeon_device *rdev = encoder->dev->dev_private;
		654	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
		655
		656	if (rdev->is_atom_bios)
		657	radeon_atom_output_lock(encoder, false);
		658	else
		659	radeon_combios_output_lock(encoder, false);
		660	}
		661
		662	static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
		663	struct drm_display_mode *mode,
		664	struct drm_display_mode *adjusted_mode)
		665	{
		666	struct drm_device *dev = encoder->dev;
		667	struct radeon_device *rdev = dev->dev_private;
		668	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		669	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		670	uint32_t fp2_gen_cntl;
		671
		672	DRM_DEBUG("\n");
		673
		674	if (rdev->is_atom_bios) {
		675	radeon_encoder->pixel_clock = adjusted_mode->clock;
		676	atombios_external_tmds_setup(encoder, ATOM_ENABLE);
		677	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		678	} else {
		679	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		680
		681	if (1) /* FIXME rgbBits == 8 */
		682	fp2_gen_cntl \|= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
		683	else
		684	fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
		685
		686	fp2_gen_cntl &= ~(RADEON_FP2_ON \|
		687	RADEON_FP2_DVO_EN \|
		688	RADEON_FP2_DVO_RATE_SEL_SDR);
		689
		690	/* XXX: these are oem specific */
		691	if (ASIC_IS_R300(rdev)) {
		692	if ((dev->pdev->device == 0x4850) &&
		693	(dev->pdev->subsystem_vendor == 0x1028) &&
		694	(dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
		695	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
		696	else
		697	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;
		698
		699	/*if (mode->clock > 165000)
		700	fp2_gen_cntl \|= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
		701	}
1321	serge	702	if (!radeon_combios_external_tmds_setup(encoder))
		703	radeon_external_tmds_setup(encoder);
1123	serge	704	}
		705
		706	if (radeon_crtc->crtc_id == 0) {
		707	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		708	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1179	serge	709	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	710	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_RMX;
		711	else
		712	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC1;
		713	} else
		714	fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
		715	} else {
		716	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		717	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
		718	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		719	} else
		720	fp2_gen_cntl \|= RADEON_FP2_SRC_SEL_CRTC2;
		721	}
		722
		723	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		724
		725	if (rdev->is_atom_bios)
		726	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		727	else
		728	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		729	}
		730
1321	serge	731	static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
		732	{
		733	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		734	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		735	if (tmds) {
		736	if (tmds->i2c_bus)
		737	radeon_i2c_destroy(tmds->i2c_bus);
		738	}
		739	kfree(radeon_encoder->enc_priv);
		740	drm_encoder_cleanup(encoder);
		741	kfree(radeon_encoder);
		742	}
		743
1123	serge	744	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
		745	.dpms = radeon_legacy_tmds_ext_dpms,
1321	serge	746	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	747	.prepare = radeon_legacy_tmds_ext_prepare,
		748	.mode_set = radeon_legacy_tmds_ext_mode_set,
		749	.commit = radeon_legacy_tmds_ext_commit,
1179	serge	750	.disable = radeon_legacy_encoder_disable,
1123	serge	751	};
		752
		753
		754	static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1321	serge	755	.destroy = radeon_ext_tmds_enc_destroy,
1123	serge	756	};
		757
		758	static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
		759	{
		760	struct drm_device *dev = encoder->dev;
		761	struct radeon_device *rdev = dev->dev_private;
1179	serge	762	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1123	serge	763	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1179	serge	764	uint32_t tv_master_cntl = 0;
		765	bool is_tv;
1123	serge	766	DRM_DEBUG("\n");
		767
1179	serge	768	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
		769
1123	serge	770	if (rdev->family == CHIP_R200)
		771	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		772	else {
1179	serge	773	if (is_tv)
		774	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		775	else
1123	serge	776	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		777	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		778	}
		779
		780	switch (mode) {
		781	case DRM_MODE_DPMS_ON:
		782	if (rdev->family == CHIP_R200) {
		783	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		784	} else {
1179	serge	785	if (is_tv)
		786	tv_master_cntl \|= RADEON_TV_ON;
		787	else
1123	serge	788	crtc2_gen_cntl \|= RADEON_CRTC2_CRT2_ON;
1179	serge	789
1123	serge	790	if (rdev->family == CHIP_R420 \|\|
		791	rdev->family == CHIP_R423 \|\|
		792	rdev->family == CHIP_RV410)
		793	tv_dac_cntl &= ~(R420_TV_DAC_RDACPD \|
		794	R420_TV_DAC_GDACPD \|
		795	R420_TV_DAC_BDACPD \|
		796	RADEON_TV_DAC_BGSLEEP);
		797	else
		798	tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD \|
		799	RADEON_TV_DAC_GDACPD \|
		800	RADEON_TV_DAC_BDACPD \|
		801	RADEON_TV_DAC_BGSLEEP);
		802	}
		803	break;
		804	case DRM_MODE_DPMS_STANDBY:
		805	case DRM_MODE_DPMS_SUSPEND:
		806	case DRM_MODE_DPMS_OFF:
		807	if (rdev->family == CHIP_R200)
		808	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		809	else {
1179	serge	810	if (is_tv)
		811	tv_master_cntl &= ~RADEON_TV_ON;
		812	else
1123	serge	813	crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1179	serge	814
1123	serge	815	if (rdev->family == CHIP_R420 \|\|
		816	rdev->family == CHIP_R423 \|\|
		817	rdev->family == CHIP_RV410)
		818	tv_dac_cntl \|= (R420_TV_DAC_RDACPD \|
		819	R420_TV_DAC_GDACPD \|
		820	R420_TV_DAC_BDACPD \|
		821	RADEON_TV_DAC_BGSLEEP);
		822	else
		823	tv_dac_cntl \|= (RADEON_TV_DAC_RDACPD \|
		824	RADEON_TV_DAC_GDACPD \|
		825	RADEON_TV_DAC_BDACPD \|
		826	RADEON_TV_DAC_BGSLEEP);
		827	}
		828	break;
		829	}
		830
		831	if (rdev->family == CHIP_R200) {
		832	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		833	} else {
1179	serge	834	if (is_tv)
		835	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		836	else
1123	serge	837	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		838	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		839	}
		840
		841	if (rdev->is_atom_bios)
		842	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		843	else
		844	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		845	}
		846
		847	static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
		848	{
		849	struct radeon_device *rdev = encoder->dev->dev_private;
		850
		851	if (rdev->is_atom_bios)
		852	radeon_atom_output_lock(encoder, true);
		853	else
		854	radeon_combios_output_lock(encoder, true);
		855	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		856	}
		857
		858	static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
		859	{
		860	struct radeon_device *rdev = encoder->dev->dev_private;
		861
		862	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		863
		864	if (rdev->is_atom_bios)
		865	radeon_atom_output_lock(encoder, true);
		866	else
		867	radeon_combios_output_lock(encoder, true);
		868	}
		869
		870	static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
		871	struct drm_display_mode *mode,
		872	struct drm_display_mode *adjusted_mode)
		873	{
		874	struct drm_device *dev = encoder->dev;
		875	struct radeon_device *rdev = dev->dev_private;
		876	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		877	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	878	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	879	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1179	serge	880	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
		881	bool is_tv = false;
1123	serge	882
		883	DRM_DEBUG("\n");
		884
1179	serge	885	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1123	serge	886
		887	if (rdev->family != CHIP_R200) {
		888	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		889	if (rdev->family == CHIP_R420 \|\|
		890	rdev->family == CHIP_R423 \|\|
		891	rdev->family == CHIP_RV410) {
		892	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		893	RADEON_TV_DAC_BGADJ_MASK \|
		894	R420_TV_DAC_DACADJ_MASK \|
		895	R420_TV_DAC_RDACPD \|
		896	R420_TV_DAC_GDACPD \|
1221	serge	897	R420_TV_DAC_BDACPD \|
1123	serge	898	R420_TV_DAC_TVENABLE);
		899	} else {
		900	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		901	RADEON_TV_DAC_BGADJ_MASK \|
		902	RADEON_TV_DAC_DACADJ_MASK \|
		903	RADEON_TV_DAC_RDACPD \|
		904	RADEON_TV_DAC_GDACPD \|
1221	serge	905	RADEON_TV_DAC_BDACPD);
1123	serge	906	}
		907
		908	/* FIXME TV */
1179	serge	909	if (tv_dac) {
1123	serge	910	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
		911	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		912	RADEON_TV_DAC_NHOLD \|
		913	RADEON_TV_DAC_STD_PS2 \|
		914	tv_dac->ps2_tvdac_adj);
		915	} else
		916	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		917	RADEON_TV_DAC_NHOLD \|
		918	RADEON_TV_DAC_STD_PS2);
		919
		920	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		921	}
		922
		923	if (ASIC_IS_R300(rdev)) {
		924	gpiopad_a = RREG32(RADEON_GPIOPAD_A) \| 1;
		925	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1179	serge	926	}
		927
		928	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev))
		929	disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1123	serge	930	else
		931	disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		932
1179	serge	933	if (rdev->family == CHIP_R200)
		934	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		935
		936	if (is_tv) {
		937	uint32_t dac_cntl;
		938
		939	dac_cntl = RREG32(RADEON_DAC_CNTL);
		940	dac_cntl &= ~RADEON_DAC_TVO_EN;
		941	WREG32(RADEON_DAC_CNTL, dac_cntl);
		942
		943	if (ASIC_IS_R300(rdev))
		944	gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
		945
		946	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
		947	if (radeon_crtc->crtc_id == 0) {
		948	if (ASIC_IS_R300(rdev)) {
		949	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		950	disp_output_cntl \|= (RADEON_DISP_TVDAC_SOURCE_CRTC \|
		951	RADEON_DISP_TV_SOURCE_CRTC);
		952	}
		953	if (rdev->family >= CHIP_R200) {
		954	disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
		955	} else {
		956	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		957	}
		958	} else {
		959	if (ASIC_IS_R300(rdev)) {
		960	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		961	disp_output_cntl \|= RADEON_DISP_TV_SOURCE_CRTC;
		962	}
		963	if (rdev->family >= CHIP_R200) {
		964	disp_tv_out_cntl \|= RADEON_DISP_TV_PATH_SRC_CRTC2;
		965	} else {
		966	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		967	}
		968	}
		969	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		970	} else {
		971
1123	serge	972	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC2_CLK_SEL;
		973
		974	if (radeon_crtc->crtc_id == 0) {
		975	if (ASIC_IS_R300(rdev)) {
		976	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		977	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC;
		978	} else if (rdev->family == CHIP_R200) {
		979	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		980	RADEON_FP2_DVO_RATE_SEL_SDR);
		981	} else
		982	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		983	} else {
		984	if (ASIC_IS_R300(rdev)) {
		985	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		986	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		987	} else if (rdev->family == CHIP_R200) {
		988	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		989	RADEON_FP2_DVO_RATE_SEL_SDR);
		990	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		991	} else
		992	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		993	}
		994	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1179	serge	995	}
1123	serge	996
		997	if (ASIC_IS_R300(rdev)) {
		998	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1179	serge	999	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1000	}
		1001
		1002	if (rdev->family >= CHIP_R200)
		1003	WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1123	serge	1004	else
		1005	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1006
1179	serge	1007	if (rdev->family == CHIP_R200)
		1008	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		1009
		1010	if (is_tv)
		1011	radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
		1012
1123	serge	1013	if (rdev->is_atom_bios)
		1014	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1015	else
		1016	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1017
		1018	}
		1019
1179	serge	1020	static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
		1021	struct drm_connector *connector)
		1022	{
		1023	struct drm_device *dev = encoder->dev;
		1024	struct radeon_device *rdev = dev->dev_private;
		1025	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1026	uint32_t disp_output_cntl, gpiopad_a, tmp;
		1027	bool found = false;
		1028
		1029	/* save regs needed */
		1030	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
		1031	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1032	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1033	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1034	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1035	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1036
		1037	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
		1038
		1039	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
		1040
		1041	WREG32(RADEON_CRTC2_GEN_CNTL,
		1042	RADEON_CRTC2_CRT2_ON \| RADEON_CRTC2_VSYNC_TRISTAT);
		1043
		1044	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1045	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1046	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1047
		1048	WREG32(RADEON_DAC_EXT_CNTL,
		1049	RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1050	RADEON_DAC2_FORCE_DATA_EN \|
		1051	RADEON_DAC_FORCE_DATA_SEL_RGB \|
		1052	(0xec << RADEON_DAC_FORCE_DATA_SHIFT));
		1053
		1054	WREG32(RADEON_TV_DAC_CNTL,
		1055	RADEON_TV_DAC_STD_NTSC \|
		1056	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1057	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1058
		1059	RREG32(RADEON_TV_DAC_CNTL);
		1060	mdelay(4);
		1061
		1062	WREG32(RADEON_TV_DAC_CNTL,
		1063	RADEON_TV_DAC_NBLANK \|
		1064	RADEON_TV_DAC_NHOLD \|
		1065	RADEON_TV_MONITOR_DETECT_EN \|
		1066	RADEON_TV_DAC_STD_NTSC \|
		1067	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1068	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1069
		1070	RREG32(RADEON_TV_DAC_CNTL);
		1071	mdelay(6);
		1072
		1073	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1074	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
		1075	found = true;
		1076	DRM_DEBUG("S-video TV connection detected\n");
		1077	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1078	found = true;
		1079	DRM_DEBUG("Composite TV connection detected\n");
		1080	}
		1081
		1082	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1083	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1084	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1085	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1086	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1087	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1088	return found;
		1089	}
		1090
		1091	static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
		1092	struct drm_connector *connector)
		1093	{
		1094	struct drm_device *dev = encoder->dev;
		1095	struct radeon_device *rdev = dev->dev_private;
		1096	uint32_t tv_dac_cntl, dac_cntl2;
		1097	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
		1098	bool found = false;
		1099
		1100	if (ASIC_IS_R300(rdev))
		1101	return r300_legacy_tv_detect(encoder, connector);
		1102
		1103	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1104	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		1105	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1106	config_cntl = RREG32(RADEON_CONFIG_CNTL);
		1107	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
		1108
		1109	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
		1110	WREG32(RADEON_DAC_CNTL2, tmp);
		1111
		1112	tmp = tv_master_cntl \| RADEON_TV_ON;
		1113	tmp &= ~(RADEON_TV_ASYNC_RST \|
		1114	RADEON_RESTART_PHASE_FIX \|
		1115	RADEON_CRT_FIFO_CE_EN \|
		1116	RADEON_TV_FIFO_CE_EN \|
		1117	RADEON_RE_SYNC_NOW_SEL_MASK);
		1118	tmp \|= RADEON_TV_FIFO_ASYNC_RST \| RADEON_CRT_ASYNC_RST;
		1119	WREG32(RADEON_TV_MASTER_CNTL, tmp);
		1120
		1121	tmp = RADEON_TV_DAC_NBLANK \| RADEON_TV_DAC_NHOLD \|
		1122	RADEON_TV_MONITOR_DETECT_EN \| RADEON_TV_DAC_STD_NTSC \|
		1123	(8 << RADEON_TV_DAC_BGADJ_SHIFT);
		1124
		1125	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
		1126	tmp \|= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
		1127	else
		1128	tmp \|= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
		1129	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1130
		1131	tmp = RADEON_C_GRN_EN \| RADEON_CMP_BLU_EN \|
		1132	RADEON_RED_MX_FORCE_DAC_DATA \|
		1133	RADEON_GRN_MX_FORCE_DAC_DATA \|
		1134	RADEON_BLU_MX_FORCE_DAC_DATA \|
		1135	(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
		1136	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
		1137
		1138	mdelay(3);
		1139	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1140	if (tmp & RADEON_TV_DAC_GDACDET) {
		1141	found = true;
		1142	DRM_DEBUG("S-video TV connection detected\n");
		1143	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1144	found = true;
		1145	DRM_DEBUG("Composite TV connection detected\n");
		1146	}
		1147
		1148	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
		1149	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1150	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		1151	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1152	return found;
		1153	}
		1154
1123	serge	1155	static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
		1156	struct drm_connector *connector)
		1157	{
		1158	struct drm_device *dev = encoder->dev;
		1159	struct radeon_device *rdev = dev->dev_private;
		1160	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1161	uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
		1162	enum drm_connector_status found = connector_status_disconnected;
1179	serge	1163	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1164	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	1165	bool color = true;
		1166
1179	serge	1167	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO \|\|
		1168	connector->connector_type == DRM_MODE_CONNECTOR_Composite \|\|
		1169	connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
		1170	bool tv_detect;
1123	serge	1171
1179	serge	1172	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
		1173	return connector_status_disconnected;
		1174
		1175	tv_detect = radeon_legacy_tv_detect(encoder, connector);
		1176	if (tv_detect && tv_dac)
		1177	found = connector_status_connected;
		1178	return found;
		1179	}
		1180
		1181	/* don't probe if the encoder is being used for something else not CRT related */
		1182	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
		1183	DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
		1184	return connector_status_disconnected;
		1185	}
		1186
1123	serge	1187	/* save the regs we need */
		1188	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		1189	gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
		1190	disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
		1191	disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
		1192	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1193	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1194	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1195	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1196
		1197	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
		1198	\| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
		1199	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
		1200
		1201	if (ASIC_IS_R300(rdev))
		1202	WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
		1203
		1204	tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
		1205	tmp \|= RADEON_CRTC2_CRT2_ON \|
		1206	(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
		1207
		1208	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		1209
		1210	if (ASIC_IS_R300(rdev)) {
		1211	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1212	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1213	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1214	} else {
		1215	tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
		1216	WREG32(RADEON_DISP_HW_DEBUG, tmp);
		1217	}
		1218
		1219	tmp = RADEON_TV_DAC_NBLANK \|
		1220	RADEON_TV_DAC_NHOLD \|
		1221	RADEON_TV_MONITOR_DETECT_EN \|
		1222	RADEON_TV_DAC_STD_PS2;
		1223
		1224	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1225
		1226	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1227	RADEON_DAC2_FORCE_DATA_EN;
		1228
		1229	if (color)
		1230	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		1231	else
		1232	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		1233
		1234	if (ASIC_IS_R300(rdev))
		1235	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		1236	else
		1237	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		1238
		1239	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		1240
		1241	tmp = dac_cntl2 \| RADEON_DAC2_DAC2_CLK_SEL \| RADEON_DAC2_CMP_EN;
		1242	WREG32(RADEON_DAC_CNTL2, tmp);
		1243
		1244	udelay(10000);
		1245
		1246	if (ASIC_IS_R300(rdev)) {
		1247	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
		1248	found = connector_status_connected;
		1249	} else {
		1250	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
		1251	found = connector_status_connected;
		1252	}
		1253
		1254	/* restore regs we used */
		1255	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1256	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1257	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1258	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1259
		1260	if (ASIC_IS_R300(rdev)) {
		1261	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1262	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1263	} else {
		1264	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1265	}
		1266	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		1267
1179	serge	1268	return found;
1123	serge	1269
		1270	}
		1271
		1272	static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
		1273	.dpms = radeon_legacy_tv_dac_dpms,
1321	serge	1274	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	1275	.prepare = radeon_legacy_tv_dac_prepare,
		1276	.mode_set = radeon_legacy_tv_dac_mode_set,
		1277	.commit = radeon_legacy_tv_dac_commit,
		1278	.detect = radeon_legacy_tv_dac_detect,
1179	serge	1279	.disable = radeon_legacy_encoder_disable,
1123	serge	1280	};
		1281
		1282
		1283	static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
		1284	.destroy = radeon_enc_destroy,
		1285	};
		1286
1179	serge	1287
		1288	static struct radeon_encoder_int_tmds radeon_legacy_get_tmds_info(struct radeon_encoder encoder)
		1289	{
		1290	struct drm_device *dev = encoder->base.dev;
		1291	struct radeon_device *rdev = dev->dev_private;
		1292	struct radeon_encoder_int_tmds *tmds = NULL;
		1293	bool ret;
		1294
		1295	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
		1296
		1297	if (!tmds)
		1298	return NULL;
		1299
		1300	if (rdev->is_atom_bios)
		1301	ret = radeon_atombios_get_tmds_info(encoder, tmds);
		1302	else
		1303	ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
		1304
		1305	if (ret == false)
		1306	radeon_legacy_get_tmds_info_from_table(encoder, tmds);
		1307
		1308	return tmds;
		1309	}
		1310
1321	serge	1311	static struct radeon_encoder_ext_tmds radeon_legacy_get_ext_tmds_info(struct radeon_encoder encoder)
		1312	{
		1313	struct drm_device *dev = encoder->base.dev;
		1314	struct radeon_device *rdev = dev->dev_private;
		1315	struct radeon_encoder_ext_tmds *tmds = NULL;
		1316	bool ret;
		1317
		1318	if (rdev->is_atom_bios)
		1319	return NULL;
		1320
		1321	tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
		1322
		1323	if (!tmds)
		1324	return NULL;
		1325
		1326	ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
		1327
		1328	if (ret == false)
		1329	radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
		1330
		1331	return tmds;
		1332	}
		1333
1123	serge	1334	void
		1335	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
		1336	{
		1337	struct radeon_device *rdev = dev->dev_private;
		1338	struct drm_encoder *encoder;
		1339	struct radeon_encoder *radeon_encoder;
		1340
		1341	/* see if we already added it */
		1342	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1343	radeon_encoder = to_radeon_encoder(encoder);
		1344	if (radeon_encoder->encoder_id == encoder_id) {
		1345	radeon_encoder->devices \|= supported_device;
		1346	return;
		1347	}
		1348
		1349	}
		1350
		1351	/* add a new one */
		1352	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1353	if (!radeon_encoder)
		1354	return;
		1355
		1356	encoder = &radeon_encoder->base;
1221	serge	1357	if (rdev->flags & RADEON_SINGLE_CRTC)
		1358	encoder->possible_crtcs = 0x1;
		1359	else
1123	serge	1360	encoder->possible_crtcs = 0x3;
		1361
		1362	radeon_encoder->enc_priv = NULL;
		1363
		1364	radeon_encoder->encoder_id = encoder_id;
		1365	radeon_encoder->devices = supported_device;
1179	serge	1366	radeon_encoder->rmx_type = RMX_OFF;
1123	serge	1367
		1368	switch (radeon_encoder->encoder_id) {
		1369	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1179	serge	1370	encoder->possible_crtcs = 0x1;
1123	serge	1371	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1372	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
		1373	if (rdev->is_atom_bios)
		1374	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1375	else
		1376	radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
		1377	radeon_encoder->rmx_type = RMX_FULL;
		1378	break;
		1379	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1380	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1381	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1179	serge	1382	radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1123	serge	1383	break;
		1384	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1385	drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
		1386	drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
		1387	if (rdev->is_atom_bios)
		1388	radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
		1389	else
		1390	radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
		1391	break;
		1392	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1393	drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		1394	drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
		1395	if (rdev->is_atom_bios)
		1396	radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
		1397	else
		1398	radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
		1399	break;
		1400	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1401	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1402	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
		1403	if (!rdev->is_atom_bios)
1321	serge	1404	radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1123	serge	1405	break;
		1406	}
		1407	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_encoders.c – Rev 1403