WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_legacy_encoders.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "drm_crtc_helper.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
1179	serge	32	static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
1123	serge	33	{
		34	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	35	struct drm_encoder_helper_funcs *encoder_funcs;
1123	serge	36
1179	serge	37	encoder_funcs = encoder->helper_private;
		38	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
		39	radeon_encoder->active_device = 0;
1123	serge	40	}
		41
		42	static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
		43	{
		44	struct drm_device *dev = encoder->dev;
		45	struct radeon_device *rdev = dev->dev_private;
		46	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		47	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
		48	int panel_pwr_delay = 2000;
		49	DRM_DEBUG("\n");
		50
		51	if (radeon_encoder->enc_priv) {
		52	if (rdev->is_atom_bios) {
		53	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		54	panel_pwr_delay = lvds->panel_pwr_delay;
		55	} else {
		56	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		57	panel_pwr_delay = lvds->panel_pwr_delay;
		58	}
		59	}
		60
		61	switch (mode) {
		62	case DRM_MODE_DPMS_ON:
		63	disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
		64	disp_pwr_man \|= RADEON_AUTO_PWRUP_EN;
		65	WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
		66	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		67	lvds_pll_cntl \|= RADEON_LVDS_PLL_EN;
		68	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		69	udelay(1000);
		70
		71	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		72	lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
		73	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		74
		75	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		76	lvds_gen_cntl \|= (RADEON_LVDS_ON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON \| RADEON_LVDS_BLON);
		77	lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
		78	udelay(panel_pwr_delay * 1000);
		79	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		80	break;
		81	case DRM_MODE_DPMS_STANDBY:
		82	case DRM_MODE_DPMS_SUSPEND:
		83	case DRM_MODE_DPMS_OFF:
		84	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		85	WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
		86	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		87	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		88	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_BLON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON);
		89	udelay(panel_pwr_delay * 1000);
		90	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		91	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		92	break;
		93	}
		94
		95	if (rdev->is_atom_bios)
		96	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		97	else
		98	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		99	}
		100
		101	static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
		102	{
		103	struct radeon_device *rdev = encoder->dev->dev_private;
		104
		105	if (rdev->is_atom_bios)
		106	radeon_atom_output_lock(encoder, true);
		107	else
		108	radeon_combios_output_lock(encoder, true);
		109	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
1179	serge	110
		111	radeon_encoder_set_active_device(encoder);
1123	serge	112	}
		113
		114	static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
		115	{
		116	struct radeon_device *rdev = encoder->dev->dev_private;
		117
		118	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
		119	if (rdev->is_atom_bios)
		120	radeon_atom_output_lock(encoder, false);
		121	else
		122	radeon_combios_output_lock(encoder, false);
		123	}
		124
		125	static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
		126	struct drm_display_mode *mode,
		127	struct drm_display_mode *adjusted_mode)
		128	{
		129	struct drm_device *dev = encoder->dev;
		130	struct radeon_device *rdev = dev->dev_private;
		131	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		132	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		133	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
		134
		135	DRM_DEBUG("\n");
		136
		137	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		138	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
		139
		140	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		141	if ((!rdev->is_atom_bios)) {
		142	struct radeon_encoder_lvds lvds = (struct radeon_encoder_lvds )radeon_encoder->enc_priv;
		143	if (lvds) {
		144	DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
		145	lvds_gen_cntl = lvds->lvds_gen_cntl;
		146	lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		147	(0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		148	lvds_ss_gen_cntl \|= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		149	(lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		150	} else
		151	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		152	} else
		153	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		154	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		155	lvds_gen_cntl &= ~(RADEON_LVDS_ON \|
		156	RADEON_LVDS_BLON \|
		157	RADEON_LVDS_EN \|
		158	RADEON_LVDS_RST_FM);
		159
		160	if (ASIC_IS_R300(rdev))
		161	lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
		162
		163	if (radeon_crtc->crtc_id == 0) {
		164	if (ASIC_IS_R300(rdev)) {
1179	serge	165	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	166	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_RMX;
		167	} else
		168	lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
		169	} else {
		170	if (ASIC_IS_R300(rdev))
		171	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_CRTC2;
		172	else
		173	lvds_gen_cntl \|= RADEON_LVDS_SEL_CRTC2;
		174	}
		175
		176	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		177	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		178	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
		179
		180	if (rdev->family == CHIP_RV410)
		181	WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
		182
		183	if (rdev->is_atom_bios)
		184	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		185	else
		186	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		187	}
		188
		189	static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
		190	struct drm_display_mode *mode,
		191	struct drm_display_mode *adjusted_mode)
		192	{
		193	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		194
		195	drm_mode_set_crtcinfo(adjusted_mode, 0);
		196
		197	if (radeon_encoder->rmx_type != RMX_OFF)
		198	radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
		199
		200	return true;
		201	}
		202
		203	static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
		204	.dpms = radeon_legacy_lvds_dpms,
		205	.mode_fixup = radeon_legacy_lvds_mode_fixup,
		206	.prepare = radeon_legacy_lvds_prepare,
		207	.mode_set = radeon_legacy_lvds_mode_set,
		208	.commit = radeon_legacy_lvds_commit,
1179	serge	209	.disable = radeon_legacy_encoder_disable,
1123	serge	210	};
		211
		212
		213	static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
		214	.destroy = radeon_enc_destroy,
		215	};
		216
		217	static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
		218	struct drm_display_mode *mode,
		219	struct drm_display_mode *adjusted_mode)
		220	{
		221
		222	drm_mode_set_crtcinfo(adjusted_mode, 0);
		223
		224	return true;
		225	}
		226
		227	static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
		228	{
		229	struct drm_device *dev = encoder->dev;
		230	struct radeon_device *rdev = dev->dev_private;
		231	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		232	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
		233	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		234
		235	DRM_DEBUG("\n");
		236
		237	switch (mode) {
		238	case DRM_MODE_DPMS_ON:
		239	crtc_ext_cntl \|= RADEON_CRTC_CRT_ON;
		240	dac_cntl &= ~RADEON_DAC_PDWN;
		241	dac_macro_cntl &= ~(RADEON_DAC_PDWN_R \|
		242	RADEON_DAC_PDWN_G \|
		243	RADEON_DAC_PDWN_B);
		244	break;
		245	case DRM_MODE_DPMS_STANDBY:
		246	case DRM_MODE_DPMS_SUSPEND:
		247	case DRM_MODE_DPMS_OFF:
		248	crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
		249	dac_cntl \|= RADEON_DAC_PDWN;
		250	dac_macro_cntl \|= (RADEON_DAC_PDWN_R \|
		251	RADEON_DAC_PDWN_G \|
		252	RADEON_DAC_PDWN_B);
		253	break;
		254	}
		255
		256	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		257	WREG32(RADEON_DAC_CNTL, dac_cntl);
		258	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		259
		260	if (rdev->is_atom_bios)
		261	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		262	else
		263	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		264	}
		265
		266	static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
		267	{
		268	struct radeon_device *rdev = encoder->dev->dev_private;
		269
		270	if (rdev->is_atom_bios)
		271	radeon_atom_output_lock(encoder, true);
		272	else
		273	radeon_combios_output_lock(encoder, true);
		274	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1179	serge	275	radeon_encoder_set_active_device(encoder);
1123	serge	276	}
		277
		278	static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
		279	{
		280	struct radeon_device *rdev = encoder->dev->dev_private;
		281
		282	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		283
		284	if (rdev->is_atom_bios)
		285	radeon_atom_output_lock(encoder, false);
		286	else
		287	radeon_combios_output_lock(encoder, false);
		288	}
		289
		290	static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
		291	struct drm_display_mode *mode,
		292	struct drm_display_mode *adjusted_mode)
		293	{
		294	struct drm_device *dev = encoder->dev;
		295	struct radeon_device *rdev = dev->dev_private;
		296	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		297	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		298	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
		299
		300	DRM_DEBUG("\n");
		301
		302	if (radeon_crtc->crtc_id == 0) {
		303	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		304	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		305	~(RADEON_DISP_DAC_SOURCE_MASK);
		306	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		307	} else {
		308	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
		309	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		310	}
		311	} else {
		312	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		313	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		314	~(RADEON_DISP_DAC_SOURCE_MASK);
		315	disp_output_cntl \|= RADEON_DISP_DAC_SOURCE_CRTC2;
		316	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		317	} else {
		318	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC_CLK_SEL;
		319	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		320	}
		321	}
		322
		323	dac_cntl = (RADEON_DAC_MASK_ALL \|
		324	RADEON_DAC_VGA_ADR_EN \|
		325	/* TODO 6-bits */
		326	RADEON_DAC_8BIT_EN);
		327
		328	WREG32_P(RADEON_DAC_CNTL,
		329	dac_cntl,
		330	RADEON_DAC_RANGE_CNTL \|
		331	RADEON_DAC_BLANKING);
		332
		333	if (radeon_encoder->enc_priv) {
		334	struct radeon_encoder_primary_dac p_dac = (struct radeon_encoder_primary_dac )radeon_encoder->enc_priv;
		335	dac_macro_cntl = p_dac->ps2_pdac_adj;
		336	} else
		337	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		338	dac_macro_cntl \|= RADEON_DAC_PDWN_R \| RADEON_DAC_PDWN_G \| RADEON_DAC_PDWN_B;
		339	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		340
		341	if (rdev->is_atom_bios)
		342	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		343	else
		344	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		345	}
		346
		347	static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
		348	struct drm_connector *connector)
		349	{
		350	struct drm_device *dev = encoder->dev;
		351	struct radeon_device *rdev = dev->dev_private;
		352	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
		353	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
		354	enum drm_connector_status found = connector_status_disconnected;
		355	bool color = true;
		356
		357	/* save the regs we need */
		358	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
		359	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		360	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		361	dac_cntl = RREG32(RADEON_DAC_CNTL);
		362	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		363
		364	tmp = vclk_ecp_cntl &
		365	~(RADEON_PIXCLK_ALWAYS_ONb \| RADEON_PIXCLK_DAC_ALWAYS_ONb);
		366	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
		367
		368	tmp = crtc_ext_cntl \| RADEON_CRTC_CRT_ON;
		369	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
		370
		371	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN \|
		372	RADEON_DAC_FORCE_DATA_EN;
		373
		374	if (color)
		375	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		376	else
		377	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		378
		379	if (ASIC_IS_R300(rdev))
		380	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		381	else
		382	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		383
		384	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		385
		386	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK \| RADEON_DAC_PDWN);
		387	tmp \|= RADEON_DAC_RANGE_CNTL_PS2 \| RADEON_DAC_CMP_EN;
		388	WREG32(RADEON_DAC_CNTL, tmp);
		389
		390	tmp &= ~(RADEON_DAC_PDWN_R \|
		391	RADEON_DAC_PDWN_G \|
		392	RADEON_DAC_PDWN_B);
		393
		394	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
		395
		396	udelay(2000);
		397
		398	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
		399	found = connector_status_connected;
		400
		401	/* restore the regs we used */
		402	WREG32(RADEON_DAC_CNTL, dac_cntl);
		403	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		404	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		405	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		406	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
		407
		408	return found;
		409	}
		410
		411	static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
		412	.dpms = radeon_legacy_primary_dac_dpms,
		413	.mode_fixup = radeon_legacy_primary_dac_mode_fixup,
		414	.prepare = radeon_legacy_primary_dac_prepare,
		415	.mode_set = radeon_legacy_primary_dac_mode_set,
		416	.commit = radeon_legacy_primary_dac_commit,
		417	.detect = radeon_legacy_primary_dac_detect,
1179	serge	418	.disable = radeon_legacy_encoder_disable,
1123	serge	419	};
		420
		421
		422	static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
		423	.destroy = radeon_enc_destroy,
		424	};
		425
		426	static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
		427	struct drm_display_mode *mode,
		428	struct drm_display_mode *adjusted_mode)
		429	{
		430
		431	drm_mode_set_crtcinfo(adjusted_mode, 0);
		432
		433	return true;
		434	}
		435
		436	static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
		437	{
		438	struct drm_device *dev = encoder->dev;
		439	struct radeon_device *rdev = dev->dev_private;
		440	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
		441	DRM_DEBUG("\n");
		442
		443	switch (mode) {
		444	case DRM_MODE_DPMS_ON:
		445	fp_gen_cntl \|= (RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		446	break;
		447	case DRM_MODE_DPMS_STANDBY:
		448	case DRM_MODE_DPMS_SUSPEND:
		449	case DRM_MODE_DPMS_OFF:
		450	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		451	break;
		452	}
		453
		454	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		455
		456	if (rdev->is_atom_bios)
		457	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		458	else
		459	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		460	}
		461
		462	static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
		463	{
		464	struct radeon_device *rdev = encoder->dev->dev_private;
		465
		466	if (rdev->is_atom_bios)
		467	radeon_atom_output_lock(encoder, true);
		468	else
		469	radeon_combios_output_lock(encoder, true);
		470	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
1179	serge	471	radeon_encoder_set_active_device(encoder);
1123	serge	472	}
		473
		474	static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
		475	{
		476	struct radeon_device *rdev = encoder->dev->dev_private;
		477
		478	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
		479
		480	if (rdev->is_atom_bios)
		481	radeon_atom_output_lock(encoder, true);
		482	else
		483	radeon_combios_output_lock(encoder, true);
		484	}
		485
		486	static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
		487	struct drm_display_mode *mode,
		488	struct drm_display_mode *adjusted_mode)
		489	{
		490	struct drm_device *dev = encoder->dev;
		491	struct radeon_device *rdev = dev->dev_private;
		492	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		493	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		494	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
		495	int i;
		496
		497	DRM_DEBUG("\n");
		498
		499	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
		500	tmp &= 0xfffff;
		501	if (rdev->family == CHIP_RV280) {
		502	/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
		503	tmp ^= (1 << 22);
		504	tmds_pll_cntl ^= (1 << 22);
		505	}
		506
		507	if (radeon_encoder->enc_priv) {
		508	struct radeon_encoder_int_tmds tmds = (struct radeon_encoder_int_tmds )radeon_encoder->enc_priv;
		509
		510	for (i = 0; i < 4; i++) {
		511	if (tmds->tmds_pll[i].freq == 0)
		512	break;
		513	if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
		514	tmp = tmds->tmds_pll[i].value ;
		515	break;
		516	}
		517	}
		518	}
		519
		520	if (ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV280)) {
		521	if (tmp & 0xfff00000)
		522	tmds_pll_cntl = tmp;
		523	else {
		524	tmds_pll_cntl &= 0xfff00000;
		525	tmds_pll_cntl \|= tmp;
		526	}
		527	} else
		528	tmds_pll_cntl = tmp;
		529
		530	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
		531	~(RADEON_TMDS_TRANSMITTER_PLLRST);
		532
		533	if (rdev->family == CHIP_R200 \|\|
		534	rdev->family == CHIP_R100 \|\|
		535	ASIC_IS_R300(rdev))
		536	tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
		537	else /* RV chips got this bit reversed */
		538	tmds_transmitter_cntl \|= RADEON_TMDS_TRANSMITTER_PLLEN;
		539
		540	fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) \|
		541	(RADEON_FP_CRTC_DONT_SHADOW_VPAR \|
		542	RADEON_FP_CRTC_DONT_SHADOW_HEND));
		543
		544	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		545
		546	if (1) /* FIXME rgbBits == 8 */
		547	fp_gen_cntl \|= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
		548	else
		549	fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
		550
		551	if (radeon_crtc->crtc_id == 0) {
		552	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		553	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1179	serge	554	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	555	fp_gen_cntl \|= R200_FP_SOURCE_SEL_RMX;
		556	else
		557	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC1;
		558	} else
		559	fp_gen_cntl \|= RADEON_FP_SEL_CRTC1;
		560	} else {
		561	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		562	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
		563	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC2;
		564	} else
		565	fp_gen_cntl \|= RADEON_FP_SEL_CRTC2;
		566	}
		567
		568	WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
		569	WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
		570	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		571
		572	if (rdev->is_atom_bios)
		573	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		574	else
		575	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		576	}
		577
		578	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
		579	.dpms = radeon_legacy_tmds_int_dpms,
		580	.mode_fixup = radeon_legacy_tmds_int_mode_fixup,
		581	.prepare = radeon_legacy_tmds_int_prepare,
		582	.mode_set = radeon_legacy_tmds_int_mode_set,
		583	.commit = radeon_legacy_tmds_int_commit,
1179	serge	584	.disable = radeon_legacy_encoder_disable,
1123	serge	585	};
		586
		587
		588	static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
		589	.destroy = radeon_enc_destroy,
		590	};
		591
		592	static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
		593	struct drm_display_mode *mode,
		594	struct drm_display_mode *adjusted_mode)
		595	{
		596
		597	drm_mode_set_crtcinfo(adjusted_mode, 0);
		598
		599	return true;
		600	}
		601
		602	static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
		603	{
		604	struct drm_device *dev = encoder->dev;
		605	struct radeon_device *rdev = dev->dev_private;
		606	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		607	DRM_DEBUG("\n");
		608
		609	switch (mode) {
		610	case DRM_MODE_DPMS_ON:
		611	fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
		612	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		613	break;
		614	case DRM_MODE_DPMS_STANDBY:
		615	case DRM_MODE_DPMS_SUSPEND:
		616	case DRM_MODE_DPMS_OFF:
		617	fp2_gen_cntl \|= RADEON_FP2_BLANK_EN;
		618	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		619	break;
		620	}
		621
		622	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		623
		624	if (rdev->is_atom_bios)
		625	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		626	else
		627	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		628	}
		629
		630	static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
		631	{
		632	struct radeon_device *rdev = encoder->dev->dev_private;
		633
		634	if (rdev->is_atom_bios)
		635	radeon_atom_output_lock(encoder, true);
		636	else
		637	radeon_combios_output_lock(encoder, true);
		638	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
1179	serge	639	radeon_encoder_set_active_device(encoder);
1123	serge	640	}
		641
		642	static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
		643	{
		644	struct radeon_device *rdev = encoder->dev->dev_private;
		645	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
		646
		647	if (rdev->is_atom_bios)
		648	radeon_atom_output_lock(encoder, false);
		649	else
		650	radeon_combios_output_lock(encoder, false);
		651	}
		652
		653	static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
		654	struct drm_display_mode *mode,
		655	struct drm_display_mode *adjusted_mode)
		656	{
		657	struct drm_device *dev = encoder->dev;
		658	struct radeon_device *rdev = dev->dev_private;
		659	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		660	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		661	uint32_t fp2_gen_cntl;
		662
		663	DRM_DEBUG("\n");
		664
		665	if (rdev->is_atom_bios) {
		666	radeon_encoder->pixel_clock = adjusted_mode->clock;
		667	atombios_external_tmds_setup(encoder, ATOM_ENABLE);
		668	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		669	} else {
		670	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		671
		672	if (1) /* FIXME rgbBits == 8 */
		673	fp2_gen_cntl \|= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
		674	else
		675	fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
		676
		677	fp2_gen_cntl &= ~(RADEON_FP2_ON \|
		678	RADEON_FP2_DVO_EN \|
		679	RADEON_FP2_DVO_RATE_SEL_SDR);
		680
		681	/* XXX: these are oem specific */
		682	if (ASIC_IS_R300(rdev)) {
		683	if ((dev->pdev->device == 0x4850) &&
		684	(dev->pdev->subsystem_vendor == 0x1028) &&
		685	(dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
		686	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
		687	else
		688	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;
		689
		690	/*if (mode->clock > 165000)
		691	fp2_gen_cntl \|= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
		692	}
		693	}
		694
		695	if (radeon_crtc->crtc_id == 0) {
		696	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		697	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1179	serge	698	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	699	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_RMX;
		700	else
		701	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC1;
		702	} else
		703	fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
		704	} else {
		705	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		706	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
		707	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		708	} else
		709	fp2_gen_cntl \|= RADEON_FP2_SRC_SEL_CRTC2;
		710	}
		711
		712	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		713
		714	if (rdev->is_atom_bios)
		715	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		716	else
		717	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		718	}
		719
		720	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
		721	.dpms = radeon_legacy_tmds_ext_dpms,
		722	.mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
		723	.prepare = radeon_legacy_tmds_ext_prepare,
		724	.mode_set = radeon_legacy_tmds_ext_mode_set,
		725	.commit = radeon_legacy_tmds_ext_commit,
1179	serge	726	.disable = radeon_legacy_encoder_disable,
1123	serge	727	};
		728
		729
		730	static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
		731	.destroy = radeon_enc_destroy,
		732	};
		733
		734	static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
		735	struct drm_display_mode *mode,
		736	struct drm_display_mode *adjusted_mode)
		737	{
		738
		739	drm_mode_set_crtcinfo(adjusted_mode, 0);
		740
		741	return true;
		742	}
		743
		744	static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
		745	{
		746	struct drm_device *dev = encoder->dev;
		747	struct radeon_device *rdev = dev->dev_private;
1179	serge	748	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1123	serge	749	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1179	serge	750	uint32_t tv_master_cntl = 0;
		751	bool is_tv;
1123	serge	752	DRM_DEBUG("\n");
		753
1179	serge	754	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
		755
1123	serge	756	if (rdev->family == CHIP_R200)
		757	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		758	else {
1179	serge	759	if (is_tv)
		760	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		761	else
1123	serge	762	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		763	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		764	}
		765
		766	switch (mode) {
		767	case DRM_MODE_DPMS_ON:
		768	if (rdev->family == CHIP_R200) {
		769	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		770	} else {
1179	serge	771	if (is_tv)
		772	tv_master_cntl \|= RADEON_TV_ON;
		773	else
1123	serge	774	crtc2_gen_cntl \|= RADEON_CRTC2_CRT2_ON;
1179	serge	775
1123	serge	776	if (rdev->family == CHIP_R420 \|\|
		777	rdev->family == CHIP_R423 \|\|
		778	rdev->family == CHIP_RV410)
		779	tv_dac_cntl &= ~(R420_TV_DAC_RDACPD \|
		780	R420_TV_DAC_GDACPD \|
		781	R420_TV_DAC_BDACPD \|
		782	RADEON_TV_DAC_BGSLEEP);
		783	else
		784	tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD \|
		785	RADEON_TV_DAC_GDACPD \|
		786	RADEON_TV_DAC_BDACPD \|
		787	RADEON_TV_DAC_BGSLEEP);
		788	}
		789	break;
		790	case DRM_MODE_DPMS_STANDBY:
		791	case DRM_MODE_DPMS_SUSPEND:
		792	case DRM_MODE_DPMS_OFF:
		793	if (rdev->family == CHIP_R200)
		794	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		795	else {
1179	serge	796	if (is_tv)
		797	tv_master_cntl &= ~RADEON_TV_ON;
		798	else
1123	serge	799	crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1179	serge	800
1123	serge	801	if (rdev->family == CHIP_R420 \|\|
		802	rdev->family == CHIP_R423 \|\|
		803	rdev->family == CHIP_RV410)
		804	tv_dac_cntl \|= (R420_TV_DAC_RDACPD \|
		805	R420_TV_DAC_GDACPD \|
		806	R420_TV_DAC_BDACPD \|
		807	RADEON_TV_DAC_BGSLEEP);
		808	else
		809	tv_dac_cntl \|= (RADEON_TV_DAC_RDACPD \|
		810	RADEON_TV_DAC_GDACPD \|
		811	RADEON_TV_DAC_BDACPD \|
		812	RADEON_TV_DAC_BGSLEEP);
		813	}
		814	break;
		815	}
		816
		817	if (rdev->family == CHIP_R200) {
		818	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		819	} else {
1179	serge	820	if (is_tv)
		821	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		822	else
1123	serge	823	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		824	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		825	}
		826
		827	if (rdev->is_atom_bios)
		828	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		829	else
		830	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		831	}
		832
		833	static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
		834	{
		835	struct radeon_device *rdev = encoder->dev->dev_private;
		836
		837	if (rdev->is_atom_bios)
		838	radeon_atom_output_lock(encoder, true);
		839	else
		840	radeon_combios_output_lock(encoder, true);
		841	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1179	serge	842	radeon_encoder_set_active_device(encoder);
1123	serge	843	}
		844
		845	static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
		846	{
		847	struct radeon_device *rdev = encoder->dev->dev_private;
		848
		849	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		850
		851	if (rdev->is_atom_bios)
		852	radeon_atom_output_lock(encoder, true);
		853	else
		854	radeon_combios_output_lock(encoder, true);
		855	}
		856
		857	static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
		858	struct drm_display_mode *mode,
		859	struct drm_display_mode *adjusted_mode)
		860	{
		861	struct drm_device *dev = encoder->dev;
		862	struct radeon_device *rdev = dev->dev_private;
		863	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		864	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	865	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	866	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1179	serge	867	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
		868	bool is_tv = false;
1123	serge	869
		870	DRM_DEBUG("\n");
		871
1179	serge	872	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1123	serge	873
		874	if (rdev->family != CHIP_R200) {
		875	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		876	if (rdev->family == CHIP_R420 \|\|
		877	rdev->family == CHIP_R423 \|\|
		878	rdev->family == CHIP_RV410) {
		879	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		880	RADEON_TV_DAC_BGADJ_MASK \|
		881	R420_TV_DAC_DACADJ_MASK \|
		882	R420_TV_DAC_RDACPD \|
		883	R420_TV_DAC_GDACPD \|
		884	R420_TV_DAC_GDACPD \|
		885	R420_TV_DAC_TVENABLE);
		886	} else {
		887	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		888	RADEON_TV_DAC_BGADJ_MASK \|
		889	RADEON_TV_DAC_DACADJ_MASK \|
		890	RADEON_TV_DAC_RDACPD \|
		891	RADEON_TV_DAC_GDACPD \|
		892	RADEON_TV_DAC_GDACPD);
		893	}
		894
		895	/* FIXME TV */
1179	serge	896	if (tv_dac) {
1123	serge	897	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
		898	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		899	RADEON_TV_DAC_NHOLD \|
		900	RADEON_TV_DAC_STD_PS2 \|
		901	tv_dac->ps2_tvdac_adj);
		902	} else
		903	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		904	RADEON_TV_DAC_NHOLD \|
		905	RADEON_TV_DAC_STD_PS2);
		906
		907	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		908	}
		909
		910	if (ASIC_IS_R300(rdev)) {
		911	gpiopad_a = RREG32(RADEON_GPIOPAD_A) \| 1;
		912	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1179	serge	913	}
		914
		915	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev))
		916	disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1123	serge	917	else
		918	disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		919
1179	serge	920	if (rdev->family == CHIP_R200)
		921	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		922
		923	if (is_tv) {
		924	uint32_t dac_cntl;
		925
		926	dac_cntl = RREG32(RADEON_DAC_CNTL);
		927	dac_cntl &= ~RADEON_DAC_TVO_EN;
		928	WREG32(RADEON_DAC_CNTL, dac_cntl);
		929
		930	if (ASIC_IS_R300(rdev))
		931	gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
		932
		933	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
		934	if (radeon_crtc->crtc_id == 0) {
		935	if (ASIC_IS_R300(rdev)) {
		936	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		937	disp_output_cntl \|= (RADEON_DISP_TVDAC_SOURCE_CRTC \|
		938	RADEON_DISP_TV_SOURCE_CRTC);
		939	}
		940	if (rdev->family >= CHIP_R200) {
		941	disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
		942	} else {
		943	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		944	}
		945	} else {
		946	if (ASIC_IS_R300(rdev)) {
		947	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		948	disp_output_cntl \|= RADEON_DISP_TV_SOURCE_CRTC;
		949	}
		950	if (rdev->family >= CHIP_R200) {
		951	disp_tv_out_cntl \|= RADEON_DISP_TV_PATH_SRC_CRTC2;
		952	} else {
		953	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		954	}
		955	}
		956	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		957	} else {
		958
1123	serge	959	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC2_CLK_SEL;
		960
		961	if (radeon_crtc->crtc_id == 0) {
		962	if (ASIC_IS_R300(rdev)) {
		963	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		964	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC;
		965	} else if (rdev->family == CHIP_R200) {
		966	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		967	RADEON_FP2_DVO_RATE_SEL_SDR);
		968	} else
		969	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		970	} else {
		971	if (ASIC_IS_R300(rdev)) {
		972	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		973	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		974	} else if (rdev->family == CHIP_R200) {
		975	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		976	RADEON_FP2_DVO_RATE_SEL_SDR);
		977	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		978	} else
		979	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		980	}
		981	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1179	serge	982	}
1123	serge	983
		984	if (ASIC_IS_R300(rdev)) {
		985	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1179	serge	986	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		987	}
		988
		989	if (rdev->family >= CHIP_R200)
		990	WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1123	serge	991	else
		992	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		993
1179	serge	994	if (rdev->family == CHIP_R200)
		995	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		996
		997	if (is_tv)
		998	radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
		999
1123	serge	1000	if (rdev->is_atom_bios)
		1001	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1002	else
		1003	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1004
		1005	}
		1006
1179	serge	1007	static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
		1008	struct drm_connector *connector)
		1009	{
		1010	struct drm_device *dev = encoder->dev;
		1011	struct radeon_device *rdev = dev->dev_private;
		1012	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1013	uint32_t disp_output_cntl, gpiopad_a, tmp;
		1014	bool found = false;
		1015
		1016	/* save regs needed */
		1017	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
		1018	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1019	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1020	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1021	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1022	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1023
		1024	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
		1025
		1026	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
		1027
		1028	WREG32(RADEON_CRTC2_GEN_CNTL,
		1029	RADEON_CRTC2_CRT2_ON \| RADEON_CRTC2_VSYNC_TRISTAT);
		1030
		1031	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1032	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1033	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1034
		1035	WREG32(RADEON_DAC_EXT_CNTL,
		1036	RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1037	RADEON_DAC2_FORCE_DATA_EN \|
		1038	RADEON_DAC_FORCE_DATA_SEL_RGB \|
		1039	(0xec << RADEON_DAC_FORCE_DATA_SHIFT));
		1040
		1041	WREG32(RADEON_TV_DAC_CNTL,
		1042	RADEON_TV_DAC_STD_NTSC \|
		1043	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1044	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1045
		1046	RREG32(RADEON_TV_DAC_CNTL);
		1047	mdelay(4);
		1048
		1049	WREG32(RADEON_TV_DAC_CNTL,
		1050	RADEON_TV_DAC_NBLANK \|
		1051	RADEON_TV_DAC_NHOLD \|
		1052	RADEON_TV_MONITOR_DETECT_EN \|
		1053	RADEON_TV_DAC_STD_NTSC \|
		1054	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1055	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1056
		1057	RREG32(RADEON_TV_DAC_CNTL);
		1058	mdelay(6);
		1059
		1060	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1061	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
		1062	found = true;
		1063	DRM_DEBUG("S-video TV connection detected\n");
		1064	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1065	found = true;
		1066	DRM_DEBUG("Composite TV connection detected\n");
		1067	}
		1068
		1069	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1070	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1071	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1072	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1073	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1074	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1075	return found;
		1076	}
		1077
		1078	static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
		1079	struct drm_connector *connector)
		1080	{
		1081	struct drm_device *dev = encoder->dev;
		1082	struct radeon_device *rdev = dev->dev_private;
		1083	uint32_t tv_dac_cntl, dac_cntl2;
		1084	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
		1085	bool found = false;
		1086
		1087	if (ASIC_IS_R300(rdev))
		1088	return r300_legacy_tv_detect(encoder, connector);
		1089
		1090	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1091	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		1092	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1093	config_cntl = RREG32(RADEON_CONFIG_CNTL);
		1094	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
		1095
		1096	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
		1097	WREG32(RADEON_DAC_CNTL2, tmp);
		1098
		1099	tmp = tv_master_cntl \| RADEON_TV_ON;
		1100	tmp &= ~(RADEON_TV_ASYNC_RST \|
		1101	RADEON_RESTART_PHASE_FIX \|
		1102	RADEON_CRT_FIFO_CE_EN \|
		1103	RADEON_TV_FIFO_CE_EN \|
		1104	RADEON_RE_SYNC_NOW_SEL_MASK);
		1105	tmp \|= RADEON_TV_FIFO_ASYNC_RST \| RADEON_CRT_ASYNC_RST;
		1106	WREG32(RADEON_TV_MASTER_CNTL, tmp);
		1107
		1108	tmp = RADEON_TV_DAC_NBLANK \| RADEON_TV_DAC_NHOLD \|
		1109	RADEON_TV_MONITOR_DETECT_EN \| RADEON_TV_DAC_STD_NTSC \|
		1110	(8 << RADEON_TV_DAC_BGADJ_SHIFT);
		1111
		1112	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
		1113	tmp \|= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
		1114	else
		1115	tmp \|= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
		1116	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1117
		1118	tmp = RADEON_C_GRN_EN \| RADEON_CMP_BLU_EN \|
		1119	RADEON_RED_MX_FORCE_DAC_DATA \|
		1120	RADEON_GRN_MX_FORCE_DAC_DATA \|
		1121	RADEON_BLU_MX_FORCE_DAC_DATA \|
		1122	(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
		1123	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
		1124
		1125	mdelay(3);
		1126	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1127	if (tmp & RADEON_TV_DAC_GDACDET) {
		1128	found = true;
		1129	DRM_DEBUG("S-video TV connection detected\n");
		1130	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1131	found = true;
		1132	DRM_DEBUG("Composite TV connection detected\n");
		1133	}
		1134
		1135	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
		1136	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1137	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		1138	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1139	return found;
		1140	}
		1141
1123	serge	1142	static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
		1143	struct drm_connector *connector)
		1144	{
		1145	struct drm_device *dev = encoder->dev;
		1146	struct radeon_device *rdev = dev->dev_private;
		1147	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1148	uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
		1149	enum drm_connector_status found = connector_status_disconnected;
1179	serge	1150	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1151	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	1152	bool color = true;
		1153
1179	serge	1154	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO \|\|
		1155	connector->connector_type == DRM_MODE_CONNECTOR_Composite \|\|
		1156	connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
		1157	bool tv_detect;
1123	serge	1158
1179	serge	1159	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
		1160	return connector_status_disconnected;
		1161
		1162	tv_detect = radeon_legacy_tv_detect(encoder, connector);
		1163	if (tv_detect && tv_dac)
		1164	found = connector_status_connected;
		1165	return found;
		1166	}
		1167
		1168	/* don't probe if the encoder is being used for something else not CRT related */
		1169	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
		1170	DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
		1171	return connector_status_disconnected;
		1172	}
		1173
1123	serge	1174	/* save the regs we need */
		1175	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		1176	gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
		1177	disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
		1178	disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
		1179	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1180	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1181	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1182	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1183
		1184	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
		1185	\| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
		1186	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
		1187
		1188	if (ASIC_IS_R300(rdev))
		1189	WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
		1190
		1191	tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
		1192	tmp \|= RADEON_CRTC2_CRT2_ON \|
		1193	(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
		1194
		1195	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		1196
		1197	if (ASIC_IS_R300(rdev)) {
		1198	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1199	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1200	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1201	} else {
		1202	tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
		1203	WREG32(RADEON_DISP_HW_DEBUG, tmp);
		1204	}
		1205
		1206	tmp = RADEON_TV_DAC_NBLANK \|
		1207	RADEON_TV_DAC_NHOLD \|
		1208	RADEON_TV_MONITOR_DETECT_EN \|
		1209	RADEON_TV_DAC_STD_PS2;
		1210
		1211	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1212
		1213	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1214	RADEON_DAC2_FORCE_DATA_EN;
		1215
		1216	if (color)
		1217	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		1218	else
		1219	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		1220
		1221	if (ASIC_IS_R300(rdev))
		1222	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		1223	else
		1224	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		1225
		1226	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		1227
		1228	tmp = dac_cntl2 \| RADEON_DAC2_DAC2_CLK_SEL \| RADEON_DAC2_CMP_EN;
		1229	WREG32(RADEON_DAC_CNTL2, tmp);
		1230
		1231	udelay(10000);
		1232
		1233	if (ASIC_IS_R300(rdev)) {
		1234	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
		1235	found = connector_status_connected;
		1236	} else {
		1237	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
		1238	found = connector_status_connected;
		1239	}
		1240
		1241	/* restore regs we used */
		1242	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1243	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1244	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1245	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1246
		1247	if (ASIC_IS_R300(rdev)) {
		1248	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1249	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1250	} else {
		1251	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1252	}
		1253	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		1254
1179	serge	1255	return found;
1123	serge	1256
		1257	}
		1258
		1259	static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
		1260	.dpms = radeon_legacy_tv_dac_dpms,
		1261	.mode_fixup = radeon_legacy_tv_dac_mode_fixup,
		1262	.prepare = radeon_legacy_tv_dac_prepare,
		1263	.mode_set = radeon_legacy_tv_dac_mode_set,
		1264	.commit = radeon_legacy_tv_dac_commit,
		1265	.detect = radeon_legacy_tv_dac_detect,
1179	serge	1266	.disable = radeon_legacy_encoder_disable,
1123	serge	1267	};
		1268
		1269
		1270	static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
		1271	.destroy = radeon_enc_destroy,
		1272	};
		1273
1179	serge	1274
		1275	static struct radeon_encoder_int_tmds radeon_legacy_get_tmds_info(struct radeon_encoder encoder)
		1276	{
		1277	struct drm_device *dev = encoder->base.dev;
		1278	struct radeon_device *rdev = dev->dev_private;
		1279	struct radeon_encoder_int_tmds *tmds = NULL;
		1280	bool ret;
		1281
		1282	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
		1283
		1284	if (!tmds)
		1285	return NULL;
		1286
		1287	if (rdev->is_atom_bios)
		1288	ret = radeon_atombios_get_tmds_info(encoder, tmds);
		1289	else
		1290	ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
		1291
		1292	if (ret == false)
		1293	radeon_legacy_get_tmds_info_from_table(encoder, tmds);
		1294
		1295	return tmds;
		1296	}
		1297
1123	serge	1298	void
		1299	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
		1300	{
		1301	struct radeon_device *rdev = dev->dev_private;
		1302	struct drm_encoder *encoder;
		1303	struct radeon_encoder *radeon_encoder;
		1304
		1305	/* see if we already added it */
		1306	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1307	radeon_encoder = to_radeon_encoder(encoder);
		1308	if (radeon_encoder->encoder_id == encoder_id) {
		1309	radeon_encoder->devices \|= supported_device;
		1310	return;
		1311	}
		1312
		1313	}
		1314
		1315	/* add a new one */
		1316	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1317	if (!radeon_encoder)
		1318	return;
		1319
		1320	encoder = &radeon_encoder->base;
		1321	encoder->possible_crtcs = 0x3;
		1322	encoder->possible_clones = 0;
		1323
		1324	radeon_encoder->enc_priv = NULL;
		1325
		1326	radeon_encoder->encoder_id = encoder_id;
		1327	radeon_encoder->devices = supported_device;
1179	serge	1328	radeon_encoder->rmx_type = RMX_OFF;
1123	serge	1329
		1330	switch (radeon_encoder->encoder_id) {
		1331	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1179	serge	1332	encoder->possible_crtcs = 0x1;
1123	serge	1333	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1334	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
		1335	if (rdev->is_atom_bios)
		1336	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1337	else
		1338	radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
		1339	radeon_encoder->rmx_type = RMX_FULL;
		1340	break;
		1341	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1342	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1343	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1179	serge	1344	radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1123	serge	1345	break;
		1346	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1347	drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
		1348	drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
		1349	if (rdev->is_atom_bios)
		1350	radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
		1351	else
		1352	radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
		1353	break;
		1354	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1355	drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		1356	drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
		1357	if (rdev->is_atom_bios)
		1358	radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
		1359	else
		1360	radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
		1361	break;
		1362	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1363	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1364	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
		1365	if (!rdev->is_atom_bios)
		1366	radeon_combios_get_ext_tmds_info(radeon_encoder);
		1367	break;
		1368	}
		1369	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_encoders.c – Rev 1179