WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_legacy_encoders.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "drm_crtc_helper.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
		32
		33	static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
		34	struct drm_display_mode *mode,
		35	struct drm_display_mode *adjusted_mode)
		36	{
		37	struct drm_device *dev = encoder->dev;
		38	struct radeon_device *rdev = dev->dev_private;
		39	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		40	int xres = mode->hdisplay;
		41	int yres = mode->vdisplay;
		42	bool hscale = true, vscale = true;
		43	int hsync_wid;
		44	int vsync_wid;
		45	int hsync_start;
		46	uint32_t scale, inc;
		47	uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
		48	uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
		49	struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
		50
		51	DRM_DEBUG("\n");
		52
		53	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
		54	(RADEON_VERT_STRETCH_RESERVED \|
		55	RADEON_VERT_AUTO_RATIO_INC);
		56	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
		57	(RADEON_HORZ_FP_LOOP_STRETCH \|
		58	RADEON_HORZ_AUTO_RATIO_INC);
		59
		60	crtc_more_cntl = 0;
		61	if ((rdev->family == CHIP_RS100) \|\|
		62	(rdev->family == CHIP_RS200)) {
		63	/* This is to workaround the asic bug for RMX, some versions
		64	of BIOS dosen't have this register initialized correctly. */
		65	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
		66	}
		67
		68
		69	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
		70	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
		71
		72	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
		73	if (!hsync_wid)
		74	hsync_wid = 1;
		75	hsync_start = mode->crtc_hsync_start - 8;
		76
		77	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
		78	\| ((hsync_wid & 0x3f) << 16)
		79	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
		80	? RADEON_CRTC_H_SYNC_POL
		81	: 0));
		82
		83	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
		84	\| ((mode->crtc_vdisplay - 1) << 16));
		85
		86	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
		87	if (!vsync_wid)
		88	vsync_wid = 1;
		89
		90	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
		91	\| ((vsync_wid & 0x1f) << 16)
		92	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
		93	? RADEON_CRTC_V_SYNC_POL
		94	: 0));
		95
		96	fp_horz_vert_active = 0;
		97
		98	if (native_mode->panel_xres == 0 \|\|
		99	native_mode->panel_yres == 0) {
		100	hscale = false;
		101	vscale = false;
		102	} else {
		103	if (xres > native_mode->panel_xres)
		104	xres = native_mode->panel_xres;
		105	if (yres > native_mode->panel_yres)
		106	yres = native_mode->panel_yres;
		107
		108	if (xres == native_mode->panel_xres)
		109	hscale = false;
		110	if (yres == native_mode->panel_yres)
		111	vscale = false;
		112	}
		113
		114	if (radeon_encoder->flags & RADEON_USE_RMX) {
		115	if (radeon_encoder->rmx_type != RMX_CENTER) {
		116	if (!hscale)
		117	fp_horz_stretch \|= ((xres/8-1) << 16);
		118	else {
		119	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
		120	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
		121	/ native_mode->panel_xres + 1;
		122	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|
		123	RADEON_HORZ_STRETCH_BLEND \|
		124	RADEON_HORZ_STRETCH_ENABLE \|
		125	((native_mode->panel_xres/8-1) << 16));
		126	}
		127
		128	if (!vscale)
		129	fp_vert_stretch \|= ((yres-1) << 12);
		130	else {
		131	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
		132	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
		133	/ native_mode->panel_yres + 1;
		134	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|
		135	RADEON_VERT_STRETCH_ENABLE \|
		136	RADEON_VERT_STRETCH_BLEND \|
		137	((native_mode->panel_yres-1) << 12));
		138	}
		139	} else if (radeon_encoder->rmx_type == RMX_CENTER) {
		140	int blank_width;
		141
		142	fp_horz_stretch \|= ((xres/8-1) << 16);
		143	fp_vert_stretch \|= ((yres-1) << 12);
		144
		145	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|
		146	RADEON_CRTC_AUTO_VERT_CENTER_EN);
		147
		148	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
		149	if (blank_width > 110)
		150	blank_width = 110;
		151
		152	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
		153	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
		154
		155	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
		156	if (!hsync_wid)
		157	hsync_wid = 1;
		158
		159	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
		160	\| ((hsync_wid & 0x3f) << 16)
		161	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
		162	? RADEON_CRTC_H_SYNC_POL
		163	: 0));
		164
		165	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
		166	\| ((mode->crtc_vdisplay - 1) << 16));
		167
		168	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
		169	if (!vsync_wid)
		170	vsync_wid = 1;
		171
		172	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
		173	\| ((vsync_wid & 0x1f) << 16)
		174	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
		175	? RADEON_CRTC_V_SYNC_POL
		176	: 0)));
		177
		178	fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) \|
		179	(((native_mode->panel_xres / 8) & 0x1ff) << 16));
		180	}
		181	} else {
		182	fp_horz_stretch \|= ((xres/8-1) << 16);
		183	fp_vert_stretch \|= ((yres-1) << 12);
		184	}
		185
		186	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
		187	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
		188	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
		189	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
		190	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
		191	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
		192	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
		193	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
		194
		195	}
		196
		197	static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
		198	{
		199	struct drm_device *dev = encoder->dev;
		200	struct radeon_device *rdev = dev->dev_private;
		201	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		202	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
		203	int panel_pwr_delay = 2000;
		204	DRM_DEBUG("\n");
		205
		206	if (radeon_encoder->enc_priv) {
		207	if (rdev->is_atom_bios) {
		208	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		209	panel_pwr_delay = lvds->panel_pwr_delay;
		210	} else {
		211	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		212	panel_pwr_delay = lvds->panel_pwr_delay;
		213	}
		214	}
		215
		216	switch (mode) {
		217	case DRM_MODE_DPMS_ON:
		218	disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
		219	disp_pwr_man \|= RADEON_AUTO_PWRUP_EN;
		220	WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
		221	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		222	lvds_pll_cntl \|= RADEON_LVDS_PLL_EN;
		223	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		224	udelay(1000);
		225
		226	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		227	lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
		228	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		229
		230	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		231	lvds_gen_cntl \|= (RADEON_LVDS_ON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON \| RADEON_LVDS_BLON);
		232	lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
		233	udelay(panel_pwr_delay * 1000);
		234	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		235	break;
		236	case DRM_MODE_DPMS_STANDBY:
		237	case DRM_MODE_DPMS_SUSPEND:
		238	case DRM_MODE_DPMS_OFF:
		239	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		240	WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
		241	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		242	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		243	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_BLON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON);
		244	udelay(panel_pwr_delay * 1000);
		245	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		246	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		247	break;
		248	}
		249
		250	if (rdev->is_atom_bios)
		251	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		252	else
		253	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		254	}
		255
		256	static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
		257	{
		258	struct radeon_device *rdev = encoder->dev->dev_private;
		259
		260	if (rdev->is_atom_bios)
		261	radeon_atom_output_lock(encoder, true);
		262	else
		263	radeon_combios_output_lock(encoder, true);
		264	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
		265	}
		266
		267	static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
		268	{
		269	struct radeon_device *rdev = encoder->dev->dev_private;
		270
		271	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
		272	if (rdev->is_atom_bios)
		273	radeon_atom_output_lock(encoder, false);
		274	else
		275	radeon_combios_output_lock(encoder, false);
		276	}
		277
		278	static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
		279	struct drm_display_mode *mode,
		280	struct drm_display_mode *adjusted_mode)
		281	{
		282	struct drm_device *dev = encoder->dev;
		283	struct radeon_device *rdev = dev->dev_private;
		284	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		285	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		286	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
		287
		288	DRM_DEBUG("\n");
		289
		290	if (radeon_crtc->crtc_id == 0)
		291	radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
		292
		293	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		294	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
		295
		296	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		297	if ((!rdev->is_atom_bios)) {
		298	struct radeon_encoder_lvds lvds = (struct radeon_encoder_lvds )radeon_encoder->enc_priv;
		299	if (lvds) {
		300	DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
		301	lvds_gen_cntl = lvds->lvds_gen_cntl;
		302	lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		303	(0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		304	lvds_ss_gen_cntl \|= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		305	(lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		306	} else
		307	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		308	} else
		309	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		310	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		311	lvds_gen_cntl &= ~(RADEON_LVDS_ON \|
		312	RADEON_LVDS_BLON \|
		313	RADEON_LVDS_EN \|
		314	RADEON_LVDS_RST_FM);
		315
		316	if (ASIC_IS_R300(rdev))
		317	lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
		318
		319	if (radeon_crtc->crtc_id == 0) {
		320	if (ASIC_IS_R300(rdev)) {
		321	if (radeon_encoder->flags & RADEON_USE_RMX)
		322	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_RMX;
		323	} else
		324	lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
		325	} else {
		326	if (ASIC_IS_R300(rdev))
		327	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_CRTC2;
		328	else
		329	lvds_gen_cntl \|= RADEON_LVDS_SEL_CRTC2;
		330	}
		331
		332	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		333	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		334	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
		335
		336	if (rdev->family == CHIP_RV410)
		337	WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
		338
		339	if (rdev->is_atom_bios)
		340	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		341	else
		342	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		343	}
		344
		345	static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
		346	struct drm_display_mode *mode,
		347	struct drm_display_mode *adjusted_mode)
		348	{
		349	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		350
		351	drm_mode_set_crtcinfo(adjusted_mode, 0);
		352
		353	radeon_encoder->flags &= ~RADEON_USE_RMX;
		354
		355	if (radeon_encoder->rmx_type != RMX_OFF)
		356	radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
		357
		358	return true;
		359	}
		360
		361	static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
		362	.dpms = radeon_legacy_lvds_dpms,
		363	.mode_fixup = radeon_legacy_lvds_mode_fixup,
		364	.prepare = radeon_legacy_lvds_prepare,
		365	.mode_set = radeon_legacy_lvds_mode_set,
		366	.commit = radeon_legacy_lvds_commit,
		367	};
		368
		369
		370	static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
		371	.destroy = radeon_enc_destroy,
		372	};
		373
		374	static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
		375	struct drm_display_mode *mode,
		376	struct drm_display_mode *adjusted_mode)
		377	{
		378
		379	drm_mode_set_crtcinfo(adjusted_mode, 0);
		380
		381	return true;
		382	}
		383
		384	static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
		385	{
		386	struct drm_device *dev = encoder->dev;
		387	struct radeon_device *rdev = dev->dev_private;
		388	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		389	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
		390	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		391
		392	DRM_DEBUG("\n");
		393
		394	switch (mode) {
		395	case DRM_MODE_DPMS_ON:
		396	crtc_ext_cntl \|= RADEON_CRTC_CRT_ON;
		397	dac_cntl &= ~RADEON_DAC_PDWN;
		398	dac_macro_cntl &= ~(RADEON_DAC_PDWN_R \|
		399	RADEON_DAC_PDWN_G \|
		400	RADEON_DAC_PDWN_B);
		401	break;
		402	case DRM_MODE_DPMS_STANDBY:
		403	case DRM_MODE_DPMS_SUSPEND:
		404	case DRM_MODE_DPMS_OFF:
		405	crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
		406	dac_cntl \|= RADEON_DAC_PDWN;
		407	dac_macro_cntl \|= (RADEON_DAC_PDWN_R \|
		408	RADEON_DAC_PDWN_G \|
		409	RADEON_DAC_PDWN_B);
		410	break;
		411	}
		412
		413	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		414	WREG32(RADEON_DAC_CNTL, dac_cntl);
		415	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		416
		417	if (rdev->is_atom_bios)
		418	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		419	else
		420	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		421	}
		422
		423	static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
		424	{
		425	struct radeon_device *rdev = encoder->dev->dev_private;
		426
		427	if (rdev->is_atom_bios)
		428	radeon_atom_output_lock(encoder, true);
		429	else
		430	radeon_combios_output_lock(encoder, true);
		431	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		432	}
		433
		434	static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
		435	{
		436	struct radeon_device *rdev = encoder->dev->dev_private;
		437
		438	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		439
		440	if (rdev->is_atom_bios)
		441	radeon_atom_output_lock(encoder, false);
		442	else
		443	radeon_combios_output_lock(encoder, false);
		444	}
		445
		446	static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
		447	struct drm_display_mode *mode,
		448	struct drm_display_mode *adjusted_mode)
		449	{
		450	struct drm_device *dev = encoder->dev;
		451	struct radeon_device *rdev = dev->dev_private;
		452	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		453	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		454	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
		455
		456	DRM_DEBUG("\n");
		457
		458	if (radeon_crtc->crtc_id == 0)
		459	radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
		460
		461	if (radeon_crtc->crtc_id == 0) {
		462	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		463	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		464	~(RADEON_DISP_DAC_SOURCE_MASK);
		465	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		466	} else {
		467	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
		468	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		469	}
		470	} else {
		471	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		472	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		473	~(RADEON_DISP_DAC_SOURCE_MASK);
		474	disp_output_cntl \|= RADEON_DISP_DAC_SOURCE_CRTC2;
		475	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		476	} else {
		477	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC_CLK_SEL;
		478	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		479	}
		480	}
		481
		482	dac_cntl = (RADEON_DAC_MASK_ALL \|
		483	RADEON_DAC_VGA_ADR_EN \|
		484	/* TODO 6-bits */
		485	RADEON_DAC_8BIT_EN);
		486
		487	WREG32_P(RADEON_DAC_CNTL,
		488	dac_cntl,
		489	RADEON_DAC_RANGE_CNTL \|
		490	RADEON_DAC_BLANKING);
		491
		492	if (radeon_encoder->enc_priv) {
		493	struct radeon_encoder_primary_dac p_dac = (struct radeon_encoder_primary_dac )radeon_encoder->enc_priv;
		494	dac_macro_cntl = p_dac->ps2_pdac_adj;
		495	} else
		496	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		497	dac_macro_cntl \|= RADEON_DAC_PDWN_R \| RADEON_DAC_PDWN_G \| RADEON_DAC_PDWN_B;
		498	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		499
		500	if (rdev->is_atom_bios)
		501	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		502	else
		503	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		504	}
		505
		506	static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
		507	struct drm_connector *connector)
		508	{
		509	struct drm_device *dev = encoder->dev;
		510	struct radeon_device *rdev = dev->dev_private;
		511	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
		512	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
		513	enum drm_connector_status found = connector_status_disconnected;
		514	bool color = true;
		515
		516	/* save the regs we need */
		517	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
		518	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		519	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		520	dac_cntl = RREG32(RADEON_DAC_CNTL);
		521	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		522
		523	tmp = vclk_ecp_cntl &
		524	~(RADEON_PIXCLK_ALWAYS_ONb \| RADEON_PIXCLK_DAC_ALWAYS_ONb);
		525	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
		526
		527	tmp = crtc_ext_cntl \| RADEON_CRTC_CRT_ON;
		528	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
		529
		530	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN \|
		531	RADEON_DAC_FORCE_DATA_EN;
		532
		533	if (color)
		534	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		535	else
		536	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		537
		538	if (ASIC_IS_R300(rdev))
		539	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		540	else
		541	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		542
		543	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		544
		545	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK \| RADEON_DAC_PDWN);
		546	tmp \|= RADEON_DAC_RANGE_CNTL_PS2 \| RADEON_DAC_CMP_EN;
		547	WREG32(RADEON_DAC_CNTL, tmp);
		548
		549	tmp &= ~(RADEON_DAC_PDWN_R \|
		550	RADEON_DAC_PDWN_G \|
		551	RADEON_DAC_PDWN_B);
		552
		553	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
		554
		555	udelay(2000);
		556
		557	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
		558	found = connector_status_connected;
		559
		560	/* restore the regs we used */
		561	WREG32(RADEON_DAC_CNTL, dac_cntl);
		562	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		563	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		564	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		565	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
		566
		567	return found;
		568	}
		569
		570	static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
		571	.dpms = radeon_legacy_primary_dac_dpms,
		572	.mode_fixup = radeon_legacy_primary_dac_mode_fixup,
		573	.prepare = radeon_legacy_primary_dac_prepare,
		574	.mode_set = radeon_legacy_primary_dac_mode_set,
		575	.commit = radeon_legacy_primary_dac_commit,
		576	.detect = radeon_legacy_primary_dac_detect,
		577	};
		578
		579
		580	static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
		581	.destroy = radeon_enc_destroy,
		582	};
		583
		584	static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
		585	struct drm_display_mode *mode,
		586	struct drm_display_mode *adjusted_mode)
		587	{
		588
		589	drm_mode_set_crtcinfo(adjusted_mode, 0);
		590
		591	return true;
		592	}
		593
		594	static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
		595	{
		596	struct drm_device *dev = encoder->dev;
		597	struct radeon_device *rdev = dev->dev_private;
		598	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
		599	DRM_DEBUG("\n");
		600
		601	switch (mode) {
		602	case DRM_MODE_DPMS_ON:
		603	fp_gen_cntl \|= (RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		604	break;
		605	case DRM_MODE_DPMS_STANDBY:
		606	case DRM_MODE_DPMS_SUSPEND:
		607	case DRM_MODE_DPMS_OFF:
		608	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		609	break;
		610	}
		611
		612	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		613
		614	if (rdev->is_atom_bios)
		615	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		616	else
		617	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		618	}
		619
		620	static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
		621	{
		622	struct radeon_device *rdev = encoder->dev->dev_private;
		623
		624	if (rdev->is_atom_bios)
		625	radeon_atom_output_lock(encoder, true);
		626	else
		627	radeon_combios_output_lock(encoder, true);
		628	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
		629	}
		630
		631	static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
		632	{
		633	struct radeon_device *rdev = encoder->dev->dev_private;
		634
		635	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
		636
		637	if (rdev->is_atom_bios)
		638	radeon_atom_output_lock(encoder, true);
		639	else
		640	radeon_combios_output_lock(encoder, true);
		641	}
		642
		643	static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
		644	struct drm_display_mode *mode,
		645	struct drm_display_mode *adjusted_mode)
		646	{
		647	struct drm_device *dev = encoder->dev;
		648	struct radeon_device *rdev = dev->dev_private;
		649	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		650	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		651	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
		652	int i;
		653
		654	DRM_DEBUG("\n");
		655
		656	if (radeon_crtc->crtc_id == 0)
		657	radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
		658
		659	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
		660	tmp &= 0xfffff;
		661	if (rdev->family == CHIP_RV280) {
		662	/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
		663	tmp ^= (1 << 22);
		664	tmds_pll_cntl ^= (1 << 22);
		665	}
		666
		667	if (radeon_encoder->enc_priv) {
		668	struct radeon_encoder_int_tmds tmds = (struct radeon_encoder_int_tmds )radeon_encoder->enc_priv;
		669
		670	for (i = 0; i < 4; i++) {
		671	if (tmds->tmds_pll[i].freq == 0)
		672	break;
		673	if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
		674	tmp = tmds->tmds_pll[i].value ;
		675	break;
		676	}
		677	}
		678	}
		679
		680	if (ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV280)) {
		681	if (tmp & 0xfff00000)
		682	tmds_pll_cntl = tmp;
		683	else {
		684	tmds_pll_cntl &= 0xfff00000;
		685	tmds_pll_cntl \|= tmp;
		686	}
		687	} else
		688	tmds_pll_cntl = tmp;
		689
		690	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
		691	~(RADEON_TMDS_TRANSMITTER_PLLRST);
		692
		693	if (rdev->family == CHIP_R200 \|\|
		694	rdev->family == CHIP_R100 \|\|
		695	ASIC_IS_R300(rdev))
		696	tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
		697	else /* RV chips got this bit reversed */
		698	tmds_transmitter_cntl \|= RADEON_TMDS_TRANSMITTER_PLLEN;
		699
		700	fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) \|
		701	(RADEON_FP_CRTC_DONT_SHADOW_VPAR \|
		702	RADEON_FP_CRTC_DONT_SHADOW_HEND));
		703
		704	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		705
		706	if (1) /* FIXME rgbBits == 8 */
		707	fp_gen_cntl \|= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
		708	else
		709	fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
		710
		711	if (radeon_crtc->crtc_id == 0) {
		712	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		713	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
		714	if (radeon_encoder->flags & RADEON_USE_RMX)
		715	fp_gen_cntl \|= R200_FP_SOURCE_SEL_RMX;
		716	else
		717	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC1;
		718	} else
		719	fp_gen_cntl \|= RADEON_FP_SEL_CRTC1;
		720	} else {
		721	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		722	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
		723	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC2;
		724	} else
		725	fp_gen_cntl \|= RADEON_FP_SEL_CRTC2;
		726	}
		727
		728	WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
		729	WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
		730	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		731
		732	if (rdev->is_atom_bios)
		733	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		734	else
		735	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		736	}
		737
		738	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
		739	.dpms = radeon_legacy_tmds_int_dpms,
		740	.mode_fixup = radeon_legacy_tmds_int_mode_fixup,
		741	.prepare = radeon_legacy_tmds_int_prepare,
		742	.mode_set = radeon_legacy_tmds_int_mode_set,
		743	.commit = radeon_legacy_tmds_int_commit,
		744	};
		745
		746
		747	static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
		748	.destroy = radeon_enc_destroy,
		749	};
		750
		751	static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
		752	struct drm_display_mode *mode,
		753	struct drm_display_mode *adjusted_mode)
		754	{
		755
		756	drm_mode_set_crtcinfo(adjusted_mode, 0);
		757
		758	return true;
		759	}
		760
		761	static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
		762	{
		763	struct drm_device *dev = encoder->dev;
		764	struct radeon_device *rdev = dev->dev_private;
		765	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		766	DRM_DEBUG("\n");
		767
		768	switch (mode) {
		769	case DRM_MODE_DPMS_ON:
		770	fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
		771	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		772	break;
		773	case DRM_MODE_DPMS_STANDBY:
		774	case DRM_MODE_DPMS_SUSPEND:
		775	case DRM_MODE_DPMS_OFF:
		776	fp2_gen_cntl \|= RADEON_FP2_BLANK_EN;
		777	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		778	break;
		779	}
		780
		781	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		782
		783	if (rdev->is_atom_bios)
		784	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		785	else
		786	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		787	}
		788
		789	static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
		790	{
		791	struct radeon_device *rdev = encoder->dev->dev_private;
		792
		793	if (rdev->is_atom_bios)
		794	radeon_atom_output_lock(encoder, true);
		795	else
		796	radeon_combios_output_lock(encoder, true);
		797	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
		798	}
		799
		800	static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
		801	{
		802	struct radeon_device *rdev = encoder->dev->dev_private;
		803	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
		804
		805	if (rdev->is_atom_bios)
		806	radeon_atom_output_lock(encoder, false);
		807	else
		808	radeon_combios_output_lock(encoder, false);
		809	}
		810
		811	static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
		812	struct drm_display_mode *mode,
		813	struct drm_display_mode *adjusted_mode)
		814	{
		815	struct drm_device *dev = encoder->dev;
		816	struct radeon_device *rdev = dev->dev_private;
		817	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		818	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		819	uint32_t fp2_gen_cntl;
		820
		821	DRM_DEBUG("\n");
		822
		823	if (radeon_crtc->crtc_id == 0)
		824	radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
		825
		826	if (rdev->is_atom_bios) {
		827	radeon_encoder->pixel_clock = adjusted_mode->clock;
		828	atombios_external_tmds_setup(encoder, ATOM_ENABLE);
		829	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		830	} else {
		831	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		832
		833	if (1) /* FIXME rgbBits == 8 */
		834	fp2_gen_cntl \|= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
		835	else
		836	fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
		837
		838	fp2_gen_cntl &= ~(RADEON_FP2_ON \|
		839	RADEON_FP2_DVO_EN \|
		840	RADEON_FP2_DVO_RATE_SEL_SDR);
		841
		842	/* XXX: these are oem specific */
		843	if (ASIC_IS_R300(rdev)) {
		844	if ((dev->pdev->device == 0x4850) &&
		845	(dev->pdev->subsystem_vendor == 0x1028) &&
		846	(dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
		847	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
		848	else
		849	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;
		850
		851	/*if (mode->clock > 165000)
		852	fp2_gen_cntl \|= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
		853	}
		854	}
		855
		856	if (radeon_crtc->crtc_id == 0) {
		857	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		858	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
		859	if (radeon_encoder->flags & RADEON_USE_RMX)
		860	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_RMX;
		861	else
		862	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC1;
		863	} else
		864	fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
		865	} else {
		866	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		867	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
		868	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		869	} else
		870	fp2_gen_cntl \|= RADEON_FP2_SRC_SEL_CRTC2;
		871	}
		872
		873	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		874
		875	if (rdev->is_atom_bios)
		876	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		877	else
		878	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		879	}
		880
		881	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
		882	.dpms = radeon_legacy_tmds_ext_dpms,
		883	.mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
		884	.prepare = radeon_legacy_tmds_ext_prepare,
		885	.mode_set = radeon_legacy_tmds_ext_mode_set,
		886	.commit = radeon_legacy_tmds_ext_commit,
		887	};
		888
		889
		890	static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
		891	.destroy = radeon_enc_destroy,
		892	};
		893
		894	static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
		895	struct drm_display_mode *mode,
		896	struct drm_display_mode *adjusted_mode)
		897	{
		898
		899	drm_mode_set_crtcinfo(adjusted_mode, 0);
		900
		901	return true;
		902	}
		903
		904	static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
		905	{
		906	struct drm_device *dev = encoder->dev;
		907	struct radeon_device *rdev = dev->dev_private;
		908	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
		909	/* uint32_t tv_master_cntl = 0; */
		910
		911	DRM_DEBUG("\n");
		912
		913	if (rdev->family == CHIP_R200)
		914	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		915	else {
		916	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		917	/* FIXME TV */
		918	/* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */
		919	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		920	}
		921
		922	switch (mode) {
		923	case DRM_MODE_DPMS_ON:
		924	if (rdev->family == CHIP_R200) {
		925	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		926	} else {
		927	crtc2_gen_cntl \|= RADEON_CRTC2_CRT2_ON;
		928	/* tv_master_cntl \|= RADEON_TV_ON; */
		929	if (rdev->family == CHIP_R420 \|\|
		930	rdev->family == CHIP_R423 \|\|
		931	rdev->family == CHIP_RV410)
		932	tv_dac_cntl &= ~(R420_TV_DAC_RDACPD \|
		933	R420_TV_DAC_GDACPD \|
		934	R420_TV_DAC_BDACPD \|
		935	RADEON_TV_DAC_BGSLEEP);
		936	else
		937	tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD \|
		938	RADEON_TV_DAC_GDACPD \|
		939	RADEON_TV_DAC_BDACPD \|
		940	RADEON_TV_DAC_BGSLEEP);
		941	}
		942	break;
		943	case DRM_MODE_DPMS_STANDBY:
		944	case DRM_MODE_DPMS_SUSPEND:
		945	case DRM_MODE_DPMS_OFF:
		946	if (rdev->family == CHIP_R200)
		947	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		948	else {
		949	crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
		950	/* tv_master_cntl &= ~RADEON_TV_ON; */
		951	if (rdev->family == CHIP_R420 \|\|
		952	rdev->family == CHIP_R423 \|\|
		953	rdev->family == CHIP_RV410)
		954	tv_dac_cntl \|= (R420_TV_DAC_RDACPD \|
		955	R420_TV_DAC_GDACPD \|
		956	R420_TV_DAC_BDACPD \|
		957	RADEON_TV_DAC_BGSLEEP);
		958	else
		959	tv_dac_cntl \|= (RADEON_TV_DAC_RDACPD \|
		960	RADEON_TV_DAC_GDACPD \|
		961	RADEON_TV_DAC_BDACPD \|
		962	RADEON_TV_DAC_BGSLEEP);
		963	}
		964	break;
		965	}
		966
		967	if (rdev->family == CHIP_R200) {
		968	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		969	} else {
		970	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		971	/* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */
		972	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		973	}
		974
		975	if (rdev->is_atom_bios)
		976	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		977	else
		978	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		979	}
		980
		981	static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
		982	{
		983	struct radeon_device *rdev = encoder->dev->dev_private;
		984
		985	if (rdev->is_atom_bios)
		986	radeon_atom_output_lock(encoder, true);
		987	else
		988	radeon_combios_output_lock(encoder, true);
		989	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		990	}
		991
		992	static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
		993	{
		994	struct radeon_device *rdev = encoder->dev->dev_private;
		995
		996	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		997
		998	if (rdev->is_atom_bios)
		999	radeon_atom_output_lock(encoder, true);
		1000	else
		1001	radeon_combios_output_lock(encoder, true);
		1002	}
		1003
		1004	static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
		1005	struct drm_display_mode *mode,
		1006	struct drm_display_mode *adjusted_mode)
		1007	{
		1008	struct drm_device *dev = encoder->dev;
		1009	struct radeon_device *rdev = dev->dev_private;
		1010	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1011	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1012	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
		1013	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
		1014
		1015	DRM_DEBUG("\n");
		1016
		1017	if (radeon_crtc->crtc_id == 0)
		1018	radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
		1019
		1020	if (rdev->family != CHIP_R200) {
		1021	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1022	if (rdev->family == CHIP_R420 \|\|
		1023	rdev->family == CHIP_R423 \|\|
		1024	rdev->family == CHIP_RV410) {
		1025	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		1026	RADEON_TV_DAC_BGADJ_MASK \|
		1027	R420_TV_DAC_DACADJ_MASK \|
		1028	R420_TV_DAC_RDACPD \|
		1029	R420_TV_DAC_GDACPD \|
		1030	R420_TV_DAC_GDACPD \|
		1031	R420_TV_DAC_TVENABLE);
		1032	} else {
		1033	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		1034	RADEON_TV_DAC_BGADJ_MASK \|
		1035	RADEON_TV_DAC_DACADJ_MASK \|
		1036	RADEON_TV_DAC_RDACPD \|
		1037	RADEON_TV_DAC_GDACPD \|
		1038	RADEON_TV_DAC_GDACPD);
		1039	}
		1040
		1041	/* FIXME TV */
		1042	if (radeon_encoder->enc_priv) {
		1043	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
		1044	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		1045	RADEON_TV_DAC_NHOLD \|
		1046	RADEON_TV_DAC_STD_PS2 \|
		1047	tv_dac->ps2_tvdac_adj);
		1048	} else
		1049	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		1050	RADEON_TV_DAC_NHOLD \|
		1051	RADEON_TV_DAC_STD_PS2);
		1052
		1053	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1054	}
		1055
		1056	if (ASIC_IS_R300(rdev)) {
		1057	gpiopad_a = RREG32(RADEON_GPIOPAD_A) \| 1;
		1058	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1059	} else if (rdev->family == CHIP_R200)
		1060	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		1061	else
		1062	disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1063
		1064	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC2_CLK_SEL;
		1065
		1066	if (radeon_crtc->crtc_id == 0) {
		1067	if (ASIC_IS_R300(rdev)) {
		1068	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1069	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC;
		1070	} else if (rdev->family == CHIP_R200) {
		1071	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		1072	RADEON_FP2_DVO_RATE_SEL_SDR);
		1073	} else
		1074	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1075	} else {
		1076	if (ASIC_IS_R300(rdev)) {
		1077	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1078	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1079	} else if (rdev->family == CHIP_R200) {
		1080	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		1081	RADEON_FP2_DVO_RATE_SEL_SDR);
		1082	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		1083	} else
		1084	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		1085	}
		1086
		1087	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		1088
		1089	if (ASIC_IS_R300(rdev)) {
		1090	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1091	WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
		1092	} else if (rdev->family == CHIP_R200)
		1093	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		1094	else
		1095	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1096
		1097	if (rdev->is_atom_bios)
		1098	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1099	else
		1100	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1101
		1102	}
		1103
		1104	static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
		1105	struct drm_connector *connector)
		1106	{
		1107	struct drm_device *dev = encoder->dev;
		1108	struct radeon_device *rdev = dev->dev_private;
		1109	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1110	uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
		1111	enum drm_connector_status found = connector_status_disconnected;
		1112	bool color = true;
		1113
		1114	/* FIXME tv */
		1115
		1116	/* save the regs we need */
		1117	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		1118	gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
		1119	disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
		1120	disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
		1121	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1122	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1123	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1124	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1125
		1126	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
		1127	\| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
		1128	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
		1129
		1130	if (ASIC_IS_R300(rdev))
		1131	WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
		1132
		1133	tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
		1134	tmp \|= RADEON_CRTC2_CRT2_ON \|
		1135	(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
		1136
		1137	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		1138
		1139	if (ASIC_IS_R300(rdev)) {
		1140	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1141	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1142	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1143	} else {
		1144	tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
		1145	WREG32(RADEON_DISP_HW_DEBUG, tmp);
		1146	}
		1147
		1148	tmp = RADEON_TV_DAC_NBLANK \|
		1149	RADEON_TV_DAC_NHOLD \|
		1150	RADEON_TV_MONITOR_DETECT_EN \|
		1151	RADEON_TV_DAC_STD_PS2;
		1152
		1153	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1154
		1155	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1156	RADEON_DAC2_FORCE_DATA_EN;
		1157
		1158	if (color)
		1159	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		1160	else
		1161	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		1162
		1163	if (ASIC_IS_R300(rdev))
		1164	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		1165	else
		1166	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		1167
		1168	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		1169
		1170	tmp = dac_cntl2 \| RADEON_DAC2_DAC2_CLK_SEL \| RADEON_DAC2_CMP_EN;
		1171	WREG32(RADEON_DAC_CNTL2, tmp);
		1172
		1173	udelay(10000);
		1174
		1175	if (ASIC_IS_R300(rdev)) {
		1176	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
		1177	found = connector_status_connected;
		1178	} else {
		1179	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
		1180	found = connector_status_connected;
		1181	}
		1182
		1183	/* restore regs we used */
		1184	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1185	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1186	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1187	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1188
		1189	if (ASIC_IS_R300(rdev)) {
		1190	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1191	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1192	} else {
		1193	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1194	}
		1195	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		1196
		1197	/* return found; */
		1198	return connector_status_disconnected;
		1199
		1200	}
		1201
		1202	static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
		1203	.dpms = radeon_legacy_tv_dac_dpms,
		1204	.mode_fixup = radeon_legacy_tv_dac_mode_fixup,
		1205	.prepare = radeon_legacy_tv_dac_prepare,
		1206	.mode_set = radeon_legacy_tv_dac_mode_set,
		1207	.commit = radeon_legacy_tv_dac_commit,
		1208	.detect = radeon_legacy_tv_dac_detect,
		1209	};
		1210
		1211
		1212	static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
		1213	.destroy = radeon_enc_destroy,
		1214	};
		1215
		1216	void
		1217	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
		1218	{
		1219	struct radeon_device *rdev = dev->dev_private;
		1220	struct drm_encoder *encoder;
		1221	struct radeon_encoder *radeon_encoder;
		1222
		1223	/* see if we already added it */
		1224	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1225	radeon_encoder = to_radeon_encoder(encoder);
		1226	if (radeon_encoder->encoder_id == encoder_id) {
		1227	radeon_encoder->devices \|= supported_device;
		1228	return;
		1229	}
		1230
		1231	}
		1232
		1233	/* add a new one */
		1234	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1235	if (!radeon_encoder)
		1236	return;
		1237
		1238	encoder = &radeon_encoder->base;
		1239	encoder->possible_crtcs = 0x3;
		1240	encoder->possible_clones = 0;
		1241
		1242	radeon_encoder->enc_priv = NULL;
		1243
		1244	radeon_encoder->encoder_id = encoder_id;
		1245	radeon_encoder->devices = supported_device;
		1246
		1247	switch (radeon_encoder->encoder_id) {
		1248	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1249	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1250	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
		1251	if (rdev->is_atom_bios)
		1252	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1253	else
		1254	radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
		1255	radeon_encoder->rmx_type = RMX_FULL;
		1256	break;
		1257	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1258	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1259	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
		1260	if (rdev->is_atom_bios)
		1261	radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder);
		1262	else
		1263	radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder);
		1264	break;
		1265	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1266	drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
		1267	drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
		1268	if (rdev->is_atom_bios)
		1269	radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
		1270	else
		1271	radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
		1272	break;
		1273	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1274	drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		1275	drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
		1276	if (rdev->is_atom_bios)
		1277	radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
		1278	else
		1279	radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
		1280	break;
		1281	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1282	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1283	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
		1284	if (!rdev->is_atom_bios)
		1285	radeon_combios_get_ext_tmds_info(radeon_encoder);
		1286	break;
		1287	}
		1288	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_encoders.c @ 1430 – Rev 1123