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Rev | Author | Line No. | Line |
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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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2997 | Serge | 26 | #include |
27 | #include |
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28 | #include |
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1123 | serge | 29 | #include "radeon.h" |
30 | #include "atom.h" |
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2997 | Serge | 31 | #include |
32 | #ifdef CONFIG_PMAC_BACKLIGHT |
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33 | #include |
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34 | #endif |
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1123 | serge | 35 | |
1179 | serge | 36 | static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) |
1123 | serge | 37 | { |
38 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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6104 | serge | 39 | const struct drm_encoder_helper_funcs *encoder_funcs; |
1123 | serge | 40 | |
1179 | serge | 41 | encoder_funcs = encoder->helper_private; |
42 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
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43 | radeon_encoder->active_device = 0; |
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1123 | serge | 44 | } |
45 | |||
1963 | serge | 46 | static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) |
1123 | serge | 47 | { |
48 | struct drm_device *dev = encoder->dev; |
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49 | struct radeon_device *rdev = dev->dev_private; |
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50 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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51 | uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; |
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52 | int panel_pwr_delay = 2000; |
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1403 | serge | 53 | bool is_mac = false; |
1963 | serge | 54 | uint8_t backlight_level; |
55 | DRM_DEBUG_KMS("\n"); |
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1123 | serge | 56 | |
1963 | serge | 57 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
58 | backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
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59 | |||
1123 | serge | 60 | if (radeon_encoder->enc_priv) { |
61 | if (rdev->is_atom_bios) { |
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62 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
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63 | panel_pwr_delay = lvds->panel_pwr_delay; |
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1963 | serge | 64 | if (lvds->bl_dev) |
65 | backlight_level = lvds->backlight_level; |
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1123 | serge | 66 | } else { |
67 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
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68 | panel_pwr_delay = lvds->panel_pwr_delay; |
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1963 | serge | 69 | if (lvds->bl_dev) |
70 | backlight_level = lvds->backlight_level; |
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1123 | serge | 71 | } |
72 | } |
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73 | |||
1403 | serge | 74 | /* macs (and possibly some x86 oem systems?) wire up LVDS strangely |
75 | * Taken from radeonfb. |
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76 | */ |
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77 | if ((rdev->mode_info.connector_table == CT_IBOOK) || |
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78 | (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || |
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79 | (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || |
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80 | (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) |
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81 | is_mac = true; |
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82 | |||
1123 | serge | 83 | switch (mode) { |
84 | case DRM_MODE_DPMS_ON: |
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85 | disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); |
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86 | disp_pwr_man |= RADEON_AUTO_PWRUP_EN; |
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87 | WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); |
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88 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
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89 | lvds_pll_cntl |= RADEON_LVDS_PLL_EN; |
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90 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
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2997 | Serge | 91 | mdelay(1); |
1123 | serge | 92 | |
93 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
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94 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; |
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95 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
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96 | |||
1963 | serge | 97 | lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | |
98 | RADEON_LVDS_BL_MOD_LEVEL_MASK); |
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99 | lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | |
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100 | RADEON_LVDS_DIGON | RADEON_LVDS_BLON | |
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101 | (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); |
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1403 | serge | 102 | if (is_mac) |
103 | lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; |
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2997 | Serge | 104 | mdelay(panel_pwr_delay); |
1123 | serge | 105 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
106 | break; |
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107 | case DRM_MODE_DPMS_STANDBY: |
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108 | case DRM_MODE_DPMS_SUSPEND: |
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109 | case DRM_MODE_DPMS_OFF: |
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110 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
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111 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); |
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112 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
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1403 | serge | 113 | if (is_mac) { |
114 | lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; |
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115 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
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116 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); |
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117 | } else { |
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118 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
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6104 | serge | 119 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); |
1403 | serge | 120 | } |
2997 | Serge | 121 | mdelay(panel_pwr_delay); |
1123 | serge | 122 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
123 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
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2997 | Serge | 124 | mdelay(panel_pwr_delay); |
1123 | serge | 125 | break; |
126 | } |
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127 | |||
128 | if (rdev->is_atom_bios) |
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129 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
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130 | else |
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131 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
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1430 | serge | 132 | |
1123 | serge | 133 | } |
134 | |||
1963 | serge | 135 | static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) |
136 | { |
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137 | struct radeon_device *rdev = encoder->dev->dev_private; |
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138 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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139 | DRM_DEBUG("\n"); |
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140 | |||
141 | if (radeon_encoder->enc_priv) { |
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142 | if (rdev->is_atom_bios) { |
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143 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
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144 | lvds->dpms_mode = mode; |
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145 | } else { |
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146 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
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147 | lvds->dpms_mode = mode; |
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148 | } |
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149 | } |
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150 | |||
151 | radeon_legacy_lvds_update(encoder, mode); |
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152 | } |
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153 | |||
1123 | serge | 154 | static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) |
155 | { |
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156 | struct radeon_device *rdev = encoder->dev->dev_private; |
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157 | |||
158 | if (rdev->is_atom_bios) |
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159 | radeon_atom_output_lock(encoder, true); |
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160 | else |
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161 | radeon_combios_output_lock(encoder, true); |
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162 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); |
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163 | } |
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164 | |||
165 | static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) |
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166 | { |
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167 | struct radeon_device *rdev = encoder->dev->dev_private; |
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168 | |||
169 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); |
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170 | if (rdev->is_atom_bios) |
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171 | radeon_atom_output_lock(encoder, false); |
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172 | else |
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173 | radeon_combios_output_lock(encoder, false); |
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174 | } |
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175 | |||
176 | static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, |
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177 | struct drm_display_mode *mode, |
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178 | struct drm_display_mode *adjusted_mode) |
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179 | { |
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180 | struct drm_device *dev = encoder->dev; |
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181 | struct radeon_device *rdev = dev->dev_private; |
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182 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
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183 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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184 | uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; |
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185 | |||
1963 | serge | 186 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 187 | |
188 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
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189 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; |
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190 | |||
191 | lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
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1321 | serge | 192 | if (rdev->is_atom_bios) { |
193 | /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl |
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194 | * need to call that on resume to set up the reg properly. |
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195 | */ |
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196 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
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197 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
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198 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
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199 | } else { |
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1123 | serge | 200 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
201 | if (lvds) { |
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1963 | serge | 202 | DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); |
1123 | serge | 203 | lvds_gen_cntl = lvds->lvds_gen_cntl; |
204 | lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
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205 | (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
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206 | lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
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207 | (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
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208 | } else |
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209 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
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1321 | serge | 210 | } |
1123 | serge | 211 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
212 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | |
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213 | RADEON_LVDS_BLON | |
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214 | RADEON_LVDS_EN | |
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215 | RADEON_LVDS_RST_FM); |
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216 | |||
217 | if (ASIC_IS_R300(rdev)) |
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218 | lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); |
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219 | |||
220 | if (radeon_crtc->crtc_id == 0) { |
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221 | if (ASIC_IS_R300(rdev)) { |
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1179 | serge | 222 | if (radeon_encoder->rmx_type != RMX_OFF) |
1123 | serge | 223 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; |
224 | } else |
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225 | lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; |
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226 | } else { |
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227 | if (ASIC_IS_R300(rdev)) |
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228 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; |
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229 | else |
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230 | lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; |
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231 | } |
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232 | |||
233 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
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234 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
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235 | WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); |
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236 | |||
237 | if (rdev->family == CHIP_RV410) |
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238 | WREG32(RADEON_CLOCK_CNTL_INDEX, 0); |
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239 | |||
240 | if (rdev->is_atom_bios) |
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241 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
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242 | else |
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243 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
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244 | } |
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245 | |||
1321 | serge | 246 | static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, |
2997 | Serge | 247 | const struct drm_display_mode *mode, |
6104 | serge | 248 | struct drm_display_mode *adjusted_mode) |
1123 | serge | 249 | { |
250 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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251 | |||
1268 | serge | 252 | /* set the active encoder to connector routing */ |
253 | radeon_encoder_set_active_device(encoder); |
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1123 | serge | 254 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
255 | |||
1321 | serge | 256 | /* get the native mode for LVDS */ |
1963 | serge | 257 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
258 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
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1123 | serge | 259 | |
260 | return true; |
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261 | } |
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262 | |||
263 | static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { |
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264 | .dpms = radeon_legacy_lvds_dpms, |
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1321 | serge | 265 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 266 | .prepare = radeon_legacy_lvds_prepare, |
267 | .mode_set = radeon_legacy_lvds_mode_set, |
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268 | .commit = radeon_legacy_lvds_commit, |
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1179 | serge | 269 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 270 | }; |
271 | |||
2997 | Serge | 272 | u8 |
273 | radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) |
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274 | { |
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275 | struct drm_device *dev = radeon_encoder->base.dev; |
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276 | struct radeon_device *rdev = dev->dev_private; |
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277 | u8 backlight_level; |
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1123 | serge | 278 | |
2997 | Serge | 279 | backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> |
280 | RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
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1963 | serge | 281 | |
2997 | Serge | 282 | return backlight_level; |
283 | } |
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1963 | serge | 284 | |
2997 | Serge | 285 | void |
286 | radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
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287 | { |
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288 | struct drm_device *dev = radeon_encoder->base.dev; |
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289 | struct radeon_device *rdev = dev->dev_private; |
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290 | int dpms_mode = DRM_MODE_DPMS_ON; |
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291 | |||
292 | if (radeon_encoder->enc_priv) { |
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293 | if (rdev->is_atom_bios) { |
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294 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
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295 | if (lvds->backlight_level > 0) |
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296 | dpms_mode = lvds->dpms_mode; |
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297 | else |
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298 | dpms_mode = DRM_MODE_DPMS_OFF; |
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299 | lvds->backlight_level = level; |
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300 | } else { |
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301 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
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302 | if (lvds->backlight_level > 0) |
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303 | dpms_mode = lvds->dpms_mode; |
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304 | else |
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305 | dpms_mode = DRM_MODE_DPMS_OFF; |
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306 | lvds->backlight_level = level; |
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307 | } |
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308 | } |
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309 | |||
310 | radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); |
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311 | } |
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312 | |||
313 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
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314 | |||
1963 | serge | 315 | static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) |
316 | { |
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317 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
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318 | uint8_t level; |
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319 | |||
320 | /* Convert brightness to hardware level */ |
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321 | if (bd->props.brightness < 0) |
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322 | level = 0; |
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2997 | Serge | 323 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) |
324 | level = RADEON_MAX_BL_LEVEL; |
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1963 | serge | 325 | else |
326 | level = bd->props.brightness; |
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327 | |||
328 | if (pdata->negative) |
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2997 | Serge | 329 | level = RADEON_MAX_BL_LEVEL - level; |
1963 | serge | 330 | |
331 | return level; |
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332 | } |
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333 | |||
334 | static int radeon_legacy_backlight_update_status(struct backlight_device *bd) |
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335 | { |
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336 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
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337 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
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338 | |||
2997 | Serge | 339 | radeon_legacy_set_backlight_level(radeon_encoder, |
340 | radeon_legacy_lvds_level(bd)); |
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1963 | serge | 341 | |
342 | return 0; |
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343 | } |
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344 | |||
345 | static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) |
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346 | { |
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347 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
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348 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
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349 | struct drm_device *dev = radeon_encoder->base.dev; |
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350 | struct radeon_device *rdev = dev->dev_private; |
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351 | uint8_t backlight_level; |
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352 | |||
353 | backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> |
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354 | RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
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355 | |||
2997 | Serge | 356 | return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; |
1963 | serge | 357 | } |
358 | |||
359 | static const struct backlight_ops radeon_backlight_ops = { |
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360 | .get_brightness = radeon_legacy_backlight_get_brightness, |
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361 | .update_status = radeon_legacy_backlight_update_status, |
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362 | }; |
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363 | |||
364 | void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, |
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365 | struct drm_connector *drm_connector) |
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366 | { |
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367 | struct drm_device *dev = radeon_encoder->base.dev; |
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368 | struct radeon_device *rdev = dev->dev_private; |
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369 | struct backlight_device *bd; |
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370 | struct backlight_properties props; |
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371 | struct radeon_backlight_privdata *pdata; |
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372 | uint8_t backlight_level; |
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2997 | Serge | 373 | char bl_name[16]; |
1963 | serge | 374 | |
375 | if (!radeon_encoder->enc_priv) |
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376 | return; |
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377 | |||
378 | #ifdef CONFIG_PMAC_BACKLIGHT |
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379 | if (!pmac_has_backlight_type("ati") && |
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380 | !pmac_has_backlight_type("mnca")) |
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381 | return; |
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382 | #endif |
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383 | |||
384 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); |
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385 | if (!pdata) { |
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386 | DRM_ERROR("Memory allocation failed\n"); |
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387 | goto error; |
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388 | } |
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389 | |||
2997 | Serge | 390 | memset(&props, 0, sizeof(props)); |
391 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
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1963 | serge | 392 | props.type = BACKLIGHT_RAW; |
2997 | Serge | 393 | snprintf(bl_name, sizeof(bl_name), |
394 | "radeon_bl%d", dev->primary->index); |
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5078 | serge | 395 | bd = backlight_device_register(bl_name, drm_connector->kdev, |
1963 | serge | 396 | pdata, &radeon_backlight_ops, &props); |
397 | if (IS_ERR(bd)) { |
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398 | DRM_ERROR("Backlight registration failed\n"); |
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399 | goto error; |
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400 | } |
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401 | |||
402 | pdata->encoder = radeon_encoder; |
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403 | |||
404 | backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> |
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405 | RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
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406 | |||
407 | /* First, try to detect backlight level sense based on the assumption |
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408 | * that firmware set it up at full brightness |
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409 | */ |
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410 | if (backlight_level == 0) |
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411 | pdata->negative = true; |
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412 | else if (backlight_level == 0xff) |
||
413 | pdata->negative = false; |
||
414 | else { |
||
415 | /* XXX hack... maybe some day we can figure out in what direction |
||
416 | * backlight should work on a given panel? |
||
417 | */ |
||
418 | pdata->negative = (rdev->family != CHIP_RV200 && |
||
419 | rdev->family != CHIP_RV250 && |
||
420 | rdev->family != CHIP_RV280 && |
||
421 | rdev->family != CHIP_RV350); |
||
422 | |||
423 | #ifdef CONFIG_PMAC_BACKLIGHT |
||
424 | pdata->negative = (pdata->negative || |
||
425 | of_machine_is_compatible("PowerBook4,3") || |
||
426 | of_machine_is_compatible("PowerBook6,3") || |
||
427 | of_machine_is_compatible("PowerBook6,5")); |
||
428 | #endif |
||
429 | } |
||
430 | |||
431 | if (rdev->is_atom_bios) { |
||
432 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
||
433 | lvds->bl_dev = bd; |
||
434 | } else { |
||
435 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
||
436 | lvds->bl_dev = bd; |
||
437 | } |
||
438 | |||
439 | bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); |
||
440 | bd->props.power = FB_BLANK_UNBLANK; |
||
441 | backlight_update_status(bd); |
||
442 | |||
443 | DRM_INFO("radeon legacy LVDS backlight initialized\n"); |
||
6104 | serge | 444 | rdev->mode_info.bl_encoder = radeon_encoder; |
1963 | serge | 445 | |
446 | return; |
||
447 | |||
448 | error: |
||
449 | kfree(pdata); |
||
450 | return; |
||
451 | } |
||
452 | |||
453 | static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) |
||
454 | { |
||
455 | struct drm_device *dev = radeon_encoder->base.dev; |
||
456 | struct radeon_device *rdev = dev->dev_private; |
||
457 | struct backlight_device *bd = NULL; |
||
458 | |||
459 | if (!radeon_encoder->enc_priv) |
||
460 | return; |
||
461 | |||
462 | if (rdev->is_atom_bios) { |
||
463 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
||
464 | bd = lvds->bl_dev; |
||
465 | lvds->bl_dev = NULL; |
||
466 | } else { |
||
467 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
||
468 | bd = lvds->bl_dev; |
||
469 | lvds->bl_dev = NULL; |
||
470 | } |
||
471 | |||
472 | if (bd) { |
||
2997 | Serge | 473 | struct radeon_backlight_privdata *pdata; |
1963 | serge | 474 | |
475 | pdata = bl_get_data(bd); |
||
476 | backlight_device_unregister(bd); |
||
477 | kfree(pdata); |
||
478 | |||
479 | DRM_INFO("radeon legacy LVDS backlight unloaded\n"); |
||
480 | } |
||
481 | } |
||
482 | |||
483 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ |
||
484 | |||
485 | void radeon_legacy_backlight_init(struct radeon_encoder *encoder) |
||
486 | { |
||
487 | } |
||
488 | |||
489 | static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) |
||
490 | { |
||
491 | } |
||
492 | |||
493 | #endif |
||
494 | |||
495 | |||
496 | static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) |
||
497 | { |
||
498 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
499 | |||
500 | if (radeon_encoder->enc_priv) { |
||
501 | radeon_legacy_backlight_exit(radeon_encoder); |
||
502 | kfree(radeon_encoder->enc_priv); |
||
503 | } |
||
504 | drm_encoder_cleanup(encoder); |
||
505 | kfree(radeon_encoder); |
||
506 | } |
||
507 | |||
1123 | serge | 508 | static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { |
1963 | serge | 509 | .destroy = radeon_lvds_enc_destroy, |
1123 | serge | 510 | }; |
511 | |||
512 | static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) |
||
513 | { |
||
514 | struct drm_device *dev = encoder->dev; |
||
515 | struct radeon_device *rdev = dev->dev_private; |
||
516 | uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
517 | uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); |
||
518 | uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
||
519 | |||
1963 | serge | 520 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 521 | |
522 | switch (mode) { |
||
523 | case DRM_MODE_DPMS_ON: |
||
524 | crtc_ext_cntl |= RADEON_CRTC_CRT_ON; |
||
525 | dac_cntl &= ~RADEON_DAC_PDWN; |
||
526 | dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | |
||
527 | RADEON_DAC_PDWN_G | |
||
528 | RADEON_DAC_PDWN_B); |
||
529 | break; |
||
530 | case DRM_MODE_DPMS_STANDBY: |
||
531 | case DRM_MODE_DPMS_SUSPEND: |
||
532 | case DRM_MODE_DPMS_OFF: |
||
533 | crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; |
||
534 | dac_cntl |= RADEON_DAC_PDWN; |
||
535 | dac_macro_cntl |= (RADEON_DAC_PDWN_R | |
||
536 | RADEON_DAC_PDWN_G | |
||
537 | RADEON_DAC_PDWN_B); |
||
538 | break; |
||
539 | } |
||
540 | |||
3120 | serge | 541 | /* handled in radeon_crtc_dpms() */ |
542 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) |
||
6104 | serge | 543 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
1123 | serge | 544 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
545 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
||
546 | |||
547 | if (rdev->is_atom_bios) |
||
548 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
549 | else |
||
550 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 551 | |
1123 | serge | 552 | } |
553 | |||
554 | static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) |
||
555 | { |
||
556 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
557 | |||
558 | if (rdev->is_atom_bios) |
||
559 | radeon_atom_output_lock(encoder, true); |
||
560 | else |
||
561 | radeon_combios_output_lock(encoder, true); |
||
562 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
563 | } |
||
564 | |||
565 | static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) |
||
566 | { |
||
567 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
568 | |||
569 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
||
570 | |||
571 | if (rdev->is_atom_bios) |
||
572 | radeon_atom_output_lock(encoder, false); |
||
573 | else |
||
574 | radeon_combios_output_lock(encoder, false); |
||
575 | } |
||
576 | |||
577 | static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, |
||
578 | struct drm_display_mode *mode, |
||
579 | struct drm_display_mode *adjusted_mode) |
||
580 | { |
||
581 | struct drm_device *dev = encoder->dev; |
||
582 | struct radeon_device *rdev = dev->dev_private; |
||
583 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
584 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
585 | uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; |
||
586 | |||
1963 | serge | 587 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 588 | |
589 | if (radeon_crtc->crtc_id == 0) { |
||
590 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
||
591 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
||
592 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
||
593 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
594 | } else { |
||
595 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); |
||
596 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
597 | } |
||
598 | } else { |
||
599 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
||
600 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
||
601 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
||
602 | disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; |
||
603 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
604 | } else { |
||
605 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; |
||
606 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
607 | } |
||
608 | } |
||
609 | |||
610 | dac_cntl = (RADEON_DAC_MASK_ALL | |
||
611 | RADEON_DAC_VGA_ADR_EN | |
||
612 | /* TODO 6-bits */ |
||
613 | RADEON_DAC_8BIT_EN); |
||
614 | |||
615 | WREG32_P(RADEON_DAC_CNTL, |
||
616 | dac_cntl, |
||
617 | RADEON_DAC_RANGE_CNTL | |
||
618 | RADEON_DAC_BLANKING); |
||
619 | |||
620 | if (radeon_encoder->enc_priv) { |
||
621 | struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; |
||
622 | dac_macro_cntl = p_dac->ps2_pdac_adj; |
||
623 | } else |
||
624 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
||
625 | dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; |
||
626 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
||
627 | |||
628 | if (rdev->is_atom_bios) |
||
629 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
630 | else |
||
631 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
632 | } |
||
633 | |||
634 | static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, |
||
635 | struct drm_connector *connector) |
||
636 | { |
||
637 | struct drm_device *dev = encoder->dev; |
||
638 | struct radeon_device *rdev = dev->dev_private; |
||
639 | uint32_t vclk_ecp_cntl, crtc_ext_cntl; |
||
640 | uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; |
||
641 | enum drm_connector_status found = connector_status_disconnected; |
||
642 | bool color = true; |
||
643 | |||
3764 | Serge | 644 | /* just don't bother on RN50 those chip are often connected to remoting |
645 | * console hw and often we get failure to load detect those. So to make |
||
646 | * everyone happy report the encoder as always connected. |
||
647 | */ |
||
648 | if (ASIC_IS_RN50(rdev)) { |
||
649 | return connector_status_connected; |
||
650 | } |
||
651 | |||
1123 | serge | 652 | /* save the regs we need */ |
653 | vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
654 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
655 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
||
656 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
||
657 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
||
658 | |||
659 | tmp = vclk_ecp_cntl & |
||
660 | ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
661 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
662 | |||
663 | tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; |
||
664 | WREG32(RADEON_CRTC_EXT_CNTL, tmp); |
||
665 | |||
666 | tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | |
||
667 | RADEON_DAC_FORCE_DATA_EN; |
||
668 | |||
669 | if (color) |
||
670 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
||
671 | else |
||
672 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
||
673 | |||
674 | if (ASIC_IS_R300(rdev)) |
||
675 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
3120 | serge | 676 | else if (ASIC_IS_RV100(rdev)) |
677 | tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT); |
||
1123 | serge | 678 | else |
679 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
680 | |||
681 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
||
682 | |||
683 | tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); |
||
684 | tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; |
||
685 | WREG32(RADEON_DAC_CNTL, tmp); |
||
686 | |||
3120 | serge | 687 | tmp = dac_macro_cntl; |
1123 | serge | 688 | tmp &= ~(RADEON_DAC_PDWN_R | |
689 | RADEON_DAC_PDWN_G | |
||
690 | RADEON_DAC_PDWN_B); |
||
691 | |||
692 | WREG32(RADEON_DAC_MACRO_CNTL, tmp); |
||
693 | |||
2997 | Serge | 694 | mdelay(2); |
1123 | serge | 695 | |
696 | if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) |
||
697 | found = connector_status_connected; |
||
698 | |||
699 | /* restore the regs we used */ |
||
700 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
||
701 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
||
702 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
||
703 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
704 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); |
||
705 | |||
706 | return found; |
||
707 | } |
||
708 | |||
709 | static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { |
||
710 | .dpms = radeon_legacy_primary_dac_dpms, |
||
1321 | serge | 711 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 712 | .prepare = radeon_legacy_primary_dac_prepare, |
713 | .mode_set = radeon_legacy_primary_dac_mode_set, |
||
714 | .commit = radeon_legacy_primary_dac_commit, |
||
715 | .detect = radeon_legacy_primary_dac_detect, |
||
1179 | serge | 716 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 717 | }; |
718 | |||
719 | |||
720 | static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { |
||
721 | .destroy = radeon_enc_destroy, |
||
722 | }; |
||
723 | |||
724 | static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) |
||
725 | { |
||
726 | struct drm_device *dev = encoder->dev; |
||
727 | struct radeon_device *rdev = dev->dev_private; |
||
728 | uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); |
||
1963 | serge | 729 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 730 | |
731 | switch (mode) { |
||
732 | case DRM_MODE_DPMS_ON: |
||
733 | fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
||
734 | break; |
||
735 | case DRM_MODE_DPMS_STANDBY: |
||
736 | case DRM_MODE_DPMS_SUSPEND: |
||
737 | case DRM_MODE_DPMS_OFF: |
||
738 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
||
739 | break; |
||
740 | } |
||
741 | |||
742 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
||
743 | |||
744 | if (rdev->is_atom_bios) |
||
745 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
746 | else |
||
747 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 748 | |
1123 | serge | 749 | } |
750 | |||
751 | static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) |
||
752 | { |
||
753 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
754 | |||
755 | if (rdev->is_atom_bios) |
||
756 | radeon_atom_output_lock(encoder, true); |
||
757 | else |
||
758 | radeon_combios_output_lock(encoder, true); |
||
759 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
760 | } |
||
761 | |||
762 | static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) |
||
763 | { |
||
764 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
765 | |||
766 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); |
||
767 | |||
768 | if (rdev->is_atom_bios) |
||
769 | radeon_atom_output_lock(encoder, true); |
||
770 | else |
||
771 | radeon_combios_output_lock(encoder, true); |
||
772 | } |
||
773 | |||
774 | static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, |
||
775 | struct drm_display_mode *mode, |
||
776 | struct drm_display_mode *adjusted_mode) |
||
777 | { |
||
778 | struct drm_device *dev = encoder->dev; |
||
779 | struct radeon_device *rdev = dev->dev_private; |
||
780 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
781 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
782 | uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; |
||
783 | int i; |
||
784 | |||
1963 | serge | 785 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 786 | |
787 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); |
||
788 | tmp &= 0xfffff; |
||
789 | if (rdev->family == CHIP_RV280) { |
||
790 | /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ |
||
791 | tmp ^= (1 << 22); |
||
792 | tmds_pll_cntl ^= (1 << 22); |
||
793 | } |
||
794 | |||
795 | if (radeon_encoder->enc_priv) { |
||
796 | struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; |
||
797 | |||
798 | for (i = 0; i < 4; i++) { |
||
799 | if (tmds->tmds_pll[i].freq == 0) |
||
800 | break; |
||
801 | if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { |
||
802 | tmp = tmds->tmds_pll[i].value ; |
||
803 | break; |
||
804 | } |
||
805 | } |
||
806 | } |
||
807 | |||
808 | if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { |
||
809 | if (tmp & 0xfff00000) |
||
810 | tmds_pll_cntl = tmp; |
||
811 | else { |
||
812 | tmds_pll_cntl &= 0xfff00000; |
||
813 | tmds_pll_cntl |= tmp; |
||
814 | } |
||
815 | } else |
||
816 | tmds_pll_cntl = tmp; |
||
817 | |||
818 | tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & |
||
819 | ~(RADEON_TMDS_TRANSMITTER_PLLRST); |
||
820 | |||
7146 | serge | 821 | if (rdev->family == CHIP_R200 || |
822 | rdev->family == CHIP_R100 || |
||
823 | ASIC_IS_R300(rdev)) |
||
824 | tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); |
||
825 | else /* RV chips got this bit reversed */ |
||
826 | tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; |
||
1123 | serge | 827 | |
7146 | serge | 828 | fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | |
829 | (RADEON_FP_CRTC_DONT_SHADOW_VPAR | |
||
830 | RADEON_FP_CRTC_DONT_SHADOW_HEND)); |
||
1123 | serge | 831 | |
7146 | serge | 832 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
1123 | serge | 833 | |
7146 | serge | 834 | fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | |
835 | RADEON_FP_DFP_SYNC_SEL | |
||
836 | RADEON_FP_CRT_SYNC_SEL | |
||
837 | RADEON_FP_CRTC_LOCK_8DOT | |
||
838 | RADEON_FP_USE_SHADOW_EN | |
||
839 | RADEON_FP_CRTC_USE_SHADOW_VEND | |
||
840 | RADEON_FP_CRT_SYNC_ALT); |
||
1268 | serge | 841 | |
7146 | serge | 842 | if (1) /* FIXME rgbBits == 8 */ |
843 | fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ |
||
844 | else |
||
845 | fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ |
||
1123 | serge | 846 | |
7146 | serge | 847 | if (radeon_crtc->crtc_id == 0) { |
848 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
||
849 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
||
850 | if (radeon_encoder->rmx_type != RMX_OFF) |
||
851 | fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; |
||
852 | else |
||
853 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; |
||
854 | } else |
||
855 | fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; |
||
856 | } else { |
||
857 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
||
858 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
||
859 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; |
||
860 | } else |
||
861 | fp_gen_cntl |= RADEON_FP_SEL_CRTC2; |
||
862 | } |
||
1123 | serge | 863 | |
7146 | serge | 864 | WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); |
865 | WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); |
||
866 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
||
1123 | serge | 867 | |
868 | if (rdev->is_atom_bios) |
||
869 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
870 | else |
||
871 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
872 | } |
||
873 | |||
874 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { |
||
875 | .dpms = radeon_legacy_tmds_int_dpms, |
||
1321 | serge | 876 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 877 | .prepare = radeon_legacy_tmds_int_prepare, |
878 | .mode_set = radeon_legacy_tmds_int_mode_set, |
||
879 | .commit = radeon_legacy_tmds_int_commit, |
||
1179 | serge | 880 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 881 | }; |
882 | |||
883 | |||
884 | static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { |
||
885 | .destroy = radeon_enc_destroy, |
||
886 | }; |
||
887 | |||
888 | static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) |
||
889 | { |
||
890 | struct drm_device *dev = encoder->dev; |
||
891 | struct radeon_device *rdev = dev->dev_private; |
||
892 | uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
1963 | serge | 893 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 894 | |
895 | switch (mode) { |
||
896 | case DRM_MODE_DPMS_ON: |
||
897 | fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; |
||
898 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
899 | break; |
||
900 | case DRM_MODE_DPMS_STANDBY: |
||
901 | case DRM_MODE_DPMS_SUSPEND: |
||
902 | case DRM_MODE_DPMS_OFF: |
||
903 | fp2_gen_cntl |= RADEON_FP2_BLANK_EN; |
||
904 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
905 | break; |
||
906 | } |
||
907 | |||
908 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
909 | |||
910 | if (rdev->is_atom_bios) |
||
911 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
912 | else |
||
913 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 914 | |
1123 | serge | 915 | } |
916 | |||
917 | static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) |
||
918 | { |
||
919 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
920 | |||
921 | if (rdev->is_atom_bios) |
||
922 | radeon_atom_output_lock(encoder, true); |
||
923 | else |
||
924 | radeon_combios_output_lock(encoder, true); |
||
925 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
926 | } |
||
927 | |||
928 | static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) |
||
929 | { |
||
930 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
931 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); |
||
932 | |||
933 | if (rdev->is_atom_bios) |
||
934 | radeon_atom_output_lock(encoder, false); |
||
935 | else |
||
936 | radeon_combios_output_lock(encoder, false); |
||
937 | } |
||
938 | |||
939 | static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, |
||
940 | struct drm_display_mode *mode, |
||
941 | struct drm_display_mode *adjusted_mode) |
||
942 | { |
||
943 | struct drm_device *dev = encoder->dev; |
||
944 | struct radeon_device *rdev = dev->dev_private; |
||
945 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
946 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
947 | uint32_t fp2_gen_cntl; |
||
948 | |||
1963 | serge | 949 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 950 | |
951 | if (rdev->is_atom_bios) { |
||
952 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
||
1963 | serge | 953 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
1123 | serge | 954 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
955 | } else { |
||
956 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
957 | |||
958 | if (1) /* FIXME rgbBits == 8 */ |
||
959 | fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ |
||
960 | else |
||
961 | fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ |
||
962 | |||
963 | fp2_gen_cntl &= ~(RADEON_FP2_ON | |
||
964 | RADEON_FP2_DVO_EN | |
||
965 | RADEON_FP2_DVO_RATE_SEL_SDR); |
||
966 | |||
967 | /* XXX: these are oem specific */ |
||
968 | if (ASIC_IS_R300(rdev)) { |
||
969 | if ((dev->pdev->device == 0x4850) && |
||
970 | (dev->pdev->subsystem_vendor == 0x1028) && |
||
971 | (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ |
||
972 | fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; |
||
973 | else |
||
974 | fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; |
||
975 | |||
976 | /*if (mode->clock > 165000) |
||
977 | fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ |
||
978 | } |
||
1321 | serge | 979 | if (!radeon_combios_external_tmds_setup(encoder)) |
980 | radeon_external_tmds_setup(encoder); |
||
1123 | serge | 981 | } |
982 | |||
983 | if (radeon_crtc->crtc_id == 0) { |
||
984 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
||
985 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
||
1179 | serge | 986 | if (radeon_encoder->rmx_type != RMX_OFF) |
1123 | serge | 987 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; |
988 | else |
||
989 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; |
||
990 | } else |
||
991 | fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; |
||
992 | } else { |
||
993 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
||
994 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
||
995 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
||
996 | } else |
||
997 | fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; |
||
998 | } |
||
999 | |||
1000 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
1001 | |||
1002 | if (rdev->is_atom_bios) |
||
1003 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
1004 | else |
||
1005 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
1006 | } |
||
1007 | |||
1321 | serge | 1008 | static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) |
1009 | { |
||
1010 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
2997 | Serge | 1011 | /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */ |
1321 | serge | 1012 | kfree(radeon_encoder->enc_priv); |
1013 | drm_encoder_cleanup(encoder); |
||
1014 | kfree(radeon_encoder); |
||
1015 | } |
||
1016 | |||
1123 | serge | 1017 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { |
1018 | .dpms = radeon_legacy_tmds_ext_dpms, |
||
1321 | serge | 1019 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 1020 | .prepare = radeon_legacy_tmds_ext_prepare, |
1021 | .mode_set = radeon_legacy_tmds_ext_mode_set, |
||
1022 | .commit = radeon_legacy_tmds_ext_commit, |
||
1179 | serge | 1023 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 1024 | }; |
1025 | |||
1026 | |||
1027 | static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { |
||
1321 | serge | 1028 | .destroy = radeon_ext_tmds_enc_destroy, |
1123 | serge | 1029 | }; |
1030 | |||
1031 | static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) |
||
1032 | { |
||
1033 | struct drm_device *dev = encoder->dev; |
||
1034 | struct radeon_device *rdev = dev->dev_private; |
||
1179 | serge | 1035 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1123 | serge | 1036 | uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; |
1179 | serge | 1037 | uint32_t tv_master_cntl = 0; |
1038 | bool is_tv; |
||
1963 | serge | 1039 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 1040 | |
1179 | serge | 1041 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
1042 | |||
1123 | serge | 1043 | if (rdev->family == CHIP_R200) |
1044 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
1045 | else { |
||
1179 | serge | 1046 | if (is_tv) |
1047 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
||
1048 | else |
||
6104 | serge | 1049 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
1123 | serge | 1050 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
1051 | } |
||
1052 | |||
1053 | switch (mode) { |
||
1054 | case DRM_MODE_DPMS_ON: |
||
1055 | if (rdev->family == CHIP_R200) { |
||
1056 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
1057 | } else { |
||
1179 | serge | 1058 | if (is_tv) |
1059 | tv_master_cntl |= RADEON_TV_ON; |
||
1060 | else |
||
6104 | serge | 1061 | crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; |
1179 | serge | 1062 | |
1123 | serge | 1063 | if (rdev->family == CHIP_R420 || |
6104 | serge | 1064 | rdev->family == CHIP_R423 || |
1065 | rdev->family == CHIP_RV410) |
||
1123 | serge | 1066 | tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | |
6104 | serge | 1067 | R420_TV_DAC_GDACPD | |
1068 | R420_TV_DAC_BDACPD | |
||
1069 | RADEON_TV_DAC_BGSLEEP); |
||
1123 | serge | 1070 | else |
1071 | tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | |
||
6104 | serge | 1072 | RADEON_TV_DAC_GDACPD | |
1073 | RADEON_TV_DAC_BDACPD | |
||
1074 | RADEON_TV_DAC_BGSLEEP); |
||
1123 | serge | 1075 | } |
1076 | break; |
||
1077 | case DRM_MODE_DPMS_STANDBY: |
||
1078 | case DRM_MODE_DPMS_SUSPEND: |
||
1079 | case DRM_MODE_DPMS_OFF: |
||
1080 | if (rdev->family == CHIP_R200) |
||
1081 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
||
1082 | else { |
||
1179 | serge | 1083 | if (is_tv) |
1084 | tv_master_cntl &= ~RADEON_TV_ON; |
||
1085 | else |
||
6104 | serge | 1086 | crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; |
1179 | serge | 1087 | |
1123 | serge | 1088 | if (rdev->family == CHIP_R420 || |
6104 | serge | 1089 | rdev->family == CHIP_R423 || |
1090 | rdev->family == CHIP_RV410) |
||
1123 | serge | 1091 | tv_dac_cntl |= (R420_TV_DAC_RDACPD | |
1092 | R420_TV_DAC_GDACPD | |
||
1093 | R420_TV_DAC_BDACPD | |
||
1094 | RADEON_TV_DAC_BGSLEEP); |
||
1095 | else |
||
1096 | tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | |
||
1097 | RADEON_TV_DAC_GDACPD | |
||
1098 | RADEON_TV_DAC_BDACPD | |
||
1099 | RADEON_TV_DAC_BGSLEEP); |
||
1100 | } |
||
1101 | break; |
||
1102 | } |
||
1103 | |||
1104 | if (rdev->family == CHIP_R200) { |
||
1105 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
1106 | } else { |
||
1179 | serge | 1107 | if (is_tv) |
1108 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
||
3120 | serge | 1109 | /* handled in radeon_crtc_dpms() */ |
1110 | else if (!(rdev->flags & RADEON_SINGLE_CRTC)) |
||
6104 | serge | 1111 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
1123 | serge | 1112 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
1113 | } |
||
1114 | |||
1115 | if (rdev->is_atom_bios) |
||
1116 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1117 | else |
||
1118 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
||
1430 | serge | 1119 | |
1123 | serge | 1120 | } |
1121 | |||
1122 | static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) |
||
1123 | { |
||
1124 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
1125 | |||
1126 | if (rdev->is_atom_bios) |
||
1127 | radeon_atom_output_lock(encoder, true); |
||
1128 | else |
||
1129 | radeon_combios_output_lock(encoder, true); |
||
1130 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
||
1131 | } |
||
1132 | |||
1133 | static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) |
||
1134 | { |
||
1135 | struct radeon_device *rdev = encoder->dev->dev_private; |
||
1136 | |||
1137 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
||
1138 | |||
1139 | if (rdev->is_atom_bios) |
||
1140 | radeon_atom_output_lock(encoder, true); |
||
1141 | else |
||
1142 | radeon_combios_output_lock(encoder, true); |
||
1143 | } |
||
1144 | |||
1145 | static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, |
||
1146 | struct drm_display_mode *mode, |
||
1147 | struct drm_display_mode *adjusted_mode) |
||
1148 | { |
||
1149 | struct drm_device *dev = encoder->dev; |
||
1150 | struct radeon_device *rdev = dev->dev_private; |
||
1151 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
||
1152 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1179 | serge | 1153 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
1123 | serge | 1154 | uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; |
1179 | serge | 1155 | uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; |
1156 | bool is_tv = false; |
||
1123 | serge | 1157 | |
1963 | serge | 1158 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 1159 | |
1179 | serge | 1160 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
1123 | serge | 1161 | |
1162 | if (rdev->family != CHIP_R200) { |
||
1163 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
1164 | if (rdev->family == CHIP_R420 || |
||
6104 | serge | 1165 | rdev->family == CHIP_R423 || |
1166 | rdev->family == CHIP_RV410) { |
||
1123 | serge | 1167 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
6104 | serge | 1168 | RADEON_TV_DAC_BGADJ_MASK | |
1169 | R420_TV_DAC_DACADJ_MASK | |
||
1170 | R420_TV_DAC_RDACPD | |
||
1171 | R420_TV_DAC_GDACPD | |
||
1172 | R420_TV_DAC_BDACPD | |
||
1173 | R420_TV_DAC_TVENABLE); |
||
1123 | serge | 1174 | } else { |
1175 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
||
6104 | serge | 1176 | RADEON_TV_DAC_BGADJ_MASK | |
1177 | RADEON_TV_DAC_DACADJ_MASK | |
||
1178 | RADEON_TV_DAC_RDACPD | |
||
1179 | RADEON_TV_DAC_GDACPD | |
||
1180 | RADEON_TV_DAC_BDACPD); |
||
1123 | serge | 1181 | } |
1182 | |||
1963 | serge | 1183 | tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; |
1184 | |||
1185 | if (is_tv) { |
||
1186 | if (tv_dac->tv_std == TV_STD_NTSC || |
||
1187 | tv_dac->tv_std == TV_STD_NTSC_J || |
||
1188 | tv_dac->tv_std == TV_STD_PAL_M || |
||
1189 | tv_dac->tv_std == TV_STD_PAL_60) |
||
1190 | tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; |
||
1191 | else |
||
1192 | tv_dac_cntl |= tv_dac->pal_tvdac_adj; |
||
1193 | |||
1194 | if (tv_dac->tv_std == TV_STD_NTSC || |
||
1195 | tv_dac->tv_std == TV_STD_NTSC_J) |
||
1196 | tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; |
||
1197 | else |
||
1198 | tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; |
||
1199 | } else |
||
1200 | tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | |
||
1123 | serge | 1201 | tv_dac->ps2_tvdac_adj); |
1202 | |||
1203 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
1204 | } |
||
1205 | |||
1206 | if (ASIC_IS_R300(rdev)) { |
||
1207 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; |
||
1208 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
||
1963 | serge | 1209 | } else if (rdev->family != CHIP_R200) |
1210 | disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
||
1211 | else if (rdev->family == CHIP_R200) |
||
1212 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
1179 | serge | 1213 | |
1963 | serge | 1214 | if (rdev->family >= CHIP_R200) |
1179 | serge | 1215 | disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); |
1123 | serge | 1216 | |
1179 | serge | 1217 | if (is_tv) { |
1218 | uint32_t dac_cntl; |
||
1219 | |||
1220 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
||
1221 | dac_cntl &= ~RADEON_DAC_TVO_EN; |
||
1222 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
||
1223 | |||
1224 | if (ASIC_IS_R300(rdev)) |
||
1225 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; |
||
1226 | |||
1227 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; |
||
1228 | if (radeon_crtc->crtc_id == 0) { |
||
1229 | if (ASIC_IS_R300(rdev)) { |
||
1230 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1231 | disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | |
||
1232 | RADEON_DISP_TV_SOURCE_CRTC); |
||
1233 | } |
||
1234 | if (rdev->family >= CHIP_R200) { |
||
1235 | disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; |
||
1236 | } else { |
||
1237 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
||
1238 | } |
||
1239 | } else { |
||
1240 | if (ASIC_IS_R300(rdev)) { |
||
1241 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1242 | disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; |
||
1243 | } |
||
1244 | if (rdev->family >= CHIP_R200) { |
||
1245 | disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; |
||
1246 | } else { |
||
1247 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
||
1248 | } |
||
1249 | } |
||
1250 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
1251 | } else { |
||
1252 | |||
6104 | serge | 1253 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; |
1123 | serge | 1254 | |
6104 | serge | 1255 | if (radeon_crtc->crtc_id == 0) { |
1256 | if (ASIC_IS_R300(rdev)) { |
||
1257 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1258 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; |
||
1259 | } else if (rdev->family == CHIP_R200) { |
||
1260 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
||
1261 | RADEON_FP2_DVO_RATE_SEL_SDR); |
||
1262 | } else |
||
1263 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
||
1264 | } else { |
||
1265 | if (ASIC_IS_R300(rdev)) { |
||
1266 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1267 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
||
1268 | } else if (rdev->family == CHIP_R200) { |
||
1269 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
||
1270 | RADEON_FP2_DVO_RATE_SEL_SDR); |
||
1271 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
||
1272 | } else |
||
1273 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
||
1274 | } |
||
1275 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
1123 | serge | 1276 | } |
1277 | |||
1278 | if (ASIC_IS_R300(rdev)) { |
||
1279 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
||
1179 | serge | 1280 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
1963 | serge | 1281 | } else if (rdev->family != CHIP_R200) |
1282 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
||
1283 | else if (rdev->family == CHIP_R200) |
||
1284 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
1179 | serge | 1285 | |
1286 | if (rdev->family >= CHIP_R200) |
||
1287 | WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); |
||
1123 | serge | 1288 | |
1179 | serge | 1289 | if (is_tv) |
1290 | radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); |
||
1291 | |||
1123 | serge | 1292 | if (rdev->is_atom_bios) |
1293 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
1294 | else |
||
1295 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
||
1296 | |||
1297 | } |
||
1298 | |||
1179 | serge | 1299 | static bool r300_legacy_tv_detect(struct drm_encoder *encoder, |
1300 | struct drm_connector *connector) |
||
1301 | { |
||
1302 | struct drm_device *dev = encoder->dev; |
||
1303 | struct radeon_device *rdev = dev->dev_private; |
||
1304 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
||
1305 | uint32_t disp_output_cntl, gpiopad_a, tmp; |
||
1306 | bool found = false; |
||
1307 | |||
1308 | /* save regs needed */ |
||
1309 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
||
1310 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
||
1311 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
1312 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
||
1313 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
1314 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
||
1315 | |||
1316 | WREG32_P(RADEON_GPIOPAD_A, 0, ~1); |
||
1317 | |||
1318 | WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); |
||
1319 | |||
1320 | WREG32(RADEON_CRTC2_GEN_CNTL, |
||
1321 | RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); |
||
1322 | |||
1323 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
||
1324 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
||
1325 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
||
1326 | |||
1327 | WREG32(RADEON_DAC_EXT_CNTL, |
||
1328 | RADEON_DAC2_FORCE_BLANK_OFF_EN | |
||
1329 | RADEON_DAC2_FORCE_DATA_EN | |
||
1330 | RADEON_DAC_FORCE_DATA_SEL_RGB | |
||
1331 | (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); |
||
1332 | |||
1333 | WREG32(RADEON_TV_DAC_CNTL, |
||
1334 | RADEON_TV_DAC_STD_NTSC | |
||
1335 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
||
1336 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
||
1337 | |||
1338 | RREG32(RADEON_TV_DAC_CNTL); |
||
1339 | mdelay(4); |
||
1340 | |||
1341 | WREG32(RADEON_TV_DAC_CNTL, |
||
1342 | RADEON_TV_DAC_NBLANK | |
||
1343 | RADEON_TV_DAC_NHOLD | |
||
1344 | RADEON_TV_MONITOR_DETECT_EN | |
||
1345 | RADEON_TV_DAC_STD_NTSC | |
||
1346 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
||
1347 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
||
1348 | |||
1349 | RREG32(RADEON_TV_DAC_CNTL); |
||
1350 | mdelay(6); |
||
1351 | |||
1352 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
||
1353 | if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { |
||
1354 | found = true; |
||
1963 | serge | 1355 | DRM_DEBUG_KMS("S-video TV connection detected\n"); |
1179 | serge | 1356 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
1357 | found = true; |
||
1963 | serge | 1358 | DRM_DEBUG_KMS("Composite TV connection detected\n"); |
1179 | serge | 1359 | } |
1360 | |||
1361 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
1362 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
||
1363 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
1364 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
1365 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
||
1366 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
||
1367 | return found; |
||
1368 | } |
||
1369 | |||
1370 | static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, |
||
1371 | struct drm_connector *connector) |
||
1372 | { |
||
1373 | struct drm_device *dev = encoder->dev; |
||
1374 | struct radeon_device *rdev = dev->dev_private; |
||
1375 | uint32_t tv_dac_cntl, dac_cntl2; |
||
1376 | uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; |
||
1377 | bool found = false; |
||
1378 | |||
1379 | if (ASIC_IS_R300(rdev)) |
||
1380 | return r300_legacy_tv_detect(encoder, connector); |
||
1381 | |||
1382 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
||
1383 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
||
1384 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
1385 | config_cntl = RREG32(RADEON_CONFIG_CNTL); |
||
1386 | tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); |
||
1387 | |||
1388 | tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; |
||
1389 | WREG32(RADEON_DAC_CNTL2, tmp); |
||
1390 | |||
1391 | tmp = tv_master_cntl | RADEON_TV_ON; |
||
1392 | tmp &= ~(RADEON_TV_ASYNC_RST | |
||
1393 | RADEON_RESTART_PHASE_FIX | |
||
1394 | RADEON_CRT_FIFO_CE_EN | |
||
1395 | RADEON_TV_FIFO_CE_EN | |
||
1396 | RADEON_RE_SYNC_NOW_SEL_MASK); |
||
1397 | tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; |
||
1398 | WREG32(RADEON_TV_MASTER_CNTL, tmp); |
||
1399 | |||
1400 | tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | |
||
1401 | RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | |
||
1402 | (8 << RADEON_TV_DAC_BGADJ_SHIFT); |
||
1403 | |||
1404 | if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) |
||
1405 | tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); |
||
1406 | else |
||
1407 | tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); |
||
1408 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
||
1409 | |||
1410 | tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | |
||
1411 | RADEON_RED_MX_FORCE_DAC_DATA | |
||
1412 | RADEON_GRN_MX_FORCE_DAC_DATA | |
||
1413 | RADEON_BLU_MX_FORCE_DAC_DATA | |
||
1414 | (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); |
||
1415 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); |
||
1416 | |||
1417 | mdelay(3); |
||
1418 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
||
1419 | if (tmp & RADEON_TV_DAC_GDACDET) { |
||
1420 | found = true; |
||
1963 | serge | 1421 | DRM_DEBUG_KMS("S-video TV connection detected\n"); |
1179 | serge | 1422 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
1423 | found = true; |
||
1963 | serge | 1424 | DRM_DEBUG_KMS("Composite TV connection detected\n"); |
1179 | serge | 1425 | } |
1426 | |||
1427 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); |
||
1428 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
1429 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
||
1430 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
||
1431 | return found; |
||
1432 | } |
||
1433 | |||
3120 | serge | 1434 | static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, |
1435 | struct drm_connector *connector) |
||
1436 | { |
||
1437 | struct drm_device *dev = encoder->dev; |
||
1438 | struct radeon_device *rdev = dev->dev_private; |
||
1439 | uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; |
||
1440 | uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; |
||
1441 | uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; |
||
1442 | uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; |
||
1443 | uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; |
||
1444 | bool found = false; |
||
1445 | int i; |
||
1446 | |||
1447 | /* save the regs we need */ |
||
1448 | gpio_monid = RREG32(RADEON_GPIO_MONID); |
||
1449 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
||
1450 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
||
1451 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
1452 | disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); |
||
1453 | disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); |
||
1454 | disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); |
||
1455 | disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D); |
||
1456 | disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E); |
||
1457 | disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F); |
||
1458 | crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP); |
||
1459 | crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP); |
||
1460 | crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID); |
||
1461 | crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID); |
||
1462 | |||
1463 | tmp = RREG32(RADEON_GPIO_MONID); |
||
1464 | tmp &= ~RADEON_GPIO_A_0; |
||
1465 | WREG32(RADEON_GPIO_MONID, tmp); |
||
1466 | |||
1467 | WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON | |
||
1468 | RADEON_FP2_PANEL_FORMAT | |
||
1469 | R200_FP2_SOURCE_SEL_TRANS_UNIT | |
||
1470 | RADEON_FP2_DVO_EN | |
||
1471 | R200_FP2_DVO_RATE_SEL_SDR)); |
||
1472 | |||
1473 | WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | |
||
1474 | RADEON_DISP_TRANS_MATRIX_GRAPHICS)); |
||
1475 | |||
1476 | WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | |
||
1477 | RADEON_CRTC2_DISP_REQ_EN_B)); |
||
1478 | |||
1479 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); |
||
1480 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); |
||
1481 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); |
||
1482 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); |
||
1483 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); |
||
1484 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); |
||
1485 | |||
1486 | WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); |
||
1487 | WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); |
||
1488 | WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); |
||
1489 | WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); |
||
1490 | |||
1491 | for (i = 0; i < 200; i++) { |
||
1492 | tmp = RREG32(RADEON_GPIO_MONID); |
||
1493 | if (tmp & RADEON_GPIO_Y_0) |
||
1494 | found = true; |
||
1495 | |||
1496 | if (found) |
||
1497 | break; |
||
1498 | |||
6104 | serge | 1499 | if (!drm_can_sleep()) |
1500 | mdelay(1); |
||
1501 | else |
||
3120 | serge | 1502 | msleep(1); |
1503 | } |
||
1504 | |||
1505 | /* restore the regs we used */ |
||
1506 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); |
||
1507 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); |
||
1508 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); |
||
1509 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); |
||
1510 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); |
||
1511 | WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); |
||
1512 | WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); |
||
1513 | WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); |
||
1514 | WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); |
||
1515 | WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); |
||
1516 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
1517 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
1518 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
1519 | WREG32(RADEON_GPIO_MONID, gpio_monid); |
||
1520 | |||
1521 | return found; |
||
1522 | } |
||
1523 | |||
1123 | serge | 1524 | static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, |
1525 | struct drm_connector *connector) |
||
1526 | { |
||
1527 | struct drm_device *dev = encoder->dev; |
||
1528 | struct radeon_device *rdev = dev->dev_private; |
||
3120 | serge | 1529 | uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
1530 | uint32_t gpiopad_a = 0, pixclks_cntl, tmp; |
||
1531 | uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0; |
||
1123 | serge | 1532 | enum drm_connector_status found = connector_status_disconnected; |
1179 | serge | 1533 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1534 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
||
1123 | serge | 1535 | bool color = true; |
1963 | serge | 1536 | struct drm_crtc *crtc; |
1123 | serge | 1537 | |
1963 | serge | 1538 | /* find out if crtc2 is in use or if this encoder is using it */ |
1539 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
||
1540 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1541 | if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { |
||
1542 | if (encoder->crtc != crtc) { |
||
1543 | return connector_status_disconnected; |
||
1544 | } |
||
1545 | } |
||
1546 | } |
||
1547 | |||
1179 | serge | 1548 | if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || |
1549 | connector->connector_type == DRM_MODE_CONNECTOR_Composite || |
||
1550 | connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { |
||
1551 | bool tv_detect; |
||
1123 | serge | 1552 | |
1179 | serge | 1553 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) |
1554 | return connector_status_disconnected; |
||
1555 | |||
1556 | tv_detect = radeon_legacy_tv_detect(encoder, connector); |
||
1557 | if (tv_detect && tv_dac) |
||
1558 | found = connector_status_connected; |
||
1559 | return found; |
||
1560 | } |
||
1561 | |||
1562 | /* don't probe if the encoder is being used for something else not CRT related */ |
||
1563 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { |
||
1564 | DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); |
||
1565 | return connector_status_disconnected; |
||
1566 | } |
||
1567 | |||
3120 | serge | 1568 | /* R200 uses an external DAC for secondary DAC */ |
1569 | if (rdev->family == CHIP_R200) { |
||
1570 | if (radeon_legacy_ext_dac_detect(encoder, connector)) |
||
1571 | found = connector_status_connected; |
||
1572 | return found; |
||
1573 | } |
||
1574 | |||
1123 | serge | 1575 | /* save the regs we need */ |
1576 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
3120 | serge | 1577 | |
1578 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
1579 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
1580 | } else { |
||
1581 | if (ASIC_IS_R300(rdev)) { |
||
1582 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
||
1583 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
||
1584 | } else { |
||
1585 | disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
||
1586 | } |
||
6104 | serge | 1587 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
3120 | serge | 1588 | } |
1123 | serge | 1589 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
1590 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
||
1591 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
||
1592 | |||
1593 | tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb |
||
1594 | | RADEON_PIX2CLK_DAC_ALWAYS_ONb); |
||
1595 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
1596 | |||
3120 | serge | 1597 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
1598 | tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; |
||
1599 | WREG32(RADEON_CRTC_EXT_CNTL, tmp); |
||
1600 | } else { |
||
6104 | serge | 1601 | tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; |
1602 | tmp |= RADEON_CRTC2_CRT2_ON | |
||
1603 | (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); |
||
1604 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
||
1123 | serge | 1605 | |
6104 | serge | 1606 | if (ASIC_IS_R300(rdev)) { |
3120 | serge | 1607 | WREG32_P(RADEON_GPIOPAD_A, 1, ~1); |
6104 | serge | 1608 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
1609 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
||
1610 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
||
1611 | } else { |
||
1612 | tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; |
||
1613 | WREG32(RADEON_DISP_HW_DEBUG, tmp); |
||
1614 | } |
||
1123 | serge | 1615 | } |
1616 | |||
1617 | tmp = RADEON_TV_DAC_NBLANK | |
||
1618 | RADEON_TV_DAC_NHOLD | |
||
1619 | RADEON_TV_MONITOR_DETECT_EN | |
||
1620 | RADEON_TV_DAC_STD_PS2; |
||
1621 | |||
1622 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
||
1623 | |||
1624 | tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | |
||
1625 | RADEON_DAC2_FORCE_DATA_EN; |
||
1626 | |||
1627 | if (color) |
||
1628 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
||
1629 | else |
||
1630 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
||
1631 | |||
1632 | if (ASIC_IS_R300(rdev)) |
||
1633 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
1634 | else |
||
1635 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
||
1636 | |||
1637 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
||
1638 | |||
1639 | tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; |
||
1640 | WREG32(RADEON_DAC_CNTL2, tmp); |
||
1641 | |||
2997 | Serge | 1642 | mdelay(10); |
1123 | serge | 1643 | |
1644 | if (ASIC_IS_R300(rdev)) { |
||
1645 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) |
||
1646 | found = connector_status_connected; |
||
1647 | } else { |
||
1648 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) |
||
1649 | found = connector_status_connected; |
||
1650 | } |
||
1651 | |||
1652 | /* restore regs we used */ |
||
1653 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
||
1654 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
||
1655 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
3120 | serge | 1656 | |
1657 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
1658 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
1659 | } else { |
||
6104 | serge | 1660 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
1661 | if (ASIC_IS_R300(rdev)) { |
||
1662 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
||
1663 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
||
1664 | } else { |
||
1665 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
||
1666 | } |
||
1123 | serge | 1667 | } |
3120 | serge | 1668 | |
1123 | serge | 1669 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
1670 | |||
1179 | serge | 1671 | return found; |
1123 | serge | 1672 | |
1673 | } |
||
1674 | |||
1675 | static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { |
||
1676 | .dpms = radeon_legacy_tv_dac_dpms, |
||
1321 | serge | 1677 | .mode_fixup = radeon_legacy_mode_fixup, |
1123 | serge | 1678 | .prepare = radeon_legacy_tv_dac_prepare, |
1679 | .mode_set = radeon_legacy_tv_dac_mode_set, |
||
1680 | .commit = radeon_legacy_tv_dac_commit, |
||
1681 | .detect = radeon_legacy_tv_dac_detect, |
||
1179 | serge | 1682 | .disable = radeon_legacy_encoder_disable, |
1123 | serge | 1683 | }; |
1684 | |||
1685 | |||
1686 | static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { |
||
1687 | .destroy = radeon_enc_destroy, |
||
1688 | }; |
||
1689 | |||
1179 | serge | 1690 | |
1691 | static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) |
||
1692 | { |
||
1693 | struct drm_device *dev = encoder->base.dev; |
||
1694 | struct radeon_device *rdev = dev->dev_private; |
||
1695 | struct radeon_encoder_int_tmds *tmds = NULL; |
||
1696 | bool ret; |
||
1697 | |||
1698 | tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
||
1699 | |||
1700 | if (!tmds) |
||
1701 | return NULL; |
||
1702 | |||
1703 | if (rdev->is_atom_bios) |
||
1704 | ret = radeon_atombios_get_tmds_info(encoder, tmds); |
||
1705 | else |
||
1706 | ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); |
||
1707 | |||
1708 | if (ret == false) |
||
1709 | radeon_legacy_get_tmds_info_from_table(encoder, tmds); |
||
1710 | |||
1711 | return tmds; |
||
1712 | } |
||
1713 | |||
1321 | serge | 1714 | static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) |
1715 | { |
||
1716 | struct drm_device *dev = encoder->base.dev; |
||
1717 | struct radeon_device *rdev = dev->dev_private; |
||
1718 | struct radeon_encoder_ext_tmds *tmds = NULL; |
||
1719 | bool ret; |
||
1720 | |||
1721 | if (rdev->is_atom_bios) |
||
1722 | return NULL; |
||
1723 | |||
1724 | tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); |
||
1725 | |||
1726 | if (!tmds) |
||
1727 | return NULL; |
||
1728 | |||
1729 | ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); |
||
1730 | |||
1731 | if (ret == false) |
||
1732 | radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); |
||
1733 | |||
1734 | return tmds; |
||
1735 | } |
||
1736 | |||
1123 | serge | 1737 | void |
1963 | serge | 1738 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) |
1123 | serge | 1739 | { |
1740 | struct radeon_device *rdev = dev->dev_private; |
||
1741 | struct drm_encoder *encoder; |
||
1742 | struct radeon_encoder *radeon_encoder; |
||
1743 | |||
1744 | /* see if we already added it */ |
||
1745 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
1746 | radeon_encoder = to_radeon_encoder(encoder); |
||
1963 | serge | 1747 | if (radeon_encoder->encoder_enum == encoder_enum) { |
1123 | serge | 1748 | radeon_encoder->devices |= supported_device; |
1749 | return; |
||
1750 | } |
||
1751 | |||
1752 | } |
||
1753 | |||
1754 | /* add a new one */ |
||
1755 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
||
1756 | if (!radeon_encoder) |
||
1757 | return; |
||
1758 | |||
1759 | encoder = &radeon_encoder->base; |
||
1221 | serge | 1760 | if (rdev->flags & RADEON_SINGLE_CRTC) |
1761 | encoder->possible_crtcs = 0x1; |
||
1762 | else |
||
6104 | serge | 1763 | encoder->possible_crtcs = 0x3; |
1123 | serge | 1764 | |
1765 | radeon_encoder->enc_priv = NULL; |
||
1766 | |||
1963 | serge | 1767 | radeon_encoder->encoder_enum = encoder_enum; |
1768 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
||
1123 | serge | 1769 | radeon_encoder->devices = supported_device; |
1179 | serge | 1770 | radeon_encoder->rmx_type = RMX_OFF; |
1123 | serge | 1771 | |
1772 | switch (radeon_encoder->encoder_id) { |
||
1773 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
||
1179 | serge | 1774 | encoder->possible_crtcs = 0x1; |
6938 | serge | 1775 | drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, |
1776 | DRM_MODE_ENCODER_LVDS, NULL); |
||
1123 | serge | 1777 | drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); |
1778 | if (rdev->is_atom_bios) |
||
1779 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
||
1780 | else |
||
1781 | radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); |
||
1782 | radeon_encoder->rmx_type = RMX_FULL; |
||
1783 | break; |
||
1784 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
||
6938 | serge | 1785 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, |
1786 | DRM_MODE_ENCODER_TMDS, NULL); |
||
1123 | serge | 1787 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); |
1179 | serge | 1788 | radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); |
1123 | serge | 1789 | break; |
1790 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
||
6938 | serge | 1791 | drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, |
1792 | DRM_MODE_ENCODER_DAC, NULL); |
||
1123 | serge | 1793 | drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); |
1794 | if (rdev->is_atom_bios) |
||
1795 | radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); |
||
1796 | else |
||
1797 | radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); |
||
1798 | break; |
||
1799 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
||
6938 | serge | 1800 | drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, |
1801 | DRM_MODE_ENCODER_TVDAC, NULL); |
||
1123 | serge | 1802 | drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); |
1803 | if (rdev->is_atom_bios) |
||
1804 | radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); |
||
1805 | else |
||
1806 | radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); |
||
1807 | break; |
||
1808 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
||
6938 | serge | 1809 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, |
1810 | DRM_MODE_ENCODER_TMDS, NULL); |
||
1123 | serge | 1811 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); |
1812 | if (!rdev->is_atom_bios) |
||
1321 | serge | 1813 | radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); |
1123 | serge | 1814 | break; |
1815 | } |
||
1816 | }><>><>><>>><>><>><>><>><>><>><>><>><>>>><>><>><>><>><>>><>><>><>><>><> |