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5078 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | * Christian König |
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28 | */ |
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29 | #include |
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30 | #include "radeon.h" |
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31 | |||
32 | /* |
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33 | * IB |
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34 | * IBs (Indirect Buffers) and areas of GPU accessible memory where |
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35 | * commands are stored. You can put a pointer to the IB in the |
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36 | * command ring and the hw will fetch the commands from the IB |
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37 | * and execute them. Generally userspace acceleration drivers |
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38 | * produce command buffers which are send to the kernel and |
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39 | * put in IBs for execution by the requested ring. |
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40 | */ |
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41 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
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42 | |||
43 | /** |
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44 | * radeon_ib_get - request an IB (Indirect Buffer) |
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45 | * |
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46 | * @rdev: radeon_device pointer |
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47 | * @ring: ring index the IB is associated with |
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48 | * @ib: IB object returned |
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49 | * @size: requested IB size |
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50 | * |
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51 | * Request an IB (all asics). IBs are allocated using the |
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52 | * suballocator. |
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53 | * Returns 0 on success, error on failure. |
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54 | */ |
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55 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
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56 | struct radeon_ib *ib, struct radeon_vm *vm, |
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57 | unsigned size) |
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58 | { |
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59 | int r; |
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60 | |||
61 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256); |
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62 | if (r) { |
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63 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); |
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64 | return r; |
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65 | } |
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66 | |||
67 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
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68 | if (r) { |
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69 | return r; |
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70 | } |
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71 | |||
72 | ib->ring = ring; |
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73 | ib->fence = NULL; |
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74 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
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75 | ib->vm = vm; |
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76 | if (vm) { |
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77 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
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78 | * space and soffset is the offset inside the pool bo |
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79 | */ |
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80 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
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81 | } else { |
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82 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); |
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83 | } |
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84 | ib->is_const_ib = false; |
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85 | |||
86 | return 0; |
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87 | } |
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88 | |||
89 | /** |
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90 | * radeon_ib_free - free an IB (Indirect Buffer) |
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91 | * |
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92 | * @rdev: radeon_device pointer |
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93 | * @ib: IB object to free |
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94 | * |
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95 | * Free an IB (all asics). |
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96 | */ |
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97 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
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98 | { |
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99 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
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100 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
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101 | radeon_fence_unref(&ib->fence); |
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102 | } |
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103 | |||
104 | /** |
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105 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring |
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106 | * |
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107 | * @rdev: radeon_device pointer |
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108 | * @ib: IB object to schedule |
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109 | * @const_ib: Const IB to schedule (SI only) |
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110 | * @hdp_flush: Whether or not to perform an HDP cache flush |
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111 | * |
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112 | * Schedule an IB on the associated ring (all asics). |
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113 | * Returns 0 on success, error on failure. |
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114 | * |
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115 | * On SI, there are two parallel engines fed from the primary ring, |
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116 | * the CE (Constant Engine) and the DE (Drawing Engine). Since |
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117 | * resource descriptors have moved to memory, the CE allows you to |
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118 | * prime the caches while the DE is updating register state so that |
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119 | * the resource descriptors will be already in cache when the draw is |
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120 | * processed. To accomplish this, the userspace driver submits two |
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121 | * IBs, one for the CE and one for the DE. If there is a CE IB (called |
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122 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior |
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123 | * to SI there was just a DE IB. |
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124 | */ |
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125 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
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126 | struct radeon_ib *const_ib, bool hdp_flush) |
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127 | { |
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128 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
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129 | int r = 0; |
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130 | |||
131 | if (!ib->length_dw || !ring->ready) { |
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132 | /* TODO: Nothings in the ib we should report. */ |
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133 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
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134 | return -EINVAL; |
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135 | } |
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136 | |||
137 | /* 64 dwords should be enough for fence too */ |
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138 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8); |
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139 | if (r) { |
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140 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
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141 | return r; |
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142 | } |
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143 | |||
144 | /* grab a vm id if necessary */ |
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145 | if (ib->vm) { |
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146 | struct radeon_fence *vm_id_fence; |
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147 | vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring); |
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148 | radeon_semaphore_sync_to(ib->semaphore, vm_id_fence); |
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149 | } |
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150 | |||
151 | /* sync with other rings */ |
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152 | r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring); |
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153 | if (r) { |
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154 | dev_err(rdev->dev, "failed to sync rings (%d)\n", r); |
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155 | radeon_ring_unlock_undo(rdev, ring); |
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156 | return r; |
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157 | } |
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158 | |||
159 | if (ib->vm) |
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160 | radeon_vm_flush(rdev, ib->vm, ib->ring); |
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161 | |||
162 | if (const_ib) { |
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163 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); |
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164 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); |
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165 | } |
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166 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
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167 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); |
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168 | if (r) { |
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169 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); |
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170 | radeon_ring_unlock_undo(rdev, ring); |
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171 | return r; |
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172 | } |
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173 | if (const_ib) { |
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174 | const_ib->fence = radeon_fence_ref(ib->fence); |
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175 | } |
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176 | |||
177 | if (ib->vm) |
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178 | radeon_vm_fence(rdev, ib->vm, ib->fence); |
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179 | |||
180 | radeon_ring_unlock_commit(rdev, ring, hdp_flush); |
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181 | return 0; |
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182 | } |
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183 | |||
184 | /** |
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185 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool |
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186 | * |
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187 | * @rdev: radeon_device pointer |
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188 | * |
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189 | * Initialize the suballocator to manage a pool of memory |
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190 | * for use as IBs (all asics). |
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191 | * Returns 0 on success, error on failure. |
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192 | */ |
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193 | int radeon_ib_pool_init(struct radeon_device *rdev) |
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194 | { |
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195 | int r; |
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196 | |||
197 | if (rdev->ib_pool_ready) { |
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198 | return 0; |
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199 | } |
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200 | |||
201 | if (rdev->family >= CHIP_BONAIRE) { |
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202 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
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203 | RADEON_IB_POOL_SIZE*64*1024, |
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204 | RADEON_GPU_PAGE_SIZE, |
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205 | RADEON_GEM_DOMAIN_GTT, |
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206 | RADEON_GEM_GTT_WC); |
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207 | } else { |
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208 | /* Before CIK, it's better to stick to cacheable GTT due |
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209 | * to the command stream checking |
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210 | */ |
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211 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
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212 | RADEON_IB_POOL_SIZE*64*1024, |
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213 | RADEON_GPU_PAGE_SIZE, |
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214 | RADEON_GEM_DOMAIN_GTT, 0); |
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215 | } |
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216 | if (r) { |
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217 | return r; |
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218 | } |
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219 | |||
220 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); |
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221 | if (r) { |
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222 | return r; |
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223 | } |
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224 | |||
225 | rdev->ib_pool_ready = true; |
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226 | if (radeon_debugfs_sa_init(rdev)) { |
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227 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); |
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228 | } |
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229 | return 0; |
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230 | } |
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231 | |||
232 | /** |
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233 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool |
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234 | * |
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235 | * @rdev: radeon_device pointer |
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236 | * |
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237 | * Tear down the suballocator managing the pool of memory |
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238 | * for use as IBs (all asics). |
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239 | */ |
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240 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
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241 | { |
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242 | if (rdev->ib_pool_ready) { |
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243 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
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244 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
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245 | rdev->ib_pool_ready = false; |
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246 | } |
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247 | } |
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248 | |||
249 | /** |
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250 | * radeon_ib_ring_tests - test IBs on the rings |
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251 | * |
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252 | * @rdev: radeon_device pointer |
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253 | * |
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254 | * Test an IB (Indirect Buffer) on each ring. |
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255 | * If the test fails, disable the ring. |
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256 | * Returns 0 on success, error if the primary GFX ring |
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257 | * IB test fails. |
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258 | */ |
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259 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
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260 | { |
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261 | unsigned i; |
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262 | int r; |
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263 | |||
264 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
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265 | struct radeon_ring *ring = &rdev->ring[i]; |
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266 | |||
267 | if (!ring->ready) |
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268 | continue; |
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269 | |||
270 | r = radeon_ib_test(rdev, i, ring); |
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271 | if (r) { |
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272 | ring->ready = false; |
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273 | rdev->needs_reset = false; |
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274 | |||
275 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
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276 | /* oh, oh, that's really bad */ |
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277 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
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278 | rdev->accel_working = false; |
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279 | return r; |
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280 | |||
281 | } else { |
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282 | /* still not good, but we can live with it */ |
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283 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
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284 | } |
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285 | } |
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286 | } |
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287 | return 0; |
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288 | } |
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289 | |||
290 | /* |
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291 | * Debugfs info |
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292 | */ |
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293 | #if defined(CONFIG_DEBUG_FS) |
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294 | |||
295 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
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296 | { |
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297 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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298 | struct drm_device *dev = node->minor->dev; |
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299 | struct radeon_device *rdev = dev->dev_private; |
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300 | |||
301 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
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302 | |||
303 | return 0; |
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304 | |||
305 | } |
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306 | |||
307 | static struct drm_info_list radeon_debugfs_sa_list[] = { |
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308 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, |
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309 | }; |
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310 | |||
311 | #endif |
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312 | |||
313 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
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314 | { |
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315 | #if defined(CONFIG_DEBUG_FS) |
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316 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
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317 | #else |
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318 | return 0; |
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319 | #endif |
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320 | }> |