WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_i2c.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "radeon_drm.h"
		28	#include "radeon.h"
1430	serge	29	#include "atom.h"
1123	serge	30
		31	/**
		32	* radeon_ddc_probe
		33	*
		34	*/
		35	bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
		36	{
		37	u8 out_buf[] = { 0x0, 0x0};
		38	u8 buf[2];
		39	int ret;
		40	struct i2c_msg msgs[] = {
		41	{
		42	.addr = 0x50,
		43	.flags = 0,
		44	.len = 1,
		45	.buf = out_buf,
		46	},
		47	{
		48	.addr = 0x50,
		49	.flags = I2C_M_RD,
		50	.len = 1,
		51	.buf = buf,
		52	}
		53	};
		54
1963	serge	55	/* on hw with routers, select right port */
		56	if (radeon_connector->router.ddc_valid)
		57	radeon_router_select_ddc_port(radeon_connector);
		58
1123	serge	59	ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
		60	if (ret == 2)
		61	return true;
		62
		63	return false;
		64	}
		65
1963	serge	66	/* bit banging i2c */
1123	serge	67
1430	serge	68	static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
1123	serge	69	{
1321	serge	70	struct radeon_device *rdev = i2c->dev->dev_private;
		71	struct radeon_i2c_bus_rec *rec = &i2c->rec;
1123	serge	72	uint32_t temp;
		73
		74	/* RV410 appears to have a bug where the hw i2c in reset
		75	* holds the i2c port in a bad state - switch hw i2c away before
		76	* doing DDC - do this for all r200s/r300s/r400s for safety sake
		77	*/
1321	serge	78	if (rec->hw_capable) {
1123	serge	79	if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
1430	serge	80	u32 reg;
		81
		82	if (rdev->family >= CHIP_RV350)
		83	reg = RADEON_GPIO_MONID;
		84	else if ((rdev->family == CHIP_R300) \|\|
		85	(rdev->family == CHIP_R350))
		86	reg = RADEON_GPIO_DVI_DDC;
		87	else
		88	reg = RADEON_GPIO_CRT2_DDC;
		89
		90	mutex_lock(&rdev->dc_hw_i2c_mutex);
		91	if (rec->a_clk_reg == reg) {
1123	serge	92	WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST \|
		93	R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
		94	} else {
		95	WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST \|
		96	R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
		97	}
1630	serge	98	mutex_unlock(&rdev->dc_hw_i2c_mutex);
1123	serge	99	}
1321	serge	100	}
		101
1963	serge	102	/* switch the pads to ddc mode */
		103	if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
		104	temp = RREG32(rec->mask_clk_reg);
		105	temp &= ~(1 << 16);
		106	WREG32(rec->mask_clk_reg, temp);
		107	}
		108
1321	serge	109	/* clear the output pin values */
		110	temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
1123	serge	111	WREG32(rec->a_clk_reg, temp);
		112
1321	serge	113	temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
1123	serge	114	WREG32(rec->a_data_reg, temp);
		115
1321	serge	116	/* set the pins to input */
		117	temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
		118	WREG32(rec->en_clk_reg, temp);
		119
		120	temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
		121	WREG32(rec->en_data_reg, temp);
		122
		123	/* mask the gpio pins for software use */
1123	serge	124	temp = RREG32(rec->mask_clk_reg);
		125	if (lock_state)
		126	temp \|= rec->mask_clk_mask;
		127	else
		128	temp &= ~rec->mask_clk_mask;
		129	WREG32(rec->mask_clk_reg, temp);
		130	temp = RREG32(rec->mask_clk_reg);
		131
		132	temp = RREG32(rec->mask_data_reg);
		133	if (lock_state)
		134	temp \|= rec->mask_data_mask;
		135	else
		136	temp &= ~rec->mask_data_mask;
		137	WREG32(rec->mask_data_reg, temp);
		138	temp = RREG32(rec->mask_data_reg);
		139	}
		140
		141	static int get_clock(void *i2c_priv)
		142	{
		143	struct radeon_i2c_chan *i2c = i2c_priv;
		144	struct radeon_device *rdev = i2c->dev->dev_private;
		145	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		146	uint32_t val;
		147
1321	serge	148	/* read the value off the pin */
		149	val = RREG32(rec->y_clk_reg);
		150	val &= rec->y_clk_mask;
1123	serge	151
		152	return (val != 0);
		153	}
		154
		155
		156	static int get_data(void *i2c_priv)
		157	{
		158	struct radeon_i2c_chan *i2c = i2c_priv;
		159	struct radeon_device *rdev = i2c->dev->dev_private;
		160	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		161	uint32_t val;
		162
1321	serge	163	/* read the value off the pin */
		164	val = RREG32(rec->y_data_reg);
		165	val &= rec->y_data_mask;
		166
1123	serge	167	return (val != 0);
		168	}
		169
		170	static void set_clock(void *i2c_priv, int clock)
		171	{
		172	struct radeon_i2c_chan *i2c = i2c_priv;
		173	struct radeon_device *rdev = i2c->dev->dev_private;
		174	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		175	uint32_t val;
		176
1321	serge	177	/* set pin direction */
		178	val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
		179	val \|= clock ? 0 : rec->en_clk_mask;
		180	WREG32(rec->en_clk_reg, val);
1123	serge	181	}
		182
		183	static void set_data(void *i2c_priv, int data)
		184	{
		185	struct radeon_i2c_chan *i2c = i2c_priv;
		186	struct radeon_device *rdev = i2c->dev->dev_private;
		187	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		188	uint32_t val;
		189
1321	serge	190	/* set pin direction */
		191	val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
		192	val \|= data ? 0 : rec->en_data_mask;
		193	WREG32(rec->en_data_reg, val);
1123	serge	194	}
		195
1963	serge	196	static int pre_xfer(struct i2c_adapter *i2c_adap)
		197	{
		198	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		199
		200	radeon_i2c_do_lock(i2c, 1);
		201
		202	return 0;
		203	}
		204
		205	static void post_xfer(struct i2c_adapter *i2c_adap)
		206	{
		207	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		208
		209	radeon_i2c_do_lock(i2c, 0);
		210	}
		211
		212	/* hw i2c */
		213
1430	serge	214	static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
		215	{
1963	serge	216	u32 sclk = rdev->pm.current_sclk;
1430	serge	217	u32 prescale = 0;
1963	serge	218	u32 nm;
		219	u8 n, m, loop;
1430	serge	220	int i2c_clock;
		221
		222	switch (rdev->family) {
		223	case CHIP_R100:
		224	case CHIP_RV100:
		225	case CHIP_RS100:
		226	case CHIP_RV200:
		227	case CHIP_RS200:
		228	case CHIP_R200:
		229	case CHIP_RV250:
		230	case CHIP_RS300:
		231	case CHIP_RV280:
		232	case CHIP_R300:
		233	case CHIP_R350:
		234	case CHIP_RV350:
1963	serge	235	i2c_clock = 60;
		236	nm = (sclk * 10) / (i2c_clock * 4);
1430	serge	237	for (loop = 1; loop < 255; loop++) {
1963	serge	238	if ((nm / loop) < loop)
1430	serge	239	break;
		240	}
1963	serge	241	n = loop - 1;
		242	m = loop - 2;
		243	prescale = m \| (n << 8);
1430	serge	244	break;
		245	case CHIP_RV380:
		246	case CHIP_RS400:
		247	case CHIP_RS480:
		248	case CHIP_R420:
		249	case CHIP_R423:
		250	case CHIP_RV410:
		251	prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
		252	break;
		253	case CHIP_RS600:
		254	case CHIP_RS690:
		255	case CHIP_RS740:
		256	/* todo */
		257	break;
		258	case CHIP_RV515:
		259	case CHIP_R520:
		260	case CHIP_RV530:
		261	case CHIP_RV560:
		262	case CHIP_RV570:
		263	case CHIP_R580:
		264	i2c_clock = 50;
		265	if (rdev->family == CHIP_R520)
		266	prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
		267	else
		268	prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
		269	break;
		270	case CHIP_R600:
		271	case CHIP_RV610:
		272	case CHIP_RV630:
		273	case CHIP_RV670:
		274	/* todo */
		275	break;
		276	case CHIP_RV620:
		277	case CHIP_RV635:
		278	case CHIP_RS780:
		279	case CHIP_RS880:
		280	case CHIP_RV770:
		281	case CHIP_RV730:
		282	case CHIP_RV710:
		283	case CHIP_RV740:
		284	/* todo */
		285	break;
		286	case CHIP_CEDAR:
		287	case CHIP_REDWOOD:
		288	case CHIP_JUNIPER:
		289	case CHIP_CYPRESS:
		290	case CHIP_HEMLOCK:
		291	/* todo */
		292	break;
		293	default:
		294	DRM_ERROR("i2c: unhandled radeon chip\n");
		295	break;
		296	}
		297	return prescale;
		298	}
		299
		300
		301	/* hw i2c engine for r1xx-4xx hardware
		302	* hw can buffer up to 15 bytes
		303	*/
		304	static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
		305	struct i2c_msg *msgs, int num)
		306	{
		307	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		308	struct radeon_device *rdev = i2c->dev->dev_private;
		309	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		310	struct i2c_msg *p;
		311	int i, j, k, ret = num;
		312	u32 prescale;
		313	u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
		314	u32 tmp, reg;
		315
		316	mutex_lock(&rdev->dc_hw_i2c_mutex);
		317	/* take the pm lock since we need a constant sclk */
		318	mutex_lock(&rdev->pm.mutex);
		319
		320	prescale = radeon_get_i2c_prescale(rdev);
		321
		322	reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) \|
1963	serge	323	RADEON_I2C_DRIVE_EN \|
1430	serge	324	RADEON_I2C_START \|
		325	RADEON_I2C_STOP \|
		326	RADEON_I2C_GO);
		327
		328	if (rdev->is_atom_bios) {
		329	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		330	WREG32(RADEON_BIOS_6_SCRATCH, tmp \| ATOM_S6_HW_I2C_BUSY_STATE);
		331	}
		332
		333	if (rec->mm_i2c) {
		334	i2c_cntl_0 = RADEON_I2C_CNTL_0;
		335	i2c_cntl_1 = RADEON_I2C_CNTL_1;
		336	i2c_data = RADEON_I2C_DATA;
		337	} else {
		338	i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
		339	i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
		340	i2c_data = RADEON_DVI_I2C_DATA;
		341
		342	switch (rdev->family) {
		343	case CHIP_R100:
		344	case CHIP_RV100:
		345	case CHIP_RS100:
		346	case CHIP_RV200:
		347	case CHIP_RS200:
		348	case CHIP_RS300:
		349	switch (rec->mask_clk_reg) {
		350	case RADEON_GPIO_DVI_DDC:
		351	/* no gpio select bit */
		352	break;
		353	default:
		354	DRM_ERROR("gpio not supported with hw i2c\n");
		355	ret = -EINVAL;
		356	goto done;
		357	}
		358	break;
		359	case CHIP_R200:
		360	/* only bit 4 on r200 */
		361	switch (rec->mask_clk_reg) {
		362	case RADEON_GPIO_DVI_DDC:
		363	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		364	break;
		365	case RADEON_GPIO_MONID:
		366	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		367	break;
		368	default:
		369	DRM_ERROR("gpio not supported with hw i2c\n");
		370	ret = -EINVAL;
		371	goto done;
		372	}
		373	break;
		374	case CHIP_RV250:
		375	case CHIP_RV280:
		376	/* bits 3 and 4 */
		377	switch (rec->mask_clk_reg) {
		378	case RADEON_GPIO_DVI_DDC:
		379	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		380	break;
		381	case RADEON_GPIO_VGA_DDC:
		382	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
		383	break;
		384	case RADEON_GPIO_CRT2_DDC:
		385	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		386	break;
		387	default:
		388	DRM_ERROR("gpio not supported with hw i2c\n");
		389	ret = -EINVAL;
		390	goto done;
		391	}
		392	break;
		393	case CHIP_R300:
		394	case CHIP_R350:
		395	/* only bit 4 on r300/r350 */
		396	switch (rec->mask_clk_reg) {
		397	case RADEON_GPIO_VGA_DDC:
		398	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		399	break;
		400	case RADEON_GPIO_DVI_DDC:
		401	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		402	break;
		403	default:
		404	DRM_ERROR("gpio not supported with hw i2c\n");
		405	ret = -EINVAL;
		406	goto done;
		407	}
		408	break;
		409	case CHIP_RV350:
		410	case CHIP_RV380:
		411	case CHIP_R420:
		412	case CHIP_R423:
		413	case CHIP_RV410:
		414	case CHIP_RS400:
		415	case CHIP_RS480:
		416	/* bits 3 and 4 */
		417	switch (rec->mask_clk_reg) {
		418	case RADEON_GPIO_VGA_DDC:
		419	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		420	break;
		421	case RADEON_GPIO_DVI_DDC:
		422	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
		423	break;
		424	case RADEON_GPIO_MONID:
		425	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		426	break;
		427	default:
		428	DRM_ERROR("gpio not supported with hw i2c\n");
		429	ret = -EINVAL;
		430	goto done;
		431	}
		432	break;
		433	default:
		434	DRM_ERROR("unsupported asic\n");
		435	ret = -EINVAL;
		436	goto done;
		437	break;
		438	}
		439	}
		440
		441	/* check for bus probe */
		442	p = &msgs[0];
		443	if ((num == 1) && (p->len == 0)) {
		444	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		445	RADEON_I2C_NACK \|
		446	RADEON_I2C_HALT \|
		447	RADEON_I2C_SOFT_RST));
		448	WREG32(i2c_data, (p->addr << 1) & 0xff);
		449	WREG32(i2c_data, 0);
		450	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		451	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		452	RADEON_I2C_EN \|
		453	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		454	WREG32(i2c_cntl_0, reg);
		455	for (k = 0; k < 32; k++) {
		456	udelay(10);
		457	tmp = RREG32(i2c_cntl_0);
		458	if (tmp & RADEON_I2C_GO)
		459	continue;
		460	tmp = RREG32(i2c_cntl_0);
		461	if (tmp & RADEON_I2C_DONE)
		462	break;
		463	else {
		464	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		465	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		466	ret = -EIO;
		467	goto done;
		468	}
		469	}
		470	goto done;
		471	}
		472
		473	for (i = 0; i < num; i++) {
		474	p = &msgs[i];
		475	for (j = 0; j < p->len; j++) {
		476	if (p->flags & I2C_M_RD) {
		477	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		478	RADEON_I2C_NACK \|
		479	RADEON_I2C_HALT \|
		480	RADEON_I2C_SOFT_RST));
		481	WREG32(i2c_data, ((p->addr << 1) & 0xff) \| 0x1);
		482	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		483	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		484	RADEON_I2C_EN \|
		485	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		486	WREG32(i2c_cntl_0, reg \| RADEON_I2C_RECEIVE);
		487	for (k = 0; k < 32; k++) {
		488	udelay(10);
		489	tmp = RREG32(i2c_cntl_0);
		490	if (tmp & RADEON_I2C_GO)
		491	continue;
		492	tmp = RREG32(i2c_cntl_0);
		493	if (tmp & RADEON_I2C_DONE)
		494	break;
		495	else {
		496	DRM_DEBUG("i2c read error 0x%08x\n", tmp);
		497	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		498	ret = -EIO;
		499	goto done;
		500	}
		501	}
		502	p->buf[j] = RREG32(i2c_data) & 0xff;
		503	} else {
		504	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		505	RADEON_I2C_NACK \|
		506	RADEON_I2C_HALT \|
		507	RADEON_I2C_SOFT_RST));
		508	WREG32(i2c_data, (p->addr << 1) & 0xff);
		509	WREG32(i2c_data, p->buf[j]);
		510	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		511	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		512	RADEON_I2C_EN \|
		513	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		514	WREG32(i2c_cntl_0, reg);
		515	for (k = 0; k < 32; k++) {
		516	udelay(10);
		517	tmp = RREG32(i2c_cntl_0);
		518	if (tmp & RADEON_I2C_GO)
		519	continue;
		520	tmp = RREG32(i2c_cntl_0);
		521	if (tmp & RADEON_I2C_DONE)
		522	break;
		523	else {
		524	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		525	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		526	ret = -EIO;
		527	goto done;
		528	}
		529	}
		530	}
		531	}
		532	}
		533
		534	done:
		535	WREG32(i2c_cntl_0, 0);
		536	WREG32(i2c_cntl_1, 0);
		537	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		538	RADEON_I2C_NACK \|
		539	RADEON_I2C_HALT \|
		540	RADEON_I2C_SOFT_RST));
		541
		542	if (rdev->is_atom_bios) {
		543	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		544	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
		545	WREG32(RADEON_BIOS_6_SCRATCH, tmp);
		546	}
		547
		548	mutex_unlock(&rdev->pm.mutex);
		549	mutex_unlock(&rdev->dc_hw_i2c_mutex);
		550
		551	return ret;
		552	}
		553
		554	/* hw i2c engine for r5xx hardware
		555	* hw can buffer up to 15 bytes
		556	*/
		557	static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
		558	struct i2c_msg *msgs, int num)
		559	{
		560	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		561	struct radeon_device *rdev = i2c->dev->dev_private;
		562	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		563	struct i2c_msg *p;
		564	int i, j, remaining, current_count, buffer_offset, ret = num;
		565	u32 prescale;
		566	u32 tmp, reg;
		567	u32 saved1, saved2;
		568
		569	mutex_lock(&rdev->dc_hw_i2c_mutex);
		570	/* take the pm lock since we need a constant sclk */
		571	mutex_lock(&rdev->pm.mutex);
		572
		573	prescale = radeon_get_i2c_prescale(rdev);
		574
		575	/* clear gpio mask bits */
		576	tmp = RREG32(rec->mask_clk_reg);
		577	tmp &= ~rec->mask_clk_mask;
		578	WREG32(rec->mask_clk_reg, tmp);
		579	tmp = RREG32(rec->mask_clk_reg);
		580
		581	tmp = RREG32(rec->mask_data_reg);
		582	tmp &= ~rec->mask_data_mask;
		583	WREG32(rec->mask_data_reg, tmp);
		584	tmp = RREG32(rec->mask_data_reg);
		585
		586	/* clear pin values */
		587	tmp = RREG32(rec->a_clk_reg);
		588	tmp &= ~rec->a_clk_mask;
		589	WREG32(rec->a_clk_reg, tmp);
		590	tmp = RREG32(rec->a_clk_reg);
		591
		592	tmp = RREG32(rec->a_data_reg);
		593	tmp &= ~rec->a_data_mask;
		594	WREG32(rec->a_data_reg, tmp);
		595	tmp = RREG32(rec->a_data_reg);
		596
		597	/* set the pins to input */
		598	tmp = RREG32(rec->en_clk_reg);
		599	tmp &= ~rec->en_clk_mask;
		600	WREG32(rec->en_clk_reg, tmp);
		601	tmp = RREG32(rec->en_clk_reg);
		602
		603	tmp = RREG32(rec->en_data_reg);
		604	tmp &= ~rec->en_data_mask;
		605	WREG32(rec->en_data_reg, tmp);
		606	tmp = RREG32(rec->en_data_reg);
		607
		608	/* */
		609	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		610	WREG32(RADEON_BIOS_6_SCRATCH, tmp \| ATOM_S6_HW_I2C_BUSY_STATE);
		611	saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
		612	saved2 = RREG32(0x494);
		613	WREG32(0x494, saved2 \| 0x1);
		614
		615	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
		616	for (i = 0; i < 50; i++) {
		617	udelay(1);
		618	if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
		619	break;
		620	}
		621	if (i == 50) {
		622	DRM_ERROR("failed to get i2c bus\n");
		623	ret = -EBUSY;
		624	goto done;
		625	}
		626
		627	reg = AVIVO_DC_I2C_START \| AVIVO_DC_I2C_STOP \| AVIVO_DC_I2C_EN;
		628	switch (rec->mask_clk_reg) {
		629	case AVIVO_DC_GPIO_DDC1_MASK:
		630	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
		631	break;
		632	case AVIVO_DC_GPIO_DDC2_MASK:
		633	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
		634	break;
		635	case AVIVO_DC_GPIO_DDC3_MASK:
		636	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
		637	break;
		638	default:
		639	DRM_ERROR("gpio not supported with hw i2c\n");
		640	ret = -EINVAL;
		641	goto done;
		642	}
		643
		644	/* check for bus probe */
		645	p = &msgs[0];
		646	if ((num == 1) && (p->len == 0)) {
		647	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		648	AVIVO_DC_I2C_NACK \|
		649	AVIVO_DC_I2C_HALT));
		650	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		651	udelay(1);
		652	WREG32(AVIVO_DC_I2C_RESET, 0);
		653
		654	WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
		655	WREG32(AVIVO_DC_I2C_DATA, 0);
		656
		657	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		658	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		659	AVIVO_DC_I2C_DATA_COUNT(1) \|
		660	(prescale << 16)));
		661	WREG32(AVIVO_DC_I2C_CONTROL1, reg);
		662	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		663	for (j = 0; j < 200; j++) {
		664	udelay(50);
		665	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		666	if (tmp & AVIVO_DC_I2C_GO)
		667	continue;
		668	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		669	if (tmp & AVIVO_DC_I2C_DONE)
		670	break;
		671	else {
		672	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		673	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		674	ret = -EIO;
		675	goto done;
		676	}
		677	}
		678	goto done;
		679	}
		680
		681	for (i = 0; i < num; i++) {
		682	p = &msgs[i];
		683	remaining = p->len;
		684	buffer_offset = 0;
		685	if (p->flags & I2C_M_RD) {
		686	while (remaining) {
		687	if (remaining > 15)
		688	current_count = 15;
		689	else
		690	current_count = remaining;
		691	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		692	AVIVO_DC_I2C_NACK \|
		693	AVIVO_DC_I2C_HALT));
		694	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		695	udelay(1);
		696	WREG32(AVIVO_DC_I2C_RESET, 0);
		697
		698	WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) \| 0x1);
		699	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		700	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		701	AVIVO_DC_I2C_DATA_COUNT(current_count) \|
		702	(prescale << 16)));
		703	WREG32(AVIVO_DC_I2C_CONTROL1, reg \| AVIVO_DC_I2C_RECEIVE);
		704	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		705	for (j = 0; j < 200; j++) {
		706	udelay(50);
		707	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		708	if (tmp & AVIVO_DC_I2C_GO)
		709	continue;
		710	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		711	if (tmp & AVIVO_DC_I2C_DONE)
		712	break;
		713	else {
		714	DRM_DEBUG("i2c read error 0x%08x\n", tmp);
		715	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		716	ret = -EIO;
		717	goto done;
		718	}
		719	}
		720	for (j = 0; j < current_count; j++)
		721	p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
		722	remaining -= current_count;
		723	buffer_offset += current_count;
		724	}
		725	} else {
		726	while (remaining) {
		727	if (remaining > 15)
		728	current_count = 15;
		729	else
		730	current_count = remaining;
		731	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		732	AVIVO_DC_I2C_NACK \|
		733	AVIVO_DC_I2C_HALT));
		734	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		735	udelay(1);
		736	WREG32(AVIVO_DC_I2C_RESET, 0);
		737
		738	WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
		739	for (j = 0; j < current_count; j++)
		740	WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
		741
		742	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		743	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		744	AVIVO_DC_I2C_DATA_COUNT(current_count) \|
		745	(prescale << 16)));
		746	WREG32(AVIVO_DC_I2C_CONTROL1, reg);
		747	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		748	for (j = 0; j < 200; j++) {
		749	udelay(50);
		750	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		751	if (tmp & AVIVO_DC_I2C_GO)
		752	continue;
		753	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		754	if (tmp & AVIVO_DC_I2C_DONE)
		755	break;
		756	else {
		757	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		758	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		759	ret = -EIO;
		760	goto done;
		761	}
		762	}
		763	remaining -= current_count;
		764	buffer_offset += current_count;
		765	}
		766	}
		767	}
		768
		769	done:
		770	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		771	AVIVO_DC_I2C_NACK \|
		772	AVIVO_DC_I2C_HALT));
		773	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		774	udelay(1);
		775	WREG32(AVIVO_DC_I2C_RESET, 0);
		776
		777	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
		778	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
		779	WREG32(0x494, saved2);
		780	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		781	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
		782	WREG32(RADEON_BIOS_6_SCRATCH, tmp);
		783
		784	mutex_unlock(&rdev->pm.mutex);
		785	mutex_unlock(&rdev->dc_hw_i2c_mutex);
		786
		787	return ret;
		788	}
		789
1963	serge	790	static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
1430	serge	791	struct i2c_msg *msgs, int num)
		792	{
		793	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		794	struct radeon_device *rdev = i2c->dev->dev_private;
		795	struct radeon_i2c_bus_rec *rec = &i2c->rec;
1963	serge	796	int ret = 0;
1430	serge	797
		798	switch (rdev->family) {
		799	case CHIP_R100:
		800	case CHIP_RV100:
		801	case CHIP_RS100:
		802	case CHIP_RV200:
		803	case CHIP_RS200:
		804	case CHIP_R200:
		805	case CHIP_RV250:
		806	case CHIP_RS300:
		807	case CHIP_RV280:
		808	case CHIP_R300:
		809	case CHIP_R350:
		810	case CHIP_RV350:
		811	case CHIP_RV380:
		812	case CHIP_R420:
		813	case CHIP_R423:
		814	case CHIP_RV410:
		815	case CHIP_RS400:
		816	case CHIP_RS480:
		817	ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
		818	break;
		819	case CHIP_RS600:
		820	case CHIP_RS690:
		821	case CHIP_RS740:
		822	/* XXX fill in hw i2c implementation */
		823	break;
		824	case CHIP_RV515:
		825	case CHIP_R520:
		826	case CHIP_RV530:
		827	case CHIP_RV560:
		828	case CHIP_RV570:
		829	case CHIP_R580:
		830	if (rec->mm_i2c)
		831	ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
		832	else
		833	ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
		834	break;
		835	case CHIP_R600:
		836	case CHIP_RV610:
		837	case CHIP_RV630:
		838	case CHIP_RV670:
		839	/* XXX fill in hw i2c implementation */
		840	break;
		841	case CHIP_RV620:
		842	case CHIP_RV635:
		843	case CHIP_RS780:
		844	case CHIP_RS880:
		845	case CHIP_RV770:
		846	case CHIP_RV730:
		847	case CHIP_RV710:
		848	case CHIP_RV740:
		849	/* XXX fill in hw i2c implementation */
		850	break;
		851	case CHIP_CEDAR:
		852	case CHIP_REDWOOD:
		853	case CHIP_JUNIPER:
		854	case CHIP_CYPRESS:
		855	case CHIP_HEMLOCK:
		856	/* XXX fill in hw i2c implementation */
		857	break;
		858	default:
		859	DRM_ERROR("i2c: unhandled radeon chip\n");
		860	ret = -EIO;
		861	break;
		862	}
		863
		864	return ret;
		865	}
		866
1963	serge	867	static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
1430	serge	868	{
		869	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
		870	}
		871
		872	static const struct i2c_algorithm radeon_i2c_algo = {
1963	serge	873	.master_xfer = radeon_hw_i2c_xfer,
		874	.functionality = radeon_hw_i2c_func,
1430	serge	875	};
		876
1123	serge	877	struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev,
		878	struct radeon_i2c_bus_rec *rec,
		879	const char *name)
		880	{
1963	serge	881	struct radeon_device *rdev = dev->dev_private;
1123	serge	882	struct radeon_i2c_chan *i2c;
		883	int ret;
		884
		885	i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
		886	if (i2c == NULL)
		887	return NULL;
		888
1963	serge	889	i2c->rec = *rec;
		890	// i2c->adapter.owner = THIS_MODULE;
		891	i2c->dev = dev;
		892	i2c_set_adapdata(&i2c->adapter, i2c);
		893	if (rec->mm_i2c \|\|
		894	(rec->hw_capable &&
		895	radeon_hw_i2c &&
		896	((rdev->family <= CHIP_RS480) \|\|
		897	((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
		898	/* set the radeon hw i2c adapter */
		899	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
		900	"Radeon i2c hw bus %s", name);
		901	i2c->adapter.algo = &radeon_i2c_algo;
		902	// ret = i2c_add_adapter(&i2c->adapter);
		903	// if (ret) {
		904	// DRM_ERROR("Failed to register hw i2c %s\n", name);
		905	// goto out_free;
		906	// }
		907	} else {
		908	/* set the radeon bit adapter */
		909	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
		910	"Radeon i2c bit bus %s", name);
		911	i2c->adapter.algo_data = &i2c->algo.bit;
		912	i2c->algo.bit.pre_xfer = pre_xfer;
		913	i2c->algo.bit.post_xfer = post_xfer;
		914	i2c->algo.bit.setsda = set_data;
		915	i2c->algo.bit.setscl = set_clock;
		916	i2c->algo.bit.getsda = get_data;
		917	i2c->algo.bit.getscl = get_clock;
		918	i2c->algo.bit.udelay = 20;
1123	serge	919	/* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
		920	* make this, 2 jiffies is a lot more reliable */
1963	serge	921	i2c->algo.bit.timeout = 2;
		922	i2c->algo.bit.data = i2c;
		923	ret = i2c_bit_add_bus(&i2c->adapter);
1123	serge	924	if (ret) {
1963	serge	925	DRM_ERROR("Failed to register bit i2c %s\n", name);
1123	serge	926	goto out_free;
		927	}
1963	serge	928	}
1123	serge	929
		930	return i2c;
		931	out_free:
		932	kfree(i2c);
		933	return NULL;
		934
		935	}
		936
1321	serge	937	struct radeon_i2c_chan radeon_i2c_create_dp(struct drm_device dev,
		938	struct radeon_i2c_bus_rec *rec,
		939	const char *name)
		940	{
		941	struct radeon_i2c_chan *i2c;
		942	int ret;
		943
		944	i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
		945	if (i2c == NULL)
		946	return NULL;
		947
		948	i2c->rec = *rec;
1404	serge	949	// i2c->adapter.owner = THIS_MODULE;
1963	serge	950	i2c->adapter.class = I2C_CLASS_DDC;
1321	serge	951	i2c->dev = dev;
1963	serge	952	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
		953	"Radeon aux bus %s", name);
1430	serge	954	i2c_set_adapdata(&i2c->adapter, i2c);
1321	serge	955	i2c->adapter.algo_data = &i2c->algo.dp;
		956	i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
		957	i2c->algo.dp.address = 0;
		958	ret = i2c_dp_aux_add_bus(&i2c->adapter);
		959	if (ret) {
		960	DRM_INFO("Failed to register i2c %s\n", name);
		961	goto out_free;
		962	}
		963
		964	return i2c;
		965	out_free:
		966	kfree(i2c);
		967	return NULL;
		968
		969	}
		970
1123	serge	971	void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
		972	{
		973	if (!i2c)
		974	return;
1963	serge	975	// i2c_del_adapter(&i2c->adapter);
1430	serge	976	kfree(i2c);
		977	}
1123	serge	978
1963	serge	979	/* Add the default buses */
		980	void radeon_i2c_init(struct radeon_device *rdev)
1430	serge	981	{
1963	serge	982	if (rdev->is_atom_bios)
		983	radeon_atombios_i2c_init(rdev);
		984	else
		985	radeon_combios_i2c_init(rdev);
		986	}
1430	serge	987
1963	serge	988	/* remove all the buses */
		989	void radeon_i2c_fini(struct radeon_device *rdev)
		990	{
		991	int i;
		992
		993	for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
		994	if (rdev->i2c_bus[i]) {
		995	radeon_i2c_destroy(rdev->i2c_bus[i]);
		996	rdev->i2c_bus[i] = NULL;
		997	}
		998	}
1123	serge	999	}
		1000
1963	serge	1001	/* Add additional buses */
		1002	void radeon_i2c_add(struct radeon_device *rdev,
		1003	struct radeon_i2c_bus_rec *rec,
		1004	const char *name)
		1005	{
		1006	struct drm_device *dev = rdev->ddev;
		1007	int i;
		1008
		1009	for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
		1010	if (!rdev->i2c_bus[i]) {
		1011	rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
		1012	return;
		1013	}
		1014	}
		1015	}
		1016
		1017	/* looks up bus based on id */
		1018	struct radeon_i2c_chan radeon_i2c_lookup(struct radeon_device rdev,
		1019	struct radeon_i2c_bus_rec *i2c_bus)
		1020	{
		1021	int i;
		1022
		1023	for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
		1024	if (rdev->i2c_bus[i] &&
		1025	(rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
		1026	return rdev->i2c_bus[i];
		1027	}
		1028	}
		1029	return NULL;
		1030	}
		1031
1123	serge	1032	struct drm_encoder radeon_best_encoder(struct drm_connector connector)
		1033	{
		1034	return NULL;
		1035	}
1321	serge	1036
1430	serge	1037	void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1321	serge	1038	u8 slave_addr,
		1039	u8 addr,
		1040	u8 *val)
		1041	{
		1042	u8 out_buf[2];
		1043	u8 in_buf[2];
		1044	struct i2c_msg msgs[] = {
		1045	{
		1046	.addr = slave_addr,
		1047	.flags = 0,
		1048	.len = 1,
		1049	.buf = out_buf,
		1050	},
		1051	{
		1052	.addr = slave_addr,
		1053	.flags = I2C_M_RD,
		1054	.len = 1,
		1055	.buf = in_buf,
		1056	}
		1057	};
		1058
		1059	out_buf[0] = addr;
		1060	out_buf[1] = 0;
		1061
		1062	if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
		1063	*val = in_buf[0];
		1064	DRM_DEBUG("val = 0x%02x\n", *val);
		1065	} else {
1963	serge	1066	DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1321	serge	1067	addr, *val);
		1068	}
		1069	}
		1070
1430	serge	1071	void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1321	serge	1072	u8 slave_addr,
		1073	u8 addr,
		1074	u8 val)
		1075	{
		1076	uint8_t out_buf[2];
		1077	struct i2c_msg msg = {
		1078	.addr = slave_addr,
		1079	.flags = 0,
		1080	.len = 2,
		1081	.buf = out_buf,
		1082	};
		1083
		1084	out_buf[0] = addr;
		1085	out_buf[1] = val;
		1086
		1087	if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1963	serge	1088	DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1321	serge	1089	addr, val);
		1090	}
		1091
1963	serge	1092	/* ddc router switching */
		1093	void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
		1094	{
		1095	u8 val;
		1096
		1097	if (!radeon_connector->router.ddc_valid)
		1098	return;
		1099
		1100	if (!radeon_connector->router_bus)
		1101	return;
		1102
		1103	radeon_i2c_get_byte(radeon_connector->router_bus,
		1104	radeon_connector->router.i2c_addr,
		1105	0x3, &val);
		1106	val &= ~radeon_connector->router.ddc_mux_control_pin;
		1107	radeon_i2c_put_byte(radeon_connector->router_bus,
		1108	radeon_connector->router.i2c_addr,
		1109	0x3, val);
		1110	radeon_i2c_get_byte(radeon_connector->router_bus,
		1111	radeon_connector->router.i2c_addr,
		1112	0x1, &val);
		1113	val &= ~radeon_connector->router.ddc_mux_control_pin;
		1114	val \|= radeon_connector->router.ddc_mux_state;
		1115	radeon_i2c_put_byte(radeon_connector->router_bus,
		1116	radeon_connector->router.i2c_addr,
		1117	0x1, val);
		1118	}
		1119
		1120	/* clock/data router switching */
		1121	void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
		1122	{
		1123	u8 val;
		1124
		1125	if (!radeon_connector->router.cd_valid)
		1126	return;
		1127
		1128	if (!radeon_connector->router_bus)
		1129	return;
		1130
		1131	radeon_i2c_get_byte(radeon_connector->router_bus,
		1132	radeon_connector->router.i2c_addr,
		1133	0x3, &val);
		1134	val &= ~radeon_connector->router.cd_mux_control_pin;
		1135	radeon_i2c_put_byte(radeon_connector->router_bus,
		1136	radeon_connector->router.i2c_addr,
		1137	0x3, val);
		1138	radeon_i2c_get_byte(radeon_connector->router_bus,
		1139	radeon_connector->router.i2c_addr,
		1140	0x1, &val);
		1141	val &= ~radeon_connector->router.cd_mux_control_pin;
		1142	val \|= radeon_connector->router.cd_mux_state;
		1143	radeon_i2c_put_byte(radeon_connector->router_bus,
		1144	radeon_connector->router.i2c_addr,
		1145	0x1, val);
		1146	}
		1147

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_i2c.c – Rev 1986