WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_i2c.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "radeon_drm.h"
		28	#include "radeon.h"
1430	serge	29	#include "atom.h"
1123	serge	30
		31	/**
		32	* radeon_ddc_probe
		33	*
		34	*/
		35	bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
		36	{
		37	u8 out_buf[] = { 0x0, 0x0};
		38	u8 buf[2];
		39	int ret;
		40	struct i2c_msg msgs[] = {
		41	{
		42	.addr = 0x50,
		43	.flags = 0,
		44	.len = 1,
		45	.buf = out_buf,
		46	},
		47	{
		48	.addr = 0x50,
		49	.flags = I2C_M_RD,
		50	.len = 1,
		51	.buf = buf,
		52	}
		53	};
		54
		55	ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
		56	if (ret == 2)
		57	return true;
		58
		59	return false;
		60	}
		61
		62
1430	serge	63	static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
1123	serge	64	{
1321	serge	65	struct radeon_device *rdev = i2c->dev->dev_private;
		66	struct radeon_i2c_bus_rec *rec = &i2c->rec;
1123	serge	67	uint32_t temp;
		68
		69	/* RV410 appears to have a bug where the hw i2c in reset
		70	* holds the i2c port in a bad state - switch hw i2c away before
		71	* doing DDC - do this for all r200s/r300s/r400s for safety sake
		72	*/
1321	serge	73	if (rec->hw_capable) {
1123	serge	74	if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
1430	serge	75	u32 reg;
		76
		77	if (rdev->family >= CHIP_RV350)
		78	reg = RADEON_GPIO_MONID;
		79	else if ((rdev->family == CHIP_R300) \|\|
		80	(rdev->family == CHIP_R350))
		81	reg = RADEON_GPIO_DVI_DDC;
		82	else
		83	reg = RADEON_GPIO_CRT2_DDC;
		84
		85	mutex_lock(&rdev->dc_hw_i2c_mutex);
		86	if (rec->a_clk_reg == reg) {
1123	serge	87	WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST \|
		88	R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
		89	} else {
		90	WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST \|
		91	R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
		92	}
1630	serge	93	mutex_unlock(&rdev->dc_hw_i2c_mutex);
1123	serge	94	}
1321	serge	95	}
		96
		97	/* clear the output pin values */
		98	temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
1123	serge	99	WREG32(rec->a_clk_reg, temp);
		100
1321	serge	101	temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
1123	serge	102	WREG32(rec->a_data_reg, temp);
		103
1321	serge	104	/* set the pins to input */
		105	temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
		106	WREG32(rec->en_clk_reg, temp);
		107
		108	temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
		109	WREG32(rec->en_data_reg, temp);
		110
		111	/* mask the gpio pins for software use */
1123	serge	112	temp = RREG32(rec->mask_clk_reg);
		113	if (lock_state)
		114	temp \|= rec->mask_clk_mask;
		115	else
		116	temp &= ~rec->mask_clk_mask;
		117	WREG32(rec->mask_clk_reg, temp);
		118	temp = RREG32(rec->mask_clk_reg);
		119
		120	temp = RREG32(rec->mask_data_reg);
		121	if (lock_state)
		122	temp \|= rec->mask_data_mask;
		123	else
		124	temp &= ~rec->mask_data_mask;
		125	WREG32(rec->mask_data_reg, temp);
		126	temp = RREG32(rec->mask_data_reg);
		127	}
		128
		129	static int get_clock(void *i2c_priv)
		130	{
		131	struct radeon_i2c_chan *i2c = i2c_priv;
		132	struct radeon_device *rdev = i2c->dev->dev_private;
		133	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		134	uint32_t val;
		135
1321	serge	136	/* read the value off the pin */
		137	val = RREG32(rec->y_clk_reg);
		138	val &= rec->y_clk_mask;
1123	serge	139
		140	return (val != 0);
		141	}
		142
		143
		144	static int get_data(void *i2c_priv)
		145	{
		146	struct radeon_i2c_chan *i2c = i2c_priv;
		147	struct radeon_device *rdev = i2c->dev->dev_private;
		148	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		149	uint32_t val;
		150
1321	serge	151	/* read the value off the pin */
		152	val = RREG32(rec->y_data_reg);
		153	val &= rec->y_data_mask;
		154
1123	serge	155	return (val != 0);
		156	}
		157
		158	static void set_clock(void *i2c_priv, int clock)
		159	{
		160	struct radeon_i2c_chan *i2c = i2c_priv;
		161	struct radeon_device *rdev = i2c->dev->dev_private;
		162	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		163	uint32_t val;
		164
1321	serge	165	/* set pin direction */
		166	val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
		167	val \|= clock ? 0 : rec->en_clk_mask;
		168	WREG32(rec->en_clk_reg, val);
1123	serge	169	}
		170
		171	static void set_data(void *i2c_priv, int data)
		172	{
		173	struct radeon_i2c_chan *i2c = i2c_priv;
		174	struct radeon_device *rdev = i2c->dev->dev_private;
		175	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		176	uint32_t val;
		177
1321	serge	178	/* set pin direction */
		179	val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
		180	val \|= data ? 0 : rec->en_data_mask;
		181	WREG32(rec->en_data_reg, val);
1123	serge	182	}
		183
1430	serge	184	static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
		185	{
		186	struct radeon_pll *spll = &rdev->clock.spll;
		187	u32 sclk = radeon_get_engine_clock(rdev);
		188	u32 prescale = 0;
		189	u32 n, m;
		190	u8 loop;
		191	int i2c_clock;
		192
		193	switch (rdev->family) {
		194	case CHIP_R100:
		195	case CHIP_RV100:
		196	case CHIP_RS100:
		197	case CHIP_RV200:
		198	case CHIP_RS200:
		199	case CHIP_R200:
		200	case CHIP_RV250:
		201	case CHIP_RS300:
		202	case CHIP_RV280:
		203	case CHIP_R300:
		204	case CHIP_R350:
		205	case CHIP_RV350:
		206	n = (spll->reference_freq) / (4 * 6);
		207	for (loop = 1; loop < 255; loop++) {
		208	if ((loop * (loop - 1)) > n)
		209	break;
		210	}
		211	m = loop - 1;
		212	prescale = m \| (loop << 8);
		213	break;
		214	case CHIP_RV380:
		215	case CHIP_RS400:
		216	case CHIP_RS480:
		217	case CHIP_R420:
		218	case CHIP_R423:
		219	case CHIP_RV410:
		220	sclk = radeon_get_engine_clock(rdev);
		221	prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
		222	break;
		223	case CHIP_RS600:
		224	case CHIP_RS690:
		225	case CHIP_RS740:
		226	/* todo */
		227	break;
		228	case CHIP_RV515:
		229	case CHIP_R520:
		230	case CHIP_RV530:
		231	case CHIP_RV560:
		232	case CHIP_RV570:
		233	case CHIP_R580:
		234	i2c_clock = 50;
		235	sclk = radeon_get_engine_clock(rdev);
		236	if (rdev->family == CHIP_R520)
		237	prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
		238	else
		239	prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
		240	break;
		241	case CHIP_R600:
		242	case CHIP_RV610:
		243	case CHIP_RV630:
		244	case CHIP_RV670:
		245	/* todo */
		246	break;
		247	case CHIP_RV620:
		248	case CHIP_RV635:
		249	case CHIP_RS780:
		250	case CHIP_RS880:
		251	case CHIP_RV770:
		252	case CHIP_RV730:
		253	case CHIP_RV710:
		254	case CHIP_RV740:
		255	/* todo */
		256	break;
		257	case CHIP_CEDAR:
		258	case CHIP_REDWOOD:
		259	case CHIP_JUNIPER:
		260	case CHIP_CYPRESS:
		261	case CHIP_HEMLOCK:
		262	/* todo */
		263	break;
		264	default:
		265	DRM_ERROR("i2c: unhandled radeon chip\n");
		266	break;
		267	}
		268	return prescale;
		269	}
		270
		271
		272	/* hw i2c engine for r1xx-4xx hardware
		273	* hw can buffer up to 15 bytes
		274	*/
		275	static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
		276	struct i2c_msg *msgs, int num)
		277	{
		278	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		279	struct radeon_device *rdev = i2c->dev->dev_private;
		280	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		281	struct i2c_msg *p;
		282	int i, j, k, ret = num;
		283	u32 prescale;
		284	u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
		285	u32 tmp, reg;
		286
		287	mutex_lock(&rdev->dc_hw_i2c_mutex);
		288	/* take the pm lock since we need a constant sclk */
		289	mutex_lock(&rdev->pm.mutex);
		290
		291	prescale = radeon_get_i2c_prescale(rdev);
		292
		293	reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) \|
		294	RADEON_I2C_START \|
		295	RADEON_I2C_STOP \|
		296	RADEON_I2C_GO);
		297
		298	if (rdev->is_atom_bios) {
		299	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		300	WREG32(RADEON_BIOS_6_SCRATCH, tmp \| ATOM_S6_HW_I2C_BUSY_STATE);
		301	}
		302
		303	if (rec->mm_i2c) {
		304	i2c_cntl_0 = RADEON_I2C_CNTL_0;
		305	i2c_cntl_1 = RADEON_I2C_CNTL_1;
		306	i2c_data = RADEON_I2C_DATA;
		307	} else {
		308	i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
		309	i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
		310	i2c_data = RADEON_DVI_I2C_DATA;
		311
		312	switch (rdev->family) {
		313	case CHIP_R100:
		314	case CHIP_RV100:
		315	case CHIP_RS100:
		316	case CHIP_RV200:
		317	case CHIP_RS200:
		318	case CHIP_RS300:
		319	switch (rec->mask_clk_reg) {
		320	case RADEON_GPIO_DVI_DDC:
		321	/* no gpio select bit */
		322	break;
		323	default:
		324	DRM_ERROR("gpio not supported with hw i2c\n");
		325	ret = -EINVAL;
		326	goto done;
		327	}
		328	break;
		329	case CHIP_R200:
		330	/* only bit 4 on r200 */
		331	switch (rec->mask_clk_reg) {
		332	case RADEON_GPIO_DVI_DDC:
		333	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		334	break;
		335	case RADEON_GPIO_MONID:
		336	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		337	break;
		338	default:
		339	DRM_ERROR("gpio not supported with hw i2c\n");
		340	ret = -EINVAL;
		341	goto done;
		342	}
		343	break;
		344	case CHIP_RV250:
		345	case CHIP_RV280:
		346	/* bits 3 and 4 */
		347	switch (rec->mask_clk_reg) {
		348	case RADEON_GPIO_DVI_DDC:
		349	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		350	break;
		351	case RADEON_GPIO_VGA_DDC:
		352	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
		353	break;
		354	case RADEON_GPIO_CRT2_DDC:
		355	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		356	break;
		357	default:
		358	DRM_ERROR("gpio not supported with hw i2c\n");
		359	ret = -EINVAL;
		360	goto done;
		361	}
		362	break;
		363	case CHIP_R300:
		364	case CHIP_R350:
		365	/* only bit 4 on r300/r350 */
		366	switch (rec->mask_clk_reg) {
		367	case RADEON_GPIO_VGA_DDC:
		368	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		369	break;
		370	case RADEON_GPIO_DVI_DDC:
		371	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		372	break;
		373	default:
		374	DRM_ERROR("gpio not supported with hw i2c\n");
		375	ret = -EINVAL;
		376	goto done;
		377	}
		378	break;
		379	case CHIP_RV350:
		380	case CHIP_RV380:
		381	case CHIP_R420:
		382	case CHIP_R423:
		383	case CHIP_RV410:
		384	case CHIP_RS400:
		385	case CHIP_RS480:
		386	/* bits 3 and 4 */
		387	switch (rec->mask_clk_reg) {
		388	case RADEON_GPIO_VGA_DDC:
		389	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		390	break;
		391	case RADEON_GPIO_DVI_DDC:
		392	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
		393	break;
		394	case RADEON_GPIO_MONID:
		395	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		396	break;
		397	default:
		398	DRM_ERROR("gpio not supported with hw i2c\n");
		399	ret = -EINVAL;
		400	goto done;
		401	}
		402	break;
		403	default:
		404	DRM_ERROR("unsupported asic\n");
		405	ret = -EINVAL;
		406	goto done;
		407	break;
		408	}
		409	}
		410
		411	/* check for bus probe */
		412	p = &msgs[0];
		413	if ((num == 1) && (p->len == 0)) {
		414	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		415	RADEON_I2C_NACK \|
		416	RADEON_I2C_HALT \|
		417	RADEON_I2C_SOFT_RST));
		418	WREG32(i2c_data, (p->addr << 1) & 0xff);
		419	WREG32(i2c_data, 0);
		420	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		421	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		422	RADEON_I2C_EN \|
		423	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		424	WREG32(i2c_cntl_0, reg);
		425	for (k = 0; k < 32; k++) {
		426	udelay(10);
		427	tmp = RREG32(i2c_cntl_0);
		428	if (tmp & RADEON_I2C_GO)
		429	continue;
		430	tmp = RREG32(i2c_cntl_0);
		431	if (tmp & RADEON_I2C_DONE)
		432	break;
		433	else {
		434	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		435	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		436	ret = -EIO;
		437	goto done;
		438	}
		439	}
		440	goto done;
		441	}
		442
		443	for (i = 0; i < num; i++) {
		444	p = &msgs[i];
		445	for (j = 0; j < p->len; j++) {
		446	if (p->flags & I2C_M_RD) {
		447	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		448	RADEON_I2C_NACK \|
		449	RADEON_I2C_HALT \|
		450	RADEON_I2C_SOFT_RST));
		451	WREG32(i2c_data, ((p->addr << 1) & 0xff) \| 0x1);
		452	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		453	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		454	RADEON_I2C_EN \|
		455	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		456	WREG32(i2c_cntl_0, reg \| RADEON_I2C_RECEIVE);
		457	for (k = 0; k < 32; k++) {
		458	udelay(10);
		459	tmp = RREG32(i2c_cntl_0);
		460	if (tmp & RADEON_I2C_GO)
		461	continue;
		462	tmp = RREG32(i2c_cntl_0);
		463	if (tmp & RADEON_I2C_DONE)
		464	break;
		465	else {
		466	DRM_DEBUG("i2c read error 0x%08x\n", tmp);
		467	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		468	ret = -EIO;
		469	goto done;
		470	}
		471	}
		472	p->buf[j] = RREG32(i2c_data) & 0xff;
		473	} else {
		474	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		475	RADEON_I2C_NACK \|
		476	RADEON_I2C_HALT \|
		477	RADEON_I2C_SOFT_RST));
		478	WREG32(i2c_data, (p->addr << 1) & 0xff);
		479	WREG32(i2c_data, p->buf[j]);
		480	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		481	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		482	RADEON_I2C_EN \|
		483	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		484	WREG32(i2c_cntl_0, reg);
		485	for (k = 0; k < 32; k++) {
		486	udelay(10);
		487	tmp = RREG32(i2c_cntl_0);
		488	if (tmp & RADEON_I2C_GO)
		489	continue;
		490	tmp = RREG32(i2c_cntl_0);
		491	if (tmp & RADEON_I2C_DONE)
		492	break;
		493	else {
		494	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		495	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		496	ret = -EIO;
		497	goto done;
		498	}
		499	}
		500	}
		501	}
		502	}
		503
		504	done:
		505	WREG32(i2c_cntl_0, 0);
		506	WREG32(i2c_cntl_1, 0);
		507	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		508	RADEON_I2C_NACK \|
		509	RADEON_I2C_HALT \|
		510	RADEON_I2C_SOFT_RST));
		511
		512	if (rdev->is_atom_bios) {
		513	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		514	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
		515	WREG32(RADEON_BIOS_6_SCRATCH, tmp);
		516	}
		517
		518	mutex_unlock(&rdev->pm.mutex);
		519	mutex_unlock(&rdev->dc_hw_i2c_mutex);
		520
		521	return ret;
		522	}
		523
		524	/* hw i2c engine for r5xx hardware
		525	* hw can buffer up to 15 bytes
		526	*/
		527	static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
		528	struct i2c_msg *msgs, int num)
		529	{
		530	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		531	struct radeon_device *rdev = i2c->dev->dev_private;
		532	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		533	struct i2c_msg *p;
		534	int i, j, remaining, current_count, buffer_offset, ret = num;
		535	u32 prescale;
		536	u32 tmp, reg;
		537	u32 saved1, saved2;
		538
		539	mutex_lock(&rdev->dc_hw_i2c_mutex);
		540	/* take the pm lock since we need a constant sclk */
		541	mutex_lock(&rdev->pm.mutex);
		542
		543	prescale = radeon_get_i2c_prescale(rdev);
		544
		545	/* clear gpio mask bits */
		546	tmp = RREG32(rec->mask_clk_reg);
		547	tmp &= ~rec->mask_clk_mask;
		548	WREG32(rec->mask_clk_reg, tmp);
		549	tmp = RREG32(rec->mask_clk_reg);
		550
		551	tmp = RREG32(rec->mask_data_reg);
		552	tmp &= ~rec->mask_data_mask;
		553	WREG32(rec->mask_data_reg, tmp);
		554	tmp = RREG32(rec->mask_data_reg);
		555
		556	/* clear pin values */
		557	tmp = RREG32(rec->a_clk_reg);
		558	tmp &= ~rec->a_clk_mask;
		559	WREG32(rec->a_clk_reg, tmp);
		560	tmp = RREG32(rec->a_clk_reg);
		561
		562	tmp = RREG32(rec->a_data_reg);
		563	tmp &= ~rec->a_data_mask;
		564	WREG32(rec->a_data_reg, tmp);
		565	tmp = RREG32(rec->a_data_reg);
		566
		567	/* set the pins to input */
		568	tmp = RREG32(rec->en_clk_reg);
		569	tmp &= ~rec->en_clk_mask;
		570	WREG32(rec->en_clk_reg, tmp);
		571	tmp = RREG32(rec->en_clk_reg);
		572
		573	tmp = RREG32(rec->en_data_reg);
		574	tmp &= ~rec->en_data_mask;
		575	WREG32(rec->en_data_reg, tmp);
		576	tmp = RREG32(rec->en_data_reg);
		577
		578	/* */
		579	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		580	WREG32(RADEON_BIOS_6_SCRATCH, tmp \| ATOM_S6_HW_I2C_BUSY_STATE);
		581	saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
		582	saved2 = RREG32(0x494);
		583	WREG32(0x494, saved2 \| 0x1);
		584
		585	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
		586	for (i = 0; i < 50; i++) {
		587	udelay(1);
		588	if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
		589	break;
		590	}
		591	if (i == 50) {
		592	DRM_ERROR("failed to get i2c bus\n");
		593	ret = -EBUSY;
		594	goto done;
		595	}
		596
		597	reg = AVIVO_DC_I2C_START \| AVIVO_DC_I2C_STOP \| AVIVO_DC_I2C_EN;
		598	switch (rec->mask_clk_reg) {
		599	case AVIVO_DC_GPIO_DDC1_MASK:
		600	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
		601	break;
		602	case AVIVO_DC_GPIO_DDC2_MASK:
		603	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
		604	break;
		605	case AVIVO_DC_GPIO_DDC3_MASK:
		606	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
		607	break;
		608	default:
		609	DRM_ERROR("gpio not supported with hw i2c\n");
		610	ret = -EINVAL;
		611	goto done;
		612	}
		613
		614	/* check for bus probe */
		615	p = &msgs[0];
		616	if ((num == 1) && (p->len == 0)) {
		617	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		618	AVIVO_DC_I2C_NACK \|
		619	AVIVO_DC_I2C_HALT));
		620	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		621	udelay(1);
		622	WREG32(AVIVO_DC_I2C_RESET, 0);
		623
		624	WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
		625	WREG32(AVIVO_DC_I2C_DATA, 0);
		626
		627	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		628	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		629	AVIVO_DC_I2C_DATA_COUNT(1) \|
		630	(prescale << 16)));
		631	WREG32(AVIVO_DC_I2C_CONTROL1, reg);
		632	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		633	for (j = 0; j < 200; j++) {
		634	udelay(50);
		635	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		636	if (tmp & AVIVO_DC_I2C_GO)
		637	continue;
		638	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		639	if (tmp & AVIVO_DC_I2C_DONE)
		640	break;
		641	else {
		642	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		643	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		644	ret = -EIO;
		645	goto done;
		646	}
		647	}
		648	goto done;
		649	}
		650
		651	for (i = 0; i < num; i++) {
		652	p = &msgs[i];
		653	remaining = p->len;
		654	buffer_offset = 0;
		655	if (p->flags & I2C_M_RD) {
		656	while (remaining) {
		657	if (remaining > 15)
		658	current_count = 15;
		659	else
		660	current_count = remaining;
		661	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		662	AVIVO_DC_I2C_NACK \|
		663	AVIVO_DC_I2C_HALT));
		664	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		665	udelay(1);
		666	WREG32(AVIVO_DC_I2C_RESET, 0);
		667
		668	WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) \| 0x1);
		669	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		670	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		671	AVIVO_DC_I2C_DATA_COUNT(current_count) \|
		672	(prescale << 16)));
		673	WREG32(AVIVO_DC_I2C_CONTROL1, reg \| AVIVO_DC_I2C_RECEIVE);
		674	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		675	for (j = 0; j < 200; j++) {
		676	udelay(50);
		677	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		678	if (tmp & AVIVO_DC_I2C_GO)
		679	continue;
		680	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		681	if (tmp & AVIVO_DC_I2C_DONE)
		682	break;
		683	else {
		684	DRM_DEBUG("i2c read error 0x%08x\n", tmp);
		685	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		686	ret = -EIO;
		687	goto done;
		688	}
		689	}
		690	for (j = 0; j < current_count; j++)
		691	p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
		692	remaining -= current_count;
		693	buffer_offset += current_count;
		694	}
		695	} else {
		696	while (remaining) {
		697	if (remaining > 15)
		698	current_count = 15;
		699	else
		700	current_count = remaining;
		701	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		702	AVIVO_DC_I2C_NACK \|
		703	AVIVO_DC_I2C_HALT));
		704	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		705	udelay(1);
		706	WREG32(AVIVO_DC_I2C_RESET, 0);
		707
		708	WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
		709	for (j = 0; j < current_count; j++)
		710	WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
		711
		712	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		713	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		714	AVIVO_DC_I2C_DATA_COUNT(current_count) \|
		715	(prescale << 16)));
		716	WREG32(AVIVO_DC_I2C_CONTROL1, reg);
		717	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		718	for (j = 0; j < 200; j++) {
		719	udelay(50);
		720	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		721	if (tmp & AVIVO_DC_I2C_GO)
		722	continue;
		723	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		724	if (tmp & AVIVO_DC_I2C_DONE)
		725	break;
		726	else {
		727	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		728	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		729	ret = -EIO;
		730	goto done;
		731	}
		732	}
		733	remaining -= current_count;
		734	buffer_offset += current_count;
		735	}
		736	}
		737	}
		738
		739	done:
		740	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		741	AVIVO_DC_I2C_NACK \|
		742	AVIVO_DC_I2C_HALT));
		743	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		744	udelay(1);
		745	WREG32(AVIVO_DC_I2C_RESET, 0);
		746
		747	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
		748	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
		749	WREG32(0x494, saved2);
		750	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		751	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
		752	WREG32(RADEON_BIOS_6_SCRATCH, tmp);
		753
		754	mutex_unlock(&rdev->pm.mutex);
		755	mutex_unlock(&rdev->dc_hw_i2c_mutex);
		756
		757	return ret;
		758	}
		759
		760	static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
		761	struct i2c_msg *msgs, int num)
		762	{
		763	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		764	int ret;
		765
		766	radeon_i2c_do_lock(i2c, 1);
		767	ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
		768	radeon_i2c_do_lock(i2c, 0);
		769
		770	return ret;
		771	}
		772
		773	static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
		774	struct i2c_msg *msgs, int num)
		775	{
		776	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		777	struct radeon_device *rdev = i2c->dev->dev_private;
		778	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		779	int ret;
		780
		781	switch (rdev->family) {
		782	case CHIP_R100:
		783	case CHIP_RV100:
		784	case CHIP_RS100:
		785	case CHIP_RV200:
		786	case CHIP_RS200:
		787	case CHIP_R200:
		788	case CHIP_RV250:
		789	case CHIP_RS300:
		790	case CHIP_RV280:
		791	case CHIP_R300:
		792	case CHIP_R350:
		793	case CHIP_RV350:
		794	case CHIP_RV380:
		795	case CHIP_R420:
		796	case CHIP_R423:
		797	case CHIP_RV410:
		798	case CHIP_RS400:
		799	case CHIP_RS480:
		800	if (rec->hw_capable)
		801	ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
		802	else
		803	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		804	break;
		805	case CHIP_RS600:
		806	case CHIP_RS690:
		807	case CHIP_RS740:
		808	/* XXX fill in hw i2c implementation */
		809	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		810	break;
		811	case CHIP_RV515:
		812	case CHIP_R520:
		813	case CHIP_RV530:
		814	case CHIP_RV560:
		815	case CHIP_RV570:
		816	case CHIP_R580:
		817	if (rec->hw_capable) {
		818	if (rec->mm_i2c)
		819	ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
		820	else
		821	ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
		822	} else
		823	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		824	break;
		825	case CHIP_R600:
		826	case CHIP_RV610:
		827	case CHIP_RV630:
		828	case CHIP_RV670:
		829	/* XXX fill in hw i2c implementation */
		830	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		831	break;
		832	case CHIP_RV620:
		833	case CHIP_RV635:
		834	case CHIP_RS780:
		835	case CHIP_RS880:
		836	case CHIP_RV770:
		837	case CHIP_RV730:
		838	case CHIP_RV710:
		839	case CHIP_RV740:
		840	/* XXX fill in hw i2c implementation */
		841	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		842	break;
		843	case CHIP_CEDAR:
		844	case CHIP_REDWOOD:
		845	case CHIP_JUNIPER:
		846	case CHIP_CYPRESS:
		847	case CHIP_HEMLOCK:
		848	/* XXX fill in hw i2c implementation */
		849	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		850	break;
		851	default:
		852	DRM_ERROR("i2c: unhandled radeon chip\n");
		853	ret = -EIO;
		854	break;
		855	}
		856
		857	return ret;
		858	}
		859
		860	static u32 radeon_i2c_func(struct i2c_adapter *adap)
		861	{
		862	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
		863	}
		864
		865	static const struct i2c_algorithm radeon_i2c_algo = {
		866	.master_xfer = radeon_i2c_xfer,
		867	.functionality = radeon_i2c_func,
		868	};
		869
1123	serge	870	struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev,
		871	struct radeon_i2c_bus_rec *rec,
		872	const char *name)
		873	{
		874	struct radeon_i2c_chan *i2c;
		875	int ret;
		876
		877	i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
		878	if (i2c == NULL)
		879	return NULL;
		880
1430	serge	881	/* set the internal bit adapter */
		882	// i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
		883	i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
		884	// sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
		885	i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
		886	i2c->algo.radeon.bit_data.setsda = set_data;
		887	i2c->algo.radeon.bit_data.setscl = set_clock;
		888	i2c->algo.radeon.bit_data.getsda = get_data;
		889	i2c->algo.radeon.bit_data.getscl = get_clock;
		890	i2c->algo.radeon.bit_data.udelay = 20;
1123	serge	891	/* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
		892	* make this, 2 jiffies is a lot more reliable */
1430	serge	893	i2c->algo.radeon.bit_data.timeout = 2;
		894	i2c->algo.radeon.bit_data.data = i2c;
		895	ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
1123	serge	896	if (ret) {
1430	serge	897	DRM_ERROR("Failed to register internal bit i2c %s\n", name);
1123	serge	898	goto out_free;
		899	}
1430	serge	900	/* set the radeon i2c adapter */
		901	i2c->dev = dev;
		902	i2c->rec = *rec;
		903	// i2c->adapter.owner = THIS_MODULE;
		904	i2c_set_adapdata(&i2c->adapter, i2c);
		905	// sprintf(i2c->adapter.name, "Radeon i2c %s", name);
		906	i2c->adapter.algo_data = &i2c->algo.radeon;
		907	i2c->adapter.algo = &radeon_i2c_algo;
1123	serge	908
		909	return i2c;
		910	out_free:
		911	kfree(i2c);
		912	return NULL;
		913
		914	}
		915
1321	serge	916	struct radeon_i2c_chan radeon_i2c_create_dp(struct drm_device dev,
		917	struct radeon_i2c_bus_rec *rec,
		918	const char *name)
		919	{
		920	struct radeon_i2c_chan *i2c;
		921	int ret;
		922
		923	i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
		924	if (i2c == NULL)
		925	return NULL;
		926
		927	i2c->rec = *rec;
1404	serge	928	// i2c->adapter.owner = THIS_MODULE;
1321	serge	929	i2c->dev = dev;
1430	serge	930	i2c_set_adapdata(&i2c->adapter, i2c);
1321	serge	931	i2c->adapter.algo_data = &i2c->algo.dp;
		932	i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
		933	i2c->algo.dp.address = 0;
		934	ret = i2c_dp_aux_add_bus(&i2c->adapter);
		935	if (ret) {
		936	DRM_INFO("Failed to register i2c %s\n", name);
		937	goto out_free;
		938	}
		939
		940	return i2c;
		941	out_free:
		942	kfree(i2c);
		943	return NULL;
		944
		945	}
		946
1123	serge	947	void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
		948	{
		949	if (!i2c)
		950	return;
1430	serge	951	kfree(i2c);
		952	}
1123	serge	953
1430	serge	954	void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
		955	{
		956	if (!i2c)
		957	return;
		958
1123	serge	959	kfree(i2c);
		960	}
		961
		962	struct drm_encoder radeon_best_encoder(struct drm_connector connector)
		963	{
		964	return NULL;
		965	}
1321	serge	966
1430	serge	967	void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1321	serge	968	u8 slave_addr,
		969	u8 addr,
		970	u8 *val)
		971	{
		972	u8 out_buf[2];
		973	u8 in_buf[2];
		974	struct i2c_msg msgs[] = {
		975	{
		976	.addr = slave_addr,
		977	.flags = 0,
		978	.len = 1,
		979	.buf = out_buf,
		980	},
		981	{
		982	.addr = slave_addr,
		983	.flags = I2C_M_RD,
		984	.len = 1,
		985	.buf = in_buf,
		986	}
		987	};
		988
		989	out_buf[0] = addr;
		990	out_buf[1] = 0;
		991
		992	if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
		993	*val = in_buf[0];
		994	DRM_DEBUG("val = 0x%02x\n", *val);
		995	} else {
		996	DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
		997	addr, *val);
		998	}
		999	}
		1000
1430	serge	1001	void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1321	serge	1002	u8 slave_addr,
		1003	u8 addr,
		1004	u8 val)
		1005	{
		1006	uint8_t out_buf[2];
		1007	struct i2c_msg msg = {
		1008	.addr = slave_addr,
		1009	.flags = 0,
		1010	.len = 2,
		1011	.buf = out_buf,
		1012	};
		1013
		1014	out_buf[0] = addr;
		1015	out_buf[1] = val;
		1016
		1017	if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
		1018	DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
		1019	addr, val);
		1020	}
		1021

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(root)/drivers/video/drm/radeon/radeon_i2c.c – Rev 1630