WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_i2c.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "radeon_drm.h"
		28	#include "radeon.h"
1430	serge	29	#include "atom.h"
1123	serge	30
		31	/**
		32	* radeon_ddc_probe
		33	*
		34	*/
		35	bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
		36	{
		37	u8 out_buf[] = { 0x0, 0x0};
		38	u8 buf[2];
		39	int ret;
		40	struct i2c_msg msgs[] = {
		41	{
		42	.addr = 0x50,
		43	.flags = 0,
		44	.len = 1,
		45	.buf = out_buf,
		46	},
		47	{
		48	.addr = 0x50,
		49	.flags = I2C_M_RD,
		50	.len = 1,
		51	.buf = buf,
		52	}
		53	};
		54
		55	ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
		56	if (ret == 2)
		57	return true;
		58
		59	return false;
		60	}
		61
		62
1430	serge	63	static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
1123	serge	64	{
1321	serge	65	struct radeon_device *rdev = i2c->dev->dev_private;
		66	struct radeon_i2c_bus_rec *rec = &i2c->rec;
1123	serge	67	uint32_t temp;
		68
		69	/* RV410 appears to have a bug where the hw i2c in reset
		70	* holds the i2c port in a bad state - switch hw i2c away before
		71	* doing DDC - do this for all r200s/r300s/r400s for safety sake
		72	*/
1321	serge	73	if (rec->hw_capable) {
1123	serge	74	if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
1430	serge	75	u32 reg;
		76
		77	if (rdev->family >= CHIP_RV350)
		78	reg = RADEON_GPIO_MONID;
		79	else if ((rdev->family == CHIP_R300) \|\|
		80	(rdev->family == CHIP_R350))
		81	reg = RADEON_GPIO_DVI_DDC;
		82	else
		83	reg = RADEON_GPIO_CRT2_DDC;
		84
		85	mutex_lock(&rdev->dc_hw_i2c_mutex);
		86	if (rec->a_clk_reg == reg) {
1123	serge	87	WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST \|
		88	R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
		89	} else {
		90	WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST \|
		91	R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
		92	}
		93	}
1321	serge	94	}
		95
		96	/* clear the output pin values */
		97	temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
1123	serge	98	WREG32(rec->a_clk_reg, temp);
		99
1321	serge	100	temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
1123	serge	101	WREG32(rec->a_data_reg, temp);
		102
1321	serge	103	/* set the pins to input */
		104	temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
		105	WREG32(rec->en_clk_reg, temp);
		106
		107	temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
		108	WREG32(rec->en_data_reg, temp);
		109
		110	/* mask the gpio pins for software use */
1123	serge	111	temp = RREG32(rec->mask_clk_reg);
		112	if (lock_state)
		113	temp \|= rec->mask_clk_mask;
		114	else
		115	temp &= ~rec->mask_clk_mask;
		116	WREG32(rec->mask_clk_reg, temp);
		117	temp = RREG32(rec->mask_clk_reg);
		118
		119	temp = RREG32(rec->mask_data_reg);
		120	if (lock_state)
		121	temp \|= rec->mask_data_mask;
		122	else
		123	temp &= ~rec->mask_data_mask;
		124	WREG32(rec->mask_data_reg, temp);
		125	temp = RREG32(rec->mask_data_reg);
		126	}
		127
		128	static int get_clock(void *i2c_priv)
		129	{
		130	struct radeon_i2c_chan *i2c = i2c_priv;
		131	struct radeon_device *rdev = i2c->dev->dev_private;
		132	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		133	uint32_t val;
		134
1321	serge	135	/* read the value off the pin */
		136	val = RREG32(rec->y_clk_reg);
		137	val &= rec->y_clk_mask;
1123	serge	138
		139	return (val != 0);
		140	}
		141
		142
		143	static int get_data(void *i2c_priv)
		144	{
		145	struct radeon_i2c_chan *i2c = i2c_priv;
		146	struct radeon_device *rdev = i2c->dev->dev_private;
		147	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		148	uint32_t val;
		149
1321	serge	150	/* read the value off the pin */
		151	val = RREG32(rec->y_data_reg);
		152	val &= rec->y_data_mask;
		153
1123	serge	154	return (val != 0);
		155	}
		156
		157	static void set_clock(void *i2c_priv, int clock)
		158	{
		159	struct radeon_i2c_chan *i2c = i2c_priv;
		160	struct radeon_device *rdev = i2c->dev->dev_private;
		161	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		162	uint32_t val;
		163
1321	serge	164	/* set pin direction */
		165	val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
		166	val \|= clock ? 0 : rec->en_clk_mask;
		167	WREG32(rec->en_clk_reg, val);
1123	serge	168	}
		169
		170	static void set_data(void *i2c_priv, int data)
		171	{
		172	struct radeon_i2c_chan *i2c = i2c_priv;
		173	struct radeon_device *rdev = i2c->dev->dev_private;
		174	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		175	uint32_t val;
		176
1321	serge	177	/* set pin direction */
		178	val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
		179	val \|= data ? 0 : rec->en_data_mask;
		180	WREG32(rec->en_data_reg, val);
1123	serge	181	}
		182
1430	serge	183	static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
		184	{
		185	struct radeon_pll *spll = &rdev->clock.spll;
		186	u32 sclk = radeon_get_engine_clock(rdev);
		187	u32 prescale = 0;
		188	u32 n, m;
		189	u8 loop;
		190	int i2c_clock;
		191
		192	switch (rdev->family) {
		193	case CHIP_R100:
		194	case CHIP_RV100:
		195	case CHIP_RS100:
		196	case CHIP_RV200:
		197	case CHIP_RS200:
		198	case CHIP_R200:
		199	case CHIP_RV250:
		200	case CHIP_RS300:
		201	case CHIP_RV280:
		202	case CHIP_R300:
		203	case CHIP_R350:
		204	case CHIP_RV350:
		205	n = (spll->reference_freq) / (4 * 6);
		206	for (loop = 1; loop < 255; loop++) {
		207	if ((loop * (loop - 1)) > n)
		208	break;
		209	}
		210	m = loop - 1;
		211	prescale = m \| (loop << 8);
		212	break;
		213	case CHIP_RV380:
		214	case CHIP_RS400:
		215	case CHIP_RS480:
		216	case CHIP_R420:
		217	case CHIP_R423:
		218	case CHIP_RV410:
		219	sclk = radeon_get_engine_clock(rdev);
		220	prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
		221	break;
		222	case CHIP_RS600:
		223	case CHIP_RS690:
		224	case CHIP_RS740:
		225	/* todo */
		226	break;
		227	case CHIP_RV515:
		228	case CHIP_R520:
		229	case CHIP_RV530:
		230	case CHIP_RV560:
		231	case CHIP_RV570:
		232	case CHIP_R580:
		233	i2c_clock = 50;
		234	sclk = radeon_get_engine_clock(rdev);
		235	if (rdev->family == CHIP_R520)
		236	prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
		237	else
		238	prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
		239	break;
		240	case CHIP_R600:
		241	case CHIP_RV610:
		242	case CHIP_RV630:
		243	case CHIP_RV670:
		244	/* todo */
		245	break;
		246	case CHIP_RV620:
		247	case CHIP_RV635:
		248	case CHIP_RS780:
		249	case CHIP_RS880:
		250	case CHIP_RV770:
		251	case CHIP_RV730:
		252	case CHIP_RV710:
		253	case CHIP_RV740:
		254	/* todo */
		255	break;
		256	case CHIP_CEDAR:
		257	case CHIP_REDWOOD:
		258	case CHIP_JUNIPER:
		259	case CHIP_CYPRESS:
		260	case CHIP_HEMLOCK:
		261	/* todo */
		262	break;
		263	default:
		264	DRM_ERROR("i2c: unhandled radeon chip\n");
		265	break;
		266	}
		267	return prescale;
		268	}
		269
		270
		271	/* hw i2c engine for r1xx-4xx hardware
		272	* hw can buffer up to 15 bytes
		273	*/
		274	static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
		275	struct i2c_msg *msgs, int num)
		276	{
		277	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		278	struct radeon_device *rdev = i2c->dev->dev_private;
		279	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		280	struct i2c_msg *p;
		281	int i, j, k, ret = num;
		282	u32 prescale;
		283	u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
		284	u32 tmp, reg;
		285
		286	mutex_lock(&rdev->dc_hw_i2c_mutex);
		287	/* take the pm lock since we need a constant sclk */
		288	mutex_lock(&rdev->pm.mutex);
		289
		290	prescale = radeon_get_i2c_prescale(rdev);
		291
		292	reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) \|
		293	RADEON_I2C_START \|
		294	RADEON_I2C_STOP \|
		295	RADEON_I2C_GO);
		296
		297	if (rdev->is_atom_bios) {
		298	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		299	WREG32(RADEON_BIOS_6_SCRATCH, tmp \| ATOM_S6_HW_I2C_BUSY_STATE);
		300	}
		301
		302	if (rec->mm_i2c) {
		303	i2c_cntl_0 = RADEON_I2C_CNTL_0;
		304	i2c_cntl_1 = RADEON_I2C_CNTL_1;
		305	i2c_data = RADEON_I2C_DATA;
		306	} else {
		307	i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
		308	i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
		309	i2c_data = RADEON_DVI_I2C_DATA;
		310
		311	switch (rdev->family) {
		312	case CHIP_R100:
		313	case CHIP_RV100:
		314	case CHIP_RS100:
		315	case CHIP_RV200:
		316	case CHIP_RS200:
		317	case CHIP_RS300:
		318	switch (rec->mask_clk_reg) {
		319	case RADEON_GPIO_DVI_DDC:
		320	/* no gpio select bit */
		321	break;
		322	default:
		323	DRM_ERROR("gpio not supported with hw i2c\n");
		324	ret = -EINVAL;
		325	goto done;
		326	}
		327	break;
		328	case CHIP_R200:
		329	/* only bit 4 on r200 */
		330	switch (rec->mask_clk_reg) {
		331	case RADEON_GPIO_DVI_DDC:
		332	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		333	break;
		334	case RADEON_GPIO_MONID:
		335	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		336	break;
		337	default:
		338	DRM_ERROR("gpio not supported with hw i2c\n");
		339	ret = -EINVAL;
		340	goto done;
		341	}
		342	break;
		343	case CHIP_RV250:
		344	case CHIP_RV280:
		345	/* bits 3 and 4 */
		346	switch (rec->mask_clk_reg) {
		347	case RADEON_GPIO_DVI_DDC:
		348	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		349	break;
		350	case RADEON_GPIO_VGA_DDC:
		351	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
		352	break;
		353	case RADEON_GPIO_CRT2_DDC:
		354	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		355	break;
		356	default:
		357	DRM_ERROR("gpio not supported with hw i2c\n");
		358	ret = -EINVAL;
		359	goto done;
		360	}
		361	break;
		362	case CHIP_R300:
		363	case CHIP_R350:
		364	/* only bit 4 on r300/r350 */
		365	switch (rec->mask_clk_reg) {
		366	case RADEON_GPIO_VGA_DDC:
		367	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		368	break;
		369	case RADEON_GPIO_DVI_DDC:
		370	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		371	break;
		372	default:
		373	DRM_ERROR("gpio not supported with hw i2c\n");
		374	ret = -EINVAL;
		375	goto done;
		376	}
		377	break;
		378	case CHIP_RV350:
		379	case CHIP_RV380:
		380	case CHIP_R420:
		381	case CHIP_R423:
		382	case CHIP_RV410:
		383	case CHIP_RS400:
		384	case CHIP_RS480:
		385	/* bits 3 and 4 */
		386	switch (rec->mask_clk_reg) {
		387	case RADEON_GPIO_VGA_DDC:
		388	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
		389	break;
		390	case RADEON_GPIO_DVI_DDC:
		391	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
		392	break;
		393	case RADEON_GPIO_MONID:
		394	reg \|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
		395	break;
		396	default:
		397	DRM_ERROR("gpio not supported with hw i2c\n");
		398	ret = -EINVAL;
		399	goto done;
		400	}
		401	break;
		402	default:
		403	DRM_ERROR("unsupported asic\n");
		404	ret = -EINVAL;
		405	goto done;
		406	break;
		407	}
		408	}
		409
		410	/* check for bus probe */
		411	p = &msgs[0];
		412	if ((num == 1) && (p->len == 0)) {
		413	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		414	RADEON_I2C_NACK \|
		415	RADEON_I2C_HALT \|
		416	RADEON_I2C_SOFT_RST));
		417	WREG32(i2c_data, (p->addr << 1) & 0xff);
		418	WREG32(i2c_data, 0);
		419	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		420	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		421	RADEON_I2C_EN \|
		422	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		423	WREG32(i2c_cntl_0, reg);
		424	for (k = 0; k < 32; k++) {
		425	udelay(10);
		426	tmp = RREG32(i2c_cntl_0);
		427	if (tmp & RADEON_I2C_GO)
		428	continue;
		429	tmp = RREG32(i2c_cntl_0);
		430	if (tmp & RADEON_I2C_DONE)
		431	break;
		432	else {
		433	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		434	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		435	ret = -EIO;
		436	goto done;
		437	}
		438	}
		439	goto done;
		440	}
		441
		442	for (i = 0; i < num; i++) {
		443	p = &msgs[i];
		444	for (j = 0; j < p->len; j++) {
		445	if (p->flags & I2C_M_RD) {
		446	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		447	RADEON_I2C_NACK \|
		448	RADEON_I2C_HALT \|
		449	RADEON_I2C_SOFT_RST));
		450	WREG32(i2c_data, ((p->addr << 1) & 0xff) \| 0x1);
		451	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		452	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		453	RADEON_I2C_EN \|
		454	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		455	WREG32(i2c_cntl_0, reg \| RADEON_I2C_RECEIVE);
		456	for (k = 0; k < 32; k++) {
		457	udelay(10);
		458	tmp = RREG32(i2c_cntl_0);
		459	if (tmp & RADEON_I2C_GO)
		460	continue;
		461	tmp = RREG32(i2c_cntl_0);
		462	if (tmp & RADEON_I2C_DONE)
		463	break;
		464	else {
		465	DRM_DEBUG("i2c read error 0x%08x\n", tmp);
		466	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		467	ret = -EIO;
		468	goto done;
		469	}
		470	}
		471	p->buf[j] = RREG32(i2c_data) & 0xff;
		472	} else {
		473	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		474	RADEON_I2C_NACK \|
		475	RADEON_I2C_HALT \|
		476	RADEON_I2C_SOFT_RST));
		477	WREG32(i2c_data, (p->addr << 1) & 0xff);
		478	WREG32(i2c_data, p->buf[j]);
		479	WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) \|
		480	(1 << RADEON_I2C_ADDR_COUNT_SHIFT) \|
		481	RADEON_I2C_EN \|
		482	(48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
		483	WREG32(i2c_cntl_0, reg);
		484	for (k = 0; k < 32; k++) {
		485	udelay(10);
		486	tmp = RREG32(i2c_cntl_0);
		487	if (tmp & RADEON_I2C_GO)
		488	continue;
		489	tmp = RREG32(i2c_cntl_0);
		490	if (tmp & RADEON_I2C_DONE)
		491	break;
		492	else {
		493	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		494	WREG32(i2c_cntl_0, tmp \| RADEON_I2C_ABORT);
		495	ret = -EIO;
		496	goto done;
		497	}
		498	}
		499	}
		500	}
		501	}
		502
		503	done:
		504	WREG32(i2c_cntl_0, 0);
		505	WREG32(i2c_cntl_1, 0);
		506	WREG32(i2c_cntl_0, (RADEON_I2C_DONE \|
		507	RADEON_I2C_NACK \|
		508	RADEON_I2C_HALT \|
		509	RADEON_I2C_SOFT_RST));
		510
		511	if (rdev->is_atom_bios) {
		512	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		513	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
		514	WREG32(RADEON_BIOS_6_SCRATCH, tmp);
		515	}
		516
		517	mutex_unlock(&rdev->pm.mutex);
		518	mutex_unlock(&rdev->dc_hw_i2c_mutex);
		519
		520	return ret;
		521	}
		522
		523	/* hw i2c engine for r5xx hardware
		524	* hw can buffer up to 15 bytes
		525	*/
		526	static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
		527	struct i2c_msg *msgs, int num)
		528	{
		529	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		530	struct radeon_device *rdev = i2c->dev->dev_private;
		531	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		532	struct i2c_msg *p;
		533	int i, j, remaining, current_count, buffer_offset, ret = num;
		534	u32 prescale;
		535	u32 tmp, reg;
		536	u32 saved1, saved2;
		537
		538	mutex_lock(&rdev->dc_hw_i2c_mutex);
		539	/* take the pm lock since we need a constant sclk */
		540	mutex_lock(&rdev->pm.mutex);
		541
		542	prescale = radeon_get_i2c_prescale(rdev);
		543
		544	/* clear gpio mask bits */
		545	tmp = RREG32(rec->mask_clk_reg);
		546	tmp &= ~rec->mask_clk_mask;
		547	WREG32(rec->mask_clk_reg, tmp);
		548	tmp = RREG32(rec->mask_clk_reg);
		549
		550	tmp = RREG32(rec->mask_data_reg);
		551	tmp &= ~rec->mask_data_mask;
		552	WREG32(rec->mask_data_reg, tmp);
		553	tmp = RREG32(rec->mask_data_reg);
		554
		555	/* clear pin values */
		556	tmp = RREG32(rec->a_clk_reg);
		557	tmp &= ~rec->a_clk_mask;
		558	WREG32(rec->a_clk_reg, tmp);
		559	tmp = RREG32(rec->a_clk_reg);
		560
		561	tmp = RREG32(rec->a_data_reg);
		562	tmp &= ~rec->a_data_mask;
		563	WREG32(rec->a_data_reg, tmp);
		564	tmp = RREG32(rec->a_data_reg);
		565
		566	/* set the pins to input */
		567	tmp = RREG32(rec->en_clk_reg);
		568	tmp &= ~rec->en_clk_mask;
		569	WREG32(rec->en_clk_reg, tmp);
		570	tmp = RREG32(rec->en_clk_reg);
		571
		572	tmp = RREG32(rec->en_data_reg);
		573	tmp &= ~rec->en_data_mask;
		574	WREG32(rec->en_data_reg, tmp);
		575	tmp = RREG32(rec->en_data_reg);
		576
		577	/* */
		578	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		579	WREG32(RADEON_BIOS_6_SCRATCH, tmp \| ATOM_S6_HW_I2C_BUSY_STATE);
		580	saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
		581	saved2 = RREG32(0x494);
		582	WREG32(0x494, saved2 \| 0x1);
		583
		584	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
		585	for (i = 0; i < 50; i++) {
		586	udelay(1);
		587	if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
		588	break;
		589	}
		590	if (i == 50) {
		591	DRM_ERROR("failed to get i2c bus\n");
		592	ret = -EBUSY;
		593	goto done;
		594	}
		595
		596	reg = AVIVO_DC_I2C_START \| AVIVO_DC_I2C_STOP \| AVIVO_DC_I2C_EN;
		597	switch (rec->mask_clk_reg) {
		598	case AVIVO_DC_GPIO_DDC1_MASK:
		599	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
		600	break;
		601	case AVIVO_DC_GPIO_DDC2_MASK:
		602	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
		603	break;
		604	case AVIVO_DC_GPIO_DDC3_MASK:
		605	reg \|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
		606	break;
		607	default:
		608	DRM_ERROR("gpio not supported with hw i2c\n");
		609	ret = -EINVAL;
		610	goto done;
		611	}
		612
		613	/* check for bus probe */
		614	p = &msgs[0];
		615	if ((num == 1) && (p->len == 0)) {
		616	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		617	AVIVO_DC_I2C_NACK \|
		618	AVIVO_DC_I2C_HALT));
		619	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		620	udelay(1);
		621	WREG32(AVIVO_DC_I2C_RESET, 0);
		622
		623	WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
		624	WREG32(AVIVO_DC_I2C_DATA, 0);
		625
		626	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		627	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		628	AVIVO_DC_I2C_DATA_COUNT(1) \|
		629	(prescale << 16)));
		630	WREG32(AVIVO_DC_I2C_CONTROL1, reg);
		631	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		632	for (j = 0; j < 200; j++) {
		633	udelay(50);
		634	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		635	if (tmp & AVIVO_DC_I2C_GO)
		636	continue;
		637	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		638	if (tmp & AVIVO_DC_I2C_DONE)
		639	break;
		640	else {
		641	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		642	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		643	ret = -EIO;
		644	goto done;
		645	}
		646	}
		647	goto done;
		648	}
		649
		650	for (i = 0; i < num; i++) {
		651	p = &msgs[i];
		652	remaining = p->len;
		653	buffer_offset = 0;
		654	if (p->flags & I2C_M_RD) {
		655	while (remaining) {
		656	if (remaining > 15)
		657	current_count = 15;
		658	else
		659	current_count = remaining;
		660	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		661	AVIVO_DC_I2C_NACK \|
		662	AVIVO_DC_I2C_HALT));
		663	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		664	udelay(1);
		665	WREG32(AVIVO_DC_I2C_RESET, 0);
		666
		667	WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) \| 0x1);
		668	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		669	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		670	AVIVO_DC_I2C_DATA_COUNT(current_count) \|
		671	(prescale << 16)));
		672	WREG32(AVIVO_DC_I2C_CONTROL1, reg \| AVIVO_DC_I2C_RECEIVE);
		673	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		674	for (j = 0; j < 200; j++) {
		675	udelay(50);
		676	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		677	if (tmp & AVIVO_DC_I2C_GO)
		678	continue;
		679	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		680	if (tmp & AVIVO_DC_I2C_DONE)
		681	break;
		682	else {
		683	DRM_DEBUG("i2c read error 0x%08x\n", tmp);
		684	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		685	ret = -EIO;
		686	goto done;
		687	}
		688	}
		689	for (j = 0; j < current_count; j++)
		690	p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
		691	remaining -= current_count;
		692	buffer_offset += current_count;
		693	}
		694	} else {
		695	while (remaining) {
		696	if (remaining > 15)
		697	current_count = 15;
		698	else
		699	current_count = remaining;
		700	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		701	AVIVO_DC_I2C_NACK \|
		702	AVIVO_DC_I2C_HALT));
		703	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		704	udelay(1);
		705	WREG32(AVIVO_DC_I2C_RESET, 0);
		706
		707	WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
		708	for (j = 0; j < current_count; j++)
		709	WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
		710
		711	WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
		712	WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) \|
		713	AVIVO_DC_I2C_DATA_COUNT(current_count) \|
		714	(prescale << 16)));
		715	WREG32(AVIVO_DC_I2C_CONTROL1, reg);
		716	WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
		717	for (j = 0; j < 200; j++) {
		718	udelay(50);
		719	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		720	if (tmp & AVIVO_DC_I2C_GO)
		721	continue;
		722	tmp = RREG32(AVIVO_DC_I2C_STATUS1);
		723	if (tmp & AVIVO_DC_I2C_DONE)
		724	break;
		725	else {
		726	DRM_DEBUG("i2c write error 0x%08x\n", tmp);
		727	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
		728	ret = -EIO;
		729	goto done;
		730	}
		731	}
		732	remaining -= current_count;
		733	buffer_offset += current_count;
		734	}
		735	}
		736	}
		737
		738	done:
		739	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE \|
		740	AVIVO_DC_I2C_NACK \|
		741	AVIVO_DC_I2C_HALT));
		742	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
		743	udelay(1);
		744	WREG32(AVIVO_DC_I2C_RESET, 0);
		745
		746	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
		747	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
		748	WREG32(0x494, saved2);
		749	tmp = RREG32(RADEON_BIOS_6_SCRATCH);
		750	tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
		751	WREG32(RADEON_BIOS_6_SCRATCH, tmp);
		752
		753	mutex_unlock(&rdev->pm.mutex);
		754	mutex_unlock(&rdev->dc_hw_i2c_mutex);
		755
		756	return ret;
		757	}
		758
		759	static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap,
		760	struct i2c_msg *msgs, int num)
		761	{
		762	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		763	int ret;
		764
		765	radeon_i2c_do_lock(i2c, 1);
		766	ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num);
		767	radeon_i2c_do_lock(i2c, 0);
		768
		769	return ret;
		770	}
		771
		772	static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap,
		773	struct i2c_msg *msgs, int num)
		774	{
		775	struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
		776	struct radeon_device *rdev = i2c->dev->dev_private;
		777	struct radeon_i2c_bus_rec *rec = &i2c->rec;
		778	int ret;
		779
		780	switch (rdev->family) {
		781	case CHIP_R100:
		782	case CHIP_RV100:
		783	case CHIP_RS100:
		784	case CHIP_RV200:
		785	case CHIP_RS200:
		786	case CHIP_R200:
		787	case CHIP_RV250:
		788	case CHIP_RS300:
		789	case CHIP_RV280:
		790	case CHIP_R300:
		791	case CHIP_R350:
		792	case CHIP_RV350:
		793	case CHIP_RV380:
		794	case CHIP_R420:
		795	case CHIP_R423:
		796	case CHIP_RV410:
		797	case CHIP_RS400:
		798	case CHIP_RS480:
		799	if (rec->hw_capable)
		800	ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
		801	else
		802	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		803	break;
		804	case CHIP_RS600:
		805	case CHIP_RS690:
		806	case CHIP_RS740:
		807	/* XXX fill in hw i2c implementation */
		808	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		809	break;
		810	case CHIP_RV515:
		811	case CHIP_R520:
		812	case CHIP_RV530:
		813	case CHIP_RV560:
		814	case CHIP_RV570:
		815	case CHIP_R580:
		816	if (rec->hw_capable) {
		817	if (rec->mm_i2c)
		818	ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
		819	else
		820	ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
		821	} else
		822	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		823	break;
		824	case CHIP_R600:
		825	case CHIP_RV610:
		826	case CHIP_RV630:
		827	case CHIP_RV670:
		828	/* XXX fill in hw i2c implementation */
		829	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		830	break;
		831	case CHIP_RV620:
		832	case CHIP_RV635:
		833	case CHIP_RS780:
		834	case CHIP_RS880:
		835	case CHIP_RV770:
		836	case CHIP_RV730:
		837	case CHIP_RV710:
		838	case CHIP_RV740:
		839	/* XXX fill in hw i2c implementation */
		840	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		841	break;
		842	case CHIP_CEDAR:
		843	case CHIP_REDWOOD:
		844	case CHIP_JUNIPER:
		845	case CHIP_CYPRESS:
		846	case CHIP_HEMLOCK:
		847	/* XXX fill in hw i2c implementation */
		848	ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num);
		849	break;
		850	default:
		851	DRM_ERROR("i2c: unhandled radeon chip\n");
		852	ret = -EIO;
		853	break;
		854	}
		855
		856	return ret;
		857	}
		858
		859	static u32 radeon_i2c_func(struct i2c_adapter *adap)
		860	{
		861	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
		862	}
		863
		864	static const struct i2c_algorithm radeon_i2c_algo = {
		865	.master_xfer = radeon_i2c_xfer,
		866	.functionality = radeon_i2c_func,
		867	};
		868
1123	serge	869	struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev,
		870	struct radeon_i2c_bus_rec *rec,
		871	const char *name)
		872	{
		873	struct radeon_i2c_chan *i2c;
		874	int ret;
		875
		876	i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
		877	if (i2c == NULL)
		878	return NULL;
		879
1430	serge	880	/* set the internal bit adapter */
		881	// i2c->algo.radeon.bit_adapter.owner = THIS_MODULE;
		882	i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c);
		883	// sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name);
		884	i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data;
		885	i2c->algo.radeon.bit_data.setsda = set_data;
		886	i2c->algo.radeon.bit_data.setscl = set_clock;
		887	i2c->algo.radeon.bit_data.getsda = get_data;
		888	i2c->algo.radeon.bit_data.getscl = get_clock;
		889	i2c->algo.radeon.bit_data.udelay = 20;
1123	serge	890	/* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
		891	* make this, 2 jiffies is a lot more reliable */
1430	serge	892	i2c->algo.radeon.bit_data.timeout = 2;
		893	i2c->algo.radeon.bit_data.data = i2c;
		894	ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter);
1123	serge	895	if (ret) {
1430	serge	896	DRM_ERROR("Failed to register internal bit i2c %s\n", name);
1123	serge	897	goto out_free;
		898	}
1430	serge	899	/* set the radeon i2c adapter */
		900	i2c->dev = dev;
		901	i2c->rec = *rec;
		902	// i2c->adapter.owner = THIS_MODULE;
		903	i2c_set_adapdata(&i2c->adapter, i2c);
		904	// sprintf(i2c->adapter.name, "Radeon i2c %s", name);
		905	i2c->adapter.algo_data = &i2c->algo.radeon;
		906	i2c->adapter.algo = &radeon_i2c_algo;
1123	serge	907
		908	return i2c;
		909	out_free:
		910	kfree(i2c);
		911	return NULL;
		912
		913	}
		914
1321	serge	915	struct radeon_i2c_chan radeon_i2c_create_dp(struct drm_device dev,
		916	struct radeon_i2c_bus_rec *rec,
		917	const char *name)
		918	{
		919	struct radeon_i2c_chan *i2c;
		920	int ret;
		921
		922	i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
		923	if (i2c == NULL)
		924	return NULL;
		925
		926	i2c->rec = *rec;
1404	serge	927	// i2c->adapter.owner = THIS_MODULE;
1321	serge	928	i2c->dev = dev;
1430	serge	929	i2c_set_adapdata(&i2c->adapter, i2c);
1321	serge	930	i2c->adapter.algo_data = &i2c->algo.dp;
		931	i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
		932	i2c->algo.dp.address = 0;
		933	ret = i2c_dp_aux_add_bus(&i2c->adapter);
		934	if (ret) {
		935	DRM_INFO("Failed to register i2c %s\n", name);
		936	goto out_free;
		937	}
		938
		939	return i2c;
		940	out_free:
		941	kfree(i2c);
		942	return NULL;
		943
		944	}
		945
1123	serge	946	void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
		947	{
		948	if (!i2c)
		949	return;
1430	serge	950	kfree(i2c);
		951	}
1123	serge	952
1430	serge	953	void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c)
		954	{
		955	if (!i2c)
		956	return;
		957
1123	serge	958	kfree(i2c);
		959	}
		960
		961	struct drm_encoder radeon_best_encoder(struct drm_connector connector)
		962	{
		963	return NULL;
		964	}
1321	serge	965
1430	serge	966	void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1321	serge	967	u8 slave_addr,
		968	u8 addr,
		969	u8 *val)
		970	{
		971	u8 out_buf[2];
		972	u8 in_buf[2];
		973	struct i2c_msg msgs[] = {
		974	{
		975	.addr = slave_addr,
		976	.flags = 0,
		977	.len = 1,
		978	.buf = out_buf,
		979	},
		980	{
		981	.addr = slave_addr,
		982	.flags = I2C_M_RD,
		983	.len = 1,
		984	.buf = in_buf,
		985	}
		986	};
		987
		988	out_buf[0] = addr;
		989	out_buf[1] = 0;
		990
		991	if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
		992	*val = in_buf[0];
		993	DRM_DEBUG("val = 0x%02x\n", *val);
		994	} else {
		995	DRM_ERROR("i2c 0x%02x 0x%02x read failed\n",
		996	addr, *val);
		997	}
		998	}
		999
1430	serge	1000	void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1321	serge	1001	u8 slave_addr,
		1002	u8 addr,
		1003	u8 val)
		1004	{
		1005	uint8_t out_buf[2];
		1006	struct i2c_msg msg = {
		1007	.addr = slave_addr,
		1008	.flags = 0,
		1009	.len = 2,
		1010	.buf = out_buf,
		1011	};
		1012
		1013	out_buf[0] = addr;
		1014	out_buf[1] = val;
		1015
		1016	if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
		1017	DRM_ERROR("i2c 0x%02x 0x%02x write failed\n",
		1018	addr, val);
		1019	}
		1020

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(root)/drivers/video/drm/radeon/radeon_i2c.c – Rev 1430