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1120 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
1125 serge 28
#include "drmP.h"
1120 serge 29
#include "radeon_drm.h"
30
#include "radeon.h"
31
#include "radeon_reg.h"
32
 
1631 serge 33
 
34
static inline void *
35
pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
36
                      addr_t *dma_handle)
37
{
38
 
39
    size = (size + 0x7FFF) & ~0x7FFF;
40
 
41
    *dma_handle = AllocPages(size >> 12);
42
    return (void*)MapIoMem(*dma_handle, size, PG_SW+PG_NOCACHE);
43
}
44
 
1120 serge 45
/*
46
 * Common GART table functions.
47
 */
48
int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
49
{
50
	void *ptr;
51
 
1246 serge 52
    ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
53
                  &rdev->gart.table_addr);
1120 serge 54
	if (ptr == NULL) {
55
		return -ENOMEM;
56
	}
57
#ifdef CONFIG_X86
58
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
59
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
60
		set_memory_uc((unsigned long)ptr,
61
			      rdev->gart.table_size >> PAGE_SHIFT);
62
	}
63
#endif
64
	rdev->gart.table.ram.ptr = ptr;
65
	memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
66
	return 0;
67
}
68
 
69
void radeon_gart_table_ram_free(struct radeon_device *rdev)
70
{
71
	if (rdev->gart.table.ram.ptr == NULL) {
72
		return;
73
	}
74
#ifdef CONFIG_X86
75
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
76
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
77
		set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
78
			      rdev->gart.table_size >> PAGE_SHIFT);
79
	}
80
#endif
1128 serge 81
//   pci_free_consistent(rdev->pdev, rdev->gart.table_size,
82
//               (void *)rdev->gart.table.ram.ptr,
83
//               rdev->gart.table_addr);
1120 serge 84
	rdev->gart.table.ram.ptr = NULL;
85
	rdev->gart.table_addr = 0;
86
}
87
 
88
int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
89
{
90
    int r;
91
 
92
    if (rdev->gart.table.vram.robj == NULL) {
1963 serge 93
		r = radeon_bo_create(rdev, rdev->gart.table_size,
94
				     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1404 serge 95
					&rdev->gart.table.vram.robj);
1120 serge 96
        if (r) {
97
            return r;
98
        }
99
    }
1179 serge 100
	return 0;
101
}
102
 
103
int radeon_gart_table_vram_pin(struct radeon_device *rdev)
104
{
105
	uint64_t gpu_addr;
106
	int r;
107
 
1404 serge 108
	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
109
	if (unlikely(r != 0))
110
		return r;
111
	r = radeon_bo_pin(rdev->gart.table.vram.robj,
1120 serge 112
                  RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
113
    if (r) {
1404 serge 114
		radeon_bo_unreserve(rdev->gart.table.vram.robj);
1120 serge 115
        return r;
116
    }
1404 serge 117
	r = radeon_bo_kmap(rdev->gart.table.vram.robj,
1120 serge 118
                   (void **)&rdev->gart.table.vram.ptr);
1404 serge 119
	if (r)
120
		radeon_bo_unpin(rdev->gart.table.vram.robj);
121
	radeon_bo_unreserve(rdev->gart.table.vram.robj);
122
	rdev->gart.table_addr = gpu_addr;
123
    return r;
1120 serge 124
}
125
 
126
void radeon_gart_table_vram_free(struct radeon_device *rdev)
127
{
1404 serge 128
	int r;
129
 
1120 serge 130
	if (rdev->gart.table.vram.robj == NULL) {
131
		return;
132
	}
1404 serge 133
	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
134
	if (likely(r == 0)) {
135
		radeon_bo_kunmap(rdev->gart.table.vram.robj);
136
		radeon_bo_unpin(rdev->gart.table.vram.robj);
137
		radeon_bo_unreserve(rdev->gart.table.vram.robj);
138
	}
139
	radeon_bo_unref(&rdev->gart.table.vram.robj);
1120 serge 140
}
141
 
142
 
143
 
144
 
145
/*
146
 * Common gart functions.
147
 */
148
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
149
			int pages)
150
{
151
	unsigned t;
152
	unsigned p;
153
	int i, j;
1430 serge 154
	u64 page_base;
1120 serge 155
 
156
	if (!rdev->gart.ready) {
1404 serge 157
		WARN(1, "trying to unbind memory to unitialized GART !\n");
1120 serge 158
		return;
159
	}
1268 serge 160
	t = offset / RADEON_GPU_PAGE_SIZE;
161
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
1120 serge 162
	for (i = 0; i < pages; i++, p++) {
163
		if (rdev->gart.pages[p]) {
164
//           pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
165
//                      PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
166
			rdev->gart.pages[p] = NULL;
1430 serge 167
			rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
168
			page_base = rdev->gart.pages_addr[p];
1268 serge 169
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
1430 serge 170
				radeon_gart_set_page(rdev, t, page_base);
171
				page_base += RADEON_GPU_PAGE_SIZE;
1120 serge 172
			}
173
		}
174
	}
175
	mb();
176
	radeon_gart_tlb_flush(rdev);
177
}
178
 
179
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
180
             int pages, u32_t *pagelist)
181
{
182
    unsigned t;
183
    unsigned p;
184
    uint64_t page_base;
185
    int i, j;
186
 
2005 serge 187
//    dbgprintf("offset %x pages %d list %x\n",
188
//               offset, pages, pagelist);
1120 serge 189
    if (!rdev->gart.ready) {
1963 serge 190
		WARN(1, "trying to bind memory to unitialized GART !\n");
1120 serge 191
        return -EINVAL;
192
    }
1268 serge 193
	t = offset / RADEON_GPU_PAGE_SIZE;
194
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
1120 serge 195
 
196
    for (i = 0; i < pages; i++, p++) {
197
        /* we need to support large memory configurations */
198
        /* assume that unbind have already been call on the range */
199
 
200
        rdev->gart.pages_addr[p] = pagelist[i] & ~4095;
201
 
1430 serge 202
 
1120 serge 203
        rdev->gart.pages[p] = pagelist[i];
1268 serge 204
		page_base = rdev->gart.pages_addr[p];
205
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
1120 serge 206
            radeon_gart_set_page(rdev, t, page_base);
1268 serge 207
			page_base += RADEON_GPU_PAGE_SIZE;
1120 serge 208
        }
209
    }
210
    mb();
211
    radeon_gart_tlb_flush(rdev);
212
    return 0;
213
}
214
 
1430 serge 215
void radeon_gart_restore(struct radeon_device *rdev)
216
{
217
	int i, j, t;
218
	u64 page_base;
219
 
220
	for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
221
		page_base = rdev->gart.pages_addr[i];
222
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
223
			radeon_gart_set_page(rdev, t, page_base);
224
			page_base += RADEON_GPU_PAGE_SIZE;
225
		}
226
	}
227
	mb();
228
	radeon_gart_tlb_flush(rdev);
229
}
230
 
1120 serge 231
int radeon_gart_init(struct radeon_device *rdev)
232
{
1430 serge 233
	int r, i;
234
 
1120 serge 235
    if (rdev->gart.pages) {
236
        return 0;
237
    }
1268 serge 238
	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
239
	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
1120 serge 240
        DRM_ERROR("Page size is smaller than GPU page size!\n");
241
        return -EINVAL;
242
    }
1430 serge 243
	r = radeon_dummy_page_init(rdev);
244
	if (r)
245
		return r;
1120 serge 246
    /* Compute table size */
247
    rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
1268 serge 248
	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
1120 serge 249
    DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
250
         rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
251
    /* Allocate pages table */
252
    rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
253
                   GFP_KERNEL);
254
    if (rdev->gart.pages == NULL) {
1404 serge 255
		radeon_gart_fini(rdev);
1120 serge 256
        return -ENOMEM;
257
    }
1404 serge 258
	rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
1120 serge 259
                    rdev->gart.num_cpu_pages, GFP_KERNEL);
260
    if (rdev->gart.pages_addr == NULL) {
1404 serge 261
		radeon_gart_fini(rdev);
1120 serge 262
        return -ENOMEM;
263
    }
1430 serge 264
	/* set GART entry to point to the dummy page by default */
265
	for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
266
		rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
267
	}
1120 serge 268
    return 0;
269
}
270
 
271
void radeon_gart_fini(struct radeon_device *rdev)
272
{
273
	if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
274
		/* unbind pages */
275
		radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
276
	}
277
	rdev->gart.ready = false;
278
	kfree(rdev->gart.pages);
279
	kfree(rdev->gart.pages_addr);
280
	rdev->gart.pages = NULL;
281
	rdev->gart.pages_addr = NULL;
282
}