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1125 serge 1
/*
2
 * Copyright 2009 Jerome Glisse.
3
 * All Rights Reserved.
4
 *
5
 * Permission is hereby granted, free of charge, to any person obtaining a
6
 * copy of this software and associated documentation files (the
7
 * "Software"), to deal in the Software without restriction, including
8
 * without limitation the rights to use, copy, modify, merge, publish,
9
 * distribute, sub license, and/or sell copies of the Software, and to
10
 * permit persons to whom the Software is furnished to do so, subject to
11
 * the following conditions:
12
 *
13
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20
 *
21
 * The above copyright notice and this permission notice (including the
22
 * next paragraph) shall be included in all copies or substantial portions
23
 * of the Software.
24
 *
25
 */
26
/*
27
 * Authors:
28
 *    Jerome Glisse 
29
 *    Dave Airlie
30
 */
31
#include 
32
#include 
33
#include 
34
#include 
35
#include 
36
#include "drmP.h"
37
#include "drm.h"
38
#include "radeon_reg.h"
39
#include "radeon.h"
40
 
41
int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
42
{
43
	unsigned long irq_flags;
44
 
45
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
46
	if (fence->emited) {
47
		write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
48
		return 0;
49
	}
50
	fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
51
	if (!rdev->cp.ready) {
52
		/* FIXME: cp is not running assume everythings is done right
53
		 * away
54
		 */
55
		WREG32(rdev->fence_drv.scratch_reg, fence->seq);
1179 serge 56
	} else
1125 serge 57
		radeon_fence_ring_emit(rdev, fence);
1179 serge 58
 
1125 serge 59
	fence->emited = true;
60
	fence->timeout = jiffies + ((2000 * HZ) / 1000);
61
	list_del(&fence->list);
62
	list_add_tail(&fence->list, &rdev->fence_drv.emited);
63
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
64
	return 0;
65
}
66
 
67
static bool radeon_fence_poll_locked(struct radeon_device *rdev)
68
{
69
	struct radeon_fence *fence;
70
	struct list_head *i, *n;
71
	uint32_t seq;
72
	bool wake = false;
73
 
74
	if (rdev == NULL) {
75
		return true;
76
	}
77
	if (rdev->shutdown) {
78
		return true;
79
	}
80
	seq = RREG32(rdev->fence_drv.scratch_reg);
81
	rdev->fence_drv.last_seq = seq;
82
	n = NULL;
83
	list_for_each(i, &rdev->fence_drv.emited) {
84
		fence = list_entry(i, struct radeon_fence, list);
85
		if (fence->seq == seq) {
86
			n = i;
87
			break;
88
		}
89
	}
90
	/* all fence previous to this one are considered as signaled */
91
	if (n) {
92
		i = n;
93
		do {
94
			n = i->prev;
95
			list_del(i);
96
			list_add_tail(i, &rdev->fence_drv.signaled);
97
			fence = list_entry(i, struct radeon_fence, list);
98
			fence->signaled = true;
99
			i = n;
100
		} while (i != &rdev->fence_drv.emited);
101
		wake = true;
102
	}
103
	return wake;
104
}
105
 
106
static void radeon_fence_destroy(struct kref *kref)
107
{
108
	unsigned long irq_flags;
109
        struct radeon_fence *fence;
110
 
111
	fence = container_of(kref, struct radeon_fence, kref);
112
	write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
113
	list_del(&fence->list);
114
	fence->emited = false;
115
	write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
116
	kfree(fence);
117
}
118
 
119
int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
120
{
121
	unsigned long irq_flags;
122
 
123
	*fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
124
	if ((*fence) == NULL) {
125
		return -ENOMEM;
126
	}
127
	kref_init(&((*fence)->kref));
128
	(*fence)->rdev = rdev;
129
	(*fence)->emited = false;
130
	(*fence)->signaled = false;
131
	(*fence)->seq = 0;
132
	INIT_LIST_HEAD(&(*fence)->list);
133
 
134
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
135
	list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
136
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
137
	return 0;
138
}
139
 
140
 
141
bool radeon_fence_signaled(struct radeon_fence *fence)
142
{
143
	struct radeon_device *rdev = fence->rdev;
144
	unsigned long irq_flags;
145
	bool signaled = false;
146
 
147
	if (rdev->gpu_lockup) {
148
		return true;
149
	}
150
	if (fence == NULL) {
151
		return true;
152
	}
153
	write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
154
	signaled = fence->signaled;
155
	/* if we are shuting down report all fence as signaled */
156
	if (fence->rdev->shutdown) {
157
		signaled = true;
158
	}
159
	if (!fence->emited) {
160
		WARN(1, "Querying an unemited fence : %p !\n", fence);
161
		signaled = true;
162
	}
163
	if (!signaled) {
164
		radeon_fence_poll_locked(fence->rdev);
165
		signaled = fence->signaled;
166
	}
167
	write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
168
	return signaled;
169
}
170
 
1179 serge 171
int radeon_fence_wait(struct radeon_fence *fence, bool intr)
172
{
173
	struct radeon_device *rdev;
1125 serge 174
	unsigned long cur_jiffies;
175
	unsigned long timeout;
176
	bool expired = false;
177
	int r;
178
 
179
	if (fence == NULL) {
180
		WARN(1, "Querying an invalid fence : %p !\n", fence);
181
		return 0;
182
	}
183
	rdev = fence->rdev;
184
	if (radeon_fence_signaled(fence)) {
185
		return 0;
186
	}
1179 serge 187
 
1125 serge 188
retry:
189
	cur_jiffies = jiffies;
190
	timeout = HZ / 100;
191
	if (time_after(fence->timeout, cur_jiffies)) {
192
		timeout = fence->timeout - cur_jiffies;
193
	}
1182 serge 194
 
1179 serge 195
	if (intr) {
1321 serge 196
		radeon_irq_kms_sw_irq_get(rdev);
1125 serge 197
		r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
198
				radeon_fence_signaled(fence), timeout);
1321 serge 199
		radeon_irq_kms_sw_irq_put(rdev);
200
		if (unlikely(r < 0))
201
			return r;
1125 serge 202
	} else {
1321 serge 203
		radeon_irq_kms_sw_irq_get(rdev);
1125 serge 204
		r = wait_event_timeout(rdev->fence_drv.queue,
205
			 radeon_fence_signaled(fence), timeout);
1321 serge 206
		radeon_irq_kms_sw_irq_put(rdev);
1125 serge 207
	}
208
	if (unlikely(!radeon_fence_signaled(fence))) {
209
		if (unlikely(r == 0)) {
210
			expired = true;
211
		}
212
		if (unlikely(expired)) {
213
			timeout = 1;
214
			if (time_after(cur_jiffies, fence->timeout)) {
215
				timeout = cur_jiffies - fence->timeout;
216
			}
217
			timeout = jiffies_to_msecs(timeout);
218
			if (timeout > 500) {
219
				DRM_ERROR("fence(%p:0x%08X) %lums timeout "
220
					  "going to reset GPU\n",
221
					  fence, fence->seq, timeout);
222
				radeon_gpu_reset(rdev);
223
				WREG32(rdev->fence_drv.scratch_reg, fence->seq);
224
			}
225
		}
226
		goto retry;
227
	}
228
	if (unlikely(expired)) {
229
		rdev->fence_drv.count_timeout++;
230
		cur_jiffies = jiffies;
231
		timeout = 1;
232
		if (time_after(cur_jiffies, fence->timeout)) {
233
			timeout = cur_jiffies - fence->timeout;
234
		}
235
		timeout = jiffies_to_msecs(timeout);
236
		DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
237
			  fence, fence->seq, timeout);
238
		DRM_ERROR("last signaled fence(0x%08X)\n",
239
			  rdev->fence_drv.last_seq);
240
	}
241
	return 0;
242
}
243
 
244
int radeon_fence_wait_next(struct radeon_device *rdev)
245
{
246
	unsigned long irq_flags;
247
	struct radeon_fence *fence;
248
	int r;
249
 
250
	if (rdev->gpu_lockup) {
251
		return 0;
252
	}
253
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
254
	if (list_empty(&rdev->fence_drv.emited)) {
255
		write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
256
		return 0;
257
	}
258
	fence = list_entry(rdev->fence_drv.emited.next,
259
			   struct radeon_fence, list);
260
	radeon_fence_ref(fence);
261
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
262
	r = radeon_fence_wait(fence, false);
263
	radeon_fence_unref(&fence);
264
	return r;
265
}
266
 
267
int radeon_fence_wait_last(struct radeon_device *rdev)
268
{
269
	unsigned long irq_flags;
270
	struct radeon_fence *fence;
271
	int r;
272
 
273
	if (rdev->gpu_lockup) {
274
		return 0;
275
	}
276
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
277
	if (list_empty(&rdev->fence_drv.emited)) {
278
		write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
279
		return 0;
280
	}
281
	fence = list_entry(rdev->fence_drv.emited.prev,
282
			   struct radeon_fence, list);
283
	radeon_fence_ref(fence);
284
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
285
	r = radeon_fence_wait(fence, false);
286
	radeon_fence_unref(&fence);
287
	return r;
288
}
289
 
290
struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
291
{
292
	kref_get(&fence->kref);
293
	return fence;
294
}
295
 
296
void radeon_fence_unref(struct radeon_fence **fence)
297
{
298
	struct radeon_fence *tmp = *fence;
299
 
300
	*fence = NULL;
301
	if (tmp) {
302
		kref_put(&tmp->kref, &radeon_fence_destroy);
303
	}
304
}
305
 
306
void radeon_fence_process(struct radeon_device *rdev)
307
{
308
	unsigned long irq_flags;
309
	bool wake;
310
 
311
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
312
	wake = radeon_fence_poll_locked(rdev);
313
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
314
	if (wake) {
315
		wake_up_all(&rdev->fence_drv.queue);
316
	}
317
}
318
 
319
int radeon_fence_driver_init(struct radeon_device *rdev)
320
{
321
	unsigned long irq_flags;
322
	int r;
323
 
324
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
325
	r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
326
	if (r) {
327
		DRM_ERROR("Fence failed to get a scratch register.");
328
		write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
329
		return r;
330
	}
331
	WREG32(rdev->fence_drv.scratch_reg, 0);
332
	atomic_set(&rdev->fence_drv.seq, 0);
333
	INIT_LIST_HEAD(&rdev->fence_drv.created);
334
	INIT_LIST_HEAD(&rdev->fence_drv.emited);
335
	INIT_LIST_HEAD(&rdev->fence_drv.signaled);
336
	rdev->fence_drv.count_timeout = 0;
337
	init_waitqueue_head(&rdev->fence_drv.queue);
338
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
339
	if (radeon_debugfs_fence_init(rdev)) {
340
		DRM_ERROR("Failed to register debugfs file for fence !\n");
341
	}
342
	return 0;
343
}
344
 
345
void radeon_fence_driver_fini(struct radeon_device *rdev)
346
{
347
	unsigned long irq_flags;
348
 
349
	wake_up_all(&rdev->fence_drv.queue);
350
	write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
351
	radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
352
	write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
353
	DRM_INFO("radeon: fence finalized\n");
354
}
355
 
356
 
357
/*
358
 * Fence debugfs
359
 */
360
#if defined(CONFIG_DEBUG_FS)
361
static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
362
{
363
	struct drm_info_node *node = (struct drm_info_node *)m->private;
364
	struct drm_device *dev = node->minor->dev;
365
	struct radeon_device *rdev = dev->dev_private;
366
	struct radeon_fence *fence;
367
 
368
	seq_printf(m, "Last signaled fence 0x%08X\n",
369
		   RREG32(rdev->fence_drv.scratch_reg));
370
	if (!list_empty(&rdev->fence_drv.emited)) {
371
		   fence = list_entry(rdev->fence_drv.emited.prev,
372
				      struct radeon_fence, list);
373
		   seq_printf(m, "Last emited fence %p with 0x%08X\n",
374
			      fence,  fence->seq);
375
	}
376
	return 0;
377
}
378
 
379
static struct drm_info_list radeon_debugfs_fence_list[] = {
380
	{"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
381
};
382
#endif
383
 
384
int radeon_debugfs_fence_init(struct radeon_device *rdev)
385
{
386
#if defined(CONFIG_DEBUG_FS)
387
	return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
388
#else
389
	return 0;
390
#endif
391
}