WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_encoders.c

Rev	Author	Line No.	Line
1125	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "drm_crtc_helper.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	extern int atom_debug;
		33
1268	serge	34	/* evil but including atombios.h is much worse */
		35	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
		36	struct drm_display_mode *mode);
		37
1321	serge	38	static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
		39	{
		40	struct drm_device *dev = encoder->dev;
		41	struct radeon_device *rdev = dev->dev_private;
		42	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		43	struct drm_encoder *clone_encoder;
		44	uint32_t index_mask = 0;
		45	int count;
		46
		47	/* DIG routing gets problematic */
		48	if (rdev->family >= CHIP_R600)
		49	return index_mask;
		50	/* LVDS/TV are too wacky */
		51	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
		52	return index_mask;
		53	/* DVO requires 2x ppll clocks depending on tmds chip */
		54	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
		55	return index_mask;
		56
		57	count = -1;
		58	list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
		59	struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
		60	count++;
		61
		62	if (clone_encoder == encoder)
		63	continue;
		64	if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
		65	continue;
		66	if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
		67	continue;
		68	else
		69	index_mask \|= (1 << count);
		70	}
		71	return index_mask;
		72	}
		73
		74	void radeon_setup_encoder_clones(struct drm_device *dev)
		75	{
		76	struct drm_encoder *encoder;
		77
		78	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		79	encoder->possible_clones = radeon_encoder_clones(encoder);
		80	}
		81	}
		82
1125	serge	83	uint32_t
		84	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
		85	{
		86	struct radeon_device *rdev = dev->dev_private;
		87	uint32_t ret = 0;
		88
		89	switch (supported_device) {
		90	case ATOM_DEVICE_CRT1_SUPPORT:
		91	case ATOM_DEVICE_TV1_SUPPORT:
		92	case ATOM_DEVICE_TV2_SUPPORT:
		93	case ATOM_DEVICE_CRT2_SUPPORT:
		94	case ATOM_DEVICE_CV_SUPPORT:
		95	switch (dac) {
		96	case 1: /* dac a */
		97	if ((rdev->family == CHIP_RS300) \|\|
		98	(rdev->family == CHIP_RS400) \|\|
		99	(rdev->family == CHIP_RS480))
		100	ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
		101	else if (ASIC_IS_AVIVO(rdev))
		102	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
		103	else
		104	ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
		105	break;
		106	case 2: /* dac b */
		107	if (ASIC_IS_AVIVO(rdev))
		108	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
		109	else {
		110	/*if (rdev->family == CHIP_R200)
		111	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		112	else*/
		113	ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
		114	}
		115	break;
		116	case 3: /* external dac */
		117	if (ASIC_IS_AVIVO(rdev))
		118	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
		119	else
		120	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		121	break;
		122	}
		123	break;
		124	case ATOM_DEVICE_LCD1_SUPPORT:
		125	if (ASIC_IS_AVIVO(rdev))
		126	ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
		127	else
		128	ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
		129	break;
		130	case ATOM_DEVICE_DFP1_SUPPORT:
		131	if ((rdev->family == CHIP_RS300) \|\|
		132	(rdev->family == CHIP_RS400) \|\|
		133	(rdev->family == CHIP_RS480))
		134	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		135	else if (ASIC_IS_AVIVO(rdev))
		136	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
		137	else
		138	ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
		139	break;
		140	case ATOM_DEVICE_LCD2_SUPPORT:
		141	case ATOM_DEVICE_DFP2_SUPPORT:
		142	if ((rdev->family == CHIP_RS600) \|\|
		143	(rdev->family == CHIP_RS690) \|\|
		144	(rdev->family == CHIP_RS740))
		145	ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
		146	else if (ASIC_IS_AVIVO(rdev))
		147	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
		148	else
		149	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		150	break;
		151	case ATOM_DEVICE_DFP3_SUPPORT:
		152	ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
		153	break;
		154	}
		155
		156	return ret;
		157	}
		158
1403	serge	159	static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
		160	{
		161	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		162	switch (radeon_encoder->encoder_id) {
		163	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		164	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		165	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		166	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		167	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		168	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		169	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		170	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		171	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		172	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		173	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		174	return true;
		175	default:
		176	return false;
		177	}
		178	}
1125	serge	179	void
		180	radeon_link_encoder_connector(struct drm_device *dev)
		181	{
		182	struct drm_connector *connector;
		183	struct radeon_connector *radeon_connector;
		184	struct drm_encoder *encoder;
		185	struct radeon_encoder *radeon_encoder;
		186
		187	/* walk the list and link encoders to connectors */
		188	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		189	radeon_connector = to_radeon_connector(connector);
		190	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		191	radeon_encoder = to_radeon_encoder(encoder);
		192	if (radeon_encoder->devices & radeon_connector->devices)
		193	drm_mode_connector_attach_encoder(connector, encoder);
		194	}
		195	}
		196	}
		197
1179	serge	198	void radeon_encoder_set_active_device(struct drm_encoder *encoder)
		199	{
		200	struct drm_device *dev = encoder->dev;
		201	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		202	struct drm_connector *connector;
		203
		204	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		205	if (connector->encoder == encoder) {
		206	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		207	radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
		208	DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
		209	radeon_encoder->active_device, radeon_encoder->devices,
		210	radeon_connector->devices, encoder->encoder_type);
		211	}
		212	}
		213	}
		214
1125	serge	215	static struct drm_connector *
		216	radeon_get_connector_for_encoder(struct drm_encoder *encoder)
		217	{
		218	struct drm_device *dev = encoder->dev;
		219	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		220	struct drm_connector *connector;
		221	struct radeon_connector *radeon_connector;
		222
		223	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		224	radeon_connector = to_radeon_connector(connector);
1403	serge	225	if (radeon_encoder->active_device & radeon_connector->devices)
1125	serge	226	return connector;
		227	}
		228	return NULL;
		229	}
		230
1430	serge	231	static struct radeon_connector_atom_dig *
		232	radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
		233	{
		234	struct drm_device *dev = encoder->dev;
		235	struct radeon_device *rdev = dev->dev_private;
		236	struct drm_connector *connector;
		237	struct radeon_connector *radeon_connector;
		238	struct radeon_connector_atom_dig *dig_connector;
		239
		240	if (!rdev->is_atom_bios)
		241	return NULL;
		242
		243	connector = radeon_get_connector_for_encoder(encoder);
		244	if (!connector)
		245	return NULL;
		246
		247	radeon_connector = to_radeon_connector(connector);
		248
		249	if (!radeon_connector->con_priv)
		250	return NULL;
		251
		252	dig_connector = radeon_connector->con_priv;
		253
		254	return dig_connector;
		255	}
		256
1125	serge	257	static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
		258	struct drm_display_mode *mode,
		259	struct drm_display_mode *adjusted_mode)
		260	{
		261	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1268	serge	262	struct drm_device *dev = encoder->dev;
		263	struct radeon_device *rdev = dev->dev_private;
1125	serge	264
1430	serge	265	/* adjust pm to upcoming mode change */
		266	radeon_pm_compute_clocks(rdev);
		267
1268	serge	268	/* set the active encoder to connector routing */
		269	radeon_encoder_set_active_device(encoder);
1125	serge	270	drm_mode_set_crtcinfo(adjusted_mode, 0);
		271
		272	/* hw bug */
		273	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
		274	&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
		275	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
		276
1321	serge	277	/* get the native mode for LVDS */
		278	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
		279	struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
		280	int mode_id = adjusted_mode->base.id;
		281	adjusted_mode = native_mode;
		282	if (!ASIC_IS_AVIVO(rdev)) {
		283	adjusted_mode->hdisplay = mode->hdisplay;
		284	adjusted_mode->vdisplay = mode->vdisplay;
1403	serge	285	adjusted_mode->crtc_hdisplay = mode->hdisplay;
		286	adjusted_mode->crtc_vdisplay = mode->vdisplay;
1321	serge	287	}
		288	adjusted_mode->base.id = mode_id;
		289	}
		290
		291	/* get the native mode for TV */
1268	serge	292	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
		293	struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
		294	if (tv_dac) {
		295	if (tv_dac->tv_std == TV_STD_NTSC \|\|
		296	tv_dac->tv_std == TV_STD_NTSC_J \|\|
		297	tv_dac->tv_std == TV_STD_PAL_M)
		298	radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
		299	else
		300	radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
		301	}
		302	}
		303
1321	serge	304	if (ASIC_IS_DCE3(rdev) &&
		305	(radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
		306	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		307	radeon_dp_set_link_config(connector, mode);
		308	}
		309
1125	serge	310	return true;
		311	}
		312
		313	static void
		314	atombios_dac_setup(struct drm_encoder *encoder, int action)
		315	{
		316	struct drm_device *dev = encoder->dev;
		317	struct radeon_device *rdev = dev->dev_private;
		318	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		319	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
		320	int index = 0, num = 0;
1179	serge	321	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
1125	serge	322	enum radeon_tv_std tv_std = TV_STD_NTSC;
		323
1179	serge	324	if (dac_info->tv_std)
		325	tv_std = dac_info->tv_std;
		326
1125	serge	327	memset(&args, 0, sizeof(args));
		328
		329	switch (radeon_encoder->encoder_id) {
		330	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		331	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		332	index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
		333	num = 1;
		334	break;
		335	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		336	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		337	index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
		338	num = 2;
		339	break;
		340	}
		341
		342	args.ucAction = action;
		343
1179	serge	344	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
1125	serge	345	args.ucDacStandard = ATOM_DAC1_PS2;
1179	serge	346	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	347	args.ucDacStandard = ATOM_DAC1_CV;
		348	else {
		349	switch (tv_std) {
		350	case TV_STD_PAL:
		351	case TV_STD_PAL_M:
		352	case TV_STD_SCART_PAL:
		353	case TV_STD_SECAM:
		354	case TV_STD_PAL_CN:
		355	args.ucDacStandard = ATOM_DAC1_PAL;
		356	break;
		357	case TV_STD_NTSC:
		358	case TV_STD_NTSC_J:
		359	case TV_STD_PAL_60:
		360	default:
		361	args.ucDacStandard = ATOM_DAC1_NTSC;
		362	break;
		363	}
		364	}
		365	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		366
		367	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		368
		369	}
		370
		371	static void
		372	atombios_tv_setup(struct drm_encoder *encoder, int action)
		373	{
		374	struct drm_device *dev = encoder->dev;
		375	struct radeon_device *rdev = dev->dev_private;
		376	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		377	TV_ENCODER_CONTROL_PS_ALLOCATION args;
		378	int index = 0;
1179	serge	379	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
1125	serge	380	enum radeon_tv_std tv_std = TV_STD_NTSC;
		381
1179	serge	382	if (dac_info->tv_std)
		383	tv_std = dac_info->tv_std;
		384
1125	serge	385	memset(&args, 0, sizeof(args));
		386
		387	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
		388
		389	args.sTVEncoder.ucAction = action;
		390
1179	serge	391	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	392	args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
		393	else {
		394	switch (tv_std) {
		395	case TV_STD_NTSC:
		396	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		397	break;
		398	case TV_STD_PAL:
		399	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
		400	break;
		401	case TV_STD_PAL_M:
		402	args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
		403	break;
		404	case TV_STD_PAL_60:
		405	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
		406	break;
		407	case TV_STD_NTSC_J:
		408	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
		409	break;
		410	case TV_STD_SCART_PAL:
		411	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
		412	break;
		413	case TV_STD_SECAM:
		414	args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
		415	break;
		416	case TV_STD_PAL_CN:
		417	args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
		418	break;
		419	default:
		420	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		421	break;
		422	}
		423	}
		424
		425	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		426
		427	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		428
		429	}
		430
		431	void
		432	atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
		433	{
		434	struct drm_device *dev = encoder->dev;
		435	struct radeon_device *rdev = dev->dev_private;
		436	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		437	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
		438	int index = 0;
		439
		440	memset(&args, 0, sizeof(args));
		441
		442	index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		443
		444	args.sXTmdsEncoder.ucEnable = action;
		445
		446	if (radeon_encoder->pixel_clock > 165000)
		447	args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
		448
		449	/if (pScrn->rgbBits == 8)/
		450	args.sXTmdsEncoder.ucMisc \|= (1 << 1);
		451
		452	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		453
		454	}
		455
		456	static void
		457	atombios_ddia_setup(struct drm_encoder *encoder, int action)
		458	{
		459	struct drm_device *dev = encoder->dev;
		460	struct radeon_device *rdev = dev->dev_private;
		461	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		462	DVO_ENCODER_CONTROL_PS_ALLOCATION args;
		463	int index = 0;
		464
		465	memset(&args, 0, sizeof(args));
		466
		467	index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		468
		469	args.sDVOEncoder.ucAction = action;
		470	args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		471
		472	if (radeon_encoder->pixel_clock > 165000)
		473	args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
		474
		475	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		476
		477	}
		478
		479	union lvds_encoder_control {
		480	LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
		481	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
		482	};
		483
1321	serge	484	void
1125	serge	485	atombios_digital_setup(struct drm_encoder *encoder, int action)
		486	{
		487	struct drm_device *dev = encoder->dev;
		488	struct radeon_device *rdev = dev->dev_private;
		489	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1430	serge	490	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		491	struct radeon_connector_atom_dig *dig_connector =
		492	radeon_get_atom_connector_priv_from_encoder(encoder);
1125	serge	493	union lvds_encoder_control args;
		494	int index = 0;
1403	serge	495	int hdmi_detected = 0;
1125	serge	496	uint8_t frev, crev;
		497
1430	serge	498	if (!dig \|\| !dig_connector)
1125	serge	499	return;
		500
1430	serge	501	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1403	serge	502	hdmi_detected = 1;
		503
1125	serge	504	memset(&args, 0, sizeof(args));
		505
		506	switch (radeon_encoder->encoder_id) {
		507	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		508	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		509	break;
		510	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		511	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		512	index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
		513	break;
		514	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		515	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		516	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		517	else
		518	index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
		519	break;
		520	}
		521
		522	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		523
		524	switch (frev) {
		525	case 1:
		526	case 2:
		527	switch (crev) {
		528	case 1:
		529	args.v1.ucMisc = 0;
		530	args.v1.ucAction = action;
1403	serge	531	if (hdmi_detected)
1125	serge	532	args.v1.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		533	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		534	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1403	serge	535	if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
1125	serge	536	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
1403	serge	537	if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
1125	serge	538	args.v1.ucMisc \|= (1 << 1);
		539	} else {
		540	if (dig_connector->linkb)
		541	args.v1.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		542	if (radeon_encoder->pixel_clock > 165000)
		543	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		544	/if (pScrn->rgbBits == 8) /
		545	args.v1.ucMisc \|= (1 << 1);
		546	}
		547	break;
		548	case 2:
		549	case 3:
		550	args.v2.ucMisc = 0;
		551	args.v2.ucAction = action;
		552	if (crev == 3) {
		553	if (dig->coherent_mode)
		554	args.v2.ucMisc \|= PANEL_ENCODER_MISC_COHERENT;
		555	}
1403	serge	556	if (hdmi_detected)
1125	serge	557	args.v2.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		558	args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		559	args.v2.ucTruncate = 0;
		560	args.v2.ucSpatial = 0;
		561	args.v2.ucTemporal = 0;
		562	args.v2.ucFRC = 0;
		563	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1403	serge	564	if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
1125	serge	565	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
1403	serge	566	if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
1125	serge	567	args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
1403	serge	568	if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
1125	serge	569	args.v2.ucSpatial \|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
		570	}
1403	serge	571	if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
1125	serge	572	args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
1403	serge	573	if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
1125	serge	574	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
1403	serge	575	if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
1125	serge	576	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_LEVEL_4;
		577	}
		578	} else {
		579	if (dig_connector->linkb)
		580	args.v2.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		581	if (radeon_encoder->pixel_clock > 165000)
		582	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		583	}
		584	break;
		585	default:
		586	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		587	break;
		588	}
		589	break;
		590	default:
		591	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		592	break;
		593	}
		594
		595	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1403	serge	596	r600_hdmi_enable(encoder, hdmi_detected);
1125	serge	597	}
		598
		599	int
		600	atombios_get_encoder_mode(struct drm_encoder *encoder)
		601	{
		602	struct drm_connector *connector;
		603	struct radeon_connector *radeon_connector;
1430	serge	604	struct radeon_connector_atom_dig *dig_connector;
1125	serge	605
		606	connector = radeon_get_connector_for_encoder(encoder);
		607	if (!connector)
		608	return 0;
		609
		610	radeon_connector = to_radeon_connector(connector);
		611
		612	switch (connector->connector_type) {
		613	case DRM_MODE_CONNECTOR_DVII:
1179	serge	614	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
1268	serge	615	if (drm_detect_hdmi_monitor(radeon_connector->edid))
1125	serge	616	return ATOM_ENCODER_MODE_HDMI;
		617	else if (radeon_connector->use_digital)
		618	return ATOM_ENCODER_MODE_DVI;
		619	else
		620	return ATOM_ENCODER_MODE_CRT;
		621	break;
		622	case DRM_MODE_CONNECTOR_DVID:
		623	case DRM_MODE_CONNECTOR_HDMIA:
		624	default:
1268	serge	625	if (drm_detect_hdmi_monitor(radeon_connector->edid))
1125	serge	626	return ATOM_ENCODER_MODE_HDMI;
		627	else
		628	return ATOM_ENCODER_MODE_DVI;
		629	break;
		630	case DRM_MODE_CONNECTOR_LVDS:
		631	return ATOM_ENCODER_MODE_LVDS;
		632	break;
		633	case DRM_MODE_CONNECTOR_DisplayPort:
1403	serge	634	case DRM_MODE_CONNECTOR_eDP:
1430	serge	635	dig_connector = radeon_connector->con_priv;
		636	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) \|\|
		637	(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
1125	serge	638	return ATOM_ENCODER_MODE_DP;
1321	serge	639	else if (drm_detect_hdmi_monitor(radeon_connector->edid))
1125	serge	640	return ATOM_ENCODER_MODE_HDMI;
		641	else
		642	return ATOM_ENCODER_MODE_DVI;
		643	break;
1403	serge	644	case DRM_MODE_CONNECTOR_DVIA:
		645	case DRM_MODE_CONNECTOR_VGA:
1125	serge	646	return ATOM_ENCODER_MODE_CRT;
		647	break;
1403	serge	648	case DRM_MODE_CONNECTOR_Composite:
		649	case DRM_MODE_CONNECTOR_SVIDEO:
		650	case DRM_MODE_CONNECTOR_9PinDIN:
1125	serge	651	/* fix me */
		652	return ATOM_ENCODER_MODE_TV;
		653	/return ATOM_ENCODER_MODE_CV;/
		654	break;
		655	}
		656	}
		657
1321	serge	658	/*
		659	* DIG Encoder/Transmitter Setup
		660	*
		661	* DCE 3.0/3.1
		662	* - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
		663	* Supports up to 3 digital outputs
		664	* - 2 DIG encoder blocks.
		665	* DIG1 can drive UNIPHY link A or link B
		666	* DIG2 can drive UNIPHY link B or LVTMA
		667	*
		668	* DCE 3.2
		669	* - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
		670	* Supports up to 5 digital outputs
		671	* - 2 DIG encoder blocks.
		672	* DIG1/2 can drive UNIPHY0/1/2 link A or link B
		673	*
1430	serge	674	* DCE 4.0
		675	* - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
		676	* Supports up to 6 digital outputs
		677	* - 6 DIG encoder blocks.
		678	* - DIG to PHY mapping is hardcoded
		679	* DIG1 drives UNIPHY0 link A, A+B
		680	* DIG2 drives UNIPHY0 link B
		681	* DIG3 drives UNIPHY1 link A, A+B
		682	* DIG4 drives UNIPHY1 link B
		683	* DIG5 drives UNIPHY2 link A, A+B
		684	* DIG6 drives UNIPHY2 link B
		685	*
1321	serge	686	* Routing
		687	* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
		688	* Examples:
		689	* crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
		690	* crtc1 -> dig1 -> UNIPHY0 link B -> DP
		691	* crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
		692	* crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
		693	*/
1430	serge	694
		695	union dig_encoder_control {
		696	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
		697	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
		698	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
		699	};
		700
		701	void
1125	serge	702	atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
		703	{
		704	struct drm_device *dev = encoder->dev;
		705	struct radeon_device *rdev = dev->dev_private;
		706	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1430	serge	707	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		708	struct radeon_connector_atom_dig *dig_connector =
		709	radeon_get_atom_connector_priv_from_encoder(encoder);
		710	union dig_encoder_control args;
1125	serge	711	int index = 0, num = 0;
		712	uint8_t frev, crev;
		713
1430	serge	714	if (!dig \|\| !dig_connector)
1125	serge	715	return;
		716
		717	memset(&args, 0, sizeof(args));
		718
1430	serge	719	if (ASIC_IS_DCE4(rdev))
		720	index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
		721	else {
1403	serge	722	if (dig->dig_encoder)
1125	serge	723	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
		724	else
		725	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
1430	serge	726	}
1403	serge	727	num = dig->dig_encoder + 1;
1125	serge	728
		729	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		730
1430	serge	731	args.v1.ucAction = action;
		732	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		733	args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
1125	serge	734
1430	serge	735	if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
		736	if (dig_connector->dp_clock == 270000)
		737	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
		738	args.v1.ucLaneNum = dig_connector->dp_lane_count;
		739	} else if (radeon_encoder->pixel_clock > 165000)
		740	args.v1.ucLaneNum = 8;
		741	else
		742	args.v1.ucLaneNum = 4;
		743
		744	if (ASIC_IS_DCE4(rdev)) {
		745	args.v3.acConfig.ucDigSel = dig->dig_encoder;
		746	args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
		747	} else {
1125	serge	748	switch (radeon_encoder->encoder_id) {
		749	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1430	serge	750	args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
1125	serge	751	break;
		752	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1430	serge	753	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		754	args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
1125	serge	755	break;
		756	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1430	serge	757	args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
1125	serge	758	break;
		759	}
		760	if (dig_connector->linkb)
1430	serge	761	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_LINKB;
1125	serge	762	else
1430	serge	763	args.v1.ucConfig \|= ATOM_ENCODER_CONFIG_LINKA;
		764	}
1125	serge	765
		766	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		767
		768	}
		769
		770	union dig_transmitter_control {
		771	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
		772	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1430	serge	773	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1125	serge	774	};
		775
1321	serge	776	void
		777	atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1125	serge	778	{
		779	struct drm_device *dev = encoder->dev;
		780	struct radeon_device *rdev = dev->dev_private;
		781	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1430	serge	782	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		783	struct radeon_connector_atom_dig *dig_connector =
		784	radeon_get_atom_connector_priv_from_encoder(encoder);
		785	struct drm_connector *connector;
		786	struct radeon_connector *radeon_connector;
1125	serge	787	union dig_transmitter_control args;
		788	int index = 0, num = 0;
		789	uint8_t frev, crev;
1321	serge	790	bool is_dp = false;
1430	serge	791	int pll_id = 0;
1125	serge	792
1430	serge	793	if (!dig \|\| !dig_connector)
1125	serge	794	return;
		795
1430	serge	796	connector = radeon_get_connector_for_encoder(encoder);
1125	serge	797	radeon_connector = to_radeon_connector(connector);
		798
1321	serge	799	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
		800	is_dp = true;
		801
1125	serge	802	memset(&args, 0, sizeof(args));
		803
1430	serge	804	if (ASIC_IS_DCE32(rdev) \|\| ASIC_IS_DCE4(rdev))
1125	serge	805	index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
		806	else {
		807	switch (radeon_encoder->encoder_id) {
		808	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		809	index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
		810	break;
		811	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		812	index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
		813	break;
		814	}
		815	}
		816
		817	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		818
		819	args.v1.ucAction = action;
1268	serge	820	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
		821	args.v1.usInitInfo = radeon_connector->connector_object_id;
1321	serge	822	} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
		823	args.v1.asMode.ucLaneSel = lane_num;
		824	args.v1.asMode.ucLaneSet = lane_set;
1125	serge	825	} else {
1321	serge	826	if (is_dp)
		827	args.v1.usPixelClock =
		828	cpu_to_le16(dig_connector->dp_clock / 10);
		829	else if (radeon_encoder->pixel_clock > 165000)
1268	serge	830	args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
		831	else
		832	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1125	serge	833	}
1430	serge	834	if (ASIC_IS_DCE4(rdev)) {
		835	if (is_dp)
		836	args.v3.ucLaneNum = dig_connector->dp_lane_count;
		837	else if (radeon_encoder->pixel_clock > 165000)
		838	args.v3.ucLaneNum = 8;
		839	else
		840	args.v3.ucLaneNum = 4;
		841
		842	if (dig_connector->linkb) {
		843	args.v3.acConfig.ucLinkSel = 1;
		844	args.v3.acConfig.ucEncoderSel = 1;
		845	}
		846
		847	/* Select the PLL for the PHY
		848	* DP PHY should be clocked from external src if there is
		849	* one.
		850	*/
		851	if (encoder->crtc) {
		852	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		853	pll_id = radeon_crtc->pll_id;
		854	}
		855	if (is_dp && rdev->clock.dp_extclk)
		856	args.v3.acConfig.ucRefClkSource = 2; /* external src */
		857	else
		858	args.v3.acConfig.ucRefClkSource = pll_id;
		859
		860	switch (radeon_encoder->encoder_id) {
		861	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		862	args.v3.acConfig.ucTransmitterSel = 0;
		863	num = 0;
		864	break;
		865	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		866	args.v3.acConfig.ucTransmitterSel = 1;
		867	num = 1;
		868	break;
		869	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		870	args.v3.acConfig.ucTransmitterSel = 2;
		871	num = 2;
		872	break;
		873	}
		874
		875	if (is_dp)
		876	args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
		877	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		878	if (dig->coherent_mode)
		879	args.v3.acConfig.fCoherentMode = 1;
		880	}
		881	} else if (ASIC_IS_DCE32(rdev)) {
1403	serge	882	if (dig->dig_encoder == 1)
1125	serge	883	args.v2.acConfig.ucEncoderSel = 1;
1321	serge	884	if (dig_connector->linkb)
		885	args.v2.acConfig.ucLinkSel = 1;
1125	serge	886
		887	switch (radeon_encoder->encoder_id) {
		888	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		889	args.v2.acConfig.ucTransmitterSel = 0;
		890	num = 0;
		891	break;
		892	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		893	args.v2.acConfig.ucTransmitterSel = 1;
		894	num = 1;
		895	break;
		896	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		897	args.v2.acConfig.ucTransmitterSel = 2;
		898	num = 2;
		899	break;
		900	}
		901
1321	serge	902	if (is_dp)
		903	args.v2.acConfig.fCoherentMode = 1;
		904	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1125	serge	905	if (dig->coherent_mode)
		906	args.v2.acConfig.fCoherentMode = 1;
		907	}
		908	} else {
		909	args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
		910
1403	serge	911	if (dig->dig_encoder)
1321	serge	912	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
		913	else
1125	serge	914	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1403	serge	915
		916	switch (radeon_encoder->encoder_id) {
		917	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1125	serge	918	if (rdev->flags & RADEON_IS_IGP) {
		919	if (radeon_encoder->pixel_clock > 165000) {
		920	if (dig_connector->igp_lane_info & 0x3)
		921	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
		922	else if (dig_connector->igp_lane_info & 0xc)
		923	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
		924	} else {
		925	if (dig_connector->igp_lane_info & 0x1)
		926	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		927	else if (dig_connector->igp_lane_info & 0x2)
		928	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
		929	else if (dig_connector->igp_lane_info & 0x4)
		930	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
		931	else if (dig_connector->igp_lane_info & 0x8)
		932	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
		933	}
		934	}
		935	break;
1321	serge	936	}
		937
1125	serge	938	if (radeon_encoder->pixel_clock > 165000)
1321	serge	939	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
		940
1125	serge	941	if (dig_connector->linkb)
1321	serge	942	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKB;
1125	serge	943	else
1321	serge	944	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA;
1125	serge	945
1321	serge	946	if (is_dp)
		947	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_COHERENT;
		948	else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1125	serge	949	if (dig->coherent_mode)
		950	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_COHERENT;
		951	}
		952	}
		953
		954	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		955	}
		956
		957	static void
		958	atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
		959	{
		960	struct drm_device *dev = encoder->dev;
		961	struct radeon_device *rdev = dev->dev_private;
		962	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		963	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		964	ENABLE_YUV_PS_ALLOCATION args;
		965	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
		966	uint32_t temp, reg;
		967
		968	memset(&args, 0, sizeof(args));
		969
		970	if (rdev->family >= CHIP_R600)
		971	reg = R600_BIOS_3_SCRATCH;
		972	else
		973	reg = RADEON_BIOS_3_SCRATCH;
		974
		975	/* XXX: fix up scratch reg handling */
		976	temp = RREG32(reg);
1179	serge	977	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	978	WREG32(reg, (ATOM_S3_TV1_ACTIVE \|
		979	(radeon_crtc->crtc_id << 18)));
1179	serge	980	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	981	WREG32(reg, (ATOM_S3_CV_ACTIVE \| (radeon_crtc->crtc_id << 24)));
		982	else
		983	WREG32(reg, 0);
		984
		985	if (enable)
		986	args.ucEnable = ATOM_ENABLE;
		987	args.ucCRTC = radeon_crtc->crtc_id;
		988
		989	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		990
		991	WREG32(reg, temp);
		992	}
		993
		994	static void
		995	radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
		996	{
		997	struct drm_device *dev = encoder->dev;
		998	struct radeon_device *rdev = dev->dev_private;
		999	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1000	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
		1001	int index = 0;
		1002	bool is_dig = false;
		1003
		1004	memset(&args, 0, sizeof(args));
		1005
1179	serge	1006	DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
		1007	radeon_encoder->encoder_id, mode, radeon_encoder->devices,
		1008	radeon_encoder->active_device);
1125	serge	1009	switch (radeon_encoder->encoder_id) {
		1010	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1011	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1012	index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
		1013	break;
		1014	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1015	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1016	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1017	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1018	is_dig = true;
		1019	break;
		1020	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1021	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1022	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1023	index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
		1024	break;
		1025	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1026	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		1027	break;
		1028	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1029	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		1030	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		1031	else
		1032	index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
		1033	break;
		1034	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1035	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1268	serge	1036	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1037	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1268	serge	1038	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1039	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		1040	else
		1041	index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
		1042	break;
		1043	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1044	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1268	serge	1045	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1046	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1268	serge	1047	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1048	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		1049	else
		1050	index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
		1051	break;
		1052	}
		1053
		1054	if (is_dig) {
		1055	switch (mode) {
		1056	case DRM_MODE_DPMS_ON:
1321	serge	1057	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
		1058	{
		1059	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
		1060	dp_link_train(encoder, connector);
		1061	}
1125	serge	1062	break;
		1063	case DRM_MODE_DPMS_STANDBY:
		1064	case DRM_MODE_DPMS_SUSPEND:
		1065	case DRM_MODE_DPMS_OFF:
1321	serge	1066	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1125	serge	1067	break;
		1068	}
		1069	} else {
		1070	switch (mode) {
		1071	case DRM_MODE_DPMS_ON:
		1072	args.ucAction = ATOM_ENABLE;
		1073	break;
		1074	case DRM_MODE_DPMS_STANDBY:
		1075	case DRM_MODE_DPMS_SUSPEND:
		1076	case DRM_MODE_DPMS_OFF:
		1077	args.ucAction = ATOM_DISABLE;
		1078	break;
		1079	}
		1080	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1081	}
		1082	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	1083
		1084	/* adjust pm to dpms change */
		1085	radeon_pm_compute_clocks(rdev);
1125	serge	1086	}
		1087
1430	serge	1088	union crtc_source_param {
1125	serge	1089	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
		1090	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
		1091	};
		1092
		1093	static void
		1094	atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
		1095	{
		1096	struct drm_device *dev = encoder->dev;
		1097	struct radeon_device *rdev = dev->dev_private;
		1098	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1099	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1430	serge	1100	union crtc_source_param args;
1125	serge	1101	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
		1102	uint8_t frev, crev;
1403	serge	1103	struct radeon_encoder_atom_dig *dig;
1125	serge	1104
		1105	memset(&args, 0, sizeof(args));
		1106
		1107	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		1108
		1109	switch (frev) {
		1110	case 1:
		1111	switch (crev) {
		1112	case 1:
		1113	default:
		1114	if (ASIC_IS_AVIVO(rdev))
		1115	args.v1.ucCRTC = radeon_crtc->crtc_id;
		1116	else {
		1117	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
		1118	args.v1.ucCRTC = radeon_crtc->crtc_id;
		1119	} else {
		1120	args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
		1121	}
		1122	}
		1123	switch (radeon_encoder->encoder_id) {
		1124	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1125	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1126	args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
		1127	break;
		1128	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1129	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1130	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
		1131	args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
		1132	else
		1133	args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
		1134	break;
		1135	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1136	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1137	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1138	args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
		1139	break;
		1140	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1141	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1179	serge	1142	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1143	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1179	serge	1144	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1145	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1146	else
		1147	args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
		1148	break;
		1149	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1150	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1179	serge	1151	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1152	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1179	serge	1153	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1154	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1155	else
		1156	args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
		1157	break;
		1158	}
		1159	break;
		1160	case 2:
		1161	args.v2.ucCRTC = radeon_crtc->crtc_id;
		1162	args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
		1163	switch (radeon_encoder->encoder_id) {
		1164	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1165	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1166	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1403	serge	1167	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1168	dig = radeon_encoder->enc_priv;
1430	serge	1169	switch (dig->dig_encoder) {
		1170	case 0:
		1171	args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
		1172	break;
		1173	case 1:
1125	serge	1174	args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1430	serge	1175	break;
		1176	case 2:
		1177	args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
		1178	break;
		1179	case 3:
		1180	args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
		1181	break;
		1182	case 4:
		1183	args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
		1184	break;
		1185	case 5:
		1186	args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
		1187	break;
		1188	}
1125	serge	1189	break;
		1190	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1191	args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
		1192	break;
		1193	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1179	serge	1194	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1195	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1179	serge	1196	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1197	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1198	else
		1199	args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
		1200	break;
		1201	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1179	serge	1202	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1203	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1179	serge	1204	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1205	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1206	else
		1207	args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
		1208	break;
		1209	}
		1210	break;
		1211	}
		1212	break;
		1213	default:
		1214	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
		1215	break;
		1216	}
		1217
		1218	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1219	}
		1220
		1221	static void
		1222	atombios_apply_encoder_quirks(struct drm_encoder *encoder,
		1223	struct drm_display_mode *mode)
		1224	{
		1225	struct drm_device *dev = encoder->dev;
		1226	struct radeon_device *rdev = dev->dev_private;
		1227	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1228	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1229
		1230	/* Funky macbooks */
		1231	if ((dev->pdev->device == 0x71C5) &&
		1232	(dev->pdev->subsystem_vendor == 0x106b) &&
		1233	(dev->pdev->subsystem_device == 0x0080)) {
		1234	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1235	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
		1236
		1237	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
		1238	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
		1239
		1240	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
		1241	}
		1242	}
		1243
		1244	/* set scaler clears this on some chips */
1430	serge	1245	/* XXX check DCE4 */
1268	serge	1246	if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1125	serge	1247	if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1268	serge	1248	WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
		1249	AVIVO_D1MODE_INTERLEAVE_EN);
		1250	}
1125	serge	1251	}
		1252
1403	serge	1253	static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
		1254	{
		1255	struct drm_device *dev = encoder->dev;
		1256	struct radeon_device *rdev = dev->dev_private;
		1257	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1258	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1259	struct drm_encoder *test_encoder;
		1260	struct radeon_encoder_atom_dig *dig;
		1261	uint32_t dig_enc_in_use = 0;
1430	serge	1262
		1263	if (ASIC_IS_DCE4(rdev)) {
		1264	struct radeon_connector_atom_dig *dig_connector =
		1265	radeon_get_atom_connector_priv_from_encoder(encoder);
		1266
		1267	switch (radeon_encoder->encoder_id) {
		1268	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1269	if (dig_connector->linkb)
		1270	return 1;
		1271	else
		1272	return 0;
		1273	break;
		1274	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1275	if (dig_connector->linkb)
		1276	return 3;
		1277	else
		1278	return 2;
		1279	break;
		1280	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1281	if (dig_connector->linkb)
		1282	return 5;
		1283	else
		1284	return 4;
		1285	break;
		1286	}
		1287	}
		1288
1403	serge	1289	/* on DCE32 and encoder can driver any block so just crtc id */
		1290	if (ASIC_IS_DCE32(rdev)) {
		1291	return radeon_crtc->crtc_id;
		1292	}
		1293
		1294	/* on DCE3 - LVTMA can only be driven by DIGB */
		1295	list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
		1296	struct radeon_encoder *radeon_test_encoder;
		1297
		1298	if (encoder == test_encoder)
		1299	continue;
		1300
		1301	if (!radeon_encoder_is_digital(test_encoder))
		1302	continue;
		1303
		1304	radeon_test_encoder = to_radeon_encoder(test_encoder);
		1305	dig = radeon_test_encoder->enc_priv;
		1306
		1307	if (dig->dig_encoder >= 0)
		1308	dig_enc_in_use \|= (1 << dig->dig_encoder);
		1309	}
		1310
		1311	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
		1312	if (dig_enc_in_use & 0x2)
		1313	DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
		1314	return 1;
		1315	}
		1316	if (!(dig_enc_in_use & 1))
		1317	return 0;
		1318	return 1;
		1319	}
		1320
1125	serge	1321	static void
		1322	radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
		1323	struct drm_display_mode *mode,
		1324	struct drm_display_mode *adjusted_mode)
		1325	{
		1326	struct drm_device *dev = encoder->dev;
		1327	struct radeon_device *rdev = dev->dev_private;
		1328	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1329	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1330
1321	serge	1331	if (radeon_encoder->active_device &
		1332	(ATOM_DEVICE_DFP_SUPPORT \| ATOM_DEVICE_LCD_SUPPORT)) {
1403	serge	1333	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		1334	if (dig)
		1335	dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1125	serge	1336	}
		1337	radeon_encoder->pixel_clock = adjusted_mode->clock;
		1338
		1339	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1340	atombios_set_encoder_crtc_source(encoder);
		1341
		1342	if (ASIC_IS_AVIVO(rdev)) {
1179	serge	1343	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT \| ATOM_DEVICE_TV_SUPPORT))
1125	serge	1344	atombios_yuv_setup(encoder, true);
		1345	else
		1346	atombios_yuv_setup(encoder, false);
		1347	}
		1348
		1349	switch (radeon_encoder->encoder_id) {
		1350	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1351	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1352	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1353	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1354	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		1355	break;
		1356	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1357	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1358	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1359	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1430	serge	1360	if (ASIC_IS_DCE4(rdev)) {
		1361	/* disable the transmitter */
		1362	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
		1363	/* setup and enable the encoder */
		1364	atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
		1365
		1366	/* init and enable the transmitter */
		1367	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
		1368	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
		1369	} else {
1125	serge	1370	/* disable the encoder and transmitter */
1321	serge	1371	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1125	serge	1372	atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
		1373
		1374	/* setup and enable the encoder and transmitter */
		1375	atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1321	serge	1376	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
		1377	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
		1378	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1430	serge	1379	}
1125	serge	1380	break;
		1381	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1382	atombios_ddia_setup(encoder, ATOM_ENABLE);
		1383	break;
		1384	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1385	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1386	atombios_external_tmds_setup(encoder, ATOM_ENABLE);
		1387	break;
		1388	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1389	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1390	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1391	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1392	atombios_dac_setup(encoder, ATOM_ENABLE);
1179	serge	1393	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
1125	serge	1394	atombios_tv_setup(encoder, ATOM_ENABLE);
		1395	break;
		1396	}
		1397	atombios_apply_encoder_quirks(encoder, adjusted_mode);
1403	serge	1398
1430	serge	1399	/* XXX */
		1400	if (!ASIC_IS_DCE4(rdev))
1403	serge	1401	r600_hdmi_setmode(encoder, adjusted_mode);
1125	serge	1402	}
		1403
		1404	static bool
1179	serge	1405	atombios_dac_load_detect(struct drm_encoder encoder, struct drm_connector connector)
1125	serge	1406	{
		1407	struct drm_device *dev = encoder->dev;
		1408	struct radeon_device *rdev = dev->dev_private;
		1409	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	1410	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1125	serge	1411
		1412	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \|
		1413	ATOM_DEVICE_CV_SUPPORT \|
		1414	ATOM_DEVICE_CRT_SUPPORT)) {
		1415	DAC_LOAD_DETECTION_PS_ALLOCATION args;
		1416	int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
		1417	uint8_t frev, crev;
		1418
		1419	memset(&args, 0, sizeof(args));
		1420
		1421	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		1422
		1423	args.sDacload.ucMisc = 0;
		1424
		1425	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) \|\|
		1426	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
		1427	args.sDacload.ucDacType = ATOM_DAC_A;
		1428	else
		1429	args.sDacload.ucDacType = ATOM_DAC_B;
		1430
1179	serge	1431	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1125	serge	1432	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1179	serge	1433	else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1125	serge	1434	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1179	serge	1435	else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1125	serge	1436	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
		1437	if (crev >= 3)
		1438	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1179	serge	1439	} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1125	serge	1440	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
		1441	if (crev >= 3)
		1442	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
		1443	}
		1444
		1445	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1446
		1447	return true;
		1448	} else
		1449	return false;
		1450	}
		1451
		1452	static enum drm_connector_status
		1453	radeon_atom_dac_detect(struct drm_encoder encoder, struct drm_connector connector)
		1454	{
		1455	struct drm_device *dev = encoder->dev;
		1456	struct radeon_device *rdev = dev->dev_private;
		1457	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	1458	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1125	serge	1459	uint32_t bios_0_scratch;
		1460
1179	serge	1461	if (!atombios_dac_load_detect(encoder, connector)) {
1125	serge	1462	DRM_DEBUG("detect returned false \n");
		1463	return connector_status_unknown;
		1464	}
		1465
		1466	if (rdev->family >= CHIP_R600)
		1467	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1468	else
		1469	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1470
1179	serge	1471	DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
		1472	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1125	serge	1473	if (bios_0_scratch & ATOM_S0_CRT1_MASK)
		1474	return connector_status_connected;
1179	serge	1475	}
		1476	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1125	serge	1477	if (bios_0_scratch & ATOM_S0_CRT2_MASK)
		1478	return connector_status_connected;
1179	serge	1479	}
		1480	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1125	serge	1481	if (bios_0_scratch & (ATOM_S0_CV_MASK\|ATOM_S0_CV_MASK_A))
		1482	return connector_status_connected;
1179	serge	1483	}
		1484	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1125	serge	1485	if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE \| ATOM_S0_TV1_COMPOSITE_A))
		1486	return connector_status_connected; /* CTV */
		1487	else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO \| ATOM_S0_TV1_SVIDEO_A))
		1488	return connector_status_connected; /* STV */
		1489	}
		1490	return connector_status_disconnected;
		1491	}
		1492
		1493	static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
		1494	{
		1495	radeon_atom_output_lock(encoder, true);
		1496	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
		1497	}
		1498
		1499	static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
		1500	{
		1501	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
		1502	radeon_atom_output_lock(encoder, false);
		1503	}
		1504
1179	serge	1505	static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
		1506	{
		1507	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1403	serge	1508	struct radeon_encoder_atom_dig *dig;
1179	serge	1509	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1403	serge	1510
		1511	if (radeon_encoder_is_digital(encoder)) {
		1512	dig = radeon_encoder->enc_priv;
		1513	dig->dig_encoder = -1;
		1514	}
1179	serge	1515	radeon_encoder->active_device = 0;
		1516	}
		1517
1125	serge	1518	static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
		1519	.dpms = radeon_atom_encoder_dpms,
		1520	.mode_fixup = radeon_atom_mode_fixup,
		1521	.prepare = radeon_atom_encoder_prepare,
		1522	.mode_set = radeon_atom_encoder_mode_set,
		1523	.commit = radeon_atom_encoder_commit,
1179	serge	1524	.disable = radeon_atom_encoder_disable,
1125	serge	1525	/* no detect for TMDS/LVDS yet */
		1526	};
		1527
		1528	static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
		1529	.dpms = radeon_atom_encoder_dpms,
		1530	.mode_fixup = radeon_atom_mode_fixup,
		1531	.prepare = radeon_atom_encoder_prepare,
		1532	.mode_set = radeon_atom_encoder_mode_set,
		1533	.commit = radeon_atom_encoder_commit,
		1534	.detect = radeon_atom_dac_detect,
		1535	};
		1536
		1537	void radeon_enc_destroy(struct drm_encoder *encoder)
		1538	{
		1539	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1540	kfree(radeon_encoder->enc_priv);
		1541	drm_encoder_cleanup(encoder);
		1542	kfree(radeon_encoder);
		1543	}
		1544
		1545	static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
		1546	.destroy = radeon_enc_destroy,
		1547	};
		1548
1179	serge	1549	struct radeon_encoder_atom_dac *
		1550	radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
		1551	{
		1552	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
		1553
		1554	if (!dac)
		1555	return NULL;
		1556
		1557	dac->tv_std = TV_STD_NTSC;
		1558	return dac;
		1559	}
		1560
1125	serge	1561	struct radeon_encoder_atom_dig *
		1562	radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
		1563	{
		1564	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1565
		1566	if (!dig)
		1567	return NULL;
		1568
		1569	/* coherent mode by default */
		1570	dig->coherent_mode = true;
1403	serge	1571	dig->dig_encoder = -1;
1125	serge	1572
		1573	return dig;
		1574	}
		1575
		1576	void
		1577	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
		1578	{
1221	serge	1579	struct radeon_device *rdev = dev->dev_private;
1125	serge	1580	struct drm_encoder *encoder;
		1581	struct radeon_encoder *radeon_encoder;
		1582
		1583	/* see if we already added it */
		1584	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1585	radeon_encoder = to_radeon_encoder(encoder);
		1586	if (radeon_encoder->encoder_id == encoder_id) {
		1587	radeon_encoder->devices \|= supported_device;
		1588	return;
		1589	}
		1590
		1591	}
		1592
		1593	/* add a new one */
		1594	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1595	if (!radeon_encoder)
		1596	return;
		1597
		1598	encoder = &radeon_encoder->base;
1430	serge	1599	switch (rdev->num_crtc) {
		1600	case 1:
1221	serge	1601	encoder->possible_crtcs = 0x1;
1430	serge	1602	break;
		1603	case 2:
		1604	default:
1125	serge	1605	encoder->possible_crtcs = 0x3;
1430	serge	1606	break;
		1607	case 6:
		1608	encoder->possible_crtcs = 0x3f;
		1609	break;
		1610	}
1125	serge	1611
		1612	radeon_encoder->enc_priv = NULL;
		1613
		1614	radeon_encoder->encoder_id = encoder_id;
		1615	radeon_encoder->devices = supported_device;
1179	serge	1616	radeon_encoder->rmx_type = RMX_OFF;
1125	serge	1617
		1618	switch (radeon_encoder->encoder_id) {
		1619	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1620	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1621	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1622	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1623	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1624	radeon_encoder->rmx_type = RMX_FULL;
		1625	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1626	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1627	} else {
		1628	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1629	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		1630	}
		1631	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		1632	break;
		1633	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1634	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
		1635	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		1636	break;
		1637	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1638	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1639	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1640	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1179	serge	1641	radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1125	serge	1642	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		1643	break;
		1644	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1645	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1646	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1647	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1648	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1649	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1650	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1179	serge	1651	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1652	radeon_encoder->rmx_type = RMX_FULL;
		1653	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1654	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1655	} else {
1125	serge	1656	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1657	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1179	serge	1658	}
1125	serge	1659	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		1660	break;
		1661	}
1403	serge	1662
		1663	r600_hdmi_init(encoder);
1125	serge	1664	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_encoders.c – Rev 1430