WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_display.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
1123	serge	28	#include "radeon.h"
		29
		30	#include "atom.h"
1963	serge	31	#include
1123	serge	32
6104	serge	33	#include
2997	Serge	34	#include
6104	serge	35	#include
2997	Serge	36	#include
1123	serge	37
6104	serge	38	#include
5078	serge	39
1123	serge	40	static void avivo_crtc_load_lut(struct drm_crtc *crtc)
		41	{
		42	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		43	struct drm_device *dev = crtc->dev;
		44	struct radeon_device *rdev = dev->dev_private;
		45	int i;
		46
1963	serge	47	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1123	serge	48	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
		49
		50	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		51	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		52	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		53
		54	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		55	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		56	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		57
		58	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
		59	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
		60	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
		61
		62	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
		63	for (i = 0; i < 256; i++) {
		64	WREG32(AVIVO_DC_LUT_30_COLOR,
		65	(radeon_crtc->lut_r[i] << 20) \|
		66	(radeon_crtc->lut_g[i] << 10) \|
		67	(radeon_crtc->lut_b[i] << 0));
		68	}
		69
5078	serge	70	/* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
		71	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
1123	serge	72	}
		73
1963	serge	74	static void dce4_crtc_load_lut(struct drm_crtc *crtc)
1430	serge	75	{
		76	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		77	struct drm_device *dev = crtc->dev;
		78	struct radeon_device *rdev = dev->dev_private;
		79	int i;
		80
1963	serge	81	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1430	serge	82	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		83
		84	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		85	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		86	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		87
		88	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		89	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		90	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		91
1963	serge	92	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		93	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
1430	serge	94
1963	serge	95	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
1430	serge	96	for (i = 0; i < 256; i++) {
1963	serge	97	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
1430	serge	98	(radeon_crtc->lut_r[i] << 20) \|
		99	(radeon_crtc->lut_g[i] << 10) \|
		100	(radeon_crtc->lut_b[i] << 0));
		101	}
		102	}
		103
1963	serge	104	static void dce5_crtc_load_lut(struct drm_crtc *crtc)
		105	{
		106	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		107	struct drm_device *dev = crtc->dev;
		108	struct radeon_device *rdev = dev->dev_private;
		109	int i;
		110
		111	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
		112
		113	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		114	(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) \|
		115	NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
		116	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
		117	NI_GRPH_PRESCALE_BYPASS);
		118	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
		119	NI_OVL_PRESCALE_BYPASS);
		120	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
		121	(NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) \|
		122	NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
		123
		124	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		125
		126	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		127	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		128	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		129
		130	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		131	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		132	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		133
		134	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		135	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
		136
		137	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
		138	for (i = 0; i < 256; i++) {
		139	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
		140	(radeon_crtc->lut_r[i] << 20) \|
		141	(radeon_crtc->lut_g[i] << 10) \|
		142	(radeon_crtc->lut_b[i] << 0));
		143	}
		144
		145	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
		146	(NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		147	NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		148	NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		149	NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
		150	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
		151	(NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) \|
		152	NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
		153	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
		154	(NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) \|
		155	NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
		156	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
6104	serge	157	(NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) \|
1963	serge	158	NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
		159	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
		160	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
5078	serge	161	if (ASIC_IS_DCE8(rdev)) {
		162	/* XXX this only needs to be programmed once per crtc at startup,
		163	* not sure where the best place for it is
		164	*/
		165	WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
		166	CIK_CURSOR_ALPHA_BLND_ENA);
		167	}
1963	serge	168	}
		169
1123	serge	170	static void legacy_crtc_load_lut(struct drm_crtc *crtc)
		171	{
		172	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		173	struct drm_device *dev = crtc->dev;
		174	struct radeon_device *rdev = dev->dev_private;
		175	int i;
		176	uint32_t dac2_cntl;
		177
		178	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		179	if (radeon_crtc->crtc_id == 0)
		180	dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
		181	else
		182	dac2_cntl \|= RADEON_DAC2_PALETTE_ACC_CTL;
		183	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		184
		185	WREG8(RADEON_PALETTE_INDEX, 0);
		186	for (i = 0; i < 256; i++) {
		187	WREG32(RADEON_PALETTE_30_DATA,
		188	(radeon_crtc->lut_r[i] << 20) \|
		189	(radeon_crtc->lut_g[i] << 10) \|
		190	(radeon_crtc->lut_b[i] << 0));
		191	}
		192	}
		193
		194	void radeon_crtc_load_lut(struct drm_crtc *crtc)
		195	{
		196	struct drm_device *dev = crtc->dev;
		197	struct radeon_device *rdev = dev->dev_private;
		198
		199	if (!crtc->enabled)
		200	return;
		201
1963	serge	202	if (ASIC_IS_DCE5(rdev))
		203	dce5_crtc_load_lut(crtc);
		204	else if (ASIC_IS_DCE4(rdev))
		205	dce4_crtc_load_lut(crtc);
1430	serge	206	else if (ASIC_IS_AVIVO(rdev))
1123	serge	207	avivo_crtc_load_lut(crtc);
		208	else
		209	legacy_crtc_load_lut(crtc);
		210	}
		211
1221	serge	212	/** Sets the color ramps on behalf of fbcon */
1123	serge	213	void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		214	u16 blue, int regno)
		215	{
		216	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		217
		218	radeon_crtc->lut_r[regno] = red >> 6;
		219	radeon_crtc->lut_g[regno] = green >> 6;
		220	radeon_crtc->lut_b[regno] = blue >> 6;
		221	}
		222
1221	serge	223	/** Gets the color ramps on behalf of fbcon */
		224	void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		225	u16 *blue, int regno)
		226	{
		227	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		228
		229	*red = radeon_crtc->lut_r[regno] << 6;
		230	*green = radeon_crtc->lut_g[regno] << 6;
		231	*blue = radeon_crtc->lut_b[regno] << 6;
		232	}
		233
1123	serge	234	static void radeon_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
1963	serge	235	u16 *blue, uint32_t start, uint32_t size)
1123	serge	236	{
		237	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1963	serge	238	int end = (start + size > 256) ? 256 : start + size, i;
1123	serge	239
1221	serge	240	/* userspace palettes are always correct as is */
1963	serge	241	for (i = start; i < end; i++) {
6104	serge	242	radeon_crtc->lut_r[i] = red[i] >> 6;
		243	radeon_crtc->lut_g[i] = green[i] >> 6;
		244	radeon_crtc->lut_b[i] = blue[i] >> 6;
		245	}
1123	serge	246	radeon_crtc_load_lut(crtc);
		247	}
		248
		249	static void radeon_crtc_destroy(struct drm_crtc *crtc)
		250	{
		251	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		252
		253	drm_crtc_cleanup(crtc);
		254	kfree(radeon_crtc);
		255	}
		256
6104	serge	257	void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
		258	{
		259	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		260	unsigned long flags;
		261	u32 update_pending;
		262	int vpos, hpos;
		263
		264	/* can happen during initialization */
		265	if (radeon_crtc == NULL)
		266	return;
		267
		268	/* Skip the pageflip completion check below (based on polling) on
		269	* asics which reliably support hw pageflip completion irqs. pflip
		270	* irqs are a reliable and race-free method of handling pageflip
		271	* completion detection. A use_pflipirq module parameter < 2 allows
		272	* to override this in case of asics with faulty pflip irqs.
		273	* A module parameter of 0 would only use this polling based path,
		274	* a parameter of 1 would use pflip irq only as a backup to this
		275	* path, as in Linux 3.16.
		276	*/
		277	if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
		278	return;
		279
		280	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
		281	if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
		282	DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
		283	"RADEON_FLIP_SUBMITTED(%d)\n",
		284	radeon_crtc->flip_status,
		285	RADEON_FLIP_SUBMITTED);
		286	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
		287	return;
		288	}
		289
		290	update_pending = radeon_page_flip_pending(rdev, crtc_id);
		291
		292	/* Has the pageflip already completed in crtc, or is it certain
		293	* to complete in this vblank?
		294	*/
		295	if (update_pending &&
		296	(DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,
		297	crtc_id,
		298	USE_REAL_VBLANKSTART,
		299	&vpos, &hpos, NULL, NULL,
		300	&rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
		301	((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) \|\|
		302	(vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
		303	/* crtc didn't flip in this target vblank interval,
		304	* but flip is pending in crtc. Based on the current
		305	* scanout position we know that the current frame is
		306	* (nearly) complete and the flip will (likely)
		307	* complete before the start of the next frame.
		308	*/
		309	update_pending = 0;
		310	}
		311	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
		312	// if (!update_pending)
		313	// radeon_crtc_handle_flip(rdev, crtc_id);
		314	}
		315
5078	serge	316	static int
		317	radeon_crtc_set_config(struct drm_mode_set *set)
		318	{
		319	struct drm_device *dev;
		320	struct radeon_device *rdev;
		321	struct drm_crtc *crtc;
		322	bool active = false;
		323	int ret;
		324
		325	if (!set \|\| !set->crtc)
		326	return -EINVAL;
		327
		328	dev = set->crtc->dev;
		329
		330	ret = drm_crtc_helper_set_config(set);
		331
		332	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		333	if (crtc->enabled)
		334	active = true;
		335
		336	// pm_runtime_mark_last_busy(dev->dev);
		337
		338	rdev = dev->dev_private;
		339	/* if we have active crtcs and we don't have a power ref,
		340	take the current one */
		341	if (active && !rdev->have_disp_power_ref) {
		342	rdev->have_disp_power_ref = true;
		343	return ret;
		344	}
		345	/* if we have no active crtcs, then drop the power ref
		346	we got before */
		347	if (!active && rdev->have_disp_power_ref) {
		348	// pm_runtime_put_autosuspend(dev->dev);
		349	rdev->have_disp_power_ref = false;
		350	}
		351
		352	/* drop the power reference we got coming in here */
		353	// pm_runtime_put_autosuspend(dev->dev);
7146	serge	354
5078	serge	355	return ret;
		356	}
1123	serge	357	static const struct drm_crtc_funcs radeon_crtc_funcs = {
1221	serge	358	.cursor_set = NULL,
		359	.cursor_move = NULL,
1123	serge	360	.gamma_set = radeon_crtc_gamma_set,
5078	serge	361	.set_config = radeon_crtc_set_config,
1123	serge	362	.destroy = radeon_crtc_destroy,
1963	serge	363	.page_flip = NULL,
1123	serge	364	};
		365
		366	static void radeon_crtc_init(struct drm_device *dev, int index)
		367	{
		368	struct radeon_device *rdev = dev->dev_private;
		369	struct radeon_crtc *radeon_crtc;
		370	int i;
		371
		372	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		373	if (radeon_crtc == NULL)
		374	return;
		375
		376	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
		377
		378	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
		379	radeon_crtc->crtc_id = index;
1179	serge	380	rdev->mode_info.crtcs[index] = radeon_crtc;
1123	serge	381
5078	serge	382	if (rdev->family >= CHIP_BONAIRE) {
		383	radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
		384	radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
		385	} else {
		386	radeon_crtc->max_cursor_width = CURSOR_WIDTH;
		387	radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
		388	}
		389	dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
		390	dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
		391
1179	serge	392	#if 0
1123	serge	393	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
		394	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
		395	radeon_crtc->mode_set.num_connectors = 0;
1179	serge	396	#endif
1123	serge	397
		398	for (i = 0; i < 256; i++) {
		399	radeon_crtc->lut_r[i] = i << 2;
		400	radeon_crtc->lut_g[i] = i << 2;
		401	radeon_crtc->lut_b[i] = i << 2;
		402	}
		403
		404	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom))
		405	radeon_atombios_init_crtc(dev, radeon_crtc);
		406	else
		407	radeon_legacy_init_crtc(dev, radeon_crtc);
		408	}
		409
5078	serge	410	static const char *encoder_names[38] = {
1123	serge	411	"NONE",
		412	"INTERNAL_LVDS",
		413	"INTERNAL_TMDS1",
		414	"INTERNAL_TMDS2",
		415	"INTERNAL_DAC1",
		416	"INTERNAL_DAC2",
		417	"INTERNAL_SDVOA",
		418	"INTERNAL_SDVOB",
		419	"SI170B",
		420	"CH7303",
		421	"CH7301",
		422	"INTERNAL_DVO1",
		423	"EXTERNAL_SDVOA",
		424	"EXTERNAL_SDVOB",
		425	"TITFP513",
		426	"INTERNAL_LVTM1",
		427	"VT1623",
		428	"HDMI_SI1930",
		429	"HDMI_INTERNAL",
		430	"INTERNAL_KLDSCP_TMDS1",
		431	"INTERNAL_KLDSCP_DVO1",
		432	"INTERNAL_KLDSCP_DAC1",
		433	"INTERNAL_KLDSCP_DAC2",
		434	"SI178",
		435	"MVPU_FPGA",
		436	"INTERNAL_DDI",
		437	"VT1625",
		438	"HDMI_SI1932",
		439	"DP_AN9801",
		440	"DP_DP501",
		441	"INTERNAL_UNIPHY",
		442	"INTERNAL_KLDSCP_LVTMA",
		443	"INTERNAL_UNIPHY1",
		444	"INTERNAL_UNIPHY2",
1963	serge	445	"NUTMEG",
		446	"TRAVIS",
5078	serge	447	"INTERNAL_VCE",
		448	"INTERNAL_UNIPHY3",
1123	serge	449	};
		450
1963	serge	451	static const char *hpd_names[6] = {
1404	serge	452	"HPD1",
		453	"HPD2",
		454	"HPD3",
		455	"HPD4",
		456	"HPD5",
		457	"HPD6",
		458	};
		459
1123	serge	460	static void radeon_print_display_setup(struct drm_device *dev)
		461	{
		462	struct drm_connector *connector;
		463	struct radeon_connector *radeon_connector;
		464	struct drm_encoder *encoder;
		465	struct radeon_encoder *radeon_encoder;
		466	uint32_t devices;
		467	int i = 0;
		468
		469	DRM_INFO("Radeon Display Connectors\n");
		470	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		471	radeon_connector = to_radeon_connector(connector);
		472	DRM_INFO("Connector %d:\n", i);
5078	serge	473	DRM_INFO(" %s\n", connector->name);
1404	serge	474	if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
		475	DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
		476	if (radeon_connector->ddc_bus) {
1123	serge	477	DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
		478	radeon_connector->ddc_bus->rec.mask_clk_reg,
		479	radeon_connector->ddc_bus->rec.mask_data_reg,
		480	radeon_connector->ddc_bus->rec.a_clk_reg,
		481	radeon_connector->ddc_bus->rec.a_data_reg,
1404	serge	482	radeon_connector->ddc_bus->rec.en_clk_reg,
		483	radeon_connector->ddc_bus->rec.en_data_reg,
		484	radeon_connector->ddc_bus->rec.y_clk_reg,
		485	radeon_connector->ddc_bus->rec.y_data_reg);
1963	serge	486	if (radeon_connector->router.ddc_valid)
		487	DRM_INFO(" DDC Router 0x%x/0x%x\n",
		488	radeon_connector->router.ddc_mux_control_pin,
		489	radeon_connector->router.ddc_mux_state);
		490	if (radeon_connector->router.cd_valid)
		491	DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
		492	radeon_connector->router.cd_mux_control_pin,
		493	radeon_connector->router.cd_mux_state);
1404	serge	494	} else {
		495	if (connector->connector_type == DRM_MODE_CONNECTOR_VGA \|\|
		496	connector->connector_type == DRM_MODE_CONNECTOR_DVII \|\|
		497	connector->connector_type == DRM_MODE_CONNECTOR_DVID \|\|
		498	connector->connector_type == DRM_MODE_CONNECTOR_DVIA \|\|
		499	connector->connector_type == DRM_MODE_CONNECTOR_HDMIA \|\|
		500	connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
		501	DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
		502	}
1123	serge	503	DRM_INFO(" Encoders:\n");
		504	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		505	radeon_encoder = to_radeon_encoder(encoder);
		506	devices = radeon_encoder->devices & radeon_connector->devices;
		507	if (devices) {
		508	if (devices & ATOM_DEVICE_CRT1_SUPPORT)
		509	DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		510	if (devices & ATOM_DEVICE_CRT2_SUPPORT)
		511	DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		512	if (devices & ATOM_DEVICE_LCD1_SUPPORT)
		513	DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		514	if (devices & ATOM_DEVICE_DFP1_SUPPORT)
		515	DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		516	if (devices & ATOM_DEVICE_DFP2_SUPPORT)
		517	DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		518	if (devices & ATOM_DEVICE_DFP3_SUPPORT)
		519	DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
		520	if (devices & ATOM_DEVICE_DFP4_SUPPORT)
		521	DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
		522	if (devices & ATOM_DEVICE_DFP5_SUPPORT)
		523	DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
1963	serge	524	if (devices & ATOM_DEVICE_DFP6_SUPPORT)
		525	DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
1123	serge	526	if (devices & ATOM_DEVICE_TV1_SUPPORT)
		527	DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		528	if (devices & ATOM_DEVICE_CV_SUPPORT)
		529	DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
		530	}
		531	}
		532	i++;
		533	}
		534	}
		535
1179	serge	536	static bool radeon_setup_enc_conn(struct drm_device *dev)
1123	serge	537	{
		538	struct radeon_device *rdev = dev->dev_private;
		539	bool ret = false;
		540
		541	if (rdev->bios) {
		542	if (rdev->is_atom_bios) {
1963	serge	543	ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
		544	if (ret == false)
1123	serge	545	ret = radeon_get_atom_connector_info_from_object_table(dev);
1404	serge	546	} else {
1123	serge	547	ret = radeon_get_legacy_connector_info_from_bios(dev);
1404	serge	548	if (ret == false)
		549	ret = radeon_get_legacy_connector_info_from_table(dev);
		550	}
1123	serge	551	} else {
		552	if (!ASIC_IS_AVIVO(rdev))
		553	ret = radeon_get_legacy_connector_info_from_table(dev);
		554	}
		555	if (ret) {
1404	serge	556	radeon_setup_encoder_clones(dev);
1123	serge	557	radeon_print_display_setup(dev);
		558	}
		559
		560	return ret;
		561	}
		562
5078	serge	563	/* avivo */
		564
		565	/**
		566	* avivo_reduce_ratio - fractional number reduction
		567	*
		568	* @nom: nominator
		569	* @den: denominator
		570	* @nom_min: minimum value for nominator
		571	* @den_min: minimum value for denominator
		572	*
		573	* Find the greatest common divisor and apply it on both nominator and
		574	* denominator, but make nominator and denominator are at least as large
		575	* as their minimum values.
		576	*/
		577	static void avivo_reduce_ratio(unsigned nom, unsigned den,
		578	unsigned nom_min, unsigned den_min)
1123	serge	579	{
5078	serge	580	unsigned tmp;
1123	serge	581
5078	serge	582	/* reduce the numbers to a simpler ratio */
		583	tmp = gcd(nom, den);
		584	*nom /= tmp;
		585	*den /= tmp;
1963	serge	586
5078	serge	587	/* make sure nominator is large enough */
7146	serge	588	if (*nom < nom_min) {
5078	serge	589	tmp = DIV_ROUND_UP(nom_min, *nom);
		590	nom = tmp;
		591	den = tmp;
1404	serge	592	}
1963	serge	593
5078	serge	594	/* make sure the denominator is large enough */
		595	if (*den < den_min) {
		596	tmp = DIV_ROUND_UP(den_min, *den);
		597	nom = tmp;
		598	den = tmp;
1963	serge	599	}
1123	serge	600	}
		601
5078	serge	602	/**
		603	* avivo_get_fb_ref_div - feedback and ref divider calculation
		604	*
		605	* @nom: nominator
		606	* @den: denominator
		607	* @post_div: post divider
		608	* @fb_div_max: feedback divider maximum
		609	* @ref_div_max: reference divider maximum
		610	* @fb_div: resulting feedback divider
		611	* @ref_div: resulting reference divider
		612	*
		613	* Calculate feedback and reference divider for a given post divider. Makes
		614	* sure we stay within the limits.
		615	*/
		616	static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
		617	unsigned fb_div_max, unsigned ref_div_max,
		618	unsigned fb_div, unsigned ref_div)
1963	serge	619	{
5078	serge	620	/* limit reference * post divider to a maximum */
		621	ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
1963	serge	622
5078	serge	623	/* get matching reference and feedback divider */
		624	*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
		625	fb_div = DIV_ROUND_CLOSEST(nom ref_div post_div, den);
1963	serge	626
5078	serge	627	/* limit fb divider to its maximum */
7146	serge	628	if (*fb_div > fb_div_max) {
5078	serge	629	ref_div = DIV_ROUND_CLOSEST(ref_div * fb_div_max, *fb_div);
		630	*fb_div = fb_div_max;
		631	}
1963	serge	632	}
		633
5078	serge	634	/**
		635	* radeon_compute_pll_avivo - compute PLL paramaters
		636	*
		637	* @pll: information about the PLL
		638	* @dot_clock_p: resulting pixel clock
		639	* fb_div_p: resulting feedback divider
		640	* frac_fb_div_p: fractional part of the feedback divider
		641	* ref_div_p: resulting reference divider
		642	* post_div_p: resulting reference divider
		643	*
		644	* Try to calculate the PLL parameters to generate the given frequency:
		645	* dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
		646	*/
		647	void radeon_compute_pll_avivo(struct radeon_pll *pll,
		648	u32 freq,
		649	u32 *dot_clock_p,
		650	u32 *fb_div_p,
		651	u32 *frac_fb_div_p,
		652	u32 *ref_div_p,
		653	u32 *post_div_p)
1963	serge	654	{
5078	serge	655	unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
		656	freq : freq / 10;
1963	serge	657
5078	serge	658	unsigned fb_div_min, fb_div_max, fb_div;
		659	unsigned post_div_min, post_div_max, post_div;
		660	unsigned ref_div_min, ref_div_max, ref_div;
		661	unsigned post_div_best, diff_best;
		662	unsigned nom, den;
1963	serge	663
5078	serge	664	/* determine allowed feedback divider range */
		665	fb_div_min = pll->min_feedback_div;
		666	fb_div_max = pll->max_feedback_div;
		667
		668	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
		669	fb_div_min *= 10;
		670	fb_div_max *= 10;
		671	}
		672
		673	/* determine allowed ref divider range */
		674	if (pll->flags & RADEON_PLL_USE_REF_DIV)
		675	ref_div_min = pll->reference_div;
		676	else
		677	ref_div_min = pll->min_ref_div;
		678
		679	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
		680	pll->flags & RADEON_PLL_USE_REF_DIV)
		681	ref_div_max = pll->reference_div;
6104	serge	682	else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
		683	/* fix for problems on RS880 */
		684	ref_div_max = min(pll->max_ref_div, 7u);
6938	serge	685	else
5078	serge	686	ref_div_max = pll->max_ref_div;
		687
		688	/* determine allowed post divider range */
		689	if (pll->flags & RADEON_PLL_USE_POST_DIV) {
		690	post_div_min = pll->post_div;
		691	post_div_max = pll->post_div;
1963	serge	692	} else {
5078	serge	693	unsigned vco_min, vco_max;
		694
		695	if (pll->flags & RADEON_PLL_IS_LCD) {
		696	vco_min = pll->lcd_pll_out_min;
		697	vco_max = pll->lcd_pll_out_max;
		698	} else {
		699	vco_min = pll->pll_out_min;
		700	vco_max = pll->pll_out_max;
		701	}
		702
		703	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
		704	vco_min *= 10;
		705	vco_max *= 10;
6104	serge	706	}
1963	serge	707
5078	serge	708	post_div_min = vco_min / target_clock;
		709	if ((target_clock * post_div_min) < vco_min)
		710	++post_div_min;
		711	if (post_div_min < pll->min_post_div)
		712	post_div_min = pll->min_post_div;
1963	serge	713
5078	serge	714	post_div_max = vco_max / target_clock;
		715	if ((target_clock * post_div_max) > vco_max)
		716	--post_div_max;
		717	if (post_div_max > pll->max_post_div)
		718	post_div_max = pll->max_post_div;
1963	serge	719	}
		720
5078	serge	721	/* represent the searched ratio as fractional number */
		722	nom = target_clock;
		723	den = pll->reference_freq;
1963	serge	724
5078	serge	725	/* reduce the numbers to a simpler ratio */
		726	avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1963	serge	727
5078	serge	728	/* now search for a post divider */
		729	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
		730	post_div_best = post_div_min;
		731	else
		732	post_div_best = post_div_max;
		733	diff_best = ~0;
1963	serge	734
5078	serge	735	for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
		736	unsigned diff;
		737	avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
		738	ref_div_max, &fb_div, &ref_div);
		739	diff = abs(target_clock - (pll->reference_freq * fb_div) /
		740	(ref_div * post_div));
1963	serge	741
5078	serge	742	if (diff < diff_best \|\| (diff == diff_best &&
		743	!(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1963	serge	744
5078	serge	745	post_div_best = post_div;
		746	diff_best = diff;
1963	serge	747	}
5078	serge	748	}
		749	post_div = post_div_best;
1963	serge	750
5078	serge	751	/* get the feedback and reference divider for the optimal value */
		752	avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
		753	&fb_div, &ref_div);
		754
		755	/* reduce the numbers to a simpler ratio once more */
		756	/* this also makes sure that the reference divider is large enough */
		757	avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
		758
		759	/* avoid high jitter with small fractional dividers */
		760	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
		761	fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
		762	if (fb_div < fb_div_min) {
		763	unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
		764	fb_div *= tmp;
		765	ref_div *= tmp;
1963	serge	766	}
		767	}
		768
5078	serge	769	/* and finally save the result */
		770	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
		771	*fb_div_p = fb_div / 10;
		772	*frac_fb_div_p = fb_div % 10;
		773	} else {
		774	*fb_div_p = fb_div;
		775	*frac_fb_div_p = 0;
		776	}
		777
		778	dot_clock_p = ((pll->reference_freq fb_div_p 10) +
		779	(pll->reference_freq * *frac_fb_div_p)) /
6104	serge	780	(ref_div * post_div * 10);
1963	serge	781	*ref_div_p = ref_div;
		782	*post_div_p = post_div;
5078	serge	783
		784	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		785	freq, dot_clock_p 10, fb_div_p, frac_fb_div_p,
		786	ref_div, post_div);
1963	serge	787	}
		788
		789	/* pre-avivo */
1123	serge	790	static inline uint32_t radeon_div(uint64_t n, uint32_t d)
		791	{
		792	uint64_t mod;
		793
		794	n += d / 2;
		795
		796	mod = do_div(n, d);
		797	return n;
		798	}
		799
1963	serge	800	void radeon_compute_pll_legacy(struct radeon_pll *pll,
6104	serge	801	uint64_t freq,
		802	uint32_t *dot_clock_p,
		803	uint32_t *fb_div_p,
		804	uint32_t *frac_fb_div_p,
		805	uint32_t *ref_div_p,
		806	uint32_t *post_div_p)
1123	serge	807	{
		808	uint32_t min_ref_div = pll->min_ref_div;
		809	uint32_t max_ref_div = pll->max_ref_div;
1404	serge	810	uint32_t min_post_div = pll->min_post_div;
		811	uint32_t max_post_div = pll->max_post_div;
1123	serge	812	uint32_t min_fractional_feed_div = 0;
		813	uint32_t max_fractional_feed_div = 0;
		814	uint32_t best_vco = pll->best_vco;
		815	uint32_t best_post_div = 1;
		816	uint32_t best_ref_div = 1;
		817	uint32_t best_feedback_div = 1;
		818	uint32_t best_frac_feedback_div = 0;
		819	uint32_t best_freq = -1;
		820	uint32_t best_error = 0xffffffff;
		821	uint32_t best_vco_diff = 1;
		822	uint32_t post_div;
1963	serge	823	u32 pll_out_min, pll_out_max;
1123	serge	824
1963	serge	825	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1123	serge	826	freq = freq * 1000;
		827
1963	serge	828	if (pll->flags & RADEON_PLL_IS_LCD) {
		829	pll_out_min = pll->lcd_pll_out_min;
		830	pll_out_max = pll->lcd_pll_out_max;
		831	} else {
		832	pll_out_min = pll->pll_out_min;
		833	pll_out_max = pll->pll_out_max;
		834	}
		835
		836	if (pll_out_min > 64800)
		837	pll_out_min = 64800;
		838
1404	serge	839	if (pll->flags & RADEON_PLL_USE_REF_DIV)
1123	serge	840	min_ref_div = max_ref_div = pll->reference_div;
		841	else {
		842	while (min_ref_div < max_ref_div-1) {
		843	uint32_t mid = (min_ref_div + max_ref_div) / 2;
		844	uint32_t pll_in = pll->reference_freq / mid;
		845	if (pll_in < pll->pll_in_min)
		846	max_ref_div = mid;
		847	else if (pll_in > pll->pll_in_max)
		848	min_ref_div = mid;
		849	else
		850	break;
		851	}
		852	}
		853
1404	serge	854	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		855	min_post_div = max_post_div = pll->post_div;
		856
		857	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1123	serge	858	min_fractional_feed_div = pll->min_frac_feedback_div;
		859	max_fractional_feed_div = pll->max_frac_feedback_div;
		860	}
		861
1963	serge	862	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1123	serge	863	uint32_t ref_div;
		864
1404	serge	865	if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1123	serge	866	continue;
		867
		868	/* legacy radeons only have a few post_divs */
1404	serge	869	if (pll->flags & RADEON_PLL_LEGACY) {
1123	serge	870	if ((post_div == 5) \|\|
		871	(post_div == 7) \|\|
		872	(post_div == 9) \|\|
		873	(post_div == 10) \|\|
		874	(post_div == 11) \|\|
		875	(post_div == 13) \|\|
		876	(post_div == 14) \|\|
		877	(post_div == 15))
		878	continue;
		879	}
		880
		881	for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
		882	uint32_t feedback_div, current_freq = 0, error, vco_diff;
		883	uint32_t pll_in = pll->reference_freq / ref_div;
		884	uint32_t min_feed_div = pll->min_feedback_div;
		885	uint32_t max_feed_div = pll->max_feedback_div + 1;
		886
		887	if (pll_in < pll->pll_in_min \|\| pll_in > pll->pll_in_max)
		888	continue;
		889
		890	while (min_feed_div < max_feed_div) {
		891	uint32_t vco;
		892	uint32_t min_frac_feed_div = min_fractional_feed_div;
		893	uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
		894	uint32_t frac_feedback_div;
		895	uint64_t tmp;
		896
		897	feedback_div = (min_feed_div + max_feed_div) / 2;
		898
		899	tmp = (uint64_t)pll->reference_freq * feedback_div;
		900	vco = radeon_div(tmp, ref_div);
		901
1963	serge	902	if (vco < pll_out_min) {
1123	serge	903	min_feed_div = feedback_div + 1;
		904	continue;
1963	serge	905	} else if (vco > pll_out_max) {
1123	serge	906	max_feed_div = feedback_div;
		907	continue;
		908	}
		909
		910	while (min_frac_feed_div < max_frac_feed_div) {
		911	frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
		912	tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
		913	tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
		914	current_freq = radeon_div(tmp, ref_div * post_div);
		915
1404	serge	916	if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1963	serge	917	if (freq < current_freq)
		918	error = 0xffffffff;
		919	else
6104	serge	920	error = freq - current_freq;
1179	serge	921	} else
6104	serge	922	error = abs(current_freq - freq);
1123	serge	923	vco_diff = abs(vco - best_vco);
		924
		925	if ((best_vco == 0 && error < best_error) \|\|
		926	(best_vco != 0 &&
1963	serge	927	((best_error > 100 && error < best_error - 100) \|\|
1123	serge	928	(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
		929	best_post_div = post_div;
		930	best_ref_div = ref_div;
		931	best_feedback_div = feedback_div;
		932	best_frac_feedback_div = frac_feedback_div;
		933	best_freq = current_freq;
		934	best_error = error;
		935	best_vco_diff = vco_diff;
		936	} else if (current_freq == freq) {
		937	if (best_freq == -1) {
		938	best_post_div = post_div;
		939	best_ref_div = ref_div;
		940	best_feedback_div = feedback_div;
		941	best_frac_feedback_div = frac_feedback_div;
		942	best_freq = current_freq;
		943	best_error = error;
		944	best_vco_diff = vco_diff;
1404	serge	945	} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) \|\|
		946	((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) \|\|
		947	((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) \|\|
		948	((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) \|\|
		949	((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) \|\|
		950	((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1123	serge	951	best_post_div = post_div;
		952	best_ref_div = ref_div;
		953	best_feedback_div = feedback_div;
		954	best_frac_feedback_div = frac_feedback_div;
		955	best_freq = current_freq;
		956	best_error = error;
		957	best_vco_diff = vco_diff;
		958	}
		959	}
		960	if (current_freq < freq)
		961	min_frac_feed_div = frac_feedback_div + 1;
		962	else
		963	max_frac_feed_div = frac_feedback_div;
		964	}
		965	if (current_freq < freq)
		966	min_feed_div = feedback_div + 1;
		967	else
		968	max_feed_div = feedback_div;
		969	}
		970	}
		971	}
		972
		973	*dot_clock_p = best_freq / 10000;
		974	*fb_div_p = best_feedback_div;
		975	*frac_fb_div_p = best_frac_feedback_div;
		976	*ref_div_p = best_ref_div;
		977	*post_div_p = best_post_div;
1963	serge	978	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		979	(long long)freq,
		980	best_freq / 1000, best_feedback_div, best_frac_feedback_div,
		981	best_ref_div, best_post_div);
1123	serge	982
1430	serge	983	}
		984
1123	serge	985	static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
		986	{
		987	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		988
5078	serge	989	if (radeon_fb->obj) {
		990	drm_gem_object_unreference_unlocked(radeon_fb->obj);
		991	}
1123	serge	992	drm_framebuffer_cleanup(fb);
		993	kfree(radeon_fb);
		994	}
		995
		996	static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6104	serge	997	struct drm_file *file_priv,
		998	unsigned int *handle)
1123	serge	999	{
6104	serge	1000	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1123	serge	1001
6938	serge	1002	return 0;
1123	serge	1003	// return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
		1004	}
		1005
		1006	static const struct drm_framebuffer_funcs radeon_fb_funcs = {
		1007	.destroy = radeon_user_framebuffer_destroy,
6104	serge	1008	.create_handle = radeon_user_framebuffer_create_handle,
1123	serge	1009	};
		1010
2997	Serge	1011	int
1963	serge	1012	radeon_framebuffer_init(struct drm_device *dev,
		1013	struct radeon_framebuffer *rfb,
6938	serge	1014	const struct drm_mode_fb_cmd2 *mode_cmd,
6104	serge	1015	struct drm_gem_object *obj)
1123	serge	1016	{
2997	Serge	1017	int ret;
1963	serge	1018	rfb->obj = obj;
3764	Serge	1019	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
2997	Serge	1020	ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
		1021	if (ret) {
		1022	rfb->obj = NULL;
		1023	return ret;
		1024	}
		1025	return 0;
1123	serge	1026	}
		1027
		1028
		1029
		1030	static const struct drm_mode_config_funcs radeon_mode_funcs = {
1963	serge	1031	// .fb_create = radeon_user_framebuffer_create,
		1032	// .output_poll_changed = radeon_output_poll_changed
1123	serge	1033	};
		1034
1179	serge	1035	static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
		1036	{ { 0, "driver" },
		1037	{ 1, "bios" },
		1038	};
		1039
		1040	static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
		1041	{ { TV_STD_NTSC, "ntsc" },
		1042	{ TV_STD_PAL, "pal" },
		1043	{ TV_STD_PAL_M, "pal-m" },
		1044	{ TV_STD_PAL_60, "pal-60" },
		1045	{ TV_STD_NTSC_J, "ntsc-j" },
		1046	{ TV_STD_SCART_PAL, "scart-pal" },
		1047	{ TV_STD_PAL_CN, "pal-cn" },
		1048	{ TV_STD_SECAM, "secam" },
		1049	};
		1050
1963	serge	1051	static struct drm_prop_enum_list radeon_underscan_enum_list[] =
		1052	{ { UNDERSCAN_OFF, "off" },
		1053	{ UNDERSCAN_ON, "on" },
		1054	{ UNDERSCAN_AUTO, "auto" },
		1055	};
		1056
5078	serge	1057	static struct drm_prop_enum_list radeon_audio_enum_list[] =
		1058	{ { RADEON_AUDIO_DISABLE, "off" },
		1059	{ RADEON_AUDIO_ENABLE, "on" },
		1060	{ RADEON_AUDIO_AUTO, "auto" },
		1061	};
		1062
		1063	/* XXX support different dither options? spatial, temporal, both, etc. */
		1064	static struct drm_prop_enum_list radeon_dither_enum_list[] =
		1065	{ { RADEON_FMT_DITHER_DISABLE, "off" },
		1066	{ RADEON_FMT_DITHER_ENABLE, "on" },
		1067	};
		1068
6104	serge	1069	static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
		1070	{ { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
		1071	{ RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
		1072	{ RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
		1073	{ RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
		1074	};
		1075
1404	serge	1076	static int radeon_modeset_create_props(struct radeon_device *rdev)
1123	serge	1077	{
2997	Serge	1078	int sz;
1125	serge	1079
1179	serge	1080	if (rdev->is_atom_bios) {
		1081	rdev->mode_info.coherent_mode_property =
2997	Serge	1082	drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1179	serge	1083	if (!rdev->mode_info.coherent_mode_property)
		1084	return -ENOMEM;
		1085	}
		1086
		1087	if (!ASIC_IS_AVIVO(rdev)) {
		1088	sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
		1089	rdev->mode_info.tmds_pll_property =
2997	Serge	1090	drm_property_create_enum(rdev->ddev, 0,
		1091	"tmds_pll",
		1092	radeon_tmds_pll_enum_list, sz);
1179	serge	1093	}
		1094
		1095	rdev->mode_info.load_detect_property =
2997	Serge	1096	drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1179	serge	1097	if (!rdev->mode_info.load_detect_property)
		1098	return -ENOMEM;
		1099
		1100	drm_mode_create_scaling_mode_property(rdev->ddev);
		1101
		1102	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
		1103	rdev->mode_info.tv_std_property =
2997	Serge	1104	drm_property_create_enum(rdev->ddev, 0,
		1105	"tv standard",
		1106	radeon_tv_std_enum_list, sz);
1179	serge	1107
1963	serge	1108	sz = ARRAY_SIZE(radeon_underscan_enum_list);
		1109	rdev->mode_info.underscan_property =
2997	Serge	1110	drm_property_create_enum(rdev->ddev, 0,
		1111	"underscan",
		1112	radeon_underscan_enum_list, sz);
1963	serge	1113
		1114	rdev->mode_info.underscan_hborder_property =
2997	Serge	1115	drm_property_create_range(rdev->ddev, 0,
		1116	"underscan hborder", 0, 128);
1963	serge	1117	if (!rdev->mode_info.underscan_hborder_property)
		1118	return -ENOMEM;
		1119
		1120	rdev->mode_info.underscan_vborder_property =
2997	Serge	1121	drm_property_create_range(rdev->ddev, 0,
		1122	"underscan vborder", 0, 128);
1963	serge	1123	if (!rdev->mode_info.underscan_vborder_property)
		1124	return -ENOMEM;
		1125
5078	serge	1126	sz = ARRAY_SIZE(radeon_audio_enum_list);
		1127	rdev->mode_info.audio_property =
		1128	drm_property_create_enum(rdev->ddev, 0,
		1129	"audio",
		1130	radeon_audio_enum_list, sz);
		1131
		1132	sz = ARRAY_SIZE(radeon_dither_enum_list);
		1133	rdev->mode_info.dither_property =
		1134	drm_property_create_enum(rdev->ddev, 0,
		1135	"dither",
		1136	radeon_dither_enum_list, sz);
		1137
6104	serge	1138	sz = ARRAY_SIZE(radeon_output_csc_enum_list);
		1139	rdev->mode_info.output_csc_property =
		1140	drm_property_create_enum(rdev->ddev, 0,
		1141	"output_csc",
		1142	radeon_output_csc_enum_list, sz);
		1143
1179	serge	1144	return 0;
		1145	}
		1146
1963	serge	1147	void radeon_update_display_priority(struct radeon_device *rdev)
		1148	{
		1149	/* adjustment options for the display watermarks */
		1150	if ((radeon_disp_priority == 0) \|\| (radeon_disp_priority > 2)) {
		1151	/* set display priority to high for r3xx, rv515 chips
		1152	* this avoids flickering due to underflow to the
		1153	* display controllers during heavy acceleration.
		1154	* Don't force high on rs4xx igp chips as it seems to
		1155	* affect the sound card. See kernel bug 15982.
		1156	*/
		1157	if ((ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV515)) &&
		1158	!(rdev->flags & RADEON_IS_IGP))
		1159	rdev->disp_priority = 2;
		1160	else
		1161	rdev->disp_priority = 0;
		1162	} else
		1163	rdev->disp_priority = radeon_disp_priority;
		1164
		1165	}
		1166
2997	Serge	1167	/*
		1168	* Allocate hdmi structs and determine register offsets
		1169	*/
		1170	static void radeon_afmt_init(struct radeon_device *rdev)
		1171	{
		1172	int i;
		1173
		1174	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
		1175	rdev->mode_info.afmt[i] = NULL;
		1176
5078	serge	1177	if (ASIC_IS_NODCE(rdev)) {
		1178	/* nothing to do */
2997	Serge	1179	} else if (ASIC_IS_DCE4(rdev)) {
5078	serge	1180	static uint32_t eg_offsets[] = {
		1181	EVERGREEN_CRTC0_REGISTER_OFFSET,
		1182	EVERGREEN_CRTC1_REGISTER_OFFSET,
		1183	EVERGREEN_CRTC2_REGISTER_OFFSET,
		1184	EVERGREEN_CRTC3_REGISTER_OFFSET,
		1185	EVERGREEN_CRTC4_REGISTER_OFFSET,
		1186	EVERGREEN_CRTC5_REGISTER_OFFSET,
		1187	0x13830 - 0x7030,
		1188	};
		1189	int num_afmt;
		1190
		1191	/* DCE8 has 7 audio blocks tied to DIG encoders */
		1192	/* DCE6 has 6 audio blocks tied to DIG encoders */
2997	Serge	1193	/* DCE4/5 has 6 audio blocks tied to DIG encoders */
		1194	/* DCE4.1 has 2 audio blocks tied to DIG encoders */
5078	serge	1195	if (ASIC_IS_DCE8(rdev))
		1196	num_afmt = 7;
		1197	else if (ASIC_IS_DCE6(rdev))
		1198	num_afmt = 6;
		1199	else if (ASIC_IS_DCE5(rdev))
		1200	num_afmt = 6;
		1201	else if (ASIC_IS_DCE41(rdev))
		1202	num_afmt = 2;
		1203	else /* DCE4 */
		1204	num_afmt = 6;
		1205
		1206	BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
		1207	for (i = 0; i < num_afmt; i++) {
		1208	rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1209	if (rdev->mode_info.afmt[i]) {
		1210	rdev->mode_info.afmt[i]->offset = eg_offsets[i];
		1211	rdev->mode_info.afmt[i]->id = i;
2997	Serge	1212	}
		1213	}
		1214	} else if (ASIC_IS_DCE3(rdev)) {
		1215	/* DCE3.x has 2 audio blocks tied to DIG encoders */
		1216	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1217	if (rdev->mode_info.afmt[0]) {
		1218	rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
		1219	rdev->mode_info.afmt[0]->id = 0;
		1220	}
		1221	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1222	if (rdev->mode_info.afmt[1]) {
		1223	rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
		1224	rdev->mode_info.afmt[1]->id = 1;
		1225	}
		1226	} else if (ASIC_IS_DCE2(rdev)) {
		1227	/* DCE2 has at least 1 routable audio block */
		1228	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1229	if (rdev->mode_info.afmt[0]) {
		1230	rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
		1231	rdev->mode_info.afmt[0]->id = 0;
		1232	}
		1233	/* r6xx has 2 routable audio blocks */
		1234	if (rdev->family >= CHIP_R600) {
		1235	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1236	if (rdev->mode_info.afmt[1]) {
		1237	rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
		1238	rdev->mode_info.afmt[1]->id = 1;
		1239	}
		1240	}
		1241	}
		1242	}
		1243
		1244	static void radeon_afmt_fini(struct radeon_device *rdev)
		1245	{
		1246	int i;
		1247
		1248	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
		1249	kfree(rdev->mode_info.afmt[i]);
		1250	rdev->mode_info.afmt[i] = NULL;
		1251	}
		1252	}
		1253
1179	serge	1254	int radeon_modeset_init(struct radeon_device *rdev)
		1255	{
1430	serge	1256	int i;
1123	serge	1257	int ret;
		1258
5078	serge	1259	ENTER();
		1260
1123	serge	1261	drm_mode_config_init(rdev->ddev);
		1262	rdev->mode_info.mode_config_initialized = true;
		1263
2997	Serge	1264	rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1123	serge	1265
1963	serge	1266	if (ASIC_IS_DCE5(rdev)) {
		1267	rdev->ddev->mode_config.max_width = 16384;
		1268	rdev->ddev->mode_config.max_height = 16384;
		1269	} else if (ASIC_IS_AVIVO(rdev)) {
1123	serge	1270	rdev->ddev->mode_config.max_width = 8192;
		1271	rdev->ddev->mode_config.max_height = 8192;
		1272	} else {
		1273	rdev->ddev->mode_config.max_width = 4096;
		1274	rdev->ddev->mode_config.max_height = 4096;
		1275	}
		1276
2997	Serge	1277	rdev->ddev->mode_config.preferred_depth = 24;
		1278	rdev->ddev->mode_config.prefer_shadow = 1;
		1279
1123	serge	1280	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
		1281
1179	serge	1282	ret = radeon_modeset_create_props(rdev);
		1283	if (ret) {
		1284	return ret;
		1285	}
1221	serge	1286
1963	serge	1287	/* init i2c buses */
		1288	radeon_i2c_init(rdev);
		1289
1430	serge	1290	/* check combios for a valid hardcoded EDID - Sun servers */
		1291	if (!rdev->is_atom_bios) {
		1292	/* check for hardcoded EDID in BIOS */
		1293	radeon_combios_check_hardcoded_edid(rdev);
		1294	}
		1295
1221	serge	1296	/* allocate crtcs */
1430	serge	1297	for (i = 0; i < rdev->num_crtc; i++) {
1123	serge	1298	radeon_crtc_init(rdev->ddev, i);
		1299	}
		1300
		1301	/* okay we should have all the bios connectors */
		1302	ret = radeon_setup_enc_conn(rdev->ddev);
		1303	if (!ret) {
		1304	return ret;
		1305	}
1963	serge	1306
2997	Serge	1307	/* init dig PHYs, disp eng pll */
		1308	if (rdev->is_atom_bios) {
1963	serge	1309	radeon_atom_encoder_init(rdev);
2997	Serge	1310	radeon_atom_disp_eng_pll_init(rdev);
		1311	}
1963	serge	1312
1404	serge	1313	/* initialize hpd */
1963	serge	1314	// radeon_hpd_init(rdev);
		1315
2997	Serge	1316	/* setup afmt */
5078	serge	1317	radeon_afmt_init(rdev);
2997	Serge	1318
1963	serge	1319	radeon_fbdev_init(rdev);
		1320
5078	serge	1321	LEAVE();
		1322
1123	serge	1323	return 0;
		1324	}
		1325
		1326	void radeon_modeset_fini(struct radeon_device *rdev)
		1327	{
1430	serge	1328	kfree(rdev->mode_info.bios_hardcoded_edid);
		1329
7146	serge	1330	/* free i2c buses */
		1331	radeon_i2c_fini(rdev);
		1332
1123	serge	1333	if (rdev->mode_info.mode_config_initialized) {
2997	Serge	1334	// radeon_afmt_fini(rdev);
1963	serge	1335	// drm_kms_helper_poll_fini(rdev->ddev);
		1336	// radeon_hpd_fini(rdev);
3764	Serge	1337	// drm_mode_config_cleanup(rdev->ddev);
1123	serge	1338	rdev->mode_info.mode_config_initialized = false;
		1339	}
		1340	}
		1341
2997	Serge	1342	static bool is_hdtv_mode(const struct drm_display_mode *mode)
1963	serge	1343	{
		1344	/* try and guess if this is a tv or a monitor */
		1345	if ((mode->vdisplay == 480 && mode->hdisplay == 720) \|\| /* 480p */
		1346	(mode->vdisplay == 576) \|\| /* 576p */
		1347	(mode->vdisplay == 720) \|\| /* 720p */
		1348	(mode->vdisplay == 1080)) /* 1080p */
		1349	return true;
		1350	else
		1351	return false;
		1352	}
		1353
1179	serge	1354	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
2997	Serge	1355	const struct drm_display_mode *mode,
1179	serge	1356	struct drm_display_mode *adjusted_mode)
1123	serge	1357	{
1179	serge	1358	struct drm_device *dev = crtc->dev;
1963	serge	1359	struct radeon_device *rdev = dev->dev_private;
1179	serge	1360	struct drm_encoder *encoder;
6938	serge	1361	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1179	serge	1362	struct radeon_encoder *radeon_encoder;
1963	serge	1363	struct drm_connector *connector;
		1364	struct radeon_connector *radeon_connector;
1179	serge	1365	bool first = true;
1963	serge	1366	u32 src_v = 1, dst_v = 1;
		1367	u32 src_h = 1, dst_h = 1;
1123	serge	1368
1963	serge	1369	radeon_crtc->h_border = 0;
		1370	radeon_crtc->v_border = 0;
		1371
1179	serge	1372	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1373	if (encoder->crtc != crtc)
		1374	continue;
1963	serge	1375	radeon_encoder = to_radeon_encoder(encoder);
		1376	connector = radeon_get_connector_for_encoder(encoder);
		1377	radeon_connector = to_radeon_connector(connector);
		1378
1179	serge	1379	if (first) {
1404	serge	1380	/* set scaling */
		1381	if (radeon_encoder->rmx_type == RMX_OFF)
		1382	radeon_crtc->rmx_type = RMX_OFF;
		1383	else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay \|\|
		1384	mode->vdisplay < radeon_encoder->native_mode.vdisplay)
6938	serge	1385	radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1404	serge	1386	else
		1387	radeon_crtc->rmx_type = RMX_OFF;
		1388	/* copy native mode */
1179	serge	1389	memcpy(&radeon_crtc->native_mode,
6938	serge	1390	&radeon_encoder->native_mode,
1268	serge	1391	sizeof(struct drm_display_mode));
1963	serge	1392	src_v = crtc->mode.vdisplay;
		1393	dst_v = radeon_crtc->native_mode.vdisplay;
		1394	src_h = crtc->mode.hdisplay;
		1395	dst_h = radeon_crtc->native_mode.hdisplay;
		1396
		1397	/* fix up for overscan on hdmi */
		1398	if (ASIC_IS_AVIVO(rdev) &&
		1399	(!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
		1400	((radeon_encoder->underscan_type == UNDERSCAN_ON) \|\|
		1401	((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
5078	serge	1402	drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1963	serge	1403	is_hdtv_mode(mode)))) {
		1404	if (radeon_encoder->underscan_hborder != 0)
		1405	radeon_crtc->h_border = radeon_encoder->underscan_hborder;
		1406	else
6938	serge	1407	radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1963	serge	1408	if (radeon_encoder->underscan_vborder != 0)
		1409	radeon_crtc->v_border = radeon_encoder->underscan_vborder;
		1410	else
6938	serge	1411	radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1963	serge	1412	radeon_crtc->rmx_type = RMX_FULL;
		1413	src_v = crtc->mode.vdisplay;
		1414	dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
		1415	src_h = crtc->mode.hdisplay;
		1416	dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
		1417	}
1179	serge	1418	first = false;
		1419	} else {
		1420	if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
		1421	/* WARNING: Right now this can't happen but
		1422	* in the future we need to check that scaling
1963	serge	1423	* are consistent across different encoder
1179	serge	1424	* (ie all encoder can work with the same
		1425	* scaling).
		1426	*/
1963	serge	1427	DRM_ERROR("Scaling not consistent across encoder.\n");
1179	serge	1428	return false;
		1429	}
1123	serge	1430	}
		1431	}
1179	serge	1432	if (radeon_crtc->rmx_type != RMX_OFF) {
6938	serge	1433	fixed20_12 a, b;
1963	serge	1434	a.full = dfixed_const(src_v);
		1435	b.full = dfixed_const(dst_v);
		1436	radeon_crtc->vsc.full = dfixed_div(a, b);
		1437	a.full = dfixed_const(src_h);
		1438	b.full = dfixed_const(dst_h);
		1439	radeon_crtc->hsc.full = dfixed_div(a, b);
1123	serge	1440	} else {
1963	serge	1441	radeon_crtc->vsc.full = dfixed_const(1);
		1442	radeon_crtc->hsc.full = dfixed_const(1);
1123	serge	1443	}
1179	serge	1444	return true;
1123	serge	1445	}
1963	serge	1446
		1447	/*
5078	serge	1448	* Retrieve current video scanout position of crtc on a given gpu, and
		1449	* an optional accurate timestamp of when query happened.
1963	serge	1450	*
		1451	* \param dev Device to query.
		1452	* \param crtc Crtc to query.
5078	serge	1453	* \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
6321	serge	1454	* For driver internal use only also supports these flags:
		1455	*
		1456	* USE_REAL_VBLANKSTART to use the real start of vblank instead
		1457	* of a fudged earlier start of vblank.
		1458	*
		1459	* GET_DISTANCE_TO_VBLANKSTART to return distance to the
		1460	* fudged earlier start of vblank in *vpos and the distance
		1461	* to true start of vblank in *hpos.
		1462	*
1963	serge	1463	* \param *vpos Location where vertical scanout position should be stored.
		1464	* \param *hpos Location where horizontal scanout position should go.
5078	serge	1465	* \param *stime Target location for timestamp taken immediately before
		1466	* scanout position query. Can be NULL to skip timestamp.
		1467	* \param *etime Target location for timestamp taken immediately after
		1468	* scanout position query. Can be NULL to skip timestamp.
1963	serge	1469	*
		1470	* Returns vpos as a positive number while in active scanout area.
		1471	* Returns vpos as a negative number inside vblank, counting the number
		1472	* of scanlines to go until end of vblank, e.g., -1 means "one scanline
		1473	* until start of active scanout / end of vblank."
		1474	*
		1475	* \return Flags, or'ed together as follows:
		1476	*
		1477	* DRM_SCANOUTPOS_VALID = Query successful.
		1478	* DRM_SCANOUTPOS_INVBL = Inside vblank.
		1479	* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
		1480	* this flag means that returned position may be offset by a constant but
		1481	* unknown small number of scanlines wrt. real scanout position.
		1482	*
		1483	*/
6104	serge	1484	int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
		1485	unsigned int flags, int vpos, int hpos,
		1486	ktime_t stime, ktime_t etime,
		1487	const struct drm_display_mode *mode)
1963	serge	1488	{
		1489	u32 stat_crtc = 0, vbl = 0, position = 0;
		1490	int vbl_start, vbl_end, vtotal, ret = 0;
		1491	bool in_vbl = true;
		1492
		1493	struct radeon_device *rdev = dev->dev_private;
		1494
6104	serge	1495	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
		1496
		1497	/* Get optional system timestamp before query. */
		1498	if (stime)
		1499	*stime = ktime_get();
		1500
1963	serge	1501	if (ASIC_IS_DCE4(rdev)) {
6104	serge	1502	if (pipe == 0) {
1963	serge	1503	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1504	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1505	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1506	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1507	ret \|= DRM_SCANOUTPOS_VALID;
		1508	}
6104	serge	1509	if (pipe == 1) {
1963	serge	1510	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1511	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1512	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1513	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1514	ret \|= DRM_SCANOUTPOS_VALID;
		1515	}
6104	serge	1516	if (pipe == 2) {
1963	serge	1517	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1518	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1519	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1520	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1521	ret \|= DRM_SCANOUTPOS_VALID;
		1522	}
6104	serge	1523	if (pipe == 3) {
1963	serge	1524	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1525	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1526	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1527	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1528	ret \|= DRM_SCANOUTPOS_VALID;
		1529	}
6104	serge	1530	if (pipe == 4) {
1963	serge	1531	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1532	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1533	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1534	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1535	ret \|= DRM_SCANOUTPOS_VALID;
		1536	}
6104	serge	1537	if (pipe == 5) {
1963	serge	1538	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1539	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1540	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1541	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1542	ret \|= DRM_SCANOUTPOS_VALID;
		1543	}
		1544	} else if (ASIC_IS_AVIVO(rdev)) {
6104	serge	1545	if (pipe == 0) {
1963	serge	1546	vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
		1547	position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
		1548	ret \|= DRM_SCANOUTPOS_VALID;
		1549	}
6104	serge	1550	if (pipe == 1) {
1963	serge	1551	vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
		1552	position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
		1553	ret \|= DRM_SCANOUTPOS_VALID;
		1554	}
		1555	} else {
		1556	/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
6104	serge	1557	if (pipe == 0) {
1963	serge	1558	/* Assume vbl_end == 0, get vbl_start from
		1559	* upper 16 bits.
		1560	*/
		1561	vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
		1562	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1563	/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
		1564	position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1565	stat_crtc = RREG32(RADEON_CRTC_STATUS);
		1566	if (!(stat_crtc & 1))
		1567	in_vbl = false;
		1568
		1569	ret \|= DRM_SCANOUTPOS_VALID;
		1570	}
6104	serge	1571	if (pipe == 1) {
1963	serge	1572	vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
		1573	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1574	position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1575	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
		1576	if (!(stat_crtc & 1))
		1577	in_vbl = false;
		1578
		1579	ret \|= DRM_SCANOUTPOS_VALID;
		1580	}
		1581	}
		1582
6104	serge	1583	/* Get optional system timestamp after query. */
		1584	if (etime)
		1585	*etime = ktime_get();
		1586
		1587	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
		1588
1963	serge	1589	/* Decode into vertical and horizontal scanout position. */
		1590	*vpos = position & 0x1fff;
		1591	*hpos = (position >> 16) & 0x1fff;
		1592
		1593	/* Valid vblank area boundaries from gpu retrieved? */
		1594	if (vbl > 0) {
		1595	/* Yes: Decode. */
		1596	ret \|= DRM_SCANOUTPOS_ACCURATE;
		1597	vbl_start = vbl & 0x1fff;
		1598	vbl_end = (vbl >> 16) & 0x1fff;
		1599	}
		1600	else {
		1601	/* No: Fake something reasonable which gives at least ok results. */
6104	serge	1602	vbl_start = mode->crtc_vdisplay;
1963	serge	1603	vbl_end = 0;
		1604	}
		1605
6321	serge	1606	/* Called from driver internal vblank counter query code? */
		1607	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
		1608	/* Caller wants distance from real vbl_start in hpos /
		1609	hpos = vpos - vbl_start;
		1610	}
		1611
		1612	/* Fudge vblank to start a few scanlines earlier to handle the
		1613	* problem that vblank irqs fire a few scanlines before start
		1614	* of vblank. Some driver internal callers need the true vblank
		1615	* start to be used and signal this via the USE_REAL_VBLANKSTART flag.
		1616	*
		1617	* The cause of the "early" vblank irq is that the irq is triggered
		1618	* by the line buffer logic when the line buffer read position enters
		1619	* the vblank, whereas our crtc scanout position naturally lags the
		1620	* line buffer read position.
		1621	*/
		1622	if (!(flags & USE_REAL_VBLANKSTART))
		1623	vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
		1624
1963	serge	1625	/* Test scanout position against vblank region. */
		1626	if ((vpos < vbl_start) && (vpos >= vbl_end))
		1627	in_vbl = false;
		1628
6321	serge	1629	/* In vblank? */
		1630	if (in_vbl)
		1631	ret \|= DRM_SCANOUTPOS_IN_VBLANK;
		1632
		1633	/* Called from driver internal vblank counter query code? */
		1634	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
		1635	/* Caller wants distance from fudged earlier vbl_start */
		1636	*vpos -= vbl_start;
		1637	return ret;
		1638	}
		1639
1963	serge	1640	/* Check if inside vblank area and apply corrective offsets:
		1641	* vpos will then be >=0 in video scanout area, but negative
		1642	* within vblank area, counting down the number of lines until
		1643	* start of scanout.
		1644	*/
		1645
		1646	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
		1647	if (in_vbl && (*vpos >= vbl_start)) {
6104	serge	1648	vtotal = mode->crtc_vtotal;
1963	serge	1649	vpos = vpos - vtotal;
		1650	}
		1651
		1652	/* Correct for shifted end of vbl at vbl_end. */
		1653	vpos = vpos - vbl_end;
		1654
		1655	return ret;
		1656	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_display.c – Rev 7146