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Rev | Author | Line No. | Line |
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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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2997 | Serge | 26 | #include |
27 | #include |
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1123 | serge | 28 | #include "radeon.h" |
29 | |||
30 | #include "atom.h" |
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1963 | serge | 31 | #include |
1123 | serge | 32 | |
2997 | Serge | 33 | #include |
34 | #include |
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1123 | serge | 35 | |
36 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
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37 | { |
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38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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39 | struct drm_device *dev = crtc->dev; |
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40 | struct radeon_device *rdev = dev->dev_private; |
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41 | int i; |
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42 | |||
1963 | serge | 43 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
1123 | serge | 44 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
45 | |||
46 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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47 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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49 | |||
50 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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51 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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53 | |||
54 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
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55 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
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56 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
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57 | |||
58 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
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59 | for (i = 0; i < 256; i++) { |
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60 | WREG32(AVIVO_DC_LUT_30_COLOR, |
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61 | (radeon_crtc->lut_r[i] << 20) | |
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62 | (radeon_crtc->lut_g[i] << 10) | |
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63 | (radeon_crtc->lut_b[i] << 0)); |
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64 | } |
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65 | |||
66 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
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67 | } |
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68 | |||
1963 | serge | 69 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
1430 | serge | 70 | { |
71 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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72 | struct drm_device *dev = crtc->dev; |
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73 | struct radeon_device *rdev = dev->dev_private; |
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74 | int i; |
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75 | |||
1963 | serge | 76 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
1430 | serge | 77 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
78 | |||
79 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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80 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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82 | |||
83 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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84 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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86 | |||
1963 | serge | 87 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
88 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
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1430 | serge | 89 | |
1963 | serge | 90 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
1430 | serge | 91 | for (i = 0; i < 256; i++) { |
1963 | serge | 92 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
1430 | serge | 93 | (radeon_crtc->lut_r[i] << 20) | |
94 | (radeon_crtc->lut_g[i] << 10) | |
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95 | (radeon_crtc->lut_b[i] << 0)); |
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96 | } |
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97 | } |
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98 | |||
1963 | serge | 99 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
100 | { |
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101 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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102 | struct drm_device *dev = crtc->dev; |
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103 | struct radeon_device *rdev = dev->dev_private; |
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104 | int i; |
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105 | |||
106 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
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107 | |||
108 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
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109 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
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110 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
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111 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
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112 | NI_GRPH_PRESCALE_BYPASS); |
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113 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
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114 | NI_OVL_PRESCALE_BYPASS); |
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115 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
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116 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
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117 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
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118 | |||
119 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
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120 | |||
121 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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122 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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124 | |||
125 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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126 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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128 | |||
129 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
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130 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
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131 | |||
132 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
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133 | for (i = 0; i < 256; i++) { |
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134 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
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135 | (radeon_crtc->lut_r[i] << 20) | |
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136 | (radeon_crtc->lut_g[i] << 10) | |
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137 | (radeon_crtc->lut_b[i] << 0)); |
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138 | } |
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139 | |||
140 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
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141 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
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142 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
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143 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
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144 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
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145 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
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146 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
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147 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
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148 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
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149 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
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150 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
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151 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
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152 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | |
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153 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
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154 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
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155 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
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156 | |||
157 | } |
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158 | |||
1123 | serge | 159 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
160 | { |
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161 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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162 | struct drm_device *dev = crtc->dev; |
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163 | struct radeon_device *rdev = dev->dev_private; |
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164 | int i; |
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165 | uint32_t dac2_cntl; |
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166 | |||
167 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
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168 | if (radeon_crtc->crtc_id == 0) |
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169 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
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170 | else |
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171 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
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172 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
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173 | |||
174 | WREG8(RADEON_PALETTE_INDEX, 0); |
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175 | for (i = 0; i < 256; i++) { |
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176 | WREG32(RADEON_PALETTE_30_DATA, |
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177 | (radeon_crtc->lut_r[i] << 20) | |
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178 | (radeon_crtc->lut_g[i] << 10) | |
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179 | (radeon_crtc->lut_b[i] << 0)); |
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180 | } |
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181 | } |
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182 | |||
183 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
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184 | { |
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185 | struct drm_device *dev = crtc->dev; |
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186 | struct radeon_device *rdev = dev->dev_private; |
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187 | |||
188 | if (!crtc->enabled) |
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189 | return; |
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190 | |||
1963 | serge | 191 | if (ASIC_IS_DCE5(rdev)) |
192 | dce5_crtc_load_lut(crtc); |
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193 | else if (ASIC_IS_DCE4(rdev)) |
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194 | dce4_crtc_load_lut(crtc); |
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1430 | serge | 195 | else if (ASIC_IS_AVIVO(rdev)) |
1123 | serge | 196 | avivo_crtc_load_lut(crtc); |
197 | else |
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198 | legacy_crtc_load_lut(crtc); |
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199 | } |
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200 | |||
1221 | serge | 201 | /** Sets the color ramps on behalf of fbcon */ |
1123 | serge | 202 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
203 | u16 blue, int regno) |
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204 | { |
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205 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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206 | |||
207 | radeon_crtc->lut_r[regno] = red >> 6; |
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208 | radeon_crtc->lut_g[regno] = green >> 6; |
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209 | radeon_crtc->lut_b[regno] = blue >> 6; |
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210 | } |
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211 | |||
1221 | serge | 212 | /** Gets the color ramps on behalf of fbcon */ |
213 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
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214 | u16 *blue, int regno) |
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215 | { |
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216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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217 | |||
218 | *red = radeon_crtc->lut_r[regno] << 6; |
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219 | *green = radeon_crtc->lut_g[regno] << 6; |
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220 | *blue = radeon_crtc->lut_b[regno] << 6; |
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221 | } |
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222 | |||
1123 | serge | 223 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
1963 | serge | 224 | u16 *blue, uint32_t start, uint32_t size) |
1123 | serge | 225 | { |
226 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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1963 | serge | 227 | int end = (start + size > 256) ? 256 : start + size, i; |
1123 | serge | 228 | |
1221 | serge | 229 | /* userspace palettes are always correct as is */ |
1963 | serge | 230 | for (i = start; i < end; i++) { |
1123 | serge | 231 | radeon_crtc->lut_r[i] = red[i] >> 6; |
232 | radeon_crtc->lut_g[i] = green[i] >> 6; |
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233 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
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234 | } |
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235 | radeon_crtc_load_lut(crtc); |
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236 | } |
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237 | |||
238 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
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239 | { |
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240 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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241 | |||
242 | drm_crtc_cleanup(crtc); |
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243 | kfree(radeon_crtc); |
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244 | } |
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245 | |||
246 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
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1221 | serge | 247 | .cursor_set = NULL, |
248 | .cursor_move = NULL, |
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1123 | serge | 249 | .gamma_set = radeon_crtc_gamma_set, |
1126 | serge | 250 | .set_config = drm_crtc_helper_set_config, |
1123 | serge | 251 | .destroy = radeon_crtc_destroy, |
1963 | serge | 252 | .page_flip = NULL, |
1123 | serge | 253 | }; |
254 | |||
255 | static void radeon_crtc_init(struct drm_device *dev, int index) |
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256 | { |
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257 | struct radeon_device *rdev = dev->dev_private; |
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258 | struct radeon_crtc *radeon_crtc; |
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259 | int i; |
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260 | |||
261 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
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262 | if (radeon_crtc == NULL) |
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263 | return; |
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264 | |||
265 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
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266 | |||
267 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
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268 | radeon_crtc->crtc_id = index; |
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1179 | serge | 269 | rdev->mode_info.crtcs[index] = radeon_crtc; |
1123 | serge | 270 | |
1179 | serge | 271 | #if 0 |
1123 | serge | 272 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
273 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
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274 | radeon_crtc->mode_set.num_connectors = 0; |
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1179 | serge | 275 | #endif |
1123 | serge | 276 | |
277 | for (i = 0; i < 256; i++) { |
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278 | radeon_crtc->lut_r[i] = i << 2; |
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279 | radeon_crtc->lut_g[i] = i << 2; |
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280 | radeon_crtc->lut_b[i] = i << 2; |
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281 | } |
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282 | |||
283 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
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284 | radeon_atombios_init_crtc(dev, radeon_crtc); |
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285 | else |
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286 | radeon_legacy_init_crtc(dev, radeon_crtc); |
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287 | } |
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288 | |||
2997 | Serge | 289 | static const char *encoder_names[37] = { |
1123 | serge | 290 | "NONE", |
291 | "INTERNAL_LVDS", |
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292 | "INTERNAL_TMDS1", |
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293 | "INTERNAL_TMDS2", |
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294 | "INTERNAL_DAC1", |
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295 | "INTERNAL_DAC2", |
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296 | "INTERNAL_SDVOA", |
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297 | "INTERNAL_SDVOB", |
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298 | "SI170B", |
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299 | "CH7303", |
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300 | "CH7301", |
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301 | "INTERNAL_DVO1", |
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302 | "EXTERNAL_SDVOA", |
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303 | "EXTERNAL_SDVOB", |
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304 | "TITFP513", |
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305 | "INTERNAL_LVTM1", |
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306 | "VT1623", |
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307 | "HDMI_SI1930", |
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308 | "HDMI_INTERNAL", |
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309 | "INTERNAL_KLDSCP_TMDS1", |
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310 | "INTERNAL_KLDSCP_DVO1", |
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311 | "INTERNAL_KLDSCP_DAC1", |
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312 | "INTERNAL_KLDSCP_DAC2", |
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313 | "SI178", |
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314 | "MVPU_FPGA", |
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315 | "INTERNAL_DDI", |
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316 | "VT1625", |
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317 | "HDMI_SI1932", |
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318 | "DP_AN9801", |
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319 | "DP_DP501", |
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320 | "INTERNAL_UNIPHY", |
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321 | "INTERNAL_KLDSCP_LVTMA", |
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322 | "INTERNAL_UNIPHY1", |
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323 | "INTERNAL_UNIPHY2", |
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1963 | serge | 324 | "NUTMEG", |
325 | "TRAVIS", |
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2997 | Serge | 326 | "INTERNAL_VCE" |
1123 | serge | 327 | }; |
328 | |||
1963 | serge | 329 | static const char *hpd_names[6] = { |
1404 | serge | 330 | "HPD1", |
331 | "HPD2", |
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332 | "HPD3", |
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333 | "HPD4", |
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334 | "HPD5", |
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335 | "HPD6", |
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336 | }; |
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337 | |||
1123 | serge | 338 | static void radeon_print_display_setup(struct drm_device *dev) |
339 | { |
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340 | struct drm_connector *connector; |
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341 | struct radeon_connector *radeon_connector; |
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342 | struct drm_encoder *encoder; |
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343 | struct radeon_encoder *radeon_encoder; |
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344 | uint32_t devices; |
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345 | int i = 0; |
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346 | |||
347 | DRM_INFO("Radeon Display Connectors\n"); |
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348 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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349 | radeon_connector = to_radeon_connector(connector); |
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350 | DRM_INFO("Connector %d:\n", i); |
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2997 | Serge | 351 | DRM_INFO(" %s\n", drm_get_connector_name(connector)); |
1404 | serge | 352 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
353 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
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354 | if (radeon_connector->ddc_bus) { |
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1123 | serge | 355 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
356 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
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357 | radeon_connector->ddc_bus->rec.mask_data_reg, |
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358 | radeon_connector->ddc_bus->rec.a_clk_reg, |
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359 | radeon_connector->ddc_bus->rec.a_data_reg, |
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1404 | serge | 360 | radeon_connector->ddc_bus->rec.en_clk_reg, |
361 | radeon_connector->ddc_bus->rec.en_data_reg, |
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362 | radeon_connector->ddc_bus->rec.y_clk_reg, |
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363 | radeon_connector->ddc_bus->rec.y_data_reg); |
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1963 | serge | 364 | if (radeon_connector->router.ddc_valid) |
365 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
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366 | radeon_connector->router.ddc_mux_control_pin, |
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367 | radeon_connector->router.ddc_mux_state); |
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368 | if (radeon_connector->router.cd_valid) |
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369 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
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370 | radeon_connector->router.cd_mux_control_pin, |
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371 | radeon_connector->router.cd_mux_state); |
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1404 | serge | 372 | } else { |
373 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
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374 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
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375 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
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376 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
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377 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
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378 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
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379 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
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380 | } |
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1123 | serge | 381 | DRM_INFO(" Encoders:\n"); |
382 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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383 | radeon_encoder = to_radeon_encoder(encoder); |
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384 | devices = radeon_encoder->devices & radeon_connector->devices; |
||
385 | if (devices) { |
||
386 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
||
387 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
388 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
||
389 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
390 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
||
391 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
392 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
||
393 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
394 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
||
395 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
396 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
||
397 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
398 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
||
399 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
400 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
||
401 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
1963 | serge | 402 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
403 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
1123 | serge | 404 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
405 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
406 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
||
407 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
408 | } |
||
409 | } |
||
410 | i++; |
||
411 | } |
||
412 | } |
||
413 | |||
1179 | serge | 414 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
1123 | serge | 415 | { |
416 | struct radeon_device *rdev = dev->dev_private; |
||
417 | bool ret = false; |
||
418 | |||
419 | if (rdev->bios) { |
||
420 | if (rdev->is_atom_bios) { |
||
1963 | serge | 421 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
422 | if (ret == false) |
||
1123 | serge | 423 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
1404 | serge | 424 | } else { |
1123 | serge | 425 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
1404 | serge | 426 | if (ret == false) |
427 | ret = radeon_get_legacy_connector_info_from_table(dev); |
||
428 | } |
||
1123 | serge | 429 | } else { |
430 | if (!ASIC_IS_AVIVO(rdev)) |
||
431 | ret = radeon_get_legacy_connector_info_from_table(dev); |
||
432 | } |
||
433 | if (ret) { |
||
1404 | serge | 434 | radeon_setup_encoder_clones(dev); |
1123 | serge | 435 | radeon_print_display_setup(dev); |
436 | } |
||
437 | |||
438 | return ret; |
||
439 | } |
||
440 | |||
441 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
||
442 | { |
||
1430 | serge | 443 | struct drm_device *dev = radeon_connector->base.dev; |
444 | struct radeon_device *rdev = dev->dev_private; |
||
1123 | serge | 445 | int ret = 0; |
446 | |||
1963 | serge | 447 | /* on hw with routers, select right port */ |
448 | if (radeon_connector->router.ddc_valid) |
||
449 | radeon_router_select_ddc_port(radeon_connector); |
||
450 | |||
3192 | Serge | 451 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != |
452 | ENCODER_OBJECT_ID_NONE) { |
||
1404 | serge | 453 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
2997 | Serge | 454 | |
3192 | Serge | 455 | if (dig->dp_i2c_bus) |
456 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
||
457 | &dig->dp_i2c_bus->adapter); |
||
458 | } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
||
459 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
||
460 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
||
461 | |||
1404 | serge | 462 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
463 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
||
2997 | Serge | 464 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
465 | &dig->dp_i2c_bus->adapter); |
||
466 | else if (radeon_connector->ddc_bus && !radeon_connector->edid) |
||
467 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
||
468 | &radeon_connector->ddc_bus->adapter); |
||
469 | } else { |
||
470 | if (radeon_connector->ddc_bus && !radeon_connector->edid) |
||
471 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, |
||
472 | &radeon_connector->ddc_bus->adapter); |
||
1404 | serge | 473 | } |
1963 | serge | 474 | |
475 | if (!radeon_connector->edid) { |
||
476 | if (rdev->is_atom_bios) { |
||
477 | /* some laptops provide a hardcoded edid in rom for LCDs */ |
||
478 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || |
||
479 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) |
||
480 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
||
481 | } else |
||
1430 | serge | 482 | /* some servers provide a hardcoded edid in rom for KVMs */ |
1963 | serge | 483 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
484 | } |
||
1268 | serge | 485 | if (radeon_connector->edid) { |
486 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
||
487 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
||
1123 | serge | 488 | return ret; |
489 | } |
||
490 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
||
1179 | serge | 491 | return 0; |
1123 | serge | 492 | } |
493 | |||
1963 | serge | 494 | /* avivo */ |
495 | static void avivo_get_fb_div(struct radeon_pll *pll, |
||
496 | u32 target_clock, |
||
497 | u32 post_div, |
||
498 | u32 ref_div, |
||
499 | u32 *fb_div, |
||
500 | u32 *frac_fb_div) |
||
501 | { |
||
502 | u32 tmp = post_div * ref_div; |
||
503 | |||
504 | tmp *= target_clock; |
||
505 | *fb_div = tmp / pll->reference_freq; |
||
506 | *frac_fb_div = tmp % pll->reference_freq; |
||
507 | |||
508 | if (*fb_div > pll->max_feedback_div) |
||
509 | *fb_div = pll->max_feedback_div; |
||
510 | else if (*fb_div < pll->min_feedback_div) |
||
511 | *fb_div = pll->min_feedback_div; |
||
512 | } |
||
513 | |||
514 | static u32 avivo_get_post_div(struct radeon_pll *pll, |
||
515 | u32 target_clock) |
||
516 | { |
||
517 | u32 vco, post_div, tmp; |
||
518 | |||
519 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
||
520 | return pll->post_div; |
||
521 | |||
522 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
||
523 | if (pll->flags & RADEON_PLL_IS_LCD) |
||
524 | vco = pll->lcd_pll_out_min; |
||
525 | else |
||
526 | vco = pll->pll_out_min; |
||
527 | } else { |
||
528 | if (pll->flags & RADEON_PLL_IS_LCD) |
||
529 | vco = pll->lcd_pll_out_max; |
||
530 | else |
||
531 | vco = pll->pll_out_max; |
||
532 | } |
||
533 | |||
534 | post_div = vco / target_clock; |
||
535 | tmp = vco % target_clock; |
||
536 | |||
537 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
||
538 | if (tmp) |
||
539 | post_div++; |
||
540 | } else { |
||
541 | if (!tmp) |
||
542 | post_div--; |
||
543 | } |
||
544 | |||
545 | if (post_div > pll->max_post_div) |
||
546 | post_div = pll->max_post_div; |
||
547 | else if (post_div < pll->min_post_div) |
||
548 | post_div = pll->min_post_div; |
||
549 | |||
550 | return post_div; |
||
551 | } |
||
552 | |||
553 | #define MAX_TOLERANCE 10 |
||
554 | |||
555 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
||
556 | u32 freq, |
||
557 | u32 *dot_clock_p, |
||
558 | u32 *fb_div_p, |
||
559 | u32 *frac_fb_div_p, |
||
560 | u32 *ref_div_p, |
||
561 | u32 *post_div_p) |
||
562 | { |
||
563 | u32 target_clock = freq / 10; |
||
564 | u32 post_div = avivo_get_post_div(pll, target_clock); |
||
565 | u32 ref_div = pll->min_ref_div; |
||
566 | u32 fb_div = 0, frac_fb_div = 0, tmp; |
||
567 | |||
568 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
||
569 | ref_div = pll->reference_div; |
||
570 | |||
571 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
572 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); |
||
573 | frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; |
||
574 | if (frac_fb_div >= 5) { |
||
575 | frac_fb_div -= 5; |
||
576 | frac_fb_div = frac_fb_div / 10; |
||
577 | frac_fb_div++; |
||
578 | } |
||
579 | if (frac_fb_div >= 10) { |
||
580 | fb_div++; |
||
581 | frac_fb_div = 0; |
||
582 | } |
||
583 | } else { |
||
584 | while (ref_div <= pll->max_ref_div) { |
||
585 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, |
||
586 | &fb_div, &frac_fb_div); |
||
587 | if (frac_fb_div >= (pll->reference_freq / 2)) |
||
588 | fb_div++; |
||
589 | frac_fb_div = 0; |
||
590 | tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); |
||
591 | tmp = (tmp * 10000) / target_clock; |
||
592 | |||
593 | if (tmp > (10000 + MAX_TOLERANCE)) |
||
594 | ref_div++; |
||
595 | else if (tmp >= (10000 - MAX_TOLERANCE)) |
||
596 | break; |
||
597 | else |
||
598 | ref_div++; |
||
599 | } |
||
600 | } |
||
601 | |||
602 | *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / |
||
603 | (ref_div * post_div * 10); |
||
604 | *fb_div_p = fb_div; |
||
605 | *frac_fb_div_p = frac_fb_div; |
||
606 | *ref_div_p = ref_div; |
||
607 | *post_div_p = post_div; |
||
608 | DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
||
609 | *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); |
||
610 | } |
||
611 | |||
612 | /* pre-avivo */ |
||
1123 | serge | 613 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
614 | { |
||
615 | uint64_t mod; |
||
616 | |||
617 | n += d / 2; |
||
618 | |||
619 | mod = do_div(n, d); |
||
620 | return n; |
||
621 | } |
||
622 | |||
1963 | serge | 623 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
1123 | serge | 624 | uint64_t freq, |
625 | uint32_t *dot_clock_p, |
||
626 | uint32_t *fb_div_p, |
||
627 | uint32_t *frac_fb_div_p, |
||
628 | uint32_t *ref_div_p, |
||
1404 | serge | 629 | uint32_t *post_div_p) |
1123 | serge | 630 | { |
631 | uint32_t min_ref_div = pll->min_ref_div; |
||
632 | uint32_t max_ref_div = pll->max_ref_div; |
||
1404 | serge | 633 | uint32_t min_post_div = pll->min_post_div; |
634 | uint32_t max_post_div = pll->max_post_div; |
||
1123 | serge | 635 | uint32_t min_fractional_feed_div = 0; |
636 | uint32_t max_fractional_feed_div = 0; |
||
637 | uint32_t best_vco = pll->best_vco; |
||
638 | uint32_t best_post_div = 1; |
||
639 | uint32_t best_ref_div = 1; |
||
640 | uint32_t best_feedback_div = 1; |
||
641 | uint32_t best_frac_feedback_div = 0; |
||
642 | uint32_t best_freq = -1; |
||
643 | uint32_t best_error = 0xffffffff; |
||
644 | uint32_t best_vco_diff = 1; |
||
645 | uint32_t post_div; |
||
1963 | serge | 646 | u32 pll_out_min, pll_out_max; |
1123 | serge | 647 | |
1963 | serge | 648 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
1123 | serge | 649 | freq = freq * 1000; |
650 | |||
1963 | serge | 651 | if (pll->flags & RADEON_PLL_IS_LCD) { |
652 | pll_out_min = pll->lcd_pll_out_min; |
||
653 | pll_out_max = pll->lcd_pll_out_max; |
||
654 | } else { |
||
655 | pll_out_min = pll->pll_out_min; |
||
656 | pll_out_max = pll->pll_out_max; |
||
657 | } |
||
658 | |||
659 | if (pll_out_min > 64800) |
||
660 | pll_out_min = 64800; |
||
661 | |||
1404 | serge | 662 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
1123 | serge | 663 | min_ref_div = max_ref_div = pll->reference_div; |
664 | else { |
||
665 | while (min_ref_div < max_ref_div-1) { |
||
666 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
||
667 | uint32_t pll_in = pll->reference_freq / mid; |
||
668 | if (pll_in < pll->pll_in_min) |
||
669 | max_ref_div = mid; |
||
670 | else if (pll_in > pll->pll_in_max) |
||
671 | min_ref_div = mid; |
||
672 | else |
||
673 | break; |
||
674 | } |
||
675 | } |
||
676 | |||
1404 | serge | 677 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
678 | min_post_div = max_post_div = pll->post_div; |
||
679 | |||
680 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
1123 | serge | 681 | min_fractional_feed_div = pll->min_frac_feedback_div; |
682 | max_fractional_feed_div = pll->max_frac_feedback_div; |
||
683 | } |
||
684 | |||
1963 | serge | 685 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
1123 | serge | 686 | uint32_t ref_div; |
687 | |||
1404 | serge | 688 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
1123 | serge | 689 | continue; |
690 | |||
691 | /* legacy radeons only have a few post_divs */ |
||
1404 | serge | 692 | if (pll->flags & RADEON_PLL_LEGACY) { |
1123 | serge | 693 | if ((post_div == 5) || |
694 | (post_div == 7) || |
||
695 | (post_div == 9) || |
||
696 | (post_div == 10) || |
||
697 | (post_div == 11) || |
||
698 | (post_div == 13) || |
||
699 | (post_div == 14) || |
||
700 | (post_div == 15)) |
||
701 | continue; |
||
702 | } |
||
703 | |||
704 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
||
705 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
||
706 | uint32_t pll_in = pll->reference_freq / ref_div; |
||
707 | uint32_t min_feed_div = pll->min_feedback_div; |
||
708 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
||
709 | |||
710 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
||
711 | continue; |
||
712 | |||
713 | while (min_feed_div < max_feed_div) { |
||
714 | uint32_t vco; |
||
715 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
||
716 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
||
717 | uint32_t frac_feedback_div; |
||
718 | uint64_t tmp; |
||
719 | |||
720 | feedback_div = (min_feed_div + max_feed_div) / 2; |
||
721 | |||
722 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
||
723 | vco = radeon_div(tmp, ref_div); |
||
724 | |||
1963 | serge | 725 | if (vco < pll_out_min) { |
1123 | serge | 726 | min_feed_div = feedback_div + 1; |
727 | continue; |
||
1963 | serge | 728 | } else if (vco > pll_out_max) { |
1123 | serge | 729 | max_feed_div = feedback_div; |
730 | continue; |
||
731 | } |
||
732 | |||
733 | while (min_frac_feed_div < max_frac_feed_div) { |
||
734 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
||
735 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
||
736 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
||
737 | current_freq = radeon_div(tmp, ref_div * post_div); |
||
738 | |||
1404 | serge | 739 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
1963 | serge | 740 | if (freq < current_freq) |
741 | error = 0xffffffff; |
||
742 | else |
||
1179 | serge | 743 | error = freq - current_freq; |
744 | } else |
||
1123 | serge | 745 | error = abs(current_freq - freq); |
746 | vco_diff = abs(vco - best_vco); |
||
747 | |||
748 | if ((best_vco == 0 && error < best_error) || |
||
749 | (best_vco != 0 && |
||
1963 | serge | 750 | ((best_error > 100 && error < best_error - 100) || |
1123 | serge | 751 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
752 | best_post_div = post_div; |
||
753 | best_ref_div = ref_div; |
||
754 | best_feedback_div = feedback_div; |
||
755 | best_frac_feedback_div = frac_feedback_div; |
||
756 | best_freq = current_freq; |
||
757 | best_error = error; |
||
758 | best_vco_diff = vco_diff; |
||
759 | } else if (current_freq == freq) { |
||
760 | if (best_freq == -1) { |
||
761 | best_post_div = post_div; |
||
762 | best_ref_div = ref_div; |
||
763 | best_feedback_div = feedback_div; |
||
764 | best_frac_feedback_div = frac_feedback_div; |
||
765 | best_freq = current_freq; |
||
766 | best_error = error; |
||
767 | best_vco_diff = vco_diff; |
||
1404 | serge | 768 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
769 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
||
770 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
||
771 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
||
772 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
||
773 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
||
1123 | serge | 774 | best_post_div = post_div; |
775 | best_ref_div = ref_div; |
||
776 | best_feedback_div = feedback_div; |
||
777 | best_frac_feedback_div = frac_feedback_div; |
||
778 | best_freq = current_freq; |
||
779 | best_error = error; |
||
780 | best_vco_diff = vco_diff; |
||
781 | } |
||
782 | } |
||
783 | if (current_freq < freq) |
||
784 | min_frac_feed_div = frac_feedback_div + 1; |
||
785 | else |
||
786 | max_frac_feed_div = frac_feedback_div; |
||
787 | } |
||
788 | if (current_freq < freq) |
||
789 | min_feed_div = feedback_div + 1; |
||
790 | else |
||
791 | max_feed_div = feedback_div; |
||
792 | } |
||
793 | } |
||
794 | } |
||
795 | |||
796 | *dot_clock_p = best_freq / 10000; |
||
797 | *fb_div_p = best_feedback_div; |
||
798 | *frac_fb_div_p = best_frac_feedback_div; |
||
799 | *ref_div_p = best_ref_div; |
||
800 | *post_div_p = best_post_div; |
||
1963 | serge | 801 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
802 | (long long)freq, |
||
803 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
||
804 | best_ref_div, best_post_div); |
||
1123 | serge | 805 | |
1430 | serge | 806 | } |
807 | |||
1123 | serge | 808 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
809 | { |
||
810 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
811 | |||
812 | drm_framebuffer_cleanup(fb); |
||
813 | kfree(radeon_fb); |
||
814 | } |
||
815 | |||
816 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
||
817 | struct drm_file *file_priv, |
||
818 | unsigned int *handle) |
||
819 | { |
||
820 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
821 | |||
822 | return NULL; |
||
823 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
||
824 | } |
||
825 | |||
826 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
||
827 | .destroy = radeon_user_framebuffer_destroy, |
||
828 | .create_handle = radeon_user_framebuffer_create_handle, |
||
829 | }; |
||
830 | |||
2997 | Serge | 831 | int |
1963 | serge | 832 | radeon_framebuffer_init(struct drm_device *dev, |
833 | struct radeon_framebuffer *rfb, |
||
2997 | Serge | 834 | struct drm_mode_fb_cmd2 *mode_cmd, |
1123 | serge | 835 | struct drm_gem_object *obj) |
836 | { |
||
2997 | Serge | 837 | int ret; |
1963 | serge | 838 | rfb->obj = obj; |
3764 | Serge | 839 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
2997 | Serge | 840 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
841 | if (ret) { |
||
842 | rfb->obj = NULL; |
||
843 | return ret; |
||
844 | } |
||
845 | return 0; |
||
1123 | serge | 846 | } |
847 | |||
848 | |||
849 | |||
850 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
||
1963 | serge | 851 | // .fb_create = radeon_user_framebuffer_create, |
852 | // .output_poll_changed = radeon_output_poll_changed |
||
1123 | serge | 853 | }; |
854 | |||
1179 | serge | 855 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
856 | { { 0, "driver" }, |
||
857 | { 1, "bios" }, |
||
858 | }; |
||
859 | |||
860 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
||
861 | { { TV_STD_NTSC, "ntsc" }, |
||
862 | { TV_STD_PAL, "pal" }, |
||
863 | { TV_STD_PAL_M, "pal-m" }, |
||
864 | { TV_STD_PAL_60, "pal-60" }, |
||
865 | { TV_STD_NTSC_J, "ntsc-j" }, |
||
866 | { TV_STD_SCART_PAL, "scart-pal" }, |
||
867 | { TV_STD_PAL_CN, "pal-cn" }, |
||
868 | { TV_STD_SECAM, "secam" }, |
||
869 | }; |
||
870 | |||
1963 | serge | 871 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
872 | { { UNDERSCAN_OFF, "off" }, |
||
873 | { UNDERSCAN_ON, "on" }, |
||
874 | { UNDERSCAN_AUTO, "auto" }, |
||
875 | }; |
||
876 | |||
1404 | serge | 877 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
1123 | serge | 878 | { |
2997 | Serge | 879 | int sz; |
1125 | serge | 880 | |
1179 | serge | 881 | if (rdev->is_atom_bios) { |
882 | rdev->mode_info.coherent_mode_property = |
||
2997 | Serge | 883 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
1179 | serge | 884 | if (!rdev->mode_info.coherent_mode_property) |
885 | return -ENOMEM; |
||
886 | } |
||
887 | |||
888 | if (!ASIC_IS_AVIVO(rdev)) { |
||
889 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
||
890 | rdev->mode_info.tmds_pll_property = |
||
2997 | Serge | 891 | drm_property_create_enum(rdev->ddev, 0, |
892 | "tmds_pll", |
||
893 | radeon_tmds_pll_enum_list, sz); |
||
1179 | serge | 894 | } |
895 | |||
896 | rdev->mode_info.load_detect_property = |
||
2997 | Serge | 897 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
1179 | serge | 898 | if (!rdev->mode_info.load_detect_property) |
899 | return -ENOMEM; |
||
900 | |||
901 | drm_mode_create_scaling_mode_property(rdev->ddev); |
||
902 | |||
903 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
||
904 | rdev->mode_info.tv_std_property = |
||
2997 | Serge | 905 | drm_property_create_enum(rdev->ddev, 0, |
906 | "tv standard", |
||
907 | radeon_tv_std_enum_list, sz); |
||
1179 | serge | 908 | |
1963 | serge | 909 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
910 | rdev->mode_info.underscan_property = |
||
2997 | Serge | 911 | drm_property_create_enum(rdev->ddev, 0, |
912 | "underscan", |
||
913 | radeon_underscan_enum_list, sz); |
||
1963 | serge | 914 | |
915 | rdev->mode_info.underscan_hborder_property = |
||
2997 | Serge | 916 | drm_property_create_range(rdev->ddev, 0, |
917 | "underscan hborder", 0, 128); |
||
1963 | serge | 918 | if (!rdev->mode_info.underscan_hborder_property) |
919 | return -ENOMEM; |
||
920 | |||
921 | rdev->mode_info.underscan_vborder_property = |
||
2997 | Serge | 922 | drm_property_create_range(rdev->ddev, 0, |
923 | "underscan vborder", 0, 128); |
||
1963 | serge | 924 | if (!rdev->mode_info.underscan_vborder_property) |
925 | return -ENOMEM; |
||
926 | |||
1179 | serge | 927 | return 0; |
928 | } |
||
929 | |||
1963 | serge | 930 | void radeon_update_display_priority(struct radeon_device *rdev) |
931 | { |
||
932 | /* adjustment options for the display watermarks */ |
||
933 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
||
934 | /* set display priority to high for r3xx, rv515 chips |
||
935 | * this avoids flickering due to underflow to the |
||
936 | * display controllers during heavy acceleration. |
||
937 | * Don't force high on rs4xx igp chips as it seems to |
||
938 | * affect the sound card. See kernel bug 15982. |
||
939 | */ |
||
940 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
||
941 | !(rdev->flags & RADEON_IS_IGP)) |
||
942 | rdev->disp_priority = 2; |
||
943 | else |
||
944 | rdev->disp_priority = 0; |
||
945 | } else |
||
946 | rdev->disp_priority = radeon_disp_priority; |
||
947 | |||
948 | } |
||
949 | |||
2997 | Serge | 950 | /* |
951 | * Allocate hdmi structs and determine register offsets |
||
952 | */ |
||
953 | static void radeon_afmt_init(struct radeon_device *rdev) |
||
954 | { |
||
955 | int i; |
||
956 | |||
957 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) |
||
958 | rdev->mode_info.afmt[i] = NULL; |
||
959 | |||
960 | if (ASIC_IS_DCE6(rdev)) { |
||
961 | /* todo */ |
||
962 | } else if (ASIC_IS_DCE4(rdev)) { |
||
963 | /* DCE4/5 has 6 audio blocks tied to DIG encoders */ |
||
964 | /* DCE4.1 has 2 audio blocks tied to DIG encoders */ |
||
965 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
966 | if (rdev->mode_info.afmt[0]) { |
||
967 | rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
||
968 | rdev->mode_info.afmt[0]->id = 0; |
||
969 | } |
||
970 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
971 | if (rdev->mode_info.afmt[1]) { |
||
972 | rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
||
973 | rdev->mode_info.afmt[1]->id = 1; |
||
974 | } |
||
975 | if (!ASIC_IS_DCE41(rdev)) { |
||
976 | rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
977 | if (rdev->mode_info.afmt[2]) { |
||
978 | rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
||
979 | rdev->mode_info.afmt[2]->id = 2; |
||
980 | } |
||
981 | rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
982 | if (rdev->mode_info.afmt[3]) { |
||
983 | rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
||
984 | rdev->mode_info.afmt[3]->id = 3; |
||
985 | } |
||
986 | rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
987 | if (rdev->mode_info.afmt[4]) { |
||
988 | rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
||
989 | rdev->mode_info.afmt[4]->id = 4; |
||
990 | } |
||
991 | rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
992 | if (rdev->mode_info.afmt[5]) { |
||
993 | rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
||
994 | rdev->mode_info.afmt[5]->id = 5; |
||
995 | } |
||
996 | } |
||
997 | } else if (ASIC_IS_DCE3(rdev)) { |
||
998 | /* DCE3.x has 2 audio blocks tied to DIG encoders */ |
||
999 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1000 | if (rdev->mode_info.afmt[0]) { |
||
1001 | rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; |
||
1002 | rdev->mode_info.afmt[0]->id = 0; |
||
1003 | } |
||
1004 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1005 | if (rdev->mode_info.afmt[1]) { |
||
1006 | rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; |
||
1007 | rdev->mode_info.afmt[1]->id = 1; |
||
1008 | } |
||
1009 | } else if (ASIC_IS_DCE2(rdev)) { |
||
1010 | /* DCE2 has at least 1 routable audio block */ |
||
1011 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1012 | if (rdev->mode_info.afmt[0]) { |
||
1013 | rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; |
||
1014 | rdev->mode_info.afmt[0]->id = 0; |
||
1015 | } |
||
1016 | /* r6xx has 2 routable audio blocks */ |
||
1017 | if (rdev->family >= CHIP_R600) { |
||
1018 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1019 | if (rdev->mode_info.afmt[1]) { |
||
1020 | rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; |
||
1021 | rdev->mode_info.afmt[1]->id = 1; |
||
1022 | } |
||
1023 | } |
||
1024 | } |
||
1025 | } |
||
1026 | |||
1027 | static void radeon_afmt_fini(struct radeon_device *rdev) |
||
1028 | { |
||
1029 | int i; |
||
1030 | |||
1031 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { |
||
1032 | kfree(rdev->mode_info.afmt[i]); |
||
1033 | rdev->mode_info.afmt[i] = NULL; |
||
1034 | } |
||
1035 | } |
||
1036 | |||
1179 | serge | 1037 | int radeon_modeset_init(struct radeon_device *rdev) |
1038 | { |
||
1430 | serge | 1039 | int i; |
1123 | serge | 1040 | int ret; |
1041 | |||
1042 | drm_mode_config_init(rdev->ddev); |
||
1043 | rdev->mode_info.mode_config_initialized = true; |
||
1044 | |||
2997 | Serge | 1045 | rdev->ddev->mode_config.funcs = &radeon_mode_funcs; |
1123 | serge | 1046 | |
1963 | serge | 1047 | if (ASIC_IS_DCE5(rdev)) { |
1048 | rdev->ddev->mode_config.max_width = 16384; |
||
1049 | rdev->ddev->mode_config.max_height = 16384; |
||
1050 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
1123 | serge | 1051 | rdev->ddev->mode_config.max_width = 8192; |
1052 | rdev->ddev->mode_config.max_height = 8192; |
||
1053 | } else { |
||
1054 | rdev->ddev->mode_config.max_width = 4096; |
||
1055 | rdev->ddev->mode_config.max_height = 4096; |
||
1056 | } |
||
1057 | |||
2997 | Serge | 1058 | rdev->ddev->mode_config.preferred_depth = 24; |
1059 | rdev->ddev->mode_config.prefer_shadow = 1; |
||
1060 | |||
1123 | serge | 1061 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1062 | |||
1179 | serge | 1063 | ret = radeon_modeset_create_props(rdev); |
1064 | if (ret) { |
||
1065 | return ret; |
||
1066 | } |
||
1221 | serge | 1067 | |
1963 | serge | 1068 | /* init i2c buses */ |
1069 | radeon_i2c_init(rdev); |
||
1070 | |||
1430 | serge | 1071 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1072 | if (!rdev->is_atom_bios) { |
||
1073 | /* check for hardcoded EDID in BIOS */ |
||
1074 | radeon_combios_check_hardcoded_edid(rdev); |
||
1075 | } |
||
1076 | |||
1221 | serge | 1077 | /* allocate crtcs */ |
1430 | serge | 1078 | for (i = 0; i < rdev->num_crtc; i++) { |
1123 | serge | 1079 | radeon_crtc_init(rdev->ddev, i); |
1080 | } |
||
1081 | |||
1082 | /* okay we should have all the bios connectors */ |
||
1083 | ret = radeon_setup_enc_conn(rdev->ddev); |
||
1084 | if (!ret) { |
||
1085 | return ret; |
||
1086 | } |
||
1963 | serge | 1087 | |
2997 | Serge | 1088 | /* init dig PHYs, disp eng pll */ |
1089 | if (rdev->is_atom_bios) { |
||
1963 | serge | 1090 | radeon_atom_encoder_init(rdev); |
2997 | Serge | 1091 | radeon_atom_disp_eng_pll_init(rdev); |
1092 | } |
||
1963 | serge | 1093 | |
1404 | serge | 1094 | /* initialize hpd */ |
1963 | serge | 1095 | // radeon_hpd_init(rdev); |
1096 | |||
2997 | Serge | 1097 | /* setup afmt */ |
1098 | // radeon_afmt_init(rdev); |
||
1099 | |||
1963 | serge | 1100 | /* Initialize power management */ |
1101 | // radeon_pm_init(rdev); |
||
1102 | |||
1103 | radeon_fbdev_init(rdev); |
||
1104 | // drm_kms_helper_poll_init(rdev->ddev); |
||
1105 | |||
1123 | serge | 1106 | return 0; |
1107 | } |
||
1108 | |||
1109 | void radeon_modeset_fini(struct radeon_device *rdev) |
||
1110 | { |
||
1430 | serge | 1111 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1112 | |||
1123 | serge | 1113 | if (rdev->mode_info.mode_config_initialized) { |
2997 | Serge | 1114 | // radeon_afmt_fini(rdev); |
1963 | serge | 1115 | // drm_kms_helper_poll_fini(rdev->ddev); |
1116 | // radeon_hpd_fini(rdev); |
||
3764 | Serge | 1117 | // drm_mode_config_cleanup(rdev->ddev); |
1123 | serge | 1118 | rdev->mode_info.mode_config_initialized = false; |
1119 | } |
||
1963 | serge | 1120 | /* free i2c buses */ |
1121 | radeon_i2c_fini(rdev); |
||
1123 | serge | 1122 | } |
1123 | |||
2997 | Serge | 1124 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
1963 | serge | 1125 | { |
1126 | /* try and guess if this is a tv or a monitor */ |
||
1127 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
||
1128 | (mode->vdisplay == 576) || /* 576p */ |
||
1129 | (mode->vdisplay == 720) || /* 720p */ |
||
1130 | (mode->vdisplay == 1080)) /* 1080p */ |
||
1131 | return true; |
||
1132 | else |
||
1133 | return false; |
||
1134 | } |
||
1135 | |||
1179 | serge | 1136 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
2997 | Serge | 1137 | const struct drm_display_mode *mode, |
1179 | serge | 1138 | struct drm_display_mode *adjusted_mode) |
1123 | serge | 1139 | { |
1179 | serge | 1140 | struct drm_device *dev = crtc->dev; |
1963 | serge | 1141 | struct radeon_device *rdev = dev->dev_private; |
1179 | serge | 1142 | struct drm_encoder *encoder; |
1123 | serge | 1143 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1179 | serge | 1144 | struct radeon_encoder *radeon_encoder; |
1963 | serge | 1145 | struct drm_connector *connector; |
1146 | struct radeon_connector *radeon_connector; |
||
1179 | serge | 1147 | bool first = true; |
1963 | serge | 1148 | u32 src_v = 1, dst_v = 1; |
1149 | u32 src_h = 1, dst_h = 1; |
||
1123 | serge | 1150 | |
1963 | serge | 1151 | radeon_crtc->h_border = 0; |
1152 | radeon_crtc->v_border = 0; |
||
1153 | |||
1179 | serge | 1154 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1155 | if (encoder->crtc != crtc) |
||
1156 | continue; |
||
1963 | serge | 1157 | radeon_encoder = to_radeon_encoder(encoder); |
1158 | connector = radeon_get_connector_for_encoder(encoder); |
||
1159 | radeon_connector = to_radeon_connector(connector); |
||
1160 | |||
1179 | serge | 1161 | if (first) { |
1404 | serge | 1162 | /* set scaling */ |
1163 | if (radeon_encoder->rmx_type == RMX_OFF) |
||
1164 | radeon_crtc->rmx_type = RMX_OFF; |
||
1165 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
||
1166 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
||
1179 | serge | 1167 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1404 | serge | 1168 | else |
1169 | radeon_crtc->rmx_type = RMX_OFF; |
||
1170 | /* copy native mode */ |
||
1179 | serge | 1171 | memcpy(&radeon_crtc->native_mode, |
1172 | &radeon_encoder->native_mode, |
||
1268 | serge | 1173 | sizeof(struct drm_display_mode)); |
1963 | serge | 1174 | src_v = crtc->mode.vdisplay; |
1175 | dst_v = radeon_crtc->native_mode.vdisplay; |
||
1176 | src_h = crtc->mode.hdisplay; |
||
1177 | dst_h = radeon_crtc->native_mode.hdisplay; |
||
1178 | |||
1179 | /* fix up for overscan on hdmi */ |
||
1180 | if (ASIC_IS_AVIVO(rdev) && |
||
1181 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
||
1182 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
||
1183 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
||
1184 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
||
1185 | is_hdtv_mode(mode)))) { |
||
1186 | if (radeon_encoder->underscan_hborder != 0) |
||
1187 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
||
1188 | else |
||
1189 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
||
1190 | if (radeon_encoder->underscan_vborder != 0) |
||
1191 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
||
1192 | else |
||
1193 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
||
1194 | radeon_crtc->rmx_type = RMX_FULL; |
||
1195 | src_v = crtc->mode.vdisplay; |
||
1196 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
||
1197 | src_h = crtc->mode.hdisplay; |
||
1198 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
||
1199 | } |
||
1179 | serge | 1200 | first = false; |
1201 | } else { |
||
1202 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
||
1203 | /* WARNING: Right now this can't happen but |
||
1204 | * in the future we need to check that scaling |
||
1963 | serge | 1205 | * are consistent across different encoder |
1179 | serge | 1206 | * (ie all encoder can work with the same |
1207 | * scaling). |
||
1208 | */ |
||
1963 | serge | 1209 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1179 | serge | 1210 | return false; |
1211 | } |
||
1123 | serge | 1212 | } |
1213 | } |
||
1179 | serge | 1214 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1221 | serge | 1215 | fixed20_12 a, b; |
1963 | serge | 1216 | a.full = dfixed_const(src_v); |
1217 | b.full = dfixed_const(dst_v); |
||
1218 | radeon_crtc->vsc.full = dfixed_div(a, b); |
||
1219 | a.full = dfixed_const(src_h); |
||
1220 | b.full = dfixed_const(dst_h); |
||
1221 | radeon_crtc->hsc.full = dfixed_div(a, b); |
||
1123 | serge | 1222 | } else { |
1963 | serge | 1223 | radeon_crtc->vsc.full = dfixed_const(1); |
1224 | radeon_crtc->hsc.full = dfixed_const(1); |
||
1123 | serge | 1225 | } |
1179 | serge | 1226 | return true; |
1123 | serge | 1227 | } |
1963 | serge | 1228 | |
1229 | /* |
||
1230 | * Retrieve current video scanout position of crtc on a given gpu. |
||
1231 | * |
||
1232 | * \param dev Device to query. |
||
1233 | * \param crtc Crtc to query. |
||
1234 | * \param *vpos Location where vertical scanout position should be stored. |
||
1235 | * \param *hpos Location where horizontal scanout position should go. |
||
1236 | * |
||
1237 | * Returns vpos as a positive number while in active scanout area. |
||
1238 | * Returns vpos as a negative number inside vblank, counting the number |
||
1239 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
||
1240 | * until start of active scanout / end of vblank." |
||
1241 | * |
||
1242 | * \return Flags, or'ed together as follows: |
||
1243 | * |
||
1244 | * DRM_SCANOUTPOS_VALID = Query successful. |
||
1245 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
||
1246 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
||
1247 | * this flag means that returned position may be offset by a constant but |
||
1248 | * unknown small number of scanlines wrt. real scanout position. |
||
1249 | * |
||
1250 | */ |
||
1251 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
||
1252 | { |
||
1253 | u32 stat_crtc = 0, vbl = 0, position = 0; |
||
1254 | int vbl_start, vbl_end, vtotal, ret = 0; |
||
1255 | bool in_vbl = true; |
||
1256 | |||
1257 | struct radeon_device *rdev = dev->dev_private; |
||
1258 | |||
1259 | if (ASIC_IS_DCE4(rdev)) { |
||
1260 | if (crtc == 0) { |
||
1261 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
||
1262 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
||
1263 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1264 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
||
1265 | ret |= DRM_SCANOUTPOS_VALID; |
||
1266 | } |
||
1267 | if (crtc == 1) { |
||
1268 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
||
1269 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
||
1270 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1271 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
||
1272 | ret |= DRM_SCANOUTPOS_VALID; |
||
1273 | } |
||
1274 | if (crtc == 2) { |
||
1275 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
||
1276 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
||
1277 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1278 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
||
1279 | ret |= DRM_SCANOUTPOS_VALID; |
||
1280 | } |
||
1281 | if (crtc == 3) { |
||
1282 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
||
1283 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
||
1284 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1285 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
||
1286 | ret |= DRM_SCANOUTPOS_VALID; |
||
1287 | } |
||
1288 | if (crtc == 4) { |
||
1289 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
||
1290 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
||
1291 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1292 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
||
1293 | ret |= DRM_SCANOUTPOS_VALID; |
||
1294 | } |
||
1295 | if (crtc == 5) { |
||
1296 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
||
1297 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
1298 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1299 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
1300 | ret |= DRM_SCANOUTPOS_VALID; |
||
1301 | } |
||
1302 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
1303 | if (crtc == 0) { |
||
1304 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
||
1305 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
||
1306 | ret |= DRM_SCANOUTPOS_VALID; |
||
1307 | } |
||
1308 | if (crtc == 1) { |
||
1309 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
||
1310 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
||
1311 | ret |= DRM_SCANOUTPOS_VALID; |
||
1312 | } |
||
1313 | } else { |
||
1314 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
||
1315 | if (crtc == 0) { |
||
1316 | /* Assume vbl_end == 0, get vbl_start from |
||
1317 | * upper 16 bits. |
||
1318 | */ |
||
1319 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
||
1320 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
||
1321 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
||
1322 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
||
1323 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
||
1324 | if (!(stat_crtc & 1)) |
||
1325 | in_vbl = false; |
||
1326 | |||
1327 | ret |= DRM_SCANOUTPOS_VALID; |
||
1328 | } |
||
1329 | if (crtc == 1) { |
||
1330 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
||
1331 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
||
1332 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
||
1333 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
||
1334 | if (!(stat_crtc & 1)) |
||
1335 | in_vbl = false; |
||
1336 | |||
1337 | ret |= DRM_SCANOUTPOS_VALID; |
||
1338 | } |
||
1339 | } |
||
1340 | |||
1341 | /* Decode into vertical and horizontal scanout position. */ |
||
1342 | *vpos = position & 0x1fff; |
||
1343 | *hpos = (position >> 16) & 0x1fff; |
||
1344 | |||
1345 | /* Valid vblank area boundaries from gpu retrieved? */ |
||
1346 | if (vbl > 0) { |
||
1347 | /* Yes: Decode. */ |
||
1348 | ret |= DRM_SCANOUTPOS_ACCURATE; |
||
1349 | vbl_start = vbl & 0x1fff; |
||
1350 | vbl_end = (vbl >> 16) & 0x1fff; |
||
1351 | } |
||
1352 | else { |
||
1353 | /* No: Fake something reasonable which gives at least ok results. */ |
||
1354 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
||
1355 | vbl_end = 0; |
||
1356 | } |
||
1357 | |||
1358 | /* Test scanout position against vblank region. */ |
||
1359 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
||
1360 | in_vbl = false; |
||
1361 | |||
1362 | /* Check if inside vblank area and apply corrective offsets: |
||
1363 | * vpos will then be >=0 in video scanout area, but negative |
||
1364 | * within vblank area, counting down the number of lines until |
||
1365 | * start of scanout. |
||
1366 | */ |
||
1367 | |||
1368 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
||
1369 | if (in_vbl && (*vpos >= vbl_start)) { |
||
1370 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
||
1371 | *vpos = *vpos - vtotal; |
||
1372 | } |
||
1373 | |||
1374 | /* Correct for shifted end of vbl at vbl_end. */ |
||
1375 | *vpos = *vpos - vbl_end; |
||
1376 | |||
1377 | /* In vblank? */ |
||
1378 | if (in_vbl) |
||
1379 | ret |= DRM_SCANOUTPOS_INVBL; |
||
1380 | |||
1381 | return ret; |
||
1382 | }>>>>>>>>>>>>>>>>>>>>=>>>=>>>><>><>><>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |