WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_display.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
1123	serge	28	#include "radeon.h"
		29
		30	#include "atom.h"
1963	serge	31	#include
1123	serge	32
2997	Serge	33	#include
		34	#include
1123	serge	35
		36	static void avivo_crtc_load_lut(struct drm_crtc *crtc)
		37	{
		38	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		39	struct drm_device *dev = crtc->dev;
		40	struct radeon_device *rdev = dev->dev_private;
		41	int i;
		42
1963	serge	43	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1123	serge	44	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
		45
		46	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		47	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		48	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		49
		50	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		51	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		52	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		53
		54	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
		55	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
		56	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
		57
		58	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
		59	for (i = 0; i < 256; i++) {
		60	WREG32(AVIVO_DC_LUT_30_COLOR,
		61	(radeon_crtc->lut_r[i] << 20) \|
		62	(radeon_crtc->lut_g[i] << 10) \|
		63	(radeon_crtc->lut_b[i] << 0));
		64	}
		65
		66	WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
		67	}
		68
1963	serge	69	static void dce4_crtc_load_lut(struct drm_crtc *crtc)
1430	serge	70	{
		71	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		72	struct drm_device *dev = crtc->dev;
		73	struct radeon_device *rdev = dev->dev_private;
		74	int i;
		75
1963	serge	76	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1430	serge	77	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		78
		79	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		80	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		81	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		82
		83	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		84	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		85	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		86
1963	serge	87	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		88	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
1430	serge	89
1963	serge	90	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
1430	serge	91	for (i = 0; i < 256; i++) {
1963	serge	92	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
1430	serge	93	(radeon_crtc->lut_r[i] << 20) \|
		94	(radeon_crtc->lut_g[i] << 10) \|
		95	(radeon_crtc->lut_b[i] << 0));
		96	}
		97	}
		98
1963	serge	99	static void dce5_crtc_load_lut(struct drm_crtc *crtc)
		100	{
		101	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		102	struct drm_device *dev = crtc->dev;
		103	struct radeon_device *rdev = dev->dev_private;
		104	int i;
		105
		106	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
		107
		108	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		109	(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) \|
		110	NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
		111	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
		112	NI_GRPH_PRESCALE_BYPASS);
		113	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
		114	NI_OVL_PRESCALE_BYPASS);
		115	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
		116	(NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) \|
		117	NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
		118
		119	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		120
		121	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		122	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		123	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		124
		125	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		126	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		127	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		128
		129	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		130	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
		131
		132	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
		133	for (i = 0; i < 256; i++) {
		134	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
		135	(radeon_crtc->lut_r[i] << 20) \|
		136	(radeon_crtc->lut_g[i] << 10) \|
		137	(radeon_crtc->lut_b[i] << 0));
		138	}
		139
		140	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
		141	(NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		142	NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		143	NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		144	NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
		145	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
		146	(NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) \|
		147	NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
		148	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
		149	(NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) \|
		150	NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
		151	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		152	(NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) \|
		153	NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
		154	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
		155	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
		156
		157	}
		158
1123	serge	159	static void legacy_crtc_load_lut(struct drm_crtc *crtc)
		160	{
		161	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		162	struct drm_device *dev = crtc->dev;
		163	struct radeon_device *rdev = dev->dev_private;
		164	int i;
		165	uint32_t dac2_cntl;
		166
		167	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		168	if (radeon_crtc->crtc_id == 0)
		169	dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
		170	else
		171	dac2_cntl \|= RADEON_DAC2_PALETTE_ACC_CTL;
		172	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		173
		174	WREG8(RADEON_PALETTE_INDEX, 0);
		175	for (i = 0; i < 256; i++) {
		176	WREG32(RADEON_PALETTE_30_DATA,
		177	(radeon_crtc->lut_r[i] << 20) \|
		178	(radeon_crtc->lut_g[i] << 10) \|
		179	(radeon_crtc->lut_b[i] << 0));
		180	}
		181	}
		182
		183	void radeon_crtc_load_lut(struct drm_crtc *crtc)
		184	{
		185	struct drm_device *dev = crtc->dev;
		186	struct radeon_device *rdev = dev->dev_private;
		187
		188	if (!crtc->enabled)
		189	return;
		190
1963	serge	191	if (ASIC_IS_DCE5(rdev))
		192	dce5_crtc_load_lut(crtc);
		193	else if (ASIC_IS_DCE4(rdev))
		194	dce4_crtc_load_lut(crtc);
1430	serge	195	else if (ASIC_IS_AVIVO(rdev))
1123	serge	196	avivo_crtc_load_lut(crtc);
		197	else
		198	legacy_crtc_load_lut(crtc);
		199	}
		200
1221	serge	201	/** Sets the color ramps on behalf of fbcon */
1123	serge	202	void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		203	u16 blue, int regno)
		204	{
		205	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		206
		207	radeon_crtc->lut_r[regno] = red >> 6;
		208	radeon_crtc->lut_g[regno] = green >> 6;
		209	radeon_crtc->lut_b[regno] = blue >> 6;
		210	}
		211
1221	serge	212	/** Gets the color ramps on behalf of fbcon */
		213	void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		214	u16 *blue, int regno)
		215	{
		216	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		217
		218	*red = radeon_crtc->lut_r[regno] << 6;
		219	*green = radeon_crtc->lut_g[regno] << 6;
		220	*blue = radeon_crtc->lut_b[regno] << 6;
		221	}
		222
1123	serge	223	static void radeon_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
1963	serge	224	u16 *blue, uint32_t start, uint32_t size)
1123	serge	225	{
		226	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1963	serge	227	int end = (start + size > 256) ? 256 : start + size, i;
1123	serge	228
1221	serge	229	/* userspace palettes are always correct as is */
1963	serge	230	for (i = start; i < end; i++) {
1123	serge	231	radeon_crtc->lut_r[i] = red[i] >> 6;
		232	radeon_crtc->lut_g[i] = green[i] >> 6;
		233	radeon_crtc->lut_b[i] = blue[i] >> 6;
		234	}
		235	radeon_crtc_load_lut(crtc);
		236	}
		237
		238	static void radeon_crtc_destroy(struct drm_crtc *crtc)
		239	{
		240	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		241
		242	drm_crtc_cleanup(crtc);
		243	kfree(radeon_crtc);
		244	}
		245
		246	static const struct drm_crtc_funcs radeon_crtc_funcs = {
1221	serge	247	.cursor_set = NULL,
		248	.cursor_move = NULL,
1123	serge	249	.gamma_set = radeon_crtc_gamma_set,
1126	serge	250	.set_config = drm_crtc_helper_set_config,
1123	serge	251	.destroy = radeon_crtc_destroy,
1963	serge	252	.page_flip = NULL,
1123	serge	253	};
		254
		255	static void radeon_crtc_init(struct drm_device *dev, int index)
		256	{
		257	struct radeon_device *rdev = dev->dev_private;
		258	struct radeon_crtc *radeon_crtc;
		259	int i;
		260
		261	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		262	if (radeon_crtc == NULL)
		263	return;
		264
		265	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
		266
		267	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
		268	radeon_crtc->crtc_id = index;
1179	serge	269	rdev->mode_info.crtcs[index] = radeon_crtc;
1123	serge	270
1179	serge	271	#if 0
1123	serge	272	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
		273	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
		274	radeon_crtc->mode_set.num_connectors = 0;
1179	serge	275	#endif
1123	serge	276
		277	for (i = 0; i < 256; i++) {
		278	radeon_crtc->lut_r[i] = i << 2;
		279	radeon_crtc->lut_g[i] = i << 2;
		280	radeon_crtc->lut_b[i] = i << 2;
		281	}
		282
		283	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom))
		284	radeon_atombios_init_crtc(dev, radeon_crtc);
		285	else
		286	radeon_legacy_init_crtc(dev, radeon_crtc);
		287	}
		288
2997	Serge	289	static const char *encoder_names[37] = {
1123	serge	290	"NONE",
		291	"INTERNAL_LVDS",
		292	"INTERNAL_TMDS1",
		293	"INTERNAL_TMDS2",
		294	"INTERNAL_DAC1",
		295	"INTERNAL_DAC2",
		296	"INTERNAL_SDVOA",
		297	"INTERNAL_SDVOB",
		298	"SI170B",
		299	"CH7303",
		300	"CH7301",
		301	"INTERNAL_DVO1",
		302	"EXTERNAL_SDVOA",
		303	"EXTERNAL_SDVOB",
		304	"TITFP513",
		305	"INTERNAL_LVTM1",
		306	"VT1623",
		307	"HDMI_SI1930",
		308	"HDMI_INTERNAL",
		309	"INTERNAL_KLDSCP_TMDS1",
		310	"INTERNAL_KLDSCP_DVO1",
		311	"INTERNAL_KLDSCP_DAC1",
		312	"INTERNAL_KLDSCP_DAC2",
		313	"SI178",
		314	"MVPU_FPGA",
		315	"INTERNAL_DDI",
		316	"VT1625",
		317	"HDMI_SI1932",
		318	"DP_AN9801",
		319	"DP_DP501",
		320	"INTERNAL_UNIPHY",
		321	"INTERNAL_KLDSCP_LVTMA",
		322	"INTERNAL_UNIPHY1",
		323	"INTERNAL_UNIPHY2",
1963	serge	324	"NUTMEG",
		325	"TRAVIS",
2997	Serge	326	"INTERNAL_VCE"
1123	serge	327	};
		328
1963	serge	329	static const char *hpd_names[6] = {
1404	serge	330	"HPD1",
		331	"HPD2",
		332	"HPD3",
		333	"HPD4",
		334	"HPD5",
		335	"HPD6",
		336	};
		337
1123	serge	338	static void radeon_print_display_setup(struct drm_device *dev)
		339	{
		340	struct drm_connector *connector;
		341	struct radeon_connector *radeon_connector;
		342	struct drm_encoder *encoder;
		343	struct radeon_encoder *radeon_encoder;
		344	uint32_t devices;
		345	int i = 0;
		346
		347	DRM_INFO("Radeon Display Connectors\n");
		348	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		349	radeon_connector = to_radeon_connector(connector);
		350	DRM_INFO("Connector %d:\n", i);
2997	Serge	351	DRM_INFO(" %s\n", drm_get_connector_name(connector));
1404	serge	352	if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
		353	DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
		354	if (radeon_connector->ddc_bus) {
1123	serge	355	DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
		356	radeon_connector->ddc_bus->rec.mask_clk_reg,
		357	radeon_connector->ddc_bus->rec.mask_data_reg,
		358	radeon_connector->ddc_bus->rec.a_clk_reg,
		359	radeon_connector->ddc_bus->rec.a_data_reg,
1404	serge	360	radeon_connector->ddc_bus->rec.en_clk_reg,
		361	radeon_connector->ddc_bus->rec.en_data_reg,
		362	radeon_connector->ddc_bus->rec.y_clk_reg,
		363	radeon_connector->ddc_bus->rec.y_data_reg);
1963	serge	364	if (radeon_connector->router.ddc_valid)
		365	DRM_INFO(" DDC Router 0x%x/0x%x\n",
		366	radeon_connector->router.ddc_mux_control_pin,
		367	radeon_connector->router.ddc_mux_state);
		368	if (radeon_connector->router.cd_valid)
		369	DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
		370	radeon_connector->router.cd_mux_control_pin,
		371	radeon_connector->router.cd_mux_state);
1404	serge	372	} else {
		373	if (connector->connector_type == DRM_MODE_CONNECTOR_VGA \|\|
		374	connector->connector_type == DRM_MODE_CONNECTOR_DVII \|\|
		375	connector->connector_type == DRM_MODE_CONNECTOR_DVID \|\|
		376	connector->connector_type == DRM_MODE_CONNECTOR_DVIA \|\|
		377	connector->connector_type == DRM_MODE_CONNECTOR_HDMIA \|\|
		378	connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
		379	DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
		380	}
1123	serge	381	DRM_INFO(" Encoders:\n");
		382	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		383	radeon_encoder = to_radeon_encoder(encoder);
		384	devices = radeon_encoder->devices & radeon_connector->devices;
		385	if (devices) {
		386	if (devices & ATOM_DEVICE_CRT1_SUPPORT)
		387	DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		388	if (devices & ATOM_DEVICE_CRT2_SUPPORT)
		389	DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		390	if (devices & ATOM_DEVICE_LCD1_SUPPORT)
		391	DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		392	if (devices & ATOM_DEVICE_DFP1_SUPPORT)
		393	DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		394	if (devices & ATOM_DEVICE_DFP2_SUPPORT)
		395	DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		396	if (devices & ATOM_DEVICE_DFP3_SUPPORT)
		397	DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
		398	if (devices & ATOM_DEVICE_DFP4_SUPPORT)
		399	DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
		400	if (devices & ATOM_DEVICE_DFP5_SUPPORT)
		401	DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
1963	serge	402	if (devices & ATOM_DEVICE_DFP6_SUPPORT)
		403	DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
1123	serge	404	if (devices & ATOM_DEVICE_TV1_SUPPORT)
		405	DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		406	if (devices & ATOM_DEVICE_CV_SUPPORT)
		407	DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
		408	}
		409	}
		410	i++;
		411	}
		412	}
		413
1179	serge	414	static bool radeon_setup_enc_conn(struct drm_device *dev)
1123	serge	415	{
		416	struct radeon_device *rdev = dev->dev_private;
		417	bool ret = false;
		418
		419	if (rdev->bios) {
		420	if (rdev->is_atom_bios) {
1963	serge	421	ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
		422	if (ret == false)
1123	serge	423	ret = radeon_get_atom_connector_info_from_object_table(dev);
1404	serge	424	} else {
1123	serge	425	ret = radeon_get_legacy_connector_info_from_bios(dev);
1404	serge	426	if (ret == false)
		427	ret = radeon_get_legacy_connector_info_from_table(dev);
		428	}
1123	serge	429	} else {
		430	if (!ASIC_IS_AVIVO(rdev))
		431	ret = radeon_get_legacy_connector_info_from_table(dev);
		432	}
		433	if (ret) {
1404	serge	434	radeon_setup_encoder_clones(dev);
1123	serge	435	radeon_print_display_setup(dev);
		436	}
		437
		438	return ret;
		439	}
		440
		441	int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
		442	{
1430	serge	443	struct drm_device *dev = radeon_connector->base.dev;
		444	struct radeon_device *rdev = dev->dev_private;
1123	serge	445	int ret = 0;
		446
1963	serge	447	/* on hw with routers, select right port */
		448	if (radeon_connector->router.ddc_valid)
		449	radeon_router_select_ddc_port(radeon_connector);
		450
3192	Serge	451	if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
		452	ENCODER_OBJECT_ID_NONE) {
1404	serge	453	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
2997	Serge	454
3192	Serge	455	if (dig->dp_i2c_bus)
		456	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		457	&dig->dp_i2c_bus->adapter);
		458	} else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
		459	(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
		460	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
		461
1404	serge	462	if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT \|\|
		463	dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
2997	Serge	464	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		465	&dig->dp_i2c_bus->adapter);
		466	else if (radeon_connector->ddc_bus && !radeon_connector->edid)
		467	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		468	&radeon_connector->ddc_bus->adapter);
		469	} else {
		470	if (radeon_connector->ddc_bus && !radeon_connector->edid)
		471	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		472	&radeon_connector->ddc_bus->adapter);
1404	serge	473	}
1963	serge	474
		475	if (!radeon_connector->edid) {
		476	if (rdev->is_atom_bios) {
		477	/* some laptops provide a hardcoded edid in rom for LCDs */
		478	if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) \|\|
		479	(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
		480	radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
		481	} else
1430	serge	482	/* some servers provide a hardcoded edid in rom for KVMs */
1963	serge	483	radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
		484	}
1268	serge	485	if (radeon_connector->edid) {
		486	drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
		487	ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
1123	serge	488	return ret;
		489	}
		490	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
1179	serge	491	return 0;
1123	serge	492	}
		493
1963	serge	494	/* avivo */
		495	static void avivo_get_fb_div(struct radeon_pll *pll,
		496	u32 target_clock,
		497	u32 post_div,
		498	u32 ref_div,
		499	u32 *fb_div,
		500	u32 *frac_fb_div)
		501	{
		502	u32 tmp = post_div * ref_div;
		503
		504	tmp *= target_clock;
		505	*fb_div = tmp / pll->reference_freq;
		506	*frac_fb_div = tmp % pll->reference_freq;
		507
		508	if (*fb_div > pll->max_feedback_div)
		509	*fb_div = pll->max_feedback_div;
		510	else if (*fb_div < pll->min_feedback_div)
		511	*fb_div = pll->min_feedback_div;
		512	}
		513
		514	static u32 avivo_get_post_div(struct radeon_pll *pll,
		515	u32 target_clock)
		516	{
		517	u32 vco, post_div, tmp;
		518
		519	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		520	return pll->post_div;
		521
		522	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
		523	if (pll->flags & RADEON_PLL_IS_LCD)
		524	vco = pll->lcd_pll_out_min;
		525	else
		526	vco = pll->pll_out_min;
		527	} else {
		528	if (pll->flags & RADEON_PLL_IS_LCD)
		529	vco = pll->lcd_pll_out_max;
		530	else
		531	vco = pll->pll_out_max;
		532	}
		533
		534	post_div = vco / target_clock;
		535	tmp = vco % target_clock;
		536
		537	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
		538	if (tmp)
		539	post_div++;
		540	} else {
		541	if (!tmp)
		542	post_div--;
		543	}
		544
		545	if (post_div > pll->max_post_div)
		546	post_div = pll->max_post_div;
		547	else if (post_div < pll->min_post_div)
		548	post_div = pll->min_post_div;
		549
		550	return post_div;
		551	}
		552
		553	#define MAX_TOLERANCE 10
		554
		555	void radeon_compute_pll_avivo(struct radeon_pll *pll,
		556	u32 freq,
		557	u32 *dot_clock_p,
		558	u32 *fb_div_p,
		559	u32 *frac_fb_div_p,
		560	u32 *ref_div_p,
		561	u32 *post_div_p)
		562	{
		563	u32 target_clock = freq / 10;
		564	u32 post_div = avivo_get_post_div(pll, target_clock);
		565	u32 ref_div = pll->min_ref_div;
		566	u32 fb_div = 0, frac_fb_div = 0, tmp;
		567
		568	if (pll->flags & RADEON_PLL_USE_REF_DIV)
		569	ref_div = pll->reference_div;
		570
		571	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
		572	avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
		573	frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
		574	if (frac_fb_div >= 5) {
		575	frac_fb_div -= 5;
		576	frac_fb_div = frac_fb_div / 10;
		577	frac_fb_div++;
		578	}
		579	if (frac_fb_div >= 10) {
		580	fb_div++;
		581	frac_fb_div = 0;
		582	}
		583	} else {
		584	while (ref_div <= pll->max_ref_div) {
		585	avivo_get_fb_div(pll, target_clock, post_div, ref_div,
		586	&fb_div, &frac_fb_div);
		587	if (frac_fb_div >= (pll->reference_freq / 2))
		588	fb_div++;
		589	frac_fb_div = 0;
		590	tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
		591	tmp = (tmp * 10000) / target_clock;
		592
		593	if (tmp > (10000 + MAX_TOLERANCE))
		594	ref_div++;
		595	else if (tmp >= (10000 - MAX_TOLERANCE))
		596	break;
		597	else
		598	ref_div++;
		599	}
		600	}
		601
		602	dot_clock_p = ((pll->reference_freq fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
		603	(ref_div * post_div * 10);
		604	*fb_div_p = fb_div;
		605	*frac_fb_div_p = frac_fb_div;
		606	*ref_div_p = ref_div;
		607	*post_div_p = post_div;
		608	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		609	*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
		610	}
		611
		612	/* pre-avivo */
1123	serge	613	static inline uint32_t radeon_div(uint64_t n, uint32_t d)
		614	{
		615	uint64_t mod;
		616
		617	n += d / 2;
		618
		619	mod = do_div(n, d);
		620	return n;
		621	}
		622
1963	serge	623	void radeon_compute_pll_legacy(struct radeon_pll *pll,
1123	serge	624	uint64_t freq,
		625	uint32_t *dot_clock_p,
		626	uint32_t *fb_div_p,
		627	uint32_t *frac_fb_div_p,
		628	uint32_t *ref_div_p,
1404	serge	629	uint32_t *post_div_p)
1123	serge	630	{
		631	uint32_t min_ref_div = pll->min_ref_div;
		632	uint32_t max_ref_div = pll->max_ref_div;
1404	serge	633	uint32_t min_post_div = pll->min_post_div;
		634	uint32_t max_post_div = pll->max_post_div;
1123	serge	635	uint32_t min_fractional_feed_div = 0;
		636	uint32_t max_fractional_feed_div = 0;
		637	uint32_t best_vco = pll->best_vco;
		638	uint32_t best_post_div = 1;
		639	uint32_t best_ref_div = 1;
		640	uint32_t best_feedback_div = 1;
		641	uint32_t best_frac_feedback_div = 0;
		642	uint32_t best_freq = -1;
		643	uint32_t best_error = 0xffffffff;
		644	uint32_t best_vco_diff = 1;
		645	uint32_t post_div;
1963	serge	646	u32 pll_out_min, pll_out_max;
1123	serge	647
1963	serge	648	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1123	serge	649	freq = freq * 1000;
		650
1963	serge	651	if (pll->flags & RADEON_PLL_IS_LCD) {
		652	pll_out_min = pll->lcd_pll_out_min;
		653	pll_out_max = pll->lcd_pll_out_max;
		654	} else {
		655	pll_out_min = pll->pll_out_min;
		656	pll_out_max = pll->pll_out_max;
		657	}
		658
		659	if (pll_out_min > 64800)
		660	pll_out_min = 64800;
		661
1404	serge	662	if (pll->flags & RADEON_PLL_USE_REF_DIV)
1123	serge	663	min_ref_div = max_ref_div = pll->reference_div;
		664	else {
		665	while (min_ref_div < max_ref_div-1) {
		666	uint32_t mid = (min_ref_div + max_ref_div) / 2;
		667	uint32_t pll_in = pll->reference_freq / mid;
		668	if (pll_in < pll->pll_in_min)
		669	max_ref_div = mid;
		670	else if (pll_in > pll->pll_in_max)
		671	min_ref_div = mid;
		672	else
		673	break;
		674	}
		675	}
		676
1404	serge	677	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		678	min_post_div = max_post_div = pll->post_div;
		679
		680	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1123	serge	681	min_fractional_feed_div = pll->min_frac_feedback_div;
		682	max_fractional_feed_div = pll->max_frac_feedback_div;
		683	}
		684
1963	serge	685	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1123	serge	686	uint32_t ref_div;
		687
1404	serge	688	if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1123	serge	689	continue;
		690
		691	/* legacy radeons only have a few post_divs */
1404	serge	692	if (pll->flags & RADEON_PLL_LEGACY) {
1123	serge	693	if ((post_div == 5) \|\|
		694	(post_div == 7) \|\|
		695	(post_div == 9) \|\|
		696	(post_div == 10) \|\|
		697	(post_div == 11) \|\|
		698	(post_div == 13) \|\|
		699	(post_div == 14) \|\|
		700	(post_div == 15))
		701	continue;
		702	}
		703
		704	for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
		705	uint32_t feedback_div, current_freq = 0, error, vco_diff;
		706	uint32_t pll_in = pll->reference_freq / ref_div;
		707	uint32_t min_feed_div = pll->min_feedback_div;
		708	uint32_t max_feed_div = pll->max_feedback_div + 1;
		709
		710	if (pll_in < pll->pll_in_min \|\| pll_in > pll->pll_in_max)
		711	continue;
		712
		713	while (min_feed_div < max_feed_div) {
		714	uint32_t vco;
		715	uint32_t min_frac_feed_div = min_fractional_feed_div;
		716	uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
		717	uint32_t frac_feedback_div;
		718	uint64_t tmp;
		719
		720	feedback_div = (min_feed_div + max_feed_div) / 2;
		721
		722	tmp = (uint64_t)pll->reference_freq * feedback_div;
		723	vco = radeon_div(tmp, ref_div);
		724
1963	serge	725	if (vco < pll_out_min) {
1123	serge	726	min_feed_div = feedback_div + 1;
		727	continue;
1963	serge	728	} else if (vco > pll_out_max) {
1123	serge	729	max_feed_div = feedback_div;
		730	continue;
		731	}
		732
		733	while (min_frac_feed_div < max_frac_feed_div) {
		734	frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
		735	tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
		736	tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
		737	current_freq = radeon_div(tmp, ref_div * post_div);
		738
1404	serge	739	if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1963	serge	740	if (freq < current_freq)
		741	error = 0xffffffff;
		742	else
1179	serge	743	error = freq - current_freq;
		744	} else
1123	serge	745	error = abs(current_freq - freq);
		746	vco_diff = abs(vco - best_vco);
		747
		748	if ((best_vco == 0 && error < best_error) \|\|
		749	(best_vco != 0 &&
1963	serge	750	((best_error > 100 && error < best_error - 100) \|\|
1123	serge	751	(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
		752	best_post_div = post_div;
		753	best_ref_div = ref_div;
		754	best_feedback_div = feedback_div;
		755	best_frac_feedback_div = frac_feedback_div;
		756	best_freq = current_freq;
		757	best_error = error;
		758	best_vco_diff = vco_diff;
		759	} else if (current_freq == freq) {
		760	if (best_freq == -1) {
		761	best_post_div = post_div;
		762	best_ref_div = ref_div;
		763	best_feedback_div = feedback_div;
		764	best_frac_feedback_div = frac_feedback_div;
		765	best_freq = current_freq;
		766	best_error = error;
		767	best_vco_diff = vco_diff;
1404	serge	768	} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) \|\|
		769	((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) \|\|
		770	((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) \|\|
		771	((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) \|\|
		772	((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) \|\|
		773	((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1123	serge	774	best_post_div = post_div;
		775	best_ref_div = ref_div;
		776	best_feedback_div = feedback_div;
		777	best_frac_feedback_div = frac_feedback_div;
		778	best_freq = current_freq;
		779	best_error = error;
		780	best_vco_diff = vco_diff;
		781	}
		782	}
		783	if (current_freq < freq)
		784	min_frac_feed_div = frac_feedback_div + 1;
		785	else
		786	max_frac_feed_div = frac_feedback_div;
		787	}
		788	if (current_freq < freq)
		789	min_feed_div = feedback_div + 1;
		790	else
		791	max_feed_div = feedback_div;
		792	}
		793	}
		794	}
		795
		796	*dot_clock_p = best_freq / 10000;
		797	*fb_div_p = best_feedback_div;
		798	*frac_fb_div_p = best_frac_feedback_div;
		799	*ref_div_p = best_ref_div;
		800	*post_div_p = best_post_div;
1963	serge	801	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		802	(long long)freq,
		803	best_freq / 1000, best_feedback_div, best_frac_feedback_div,
		804	best_ref_div, best_post_div);
1123	serge	805
1430	serge	806	}
		807
1123	serge	808	static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
		809	{
		810	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		811
		812	drm_framebuffer_cleanup(fb);
		813	kfree(radeon_fb);
		814	}
		815
		816	static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
		817	struct drm_file *file_priv,
		818	unsigned int *handle)
		819	{
		820	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		821
		822	return NULL;
		823	// return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
		824	}
		825
		826	static const struct drm_framebuffer_funcs radeon_fb_funcs = {
		827	.destroy = radeon_user_framebuffer_destroy,
		828	.create_handle = radeon_user_framebuffer_create_handle,
		829	};
		830
2997	Serge	831	int
1963	serge	832	radeon_framebuffer_init(struct drm_device *dev,
		833	struct radeon_framebuffer *rfb,
2997	Serge	834	struct drm_mode_fb_cmd2 *mode_cmd,
1123	serge	835	struct drm_gem_object *obj)
		836	{
2997	Serge	837	int ret;
		838
		839	ENTER();
		840
1963	serge	841	rfb->obj = obj;
2997	Serge	842	ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
		843	if (ret) {
		844	rfb->obj = NULL;
		845	return ret;
		846	}
1963	serge	847	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
2997	Serge	848	LEAVE();
		849	return 0;
1123	serge	850	}
		851
		852
		853
		854	static const struct drm_mode_config_funcs radeon_mode_funcs = {
1963	serge	855	// .fb_create = radeon_user_framebuffer_create,
		856	// .output_poll_changed = radeon_output_poll_changed
1123	serge	857	};
		858
1179	serge	859	static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
		860	{ { 0, "driver" },
		861	{ 1, "bios" },
		862	};
		863
		864	static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
		865	{ { TV_STD_NTSC, "ntsc" },
		866	{ TV_STD_PAL, "pal" },
		867	{ TV_STD_PAL_M, "pal-m" },
		868	{ TV_STD_PAL_60, "pal-60" },
		869	{ TV_STD_NTSC_J, "ntsc-j" },
		870	{ TV_STD_SCART_PAL, "scart-pal" },
		871	{ TV_STD_PAL_CN, "pal-cn" },
		872	{ TV_STD_SECAM, "secam" },
		873	};
		874
1963	serge	875	static struct drm_prop_enum_list radeon_underscan_enum_list[] =
		876	{ { UNDERSCAN_OFF, "off" },
		877	{ UNDERSCAN_ON, "on" },
		878	{ UNDERSCAN_AUTO, "auto" },
		879	};
		880
1404	serge	881	static int radeon_modeset_create_props(struct radeon_device *rdev)
1123	serge	882	{
2997	Serge	883	int sz;
1125	serge	884
1179	serge	885	if (rdev->is_atom_bios) {
		886	rdev->mode_info.coherent_mode_property =
2997	Serge	887	drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1179	serge	888	if (!rdev->mode_info.coherent_mode_property)
		889	return -ENOMEM;
		890	}
		891
		892	if (!ASIC_IS_AVIVO(rdev)) {
		893	sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
		894	rdev->mode_info.tmds_pll_property =
2997	Serge	895	drm_property_create_enum(rdev->ddev, 0,
		896	"tmds_pll",
		897	radeon_tmds_pll_enum_list, sz);
1179	serge	898	}
		899
		900	rdev->mode_info.load_detect_property =
2997	Serge	901	drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1179	serge	902	if (!rdev->mode_info.load_detect_property)
		903	return -ENOMEM;
		904
		905	drm_mode_create_scaling_mode_property(rdev->ddev);
		906
		907	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
		908	rdev->mode_info.tv_std_property =
2997	Serge	909	drm_property_create_enum(rdev->ddev, 0,
		910	"tv standard",
		911	radeon_tv_std_enum_list, sz);
1179	serge	912
1963	serge	913	sz = ARRAY_SIZE(radeon_underscan_enum_list);
		914	rdev->mode_info.underscan_property =
2997	Serge	915	drm_property_create_enum(rdev->ddev, 0,
		916	"underscan",
		917	radeon_underscan_enum_list, sz);
1963	serge	918
		919	rdev->mode_info.underscan_hborder_property =
2997	Serge	920	drm_property_create_range(rdev->ddev, 0,
		921	"underscan hborder", 0, 128);
1963	serge	922	if (!rdev->mode_info.underscan_hborder_property)
		923	return -ENOMEM;
		924
		925	rdev->mode_info.underscan_vborder_property =
2997	Serge	926	drm_property_create_range(rdev->ddev, 0,
		927	"underscan vborder", 0, 128);
1963	serge	928	if (!rdev->mode_info.underscan_vborder_property)
		929	return -ENOMEM;
		930
1179	serge	931	return 0;
		932	}
		933
1963	serge	934	void radeon_update_display_priority(struct radeon_device *rdev)
		935	{
		936	/* adjustment options for the display watermarks */
		937	if ((radeon_disp_priority == 0) \|\| (radeon_disp_priority > 2)) {
		938	/* set display priority to high for r3xx, rv515 chips
		939	* this avoids flickering due to underflow to the
		940	* display controllers during heavy acceleration.
		941	* Don't force high on rs4xx igp chips as it seems to
		942	* affect the sound card. See kernel bug 15982.
		943	*/
		944	if ((ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV515)) &&
		945	!(rdev->flags & RADEON_IS_IGP))
		946	rdev->disp_priority = 2;
		947	else
		948	rdev->disp_priority = 0;
		949	} else
		950	rdev->disp_priority = radeon_disp_priority;
		951
		952	}
		953
2997	Serge	954	/*
		955	* Allocate hdmi structs and determine register offsets
		956	*/
		957	static void radeon_afmt_init(struct radeon_device *rdev)
		958	{
		959	int i;
		960
		961	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
		962	rdev->mode_info.afmt[i] = NULL;
		963
		964	if (ASIC_IS_DCE6(rdev)) {
		965	/* todo */
		966	} else if (ASIC_IS_DCE4(rdev)) {
		967	/* DCE4/5 has 6 audio blocks tied to DIG encoders */
		968	/* DCE4.1 has 2 audio blocks tied to DIG encoders */
		969	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		970	if (rdev->mode_info.afmt[0]) {
		971	rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
		972	rdev->mode_info.afmt[0]->id = 0;
		973	}
		974	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		975	if (rdev->mode_info.afmt[1]) {
		976	rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
		977	rdev->mode_info.afmt[1]->id = 1;
		978	}
		979	if (!ASIC_IS_DCE41(rdev)) {
		980	rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		981	if (rdev->mode_info.afmt[2]) {
		982	rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
		983	rdev->mode_info.afmt[2]->id = 2;
		984	}
		985	rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		986	if (rdev->mode_info.afmt[3]) {
		987	rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
		988	rdev->mode_info.afmt[3]->id = 3;
		989	}
		990	rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		991	if (rdev->mode_info.afmt[4]) {
		992	rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
		993	rdev->mode_info.afmt[4]->id = 4;
		994	}
		995	rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		996	if (rdev->mode_info.afmt[5]) {
		997	rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
		998	rdev->mode_info.afmt[5]->id = 5;
		999	}
		1000	}
		1001	} else if (ASIC_IS_DCE3(rdev)) {
		1002	/* DCE3.x has 2 audio blocks tied to DIG encoders */
		1003	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1004	if (rdev->mode_info.afmt[0]) {
		1005	rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
		1006	rdev->mode_info.afmt[0]->id = 0;
		1007	}
		1008	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1009	if (rdev->mode_info.afmt[1]) {
		1010	rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
		1011	rdev->mode_info.afmt[1]->id = 1;
		1012	}
		1013	} else if (ASIC_IS_DCE2(rdev)) {
		1014	/* DCE2 has at least 1 routable audio block */
		1015	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1016	if (rdev->mode_info.afmt[0]) {
		1017	rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
		1018	rdev->mode_info.afmt[0]->id = 0;
		1019	}
		1020	/* r6xx has 2 routable audio blocks */
		1021	if (rdev->family >= CHIP_R600) {
		1022	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1023	if (rdev->mode_info.afmt[1]) {
		1024	rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
		1025	rdev->mode_info.afmt[1]->id = 1;
		1026	}
		1027	}
		1028	}
		1029	}
		1030
		1031	static void radeon_afmt_fini(struct radeon_device *rdev)
		1032	{
		1033	int i;
		1034
		1035	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
		1036	kfree(rdev->mode_info.afmt[i]);
		1037	rdev->mode_info.afmt[i] = NULL;
		1038	}
		1039	}
		1040
1179	serge	1041	int radeon_modeset_init(struct radeon_device *rdev)
		1042	{
1430	serge	1043	int i;
1123	serge	1044	int ret;
		1045
3192	Serge	1046	ENTER();
		1047
1123	serge	1048	drm_mode_config_init(rdev->ddev);
		1049	rdev->mode_info.mode_config_initialized = true;
		1050
2997	Serge	1051	rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1123	serge	1052
1963	serge	1053	if (ASIC_IS_DCE5(rdev)) {
		1054	rdev->ddev->mode_config.max_width = 16384;
		1055	rdev->ddev->mode_config.max_height = 16384;
		1056	} else if (ASIC_IS_AVIVO(rdev)) {
1123	serge	1057	rdev->ddev->mode_config.max_width = 8192;
		1058	rdev->ddev->mode_config.max_height = 8192;
		1059	} else {
		1060	rdev->ddev->mode_config.max_width = 4096;
		1061	rdev->ddev->mode_config.max_height = 4096;
		1062	}
		1063
2997	Serge	1064	rdev->ddev->mode_config.preferred_depth = 24;
		1065	rdev->ddev->mode_config.prefer_shadow = 1;
		1066
1123	serge	1067	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
		1068
1179	serge	1069	ret = radeon_modeset_create_props(rdev);
		1070	if (ret) {
		1071	return ret;
		1072	}
1221	serge	1073
1963	serge	1074	/* init i2c buses */
		1075	radeon_i2c_init(rdev);
		1076
3192	Serge	1077	dbgprintf("i2c init\n");
		1078
1430	serge	1079	/* check combios for a valid hardcoded EDID - Sun servers */
		1080	if (!rdev->is_atom_bios) {
		1081	/* check for hardcoded EDID in BIOS */
		1082	radeon_combios_check_hardcoded_edid(rdev);
		1083	}
		1084
1221	serge	1085	/* allocate crtcs */
1430	serge	1086	for (i = 0; i < rdev->num_crtc; i++) {
1123	serge	1087	radeon_crtc_init(rdev->ddev, i);
		1088	}
		1089
3192	Serge	1090	dbgprintf("crtc init\n");
		1091
1123	serge	1092	/* okay we should have all the bios connectors */
		1093	ret = radeon_setup_enc_conn(rdev->ddev);
		1094	if (!ret) {
		1095	return ret;
		1096	}
1963	serge	1097
2997	Serge	1098	/* init dig PHYs, disp eng pll */
		1099	if (rdev->is_atom_bios) {
1963	serge	1100	radeon_atom_encoder_init(rdev);
2997	Serge	1101	radeon_atom_disp_eng_pll_init(rdev);
		1102	}
1963	serge	1103
1404	serge	1104	/* initialize hpd */
1963	serge	1105	// radeon_hpd_init(rdev);
		1106
2997	Serge	1107	/* setup afmt */
		1108	// radeon_afmt_init(rdev);
		1109
1963	serge	1110	/* Initialize power management */
		1111	// radeon_pm_init(rdev);
		1112
		1113	radeon_fbdev_init(rdev);
		1114	// drm_kms_helper_poll_init(rdev->ddev);
		1115
3192	Serge	1116	LEAVE();
		1117
1123	serge	1118	return 0;
		1119	}
		1120
		1121	void radeon_modeset_fini(struct radeon_device *rdev)
		1122	{
1430	serge	1123	kfree(rdev->mode_info.bios_hardcoded_edid);
		1124
1123	serge	1125	if (rdev->mode_info.mode_config_initialized) {
2997	Serge	1126	// radeon_afmt_fini(rdev);
1963	serge	1127	// drm_kms_helper_poll_fini(rdev->ddev);
		1128	// radeon_hpd_fini(rdev);
1123	serge	1129	drm_mode_config_cleanup(rdev->ddev);
		1130	rdev->mode_info.mode_config_initialized = false;
		1131	}
1963	serge	1132	/* free i2c buses */
		1133	radeon_i2c_fini(rdev);
1123	serge	1134	}
		1135
2997	Serge	1136	static bool is_hdtv_mode(const struct drm_display_mode *mode)
1963	serge	1137	{
		1138	/* try and guess if this is a tv or a monitor */
		1139	if ((mode->vdisplay == 480 && mode->hdisplay == 720) \|\| /* 480p */
		1140	(mode->vdisplay == 576) \|\| /* 576p */
		1141	(mode->vdisplay == 720) \|\| /* 720p */
		1142	(mode->vdisplay == 1080)) /* 1080p */
		1143	return true;
		1144	else
		1145	return false;
		1146	}
		1147
1179	serge	1148	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
2997	Serge	1149	const struct drm_display_mode *mode,
1179	serge	1150	struct drm_display_mode *adjusted_mode)
1123	serge	1151	{
1179	serge	1152	struct drm_device *dev = crtc->dev;
1963	serge	1153	struct radeon_device *rdev = dev->dev_private;
1179	serge	1154	struct drm_encoder *encoder;
1123	serge	1155	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1179	serge	1156	struct radeon_encoder *radeon_encoder;
1963	serge	1157	struct drm_connector *connector;
		1158	struct radeon_connector *radeon_connector;
1179	serge	1159	bool first = true;
1963	serge	1160	u32 src_v = 1, dst_v = 1;
		1161	u32 src_h = 1, dst_h = 1;
1123	serge	1162
1963	serge	1163	radeon_crtc->h_border = 0;
		1164	radeon_crtc->v_border = 0;
		1165
2997	Serge	1166	ENTER();
		1167
1179	serge	1168	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1169	if (encoder->crtc != crtc)
		1170	continue;
1963	serge	1171	radeon_encoder = to_radeon_encoder(encoder);
		1172	connector = radeon_get_connector_for_encoder(encoder);
		1173	radeon_connector = to_radeon_connector(connector);
		1174
2997	Serge	1175	dbgprintf("native_hdisplay %d vdisplay %d\n",
		1176	radeon_encoder->native_mode.hdisplay,
		1177	radeon_encoder->native_mode.vdisplay);
		1178
1179	serge	1179	if (first) {
1404	serge	1180	/* set scaling */
		1181	if (radeon_encoder->rmx_type == RMX_OFF)
		1182	radeon_crtc->rmx_type = RMX_OFF;
		1183	else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay \|\|
		1184	mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1179	serge	1185	radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1404	serge	1186	else
		1187	radeon_crtc->rmx_type = RMX_OFF;
		1188	/* copy native mode */
1179	serge	1189	memcpy(&radeon_crtc->native_mode,
		1190	&radeon_encoder->native_mode,
1268	serge	1191	sizeof(struct drm_display_mode));
1963	serge	1192	src_v = crtc->mode.vdisplay;
		1193	dst_v = radeon_crtc->native_mode.vdisplay;
		1194	src_h = crtc->mode.hdisplay;
		1195	dst_h = radeon_crtc->native_mode.hdisplay;
		1196
		1197	/* fix up for overscan on hdmi */
		1198	if (ASIC_IS_AVIVO(rdev) &&
		1199	(!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
		1200	((radeon_encoder->underscan_type == UNDERSCAN_ON) \|\|
		1201	((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
		1202	drm_detect_hdmi_monitor(radeon_connector->edid) &&
		1203	is_hdtv_mode(mode)))) {
		1204	if (radeon_encoder->underscan_hborder != 0)
		1205	radeon_crtc->h_border = radeon_encoder->underscan_hborder;
		1206	else
		1207	radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
		1208	if (radeon_encoder->underscan_vborder != 0)
		1209	radeon_crtc->v_border = radeon_encoder->underscan_vborder;
		1210	else
		1211	radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
		1212	radeon_crtc->rmx_type = RMX_FULL;
		1213	src_v = crtc->mode.vdisplay;
		1214	dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
		1215	src_h = crtc->mode.hdisplay;
		1216	dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
		1217	}
1179	serge	1218	first = false;
		1219	} else {
		1220	if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
		1221	/* WARNING: Right now this can't happen but
		1222	* in the future we need to check that scaling
1963	serge	1223	* are consistent across different encoder
1179	serge	1224	* (ie all encoder can work with the same
		1225	* scaling).
		1226	*/
1963	serge	1227	DRM_ERROR("Scaling not consistent across encoder.\n");
1179	serge	1228	return false;
		1229	}
1123	serge	1230	}
		1231	}
1179	serge	1232	if (radeon_crtc->rmx_type != RMX_OFF) {
1221	serge	1233	fixed20_12 a, b;
1963	serge	1234	a.full = dfixed_const(src_v);
		1235	b.full = dfixed_const(dst_v);
		1236	radeon_crtc->vsc.full = dfixed_div(a, b);
		1237	a.full = dfixed_const(src_h);
		1238	b.full = dfixed_const(dst_h);
		1239	radeon_crtc->hsc.full = dfixed_div(a, b);
1123	serge	1240	} else {
1963	serge	1241	radeon_crtc->vsc.full = dfixed_const(1);
		1242	radeon_crtc->hsc.full = dfixed_const(1);
1123	serge	1243	}
2997	Serge	1244
		1245	LEAVE();
		1246
1179	serge	1247	return true;
1123	serge	1248	}
1963	serge	1249
		1250	/*
		1251	* Retrieve current video scanout position of crtc on a given gpu.
		1252	*
		1253	* \param dev Device to query.
		1254	* \param crtc Crtc to query.
		1255	* \param *vpos Location where vertical scanout position should be stored.
		1256	* \param *hpos Location where horizontal scanout position should go.
		1257	*
		1258	* Returns vpos as a positive number while in active scanout area.
		1259	* Returns vpos as a negative number inside vblank, counting the number
		1260	* of scanlines to go until end of vblank, e.g., -1 means "one scanline
		1261	* until start of active scanout / end of vblank."
		1262	*
		1263	* \return Flags, or'ed together as follows:
		1264	*
		1265	* DRM_SCANOUTPOS_VALID = Query successful.
		1266	* DRM_SCANOUTPOS_INVBL = Inside vblank.
		1267	* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
		1268	* this flag means that returned position may be offset by a constant but
		1269	* unknown small number of scanlines wrt. real scanout position.
		1270	*
		1271	*/
		1272	int radeon_get_crtc_scanoutpos(struct drm_device dev, int crtc, int vpos, int *hpos)
		1273	{
		1274	u32 stat_crtc = 0, vbl = 0, position = 0;
		1275	int vbl_start, vbl_end, vtotal, ret = 0;
		1276	bool in_vbl = true;
		1277
		1278	struct radeon_device *rdev = dev->dev_private;
		1279
		1280	if (ASIC_IS_DCE4(rdev)) {
		1281	if (crtc == 0) {
		1282	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1283	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1284	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1285	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1286	ret \|= DRM_SCANOUTPOS_VALID;
		1287	}
		1288	if (crtc == 1) {
		1289	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1290	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1291	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1292	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1293	ret \|= DRM_SCANOUTPOS_VALID;
		1294	}
		1295	if (crtc == 2) {
		1296	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1297	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1298	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1299	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1300	ret \|= DRM_SCANOUTPOS_VALID;
		1301	}
		1302	if (crtc == 3) {
		1303	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1304	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1305	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1306	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1307	ret \|= DRM_SCANOUTPOS_VALID;
		1308	}
		1309	if (crtc == 4) {
		1310	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1311	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1312	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1313	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1314	ret \|= DRM_SCANOUTPOS_VALID;
		1315	}
		1316	if (crtc == 5) {
		1317	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1318	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1319	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1320	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1321	ret \|= DRM_SCANOUTPOS_VALID;
		1322	}
		1323	} else if (ASIC_IS_AVIVO(rdev)) {
		1324	if (crtc == 0) {
		1325	vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
		1326	position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
		1327	ret \|= DRM_SCANOUTPOS_VALID;
		1328	}
		1329	if (crtc == 1) {
		1330	vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
		1331	position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
		1332	ret \|= DRM_SCANOUTPOS_VALID;
		1333	}
		1334	} else {
		1335	/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
		1336	if (crtc == 0) {
		1337	/* Assume vbl_end == 0, get vbl_start from
		1338	* upper 16 bits.
		1339	*/
		1340	vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
		1341	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1342	/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
		1343	position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1344	stat_crtc = RREG32(RADEON_CRTC_STATUS);
		1345	if (!(stat_crtc & 1))
		1346	in_vbl = false;
		1347
		1348	ret \|= DRM_SCANOUTPOS_VALID;
		1349	}
		1350	if (crtc == 1) {
		1351	vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
		1352	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1353	position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1354	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
		1355	if (!(stat_crtc & 1))
		1356	in_vbl = false;
		1357
		1358	ret \|= DRM_SCANOUTPOS_VALID;
		1359	}
		1360	}
		1361
		1362	/* Decode into vertical and horizontal scanout position. */
		1363	*vpos = position & 0x1fff;
		1364	*hpos = (position >> 16) & 0x1fff;
		1365
		1366	/* Valid vblank area boundaries from gpu retrieved? */
		1367	if (vbl > 0) {
		1368	/* Yes: Decode. */
		1369	ret \|= DRM_SCANOUTPOS_ACCURATE;
		1370	vbl_start = vbl & 0x1fff;
		1371	vbl_end = (vbl >> 16) & 0x1fff;
		1372	}
		1373	else {
		1374	/* No: Fake something reasonable which gives at least ok results. */
		1375	vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
		1376	vbl_end = 0;
		1377	}
		1378
		1379	/* Test scanout position against vblank region. */
		1380	if ((vpos < vbl_start) && (vpos >= vbl_end))
		1381	in_vbl = false;
		1382
		1383	/* Check if inside vblank area and apply corrective offsets:
		1384	* vpos will then be >=0 in video scanout area, but negative
		1385	* within vblank area, counting down the number of lines until
		1386	* start of scanout.
		1387	*/
		1388
		1389	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
		1390	if (in_vbl && (*vpos >= vbl_start)) {
		1391	vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
		1392	vpos = vpos - vtotal;
		1393	}
		1394
		1395	/* Correct for shifted end of vbl at vbl_end. */
		1396	vpos = vpos - vbl_end;
		1397
		1398	/* In vblank? */
		1399	if (in_vbl)
		1400	ret \|= DRM_SCANOUTPOS_INVBL;
		1401
		1402	return ret;
		1403	}

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(root)/drivers/video/drm/radeon/radeon_display.c @ 3764 – Rev 3192