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| Rev | Author | Line No. | Line |
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| 1123 | serge | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: Dave Airlie |
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| 24 | * Alex Deucher |
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| 25 | */ |
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| 2997 | Serge | 26 | #include |
| 27 | #include |
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| 1123 | serge | 28 | #include "radeon.h" |
| 29 | |||
| 30 | #include "atom.h" |
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| 1963 | serge | 31 | #include |
| 1123 | serge | 32 | |
| 2997 | Serge | 33 | #include |
| 34 | #include |
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| 1123 | serge | 35 | |
| 36 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
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| 37 | { |
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| 38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 39 | struct drm_device *dev = crtc->dev; |
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| 40 | struct radeon_device *rdev = dev->dev_private; |
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| 41 | int i; |
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| 42 | |||
| 1963 | serge | 43 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
| 1123 | serge | 44 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
| 45 | |||
| 46 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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| 47 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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| 48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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| 49 | |||
| 50 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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| 51 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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| 52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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| 53 | |||
| 54 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
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| 55 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
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| 56 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
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| 57 | |||
| 58 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
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| 59 | for (i = 0; i < 256; i++) { |
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| 60 | WREG32(AVIVO_DC_LUT_30_COLOR, |
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| 61 | (radeon_crtc->lut_r[i] << 20) | |
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| 62 | (radeon_crtc->lut_g[i] << 10) | |
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| 63 | (radeon_crtc->lut_b[i] << 0)); |
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| 64 | } |
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| 65 | |||
| 66 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
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| 67 | } |
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| 68 | |||
| 1963 | serge | 69 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
| 1430 | serge | 70 | { |
| 71 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 72 | struct drm_device *dev = crtc->dev; |
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| 73 | struct radeon_device *rdev = dev->dev_private; |
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| 74 | int i; |
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| 75 | |||
| 1963 | serge | 76 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
| 1430 | serge | 77 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
| 78 | |||
| 79 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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| 80 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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| 81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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| 82 | |||
| 83 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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| 84 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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| 85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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| 86 | |||
| 1963 | serge | 87 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
| 88 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
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| 1430 | serge | 89 | |
| 1963 | serge | 90 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
| 1430 | serge | 91 | for (i = 0; i < 256; i++) { |
| 1963 | serge | 92 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
| 1430 | serge | 93 | (radeon_crtc->lut_r[i] << 20) | |
| 94 | (radeon_crtc->lut_g[i] << 10) | |
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| 95 | (radeon_crtc->lut_b[i] << 0)); |
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| 96 | } |
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| 97 | } |
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| 98 | |||
| 1963 | serge | 99 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
| 100 | { |
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| 101 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 102 | struct drm_device *dev = crtc->dev; |
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| 103 | struct radeon_device *rdev = dev->dev_private; |
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| 104 | int i; |
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| 105 | |||
| 106 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
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| 107 | |||
| 108 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
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| 109 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
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| 110 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
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| 111 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
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| 112 | NI_GRPH_PRESCALE_BYPASS); |
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| 113 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
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| 114 | NI_OVL_PRESCALE_BYPASS); |
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| 115 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
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| 116 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
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| 117 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
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| 118 | |||
| 119 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
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| 120 | |||
| 121 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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| 122 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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| 123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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| 124 | |||
| 125 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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| 126 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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| 127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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| 128 | |||
| 129 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
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| 130 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
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| 131 | |||
| 132 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
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| 133 | for (i = 0; i < 256; i++) { |
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| 134 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
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| 135 | (radeon_crtc->lut_r[i] << 20) | |
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| 136 | (radeon_crtc->lut_g[i] << 10) | |
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| 137 | (radeon_crtc->lut_b[i] << 0)); |
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| 138 | } |
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| 139 | |||
| 140 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
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| 141 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
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| 142 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
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| 143 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
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| 144 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
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| 145 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
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| 146 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
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| 147 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
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| 148 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
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| 149 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
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| 150 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
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| 151 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
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| 152 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | |
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| 153 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
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| 154 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
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| 155 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
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| 156 | |||
| 157 | } |
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| 158 | |||
| 1123 | serge | 159 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
| 160 | { |
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| 161 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 162 | struct drm_device *dev = crtc->dev; |
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| 163 | struct radeon_device *rdev = dev->dev_private; |
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| 164 | int i; |
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| 165 | uint32_t dac2_cntl; |
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| 166 | |||
| 167 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
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| 168 | if (radeon_crtc->crtc_id == 0) |
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| 169 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
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| 170 | else |
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| 171 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
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| 172 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
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| 173 | |||
| 174 | WREG8(RADEON_PALETTE_INDEX, 0); |
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| 175 | for (i = 0; i < 256; i++) { |
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| 176 | WREG32(RADEON_PALETTE_30_DATA, |
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| 177 | (radeon_crtc->lut_r[i] << 20) | |
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| 178 | (radeon_crtc->lut_g[i] << 10) | |
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| 179 | (radeon_crtc->lut_b[i] << 0)); |
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| 180 | } |
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| 181 | } |
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| 182 | |||
| 183 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
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| 184 | { |
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| 185 | struct drm_device *dev = crtc->dev; |
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| 186 | struct radeon_device *rdev = dev->dev_private; |
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| 187 | |||
| 188 | if (!crtc->enabled) |
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| 189 | return; |
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| 190 | |||
| 1963 | serge | 191 | if (ASIC_IS_DCE5(rdev)) |
| 192 | dce5_crtc_load_lut(crtc); |
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| 193 | else if (ASIC_IS_DCE4(rdev)) |
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| 194 | dce4_crtc_load_lut(crtc); |
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| 1430 | serge | 195 | else if (ASIC_IS_AVIVO(rdev)) |
| 1123 | serge | 196 | avivo_crtc_load_lut(crtc); |
| 197 | else |
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| 198 | legacy_crtc_load_lut(crtc); |
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| 199 | } |
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| 200 | |||
| 1221 | serge | 201 | /** Sets the color ramps on behalf of fbcon */ |
| 1123 | serge | 202 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 203 | u16 blue, int regno) |
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| 204 | { |
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| 205 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 206 | |||
| 207 | radeon_crtc->lut_r[regno] = red >> 6; |
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| 208 | radeon_crtc->lut_g[regno] = green >> 6; |
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| 209 | radeon_crtc->lut_b[regno] = blue >> 6; |
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| 210 | } |
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| 211 | |||
| 1221 | serge | 212 | /** Gets the color ramps on behalf of fbcon */ |
| 213 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
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| 214 | u16 *blue, int regno) |
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| 215 | { |
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| 216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 217 | |||
| 218 | *red = radeon_crtc->lut_r[regno] << 6; |
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| 219 | *green = radeon_crtc->lut_g[regno] << 6; |
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| 220 | *blue = radeon_crtc->lut_b[regno] << 6; |
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| 221 | } |
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| 222 | |||
| 1123 | serge | 223 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 1963 | serge | 224 | u16 *blue, uint32_t start, uint32_t size) |
| 1123 | serge | 225 | { |
| 226 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 1963 | serge | 227 | int end = (start + size > 256) ? 256 : start + size, i; |
| 1123 | serge | 228 | |
| 1221 | serge | 229 | /* userspace palettes are always correct as is */ |
| 1963 | serge | 230 | for (i = start; i < end; i++) { |