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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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26 | #include "drmP.h" |
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27 | #include "radeon_drm.h" |
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28 | #include "radeon.h" |
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29 | |||
30 | #include "atom.h" |
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31 | //#include |
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32 | |||
33 | #include "drm_crtc_helper.h" |
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34 | #include "drm_edid.h" |
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35 | |||
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
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37 | |||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
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39 | { |
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40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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41 | struct drm_device *dev = crtc->dev; |
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42 | struct radeon_device *rdev = dev->dev_private; |
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43 | int i; |
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44 | |||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); |
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46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
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47 | |||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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51 | |||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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55 | |||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
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57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
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58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
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59 | |||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
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61 | for (i = 0; i < 256; i++) { |
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62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
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63 | (radeon_crtc->lut_r[i] << 20) | |
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64 | (radeon_crtc->lut_g[i] << 10) | |
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65 | (radeon_crtc->lut_b[i] << 0)); |
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66 | } |
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67 | |||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
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69 | } |
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70 | |||
71 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
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72 | { |
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73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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74 | struct drm_device *dev = crtc->dev; |
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75 | struct radeon_device *rdev = dev->dev_private; |
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76 | int i; |
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77 | uint32_t dac2_cntl; |
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78 | |||
79 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
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80 | if (radeon_crtc->crtc_id == 0) |
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81 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
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82 | else |
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83 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
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84 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
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85 | |||
86 | WREG8(RADEON_PALETTE_INDEX, 0); |
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87 | for (i = 0; i < 256; i++) { |
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88 | WREG32(RADEON_PALETTE_30_DATA, |
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89 | (radeon_crtc->lut_r[i] << 20) | |
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90 | (radeon_crtc->lut_g[i] << 10) | |
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91 | (radeon_crtc->lut_b[i] << 0)); |
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92 | } |
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93 | } |
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94 | |||
95 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
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96 | { |
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97 | struct drm_device *dev = crtc->dev; |
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98 | struct radeon_device *rdev = dev->dev_private; |
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99 | |||
100 | if (!crtc->enabled) |
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101 | return; |
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102 | |||
103 | if (ASIC_IS_AVIVO(rdev)) |
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104 | avivo_crtc_load_lut(crtc); |
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105 | else |
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106 | legacy_crtc_load_lut(crtc); |
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107 | } |
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108 | |||
109 | /** Sets the color ramps on behalf of RandR */ |
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110 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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111 | u16 blue, int regno) |
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112 | { |
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113 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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114 | |||
115 | if (regno == 0) |
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116 | DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id); |
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117 | radeon_crtc->lut_r[regno] = red >> 6; |
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118 | radeon_crtc->lut_g[regno] = green >> 6; |
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119 | radeon_crtc->lut_b[regno] = blue >> 6; |
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120 | } |
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121 | |||
122 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
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123 | u16 *blue, uint32_t size) |
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124 | { |
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125 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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126 | int i, j; |
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127 | |||
128 | if (size != 256) { |
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129 | return; |
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130 | } |
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131 | if (crtc->fb == NULL) { |
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132 | return; |
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133 | } |
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134 | |||
135 | if (crtc->fb->depth == 16) { |
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136 | for (i = 0; i < 64; i++) { |
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137 | if (i <= 31) { |
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138 | for (j = 0; j < 8; j++) { |
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139 | radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6; |
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140 | radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6; |
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141 | } |
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142 | } |
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143 | for (j = 0; j < 4; j++) |
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144 | radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6; |
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145 | } |
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146 | } else { |
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147 | for (i = 0; i < 256; i++) { |
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148 | radeon_crtc->lut_r[i] = red[i] >> 6; |
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149 | radeon_crtc->lut_g[i] = green[i] >> 6; |
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150 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
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151 | } |
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152 | } |
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153 | |||
154 | radeon_crtc_load_lut(crtc); |
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155 | } |
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156 | |||
157 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
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158 | { |
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159 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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160 | |||
161 | if (radeon_crtc->mode_set.mode) { |
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162 | drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode); |
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163 | } |
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164 | drm_crtc_cleanup(crtc); |
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165 | kfree(radeon_crtc); |
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166 | } |
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167 | |||
168 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
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169 | // .cursor_set = radeon_crtc_cursor_set, |
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170 | // .cursor_move = radeon_crtc_cursor_move, |
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171 | .gamma_set = radeon_crtc_gamma_set, |
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172 | // .set_config = drm_crtc_helper_set_config, |
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173 | .destroy = radeon_crtc_destroy, |
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174 | }; |
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175 | |||
176 | static void radeon_crtc_init(struct drm_device *dev, int index) |
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177 | { |
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178 | struct radeon_device *rdev = dev->dev_private; |
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179 | struct radeon_crtc *radeon_crtc; |
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180 | int i; |
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181 | |||
1125 | serge | 182 | ENTRY(); |
183 | |||
1123 | serge | 184 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
185 | if (radeon_crtc == NULL) |
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186 | return; |
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187 | |||
188 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
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189 | |||
190 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
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191 | radeon_crtc->crtc_id = index; |
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192 | |||
193 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
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194 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
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195 | radeon_crtc->mode_set.num_connectors = 0; |
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196 | |||
197 | for (i = 0; i < 256; i++) { |
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198 | radeon_crtc->lut_r[i] = i << 2; |
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199 | radeon_crtc->lut_g[i] = i << 2; |
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200 | radeon_crtc->lut_b[i] = i << 2; |
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201 | } |
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202 | |||
203 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
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204 | radeon_atombios_init_crtc(dev, radeon_crtc); |
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205 | else |
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206 | radeon_legacy_init_crtc(dev, radeon_crtc); |
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1125 | serge | 207 | |
208 | LEAVE(); |
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1123 | serge | 209 | } |
210 | |||
211 | static const char *encoder_names[34] = { |
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212 | "NONE", |
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213 | "INTERNAL_LVDS", |
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214 | "INTERNAL_TMDS1", |
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215 | "INTERNAL_TMDS2", |
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216 | "INTERNAL_DAC1", |
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217 | "INTERNAL_DAC2", |
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218 | "INTERNAL_SDVOA", |
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219 | "INTERNAL_SDVOB", |
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220 | "SI170B", |
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221 | "CH7303", |
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222 | "CH7301", |
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223 | "INTERNAL_DVO1", |
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224 | "EXTERNAL_SDVOA", |
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225 | "EXTERNAL_SDVOB", |
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226 | "TITFP513", |
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227 | "INTERNAL_LVTM1", |
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228 | "VT1623", |
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229 | "HDMI_SI1930", |
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230 | "HDMI_INTERNAL", |
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231 | "INTERNAL_KLDSCP_TMDS1", |
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232 | "INTERNAL_KLDSCP_DVO1", |
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233 | "INTERNAL_KLDSCP_DAC1", |
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234 | "INTERNAL_KLDSCP_DAC2", |
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235 | "SI178", |
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236 | "MVPU_FPGA", |
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237 | "INTERNAL_DDI", |
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238 | "VT1625", |
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239 | "HDMI_SI1932", |
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240 | "DP_AN9801", |
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241 | "DP_DP501", |
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242 | "INTERNAL_UNIPHY", |
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243 | "INTERNAL_KLDSCP_LVTMA", |
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244 | "INTERNAL_UNIPHY1", |
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245 | "INTERNAL_UNIPHY2", |
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246 | }; |
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247 | |||
248 | static const char *connector_names[13] = { |
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249 | "Unknown", |
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250 | "VGA", |
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251 | "DVI-I", |
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252 | "DVI-D", |
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253 | "DVI-A", |
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254 | "Composite", |
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255 | "S-video", |
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256 | "LVDS", |
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257 | "Component", |
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258 | "DIN", |
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259 | "DisplayPort", |
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260 | "HDMI-A", |
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261 | "HDMI-B", |
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262 | }; |
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263 | |||
264 | static void radeon_print_display_setup(struct drm_device *dev) |
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265 | { |
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266 | struct drm_connector *connector; |
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267 | struct radeon_connector *radeon_connector; |
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268 | struct drm_encoder *encoder; |
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269 | struct radeon_encoder *radeon_encoder; |
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270 | uint32_t devices; |
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271 | int i = 0; |
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272 | |||
273 | DRM_INFO("Radeon Display Connectors\n"); |
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274 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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275 | radeon_connector = to_radeon_connector(connector); |
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276 | DRM_INFO("Connector %d:\n", i); |
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277 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
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278 | if (radeon_connector->ddc_bus) |
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279 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
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280 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
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281 | radeon_connector->ddc_bus->rec.mask_data_reg, |
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282 | radeon_connector->ddc_bus->rec.a_clk_reg, |
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283 | radeon_connector->ddc_bus->rec.a_data_reg, |
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284 | radeon_connector->ddc_bus->rec.put_clk_reg, |
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285 | radeon_connector->ddc_bus->rec.put_data_reg, |
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286 | radeon_connector->ddc_bus->rec.get_clk_reg, |
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287 | radeon_connector->ddc_bus->rec.get_data_reg); |
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288 | DRM_INFO(" Encoders:\n"); |
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289 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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290 | radeon_encoder = to_radeon_encoder(encoder); |
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291 | devices = radeon_encoder->devices & radeon_connector->devices; |
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292 | if (devices) { |
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293 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
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294 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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295 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
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296 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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297 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
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298 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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299 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
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300 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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301 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
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302 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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303 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
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304 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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305 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
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306 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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307 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
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308 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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309 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
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310 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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311 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
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312 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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313 | } |
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314 | } |
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315 | i++; |
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316 | } |
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317 | } |
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318 | |||
319 | bool radeon_setup_enc_conn(struct drm_device *dev) |
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320 | { |
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321 | struct radeon_device *rdev = dev->dev_private; |
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322 | struct drm_connector *drm_connector; |
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323 | bool ret = false; |
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324 | |||
1125 | serge | 325 | ENTRY(); |
326 | |||
1123 | serge | 327 | if (rdev->bios) { |
328 | if (rdev->is_atom_bios) { |
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329 | if (rdev->family >= CHIP_R600) |
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330 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
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331 | else |
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332 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
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333 | } else |
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334 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
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335 | } else { |
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336 | if (!ASIC_IS_AVIVO(rdev)) |
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337 | ret = radeon_get_legacy_connector_info_from_table(dev); |
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338 | } |
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339 | if (ret) { |
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340 | radeon_print_display_setup(dev); |
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341 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
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342 | radeon_ddc_dump(drm_connector); |
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343 | } |
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1125 | serge | 344 | LEAVE(); |
1123 | serge | 345 | |
346 | return ret; |
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347 | } |
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348 | |||
349 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
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350 | { |
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351 | struct edid *edid; |
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352 | int ret = 0; |
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353 | |||
354 | if (!radeon_connector->ddc_bus) |
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355 | return -1; |
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356 | radeon_i2c_do_lock(radeon_connector, 1); |
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357 | edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
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358 | radeon_i2c_do_lock(radeon_connector, 0); |
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359 | if (edid) { |
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360 | /* update digital bits here */ |
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361 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
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362 | radeon_connector->use_digital = 1; |
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363 | else |
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364 | radeon_connector->use_digital = 0; |
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365 | drm_mode_connector_update_edid_property(&radeon_connector->base, edid); |
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366 | ret = drm_add_edid_modes(&radeon_connector->base, edid); |
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367 | kfree(edid); |
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368 | return ret; |
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369 | } |
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370 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
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371 | return -1; |
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372 | } |
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373 | |||
374 | static int radeon_ddc_dump(struct drm_connector *connector) |
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375 | { |
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376 | struct edid *edid; |
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377 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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378 | int ret = 0; |
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379 | |||
380 | if (!radeon_connector->ddc_bus) |
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381 | return -1; |
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382 | radeon_i2c_do_lock(radeon_connector, 1); |
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383 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
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384 | radeon_i2c_do_lock(radeon_connector, 0); |
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385 | if (edid) { |
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386 | kfree(edid); |
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387 | } |
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388 | return ret; |
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389 | } |
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390 | |||
391 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
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392 | { |
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393 | uint64_t mod; |
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394 | |||
395 | n += d / 2; |
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396 | |||
397 | mod = do_div(n, d); |
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398 | return n; |
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399 | } |
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400 | |||
401 | void radeon_compute_pll(struct radeon_pll *pll, |
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402 | uint64_t freq, |
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403 | uint32_t *dot_clock_p, |
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404 | uint32_t *fb_div_p, |
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405 | uint32_t *frac_fb_div_p, |
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406 | uint32_t *ref_div_p, |
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407 | uint32_t *post_div_p, |
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408 | int flags) |
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409 | { |
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410 | uint32_t min_ref_div = pll->min_ref_div; |
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411 | uint32_t max_ref_div = pll->max_ref_div; |
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412 | uint32_t min_fractional_feed_div = 0; |
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413 | uint32_t max_fractional_feed_div = 0; |
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414 | uint32_t best_vco = pll->best_vco; |
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415 | uint32_t best_post_div = 1; |
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416 | uint32_t best_ref_div = 1; |
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417 | uint32_t best_feedback_div = 1; |
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418 | uint32_t best_frac_feedback_div = 0; |
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419 | uint32_t best_freq = -1; |
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420 | uint32_t best_error = 0xffffffff; |
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421 | uint32_t best_vco_diff = 1; |
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422 | uint32_t post_div; |
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423 | |||
424 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
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425 | freq = freq * 1000; |
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426 | |||
427 | if (flags & RADEON_PLL_USE_REF_DIV) |
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428 | min_ref_div = max_ref_div = pll->reference_div; |
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429 | else { |
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430 | while (min_ref_div < max_ref_div-1) { |
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431 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
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432 | uint32_t pll_in = pll->reference_freq / mid; |
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433 | if (pll_in < pll->pll_in_min) |
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434 | max_ref_div = mid; |
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435 | else if (pll_in > pll->pll_in_max) |
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436 | min_ref_div = mid; |
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437 | else |
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438 | break; |
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439 | } |
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440 | } |
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441 | |||
442 | if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
443 | min_fractional_feed_div = pll->min_frac_feedback_div; |
||
444 | max_fractional_feed_div = pll->max_frac_feedback_div; |
||
445 | } |
||
446 | |||
447 | for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { |
||
448 | uint32_t ref_div; |
||
449 | |||
450 | if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
||
451 | continue; |
||
452 | |||
453 | /* legacy radeons only have a few post_divs */ |
||
454 | if (flags & RADEON_PLL_LEGACY) { |
||
455 | if ((post_div == 5) || |
||
456 | (post_div == 7) || |
||
457 | (post_div == 9) || |
||
458 | (post_div == 10) || |
||
459 | (post_div == 11) || |
||
460 | (post_div == 13) || |
||
461 | (post_div == 14) || |
||
462 | (post_div == 15)) |
||
463 | continue; |
||
464 | } |
||
465 | |||
466 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
||
467 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
||
468 | uint32_t pll_in = pll->reference_freq / ref_div; |
||
469 | uint32_t min_feed_div = pll->min_feedback_div; |
||
470 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
||
471 | |||
472 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
||
473 | continue; |
||
474 | |||
475 | while (min_feed_div < max_feed_div) { |
||
476 | uint32_t vco; |
||
477 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
||
478 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
||
479 | uint32_t frac_feedback_div; |
||
480 | uint64_t tmp; |
||
481 | |||
482 | feedback_div = (min_feed_div + max_feed_div) / 2; |
||
483 | |||
484 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
||
485 | vco = radeon_div(tmp, ref_div); |
||
486 | |||
487 | if (vco < pll->pll_out_min) { |
||
488 | min_feed_div = feedback_div + 1; |
||
489 | continue; |
||
490 | } else if (vco > pll->pll_out_max) { |
||
491 | max_feed_div = feedback_div; |
||
492 | continue; |
||
493 | } |
||
494 | |||
495 | while (min_frac_feed_div < max_frac_feed_div) { |
||
496 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
||
497 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
||
498 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
||
499 | current_freq = radeon_div(tmp, ref_div * post_div); |
||
500 | |||
501 | error = abs(current_freq - freq); |
||
502 | vco_diff = abs(vco - best_vco); |
||
503 | |||
504 | if ((best_vco == 0 && error < best_error) || |
||
505 | (best_vco != 0 && |
||
506 | (error < best_error - 100 || |
||
507 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
||
508 | best_post_div = post_div; |
||
509 | best_ref_div = ref_div; |
||
510 | best_feedback_div = feedback_div; |
||
511 | best_frac_feedback_div = frac_feedback_div; |
||
512 | best_freq = current_freq; |
||
513 | best_error = error; |
||
514 | best_vco_diff = vco_diff; |
||
515 | } else if (current_freq == freq) { |
||
516 | if (best_freq == -1) { |
||
517 | best_post_div = post_div; |
||
518 | best_ref_div = ref_div; |
||
519 | best_feedback_div = feedback_div; |
||
520 | best_frac_feedback_div = frac_feedback_div; |
||
521 | best_freq = current_freq; |
||
522 | best_error = error; |
||
523 | best_vco_diff = vco_diff; |
||
524 | } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
||
525 | ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
||
526 | ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
||
527 | ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
||
528 | ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
||
529 | ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
||
530 | best_post_div = post_div; |
||
531 | best_ref_div = ref_div; |
||
532 | best_feedback_div = feedback_div; |
||
533 | best_frac_feedback_div = frac_feedback_div; |
||
534 | best_freq = current_freq; |
||
535 | best_error = error; |
||
536 | best_vco_diff = vco_diff; |
||
537 | } |
||
538 | } |
||
539 | if (current_freq < freq) |
||
540 | min_frac_feed_div = frac_feedback_div + 1; |
||
541 | else |
||
542 | max_frac_feed_div = frac_feedback_div; |
||
543 | } |
||
544 | if (current_freq < freq) |
||
545 | min_feed_div = feedback_div + 1; |
||
546 | else |
||
547 | max_feed_div = feedback_div; |
||
548 | } |
||
549 | } |
||
550 | } |
||
551 | |||
552 | *dot_clock_p = best_freq / 10000; |
||
553 | *fb_div_p = best_feedback_div; |
||
554 | *frac_fb_div_p = best_frac_feedback_div; |
||
555 | *ref_div_p = best_ref_div; |
||
556 | *post_div_p = best_post_div; |
||
557 | } |
||
558 | |||
559 | #if 0 |
||
560 | |||
561 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
||
562 | { |
||
563 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
564 | struct drm_device *dev = fb->dev; |
||
565 | |||
566 | if (fb->fbdev) |
||
567 | radeonfb_remove(dev, fb); |
||
568 | |||
569 | // if (radeon_fb->obj) { |
||
570 | // radeon_gem_object_unpin(radeon_fb->obj); |
||
571 | // mutex_lock(&dev->struct_mutex); |
||
572 | // drm_gem_object_unreference(radeon_fb->obj); |
||
573 | // mutex_unlock(&dev->struct_mutex); |
||
574 | // } |
||
575 | drm_framebuffer_cleanup(fb); |
||
576 | kfree(radeon_fb); |
||
577 | } |
||
578 | |||
579 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
||
580 | struct drm_file *file_priv, |
||
581 | unsigned int *handle) |
||
582 | { |
||
583 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
584 | |||
585 | return NULL; |
||
586 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
||
587 | } |
||
588 | |||
589 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
||
590 | .destroy = radeon_user_framebuffer_destroy, |
||
591 | .create_handle = radeon_user_framebuffer_create_handle, |
||
592 | }; |
||
593 | |||
1125 | serge | 594 | #endif |
595 | |||
1123 | serge | 596 | struct drm_framebuffer * |
597 | radeon_framebuffer_create(struct drm_device *dev, |
||
598 | struct drm_mode_fb_cmd *mode_cmd, |
||
599 | struct drm_gem_object *obj) |
||
600 | { |
||
601 | struct radeon_framebuffer *radeon_fb; |
||
602 | |||
603 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); |
||
604 | if (radeon_fb == NULL) { |
||
605 | return NULL; |
||
606 | } |
||
1125 | serge | 607 | // drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); |
608 | // drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); |
||
1123 | serge | 609 | radeon_fb->obj = obj; |
610 | return &radeon_fb->base; |
||
611 | } |
||
612 | |||
613 | static struct drm_framebuffer * |
||
614 | radeon_user_framebuffer_create(struct drm_device *dev, |
||
615 | struct drm_file *file_priv, |
||
616 | struct drm_mode_fb_cmd *mode_cmd) |
||
617 | { |
||
618 | struct drm_gem_object *obj; |
||
619 | |||
1125 | serge | 620 | return NULL; |
1123 | serge | 621 | |
1125 | serge | 622 | // obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); |
623 | // |
||
624 | // return radeon_framebuffer_create(dev, mode_cmd, obj); |
||
1123 | serge | 625 | } |
626 | |||
1125 | serge | 627 | |
1123 | serge | 628 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
1125 | serge | 629 | // .fb_create = radeon_user_framebuffer_create, |
630 | // .fb_changed = radeonfb_probe, |
||
1123 | serge | 631 | }; |
632 | |||
633 | |||
634 | int radeon_modeset_init(struct radeon_device *rdev) |
||
635 | { |
||
1125 | serge | 636 | |
637 | dbgprintf("%s\n",__FUNCTION__); |
||
638 | |||
1123 | serge | 639 | int num_crtc = 2, i; |
640 | int ret; |
||
641 | |||
642 | drm_mode_config_init(rdev->ddev); |
||
643 | rdev->mode_info.mode_config_initialized = true; |
||
644 | |||
1125 | serge | 645 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
1123 | serge | 646 | |
647 | if (ASIC_IS_AVIVO(rdev)) { |
||
648 | rdev->ddev->mode_config.max_width = 8192; |
||
649 | rdev->ddev->mode_config.max_height = 8192; |
||
650 | } else { |
||
651 | rdev->ddev->mode_config.max_width = 4096; |
||
652 | rdev->ddev->mode_config.max_height = 4096; |
||
653 | } |
||
654 | |||
655 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
||
656 | |||
657 | /* allocate crtcs - TODO single crtc */ |
||
658 | for (i = 0; i < num_crtc; i++) { |
||
659 | radeon_crtc_init(rdev->ddev, i); |
||
660 | } |
||
661 | |||
662 | /* okay we should have all the bios connectors */ |
||
663 | ret = radeon_setup_enc_conn(rdev->ddev); |
||
664 | if (!ret) { |
||
665 | return ret; |
||
666 | } |
||
667 | drm_helper_initial_config(rdev->ddev); |
||
1125 | serge | 668 | |
669 | dbgprintf("done %s\n",__FUNCTION__); |
||
670 | |||
1123 | serge | 671 | return 0; |
672 | } |
||
673 | |||
674 | void radeon_modeset_fini(struct radeon_device *rdev) |
||
675 | { |
||
676 | if (rdev->mode_info.mode_config_initialized) { |
||
677 | drm_mode_config_cleanup(rdev->ddev); |
||
678 | rdev->mode_info.mode_config_initialized = false; |
||
679 | } |
||
680 | } |
||
681 | |||
682 | void radeon_init_disp_bandwidth(struct drm_device *dev) |
||
683 | { |
||
684 | struct radeon_device *rdev = dev->dev_private; |
||
685 | struct drm_display_mode *modes[2]; |
||
686 | int pixel_bytes[2]; |
||
687 | struct drm_crtc *crtc; |
||
688 | |||
689 | pixel_bytes[0] = pixel_bytes[1] = 0; |
||
690 | modes[0] = modes[1] = NULL; |
||
691 | |||
692 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
||
693 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
694 | |||
695 | if (crtc->enabled && crtc->fb) { |
||
696 | modes[radeon_crtc->crtc_id] = &crtc->mode; |
||
697 | pixel_bytes[radeon_crtc->crtc_id] = crtc->fb->bits_per_pixel / 8; |
||
698 | } |
||
699 | } |
||
700 | |||
701 | if (ASIC_IS_AVIVO(rdev)) { |
||
702 | radeon_init_disp_bw_avivo(dev, |
||
703 | modes[0], |
||
704 | pixel_bytes[0], |
||
705 | modes[1], |
||
706 | pixel_bytes[1]); |
||
707 | } else { |
||
708 | radeon_init_disp_bw_legacy(dev, |
||
709 | modes[0], |
||
710 | pixel_bytes[0], |
||
711 | modes[1], |
||
712 | pixel_bytes[1]); |
||
713 | } |
||
714 | }>>>>>>>>>>>>>>=>=>>>><>><>><>>>>>=>>><>><>><>>><>><>><>> |