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1117 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
28
//#include 
2997 Serge 29
#include 
1179 serge 30
#include 
31
#include 
1221 serge 32
#include 
1117 serge 33
#include "radeon_reg.h"
34
#include "radeon.h"
35
#include "atom.h"
3120 serge 36
 
37
#include "bitmap.h"
1428 serge 38
#include "display.h"
1117 serge 39
 
3120 serge 40
 
1221 serge 41
#include 
42
 
5078 serge 43
#define PCI_VENDOR_ID_ATI               0x1002
44
#define PCI_VENDOR_ID_APPLE             0x106b
1117 serge 45
 
5078 serge 46
int radeon_no_wb;
1430 serge 47
int radeon_modeset = -1;
48
int radeon_dynclks = -1;
49
int radeon_r4xx_atom = 0;
50
int radeon_agpmode = 0;
51
int radeon_vram_limit = 0;
5078 serge 52
int radeon_gart_size = -1; /* auto */
1430 serge 53
int radeon_benchmarking = 0;
54
int radeon_testing = 0;
55
int radeon_connector_table = 0;
56
int radeon_tv = 1;
5078 serge 57
int radeon_audio = -1;
58
int radeon_disp_priority = 0;
1963 serge 59
int radeon_hw_i2c = 0;
5078 serge 60
int radeon_pcie_gen2 = -1;
61
int radeon_msi = -1;
2997 Serge 62
int radeon_lockup_timeout = 10000;
3764 Serge 63
int radeon_fastfb = 0;
5078 serge 64
int radeon_dpm = -1;
65
int radeon_aspm = -1;
66
int radeon_runtime_pm = -1;
67
int radeon_hard_reset = 0;
68
int radeon_vm_size = 8;
69
int radeon_vm_block_size = -1;
70
int radeon_deep_color = 0;
71
int radeon_use_pflipirq = 2;
2160 serge 72
int irq_override = 0;
5078 serge 73
int radeon_bapm = -1;
1430 serge 74
 
1963 serge 75
 
5078 serge 76
extern display_t *os_display;
77
extern struct drm_device *main_device;
78
extern videomode_t usermode;
1246 serge 79
 
3120 serge 80
 
1404 serge 81
void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
82
int init_display(struct radeon_device *rdev, videomode_t *mode);
5078 serge 83
int init_display_kms(struct drm_device *dev, videomode_t *usermode);
1117 serge 84
 
2997 Serge 85
int get_modes(videomode_t *mode, u32_t *count);
1404 serge 86
int set_user_mode(videomode_t *mode);
1428 serge 87
int r100_2D_test(struct radeon_device *rdev);
1239 serge 88
 
1404 serge 89
 
1233 serge 90
 /* Legacy VGA regions */
91
#define VGA_RSRC_NONE          0x00
92
#define VGA_RSRC_LEGACY_IO     0x01
93
#define VGA_RSRC_LEGACY_MEM    0x02
94
#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
95
/* Non-legacy access */
96
#define VGA_RSRC_NORMAL_IO     0x04
97
#define VGA_RSRC_NORMAL_MEM    0x08
98
 
99
 
1963 serge 100
static const char radeon_family_name[][16] = {
101
	"R100",
102
	"RV100",
103
	"RS100",
104
	"RV200",
105
	"RS200",
106
	"R200",
107
	"RV250",
108
	"RS300",
109
	"RV280",
110
	"R300",
111
	"R350",
112
	"RV350",
113
	"RV380",
114
	"R420",
115
	"R423",
116
	"RV410",
117
	"RS400",
118
	"RS480",
119
	"RS600",
120
	"RS690",
121
	"RS740",
122
	"RV515",
123
	"R520",
124
	"RV530",
125
	"RV560",
126
	"RV570",
127
	"R580",
128
	"R600",
129
	"RV610",
130
	"RV630",
131
	"RV670",
132
	"RV620",
133
	"RV635",
134
	"RS780",
135
	"RS880",
136
	"RV770",
137
	"RV730",
138
	"RV710",
139
	"RV740",
140
	"CEDAR",
141
	"REDWOOD",
142
	"JUNIPER",
143
	"CYPRESS",
144
	"HEMLOCK",
145
	"PALM",
1986 serge 146
	"SUMO",
147
	"SUMO2",
1963 serge 148
	"BARTS",
149
	"TURKS",
150
	"CAICOS",
151
	"CAYMAN",
2997 Serge 152
	"ARUBA",
153
	"TAHITI",
154
	"PITCAIRN",
155
	"VERDE",
3764 Serge 156
	"OLAND",
157
	"HAINAN",
5078 serge 158
	"BONAIRE",
159
	"KAVERI",
160
	"KABINI",
161
	"HAWAII",
162
	"MULLINS",
1963 serge 163
	"LAST",
164
};
1233 serge 165
 
5078 serge 166
#define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
167
#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
168
 
169
struct radeon_px_quirk {
170
	u32 chip_vendor;
171
	u32 chip_device;
172
	u32 subsys_vendor;
173
	u32 subsys_device;
174
	u32 px_quirk_flags;
175
};
176
 
177
static struct radeon_px_quirk radeon_px_quirk_list[] = {
178
	/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
179
	 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
180
	 */
181
	{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
182
	/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
183
	 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
184
	 */
185
	{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
186
	/* macbook pro 8.2 */
187
	{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
188
	{ 0, 0, 0, 0, 0 },
189
};
190
 
191
bool radeon_is_px(struct drm_device *dev)
192
{
193
	struct radeon_device *rdev = dev->dev_private;
194
 
195
	if (rdev->flags & RADEON_IS_PX)
196
		return true;
197
	return false;
198
}
199
 
200
static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
201
{
202
	struct radeon_px_quirk *p = radeon_px_quirk_list;
203
 
204
	/* Apply PX quirks */
205
	while (p && p->chip_device != 0) {
206
		if (rdev->pdev->vendor == p->chip_vendor &&
207
		    rdev->pdev->device == p->chip_device &&
208
		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
209
		    rdev->pdev->subsystem_device == p->subsys_device) {
210
			rdev->px_quirk_flags = p->px_quirk_flags;
211
			break;
212
		}
213
		++p;
214
	}
215
 
216
	if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
217
		rdev->flags &= ~RADEON_IS_PX;
218
}
219
 
2997 Serge 220
/**
3764 Serge 221
 * radeon_program_register_sequence - program an array of registers.
222
 *
223
 * @rdev: radeon_device pointer
224
 * @registers: pointer to the register array
225
 * @array_size: size of the register array
226
 *
227
 * Programs an array or registers with and and or masks.
228
 * This is a helper for setting golden registers.
229
 */
230
void radeon_program_register_sequence(struct radeon_device *rdev,
231
				      const u32 *registers,
232
				      const u32 array_size)
233
{
234
	u32 tmp, reg, and_mask, or_mask;
235
	int i;
236
 
237
	if (array_size % 3)
238
		return;
239
 
240
	for (i = 0; i < array_size; i +=3) {
241
		reg = registers[i + 0];
242
		and_mask = registers[i + 1];
243
		or_mask = registers[i + 2];
244
 
245
		if (and_mask == 0xffffffff) {
246
			tmp = or_mask;
247
		} else {
248
			tmp = RREG32(reg);
249
			tmp &= ~and_mask;
250
			tmp |= or_mask;
251
		}
252
		WREG32(reg, tmp);
253
	}
254
}
255
 
5078 serge 256
void radeon_pci_config_reset(struct radeon_device *rdev)
257
{
258
	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
259
}
260
 
3764 Serge 261
/**
2997 Serge 262
 * radeon_surface_init - Clear GPU surface registers.
263
 *
264
 * @rdev: radeon_device pointer
265
 *
266
 * Clear GPU surface registers (r1xx-r5xx).
1117 serge 267
 */
1179 serge 268
void radeon_surface_init(struct radeon_device *rdev)
1117 serge 269
{
270
    /* FIXME: check this out */
271
    if (rdev->family < CHIP_R600) {
272
        int i;
273
 
1321 serge 274
		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
5078 serge 275
			if (rdev->surface_regs[i].bo)
276
				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
277
			else
1404 serge 278
           radeon_clear_surface_reg(rdev, i);
1117 serge 279
        }
1179 serge 280
		/* enable surfaces */
281
		WREG32(RADEON_SURFACE_CNTL, 0);
1117 serge 282
    }
283
}
284
 
285
/*
286
 * GPU scratch registers helpers function.
287
 */
2997 Serge 288
/**
289
 * radeon_scratch_init - Init scratch register driver information.
290
 *
291
 * @rdev: radeon_device pointer
292
 *
293
 * Init CP scratch register driver information (r1xx-r5xx)
294
 */
1179 serge 295
void radeon_scratch_init(struct radeon_device *rdev)
1117 serge 296
{
297
    int i;
298
 
299
    /* FIXME: check this out */
300
    if (rdev->family < CHIP_R300) {
301
        rdev->scratch.num_reg = 5;
302
    } else {
303
        rdev->scratch.num_reg = 7;
304
    }
1963 serge 305
	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
1117 serge 306
    for (i = 0; i < rdev->scratch.num_reg; i++) {
307
        rdev->scratch.free[i] = true;
1963 serge 308
		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1117 serge 309
    }
310
}
311
 
2997 Serge 312
/**
313
 * radeon_scratch_get - Allocate a scratch register
314
 *
315
 * @rdev: radeon_device pointer
316
 * @reg: scratch register mmio offset
317
 *
318
 * Allocate a CP scratch register for use by the driver (all asics).
319
 * Returns 0 on success or -EINVAL on failure.
320
 */
1117 serge 321
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
322
{
323
	int i;
324
 
325
	for (i = 0; i < rdev->scratch.num_reg; i++) {
326
		if (rdev->scratch.free[i]) {
327
			rdev->scratch.free[i] = false;
328
			*reg = rdev->scratch.reg[i];
329
			return 0;
330
		}
331
	}
332
	return -EINVAL;
333
}
334
 
2997 Serge 335
/**
336
 * radeon_scratch_free - Free a scratch register
337
 *
338
 * @rdev: radeon_device pointer
339
 * @reg: scratch register mmio offset
340
 *
341
 * Free a CP scratch register allocated for use by the driver (all asics)
342
 */
1117 serge 343
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
344
{
345
	int i;
346
 
347
	for (i = 0; i < rdev->scratch.num_reg; i++) {
348
		if (rdev->scratch.reg[i] == reg) {
349
			rdev->scratch.free[i] = true;
350
			return;
351
		}
352
	}
353
}
354
 
2997 Serge 355
/*
5078 serge 356
 * GPU doorbell aperture helpers function.
357
 */
358
/**
359
 * radeon_doorbell_init - Init doorbell driver information.
360
 *
361
 * @rdev: radeon_device pointer
362
 *
363
 * Init doorbell driver information (CIK)
364
 * Returns 0 on success, error on failure.
365
 */
366
static int radeon_doorbell_init(struct radeon_device *rdev)
367
{
368
	/* doorbell bar mapping */
369
	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
370
	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
371
 
372
	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
373
	if (rdev->doorbell.num_doorbells == 0)
374
		return -EINVAL;
375
 
376
	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
377
	if (rdev->doorbell.ptr == NULL) {
378
		return -ENOMEM;
379
	}
380
	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
381
	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
382
 
383
	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
384
 
385
	return 0;
386
}
387
 
388
/**
389
 * radeon_doorbell_fini - Tear down doorbell driver information.
390
 *
391
 * @rdev: radeon_device pointer
392
 *
393
 * Tear down doorbell driver information (CIK)
394
 */
395
static void radeon_doorbell_fini(struct radeon_device *rdev)
396
{
397
	iounmap(rdev->doorbell.ptr);
398
	rdev->doorbell.ptr = NULL;
399
}
400
 
401
/**
402
 * radeon_doorbell_get - Allocate a doorbell entry
403
 *
404
 * @rdev: radeon_device pointer
405
 * @doorbell: doorbell index
406
 *
407
 * Allocate a doorbell for use by the driver (all asics).
408
 * Returns 0 on success or -EINVAL on failure.
409
 */
410
int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
411
{
412
	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
413
	if (offset < rdev->doorbell.num_doorbells) {
414
		__set_bit(offset, rdev->doorbell.used);
415
		*doorbell = offset;
416
		return 0;
417
	} else {
418
		return -EINVAL;
419
	}
420
}
421
 
422
/**
423
 * radeon_doorbell_free - Free a doorbell entry
424
 *
425
 * @rdev: radeon_device pointer
426
 * @doorbell: doorbell index
427
 *
428
 * Free a doorbell allocated for use by the driver (all asics)
429
 */
430
void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
431
{
432
	if (doorbell < rdev->doorbell.num_doorbells)
433
		__clear_bit(doorbell, rdev->doorbell.used);
434
}
435
 
436
/*
2997 Serge 437
 * radeon_wb_*()
438
 * Writeback is the the method by which the the GPU updates special pages
439
 * in memory with the status of certain GPU events (fences, ring pointers,
440
 * etc.).
441
 */
442
 
443
/**
444
 * radeon_wb_disable - Disable Writeback
445
 *
446
 * @rdev: radeon_device pointer
447
 *
448
 * Disables Writeback (all asics).  Used for suspend.
449
 */
2004 serge 450
void radeon_wb_disable(struct radeon_device *rdev)
451
{
452
	rdev->wb.enabled = false;
453
}
454
 
2997 Serge 455
/**
456
 * radeon_wb_fini - Disable Writeback and free memory
457
 *
458
 * @rdev: radeon_device pointer
459
 *
460
 * Disables Writeback and frees the Writeback memory (all asics).
461
 * Used at driver shutdown.
462
 */
2004 serge 463
void radeon_wb_fini(struct radeon_device *rdev)
464
{
465
	radeon_wb_disable(rdev);
466
	if (rdev->wb.wb_obj) {
5078 serge 467
		if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
468
			radeon_bo_kunmap(rdev->wb.wb_obj);
469
			radeon_bo_unpin(rdev->wb.wb_obj);
470
			radeon_bo_unreserve(rdev->wb.wb_obj);
471
		}
2004 serge 472
		radeon_bo_unref(&rdev->wb.wb_obj);
473
		rdev->wb.wb = NULL;
474
		rdev->wb.wb_obj = NULL;
475
	}
476
}
477
 
2997 Serge 478
/**
479
 * radeon_wb_init- Init Writeback driver info and allocate memory
480
 *
481
 * @rdev: radeon_device pointer
482
 *
483
 * Disables Writeback and frees the Writeback memory (all asics).
484
 * Used at driver startup.
485
 * Returns 0 on success or an -error on failure.
486
 */
2004 serge 487
int radeon_wb_init(struct radeon_device *rdev)
488
{
489
	int r;
490
 
491
	if (rdev->wb.wb_obj == NULL) {
492
		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
5078 serge 493
				     RADEON_GEM_DOMAIN_GTT, 0, NULL,
494
				     &rdev->wb.wb_obj);
2004 serge 495
		if (r) {
496
			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
497
			return r;
498
		}
499
	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
500
	if (unlikely(r != 0)) {
501
		radeon_wb_fini(rdev);
502
		return r;
503
	}
504
	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
505
			  &rdev->wb.gpu_addr);
506
	if (r) {
507
		radeon_bo_unreserve(rdev->wb.wb_obj);
508
		dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
509
		radeon_wb_fini(rdev);
510
		return r;
511
	}
512
	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
513
	radeon_bo_unreserve(rdev->wb.wb_obj);
514
	if (r) {
515
		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
516
		radeon_wb_fini(rdev);
517
		return r;
518
	}
3764 Serge 519
	}
2004 serge 520
 
521
	/* clear wb memory */
522
	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
523
	/* disable event_write fences */
524
	rdev->wb.use_event = false;
525
	/* disabled via module param */
2997 Serge 526
	if (radeon_no_wb == 1) {
2004 serge 527
		rdev->wb.enabled = false;
2997 Serge 528
	} else {
529
		if (rdev->flags & RADEON_IS_AGP) {
2004 serge 530
		/* often unreliable on AGP */
2997 Serge 531
			rdev->wb.enabled = false;
532
		} else if (rdev->family < CHIP_R300) {
533
			/* often unreliable on pre-r300 */
534
			rdev->wb.enabled = false;
535
		} else {
2004 serge 536
			rdev->wb.enabled = true;
537
			/* event_write fences are only available on r600+ */
2997 Serge 538
			if (rdev->family >= CHIP_R600) {
2004 serge 539
				rdev->wb.use_event = true;
540
	}
2997 Serge 541
		}
542
	}
543
	/* always use writeback/events on NI, APUs */
544
	if (rdev->family >= CHIP_PALM) {
2004 serge 545
		rdev->wb.enabled = true;
546
		rdev->wb.use_event = true;
547
	}
548
 
549
	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
550
 
551
	return 0;
552
}
553
 
1430 serge 554
/**
555
 * radeon_vram_location - try to find VRAM location
556
 * @rdev: radeon device structure holding all necessary informations
557
 * @mc: memory controller structure holding memory informations
558
 * @base: base address at which to put VRAM
559
 *
560
 * Function will place try to place VRAM at base address provided
561
 * as parameter (which is so far either PCI aperture address or
562
 * for IGP TOM base address).
563
 *
564
 * If there is not enough space to fit the unvisible VRAM in the 32bits
565
 * address space then we limit the VRAM size to the aperture.
566
 *
567
 * If we are using AGP and if the AGP aperture doesn't allow us to have
568
 * room for all the VRAM than we restrict the VRAM to the PCI aperture
569
 * size and print a warning.
570
 *
571
 * This function will never fails, worst case are limiting VRAM.
572
 *
573
 * Note: GTT start, end, size should be initialized before calling this
574
 * function on AGP platform.
575
 *
1963 serge 576
 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
1430 serge 577
 * this shouldn't be a problem as we are using the PCI aperture as a reference.
578
 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
579
 * not IGP.
580
 *
581
 * Note: we use mc_vram_size as on some board we need to program the mc to
582
 * cover the whole aperture even if VRAM size is inferior to aperture size
583
 * Novell bug 204882 + along with lots of ubuntu ones
584
 *
585
 * Note: when limiting vram it's safe to overwritte real_vram_size because
586
 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
587
 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
588
 * ones)
589
 *
590
 * Note: IGP TOM addr should be the same as the aperture addr, we don't
591
 * explicitly check for that thought.
592
 *
593
 * FIXME: when reducing VRAM size align new size on power of 2.
1117 serge 594
 */
1430 serge 595
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
1117 serge 596
{
2997 Serge 597
	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
598
 
1430 serge 599
	mc->vram_start = base;
3764 Serge 600
	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
1430 serge 601
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
602
		mc->real_vram_size = mc->aper_size;
603
		mc->mc_vram_size = mc->aper_size;
604
	}
605
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1963 serge 606
	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
1430 serge 607
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
608
		mc->real_vram_size = mc->aper_size;
609
		mc->mc_vram_size = mc->aper_size;
610
		}
611
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2997 Serge 612
	if (limit && limit < mc->real_vram_size)
613
		mc->real_vram_size = limit;
1963 serge 614
	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
1430 serge 615
			mc->mc_vram_size >> 20, mc->vram_start,
616
			mc->vram_end, mc->real_vram_size >> 20);
617
}
1117 serge 618
 
1430 serge 619
/**
620
 * radeon_gtt_location - try to find GTT location
621
 * @rdev: radeon device structure holding all necessary informations
622
 * @mc: memory controller structure holding memory informations
623
 *
624
 * Function will place try to place GTT before or after VRAM.
625
 *
626
 * If GTT size is bigger than space left then we ajust GTT size.
627
 * Thus function will never fails.
628
 *
629
 * FIXME: when reducing GTT size align new size on power of 2.
630
 */
631
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
632
{
633
	u64 size_af, size_bf;
634
 
3764 Serge 635
	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
1963 serge 636
	size_bf = mc->vram_start & ~mc->gtt_base_align;
1430 serge 637
	if (size_bf > size_af) {
638
		if (mc->gtt_size > size_bf) {
639
			dev_warn(rdev->dev, "limiting GTT\n");
640
			mc->gtt_size = size_bf;
1117 serge 641
		}
1963 serge 642
		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
1430 serge 643
	} else {
644
		if (mc->gtt_size > size_af) {
645
			dev_warn(rdev->dev, "limiting GTT\n");
646
			mc->gtt_size = size_af;
1117 serge 647
		}
1963 serge 648
		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
1117 serge 649
	}
1430 serge 650
	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
1963 serge 651
	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
1430 serge 652
			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
1117 serge 653
}
654
 
655
/*
656
 * GPU helpers function.
657
 */
2997 Serge 658
/**
659
 * radeon_card_posted - check if the hw has already been initialized
660
 *
661
 * @rdev: radeon_device pointer
662
 *
663
 * Check if the asic has been initialized (all asics).
664
 * Used at driver startup.
665
 * Returns true if initialized or false if not.
666
 */
1179 serge 667
bool radeon_card_posted(struct radeon_device *rdev)
1117 serge 668
{
669
	uint32_t reg;
670
 
3764 Serge 671
	if (ASIC_IS_NODCE(rdev))
672
		goto check_memsize;
673
 
1117 serge 674
	/* first check CRTCs */
3764 Serge 675
	if (ASIC_IS_DCE4(rdev)) {
1430 serge 676
		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
1963 serge 677
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
3764 Serge 678
			if (rdev->num_crtc >= 4) {
679
				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
680
					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
681
			}
682
			if (rdev->num_crtc >= 6) {
683
				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
1430 serge 684
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
3764 Serge 685
			}
1430 serge 686
		if (reg & EVERGREEN_CRTC_MASTER_EN)
687
			return true;
688
	} else if (ASIC_IS_AVIVO(rdev)) {
1117 serge 689
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
690
		      RREG32(AVIVO_D2CRTC_CONTROL);
691
		if (reg & AVIVO_CRTC_EN) {
692
			return true;
693
		}
694
	} else {
695
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
696
		      RREG32(RADEON_CRTC2_GEN_CNTL);
697
		if (reg & RADEON_CRTC_EN) {
698
			return true;
699
		}
700
	}
701
 
3764 Serge 702
check_memsize:
1117 serge 703
	/* then check MEM_SIZE, in case the crtcs are off */
704
	if (rdev->family >= CHIP_R600)
705
		reg = RREG32(R600_CONFIG_MEMSIZE);
706
	else
707
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
708
 
709
	if (reg)
710
		return true;
711
 
712
	return false;
713
 
714
}
715
 
2997 Serge 716
/**
717
 * radeon_update_bandwidth_info - update display bandwidth params
718
 *
719
 * @rdev: radeon_device pointer
720
 *
721
 * Used when sclk/mclk are switched or display modes are set.
722
 * params are used to calculate display watermarks (all asics)
723
 */
1963 serge 724
void radeon_update_bandwidth_info(struct radeon_device *rdev)
725
{
726
	fixed20_12 a;
727
	u32 sclk = rdev->pm.current_sclk;
728
	u32 mclk = rdev->pm.current_mclk;
729
 
730
	/* sclk/mclk in Mhz */
731
		a.full = dfixed_const(100);
732
		rdev->pm.sclk.full = dfixed_const(sclk);
733
		rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
734
		rdev->pm.mclk.full = dfixed_const(mclk);
735
		rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
736
 
737
	if (rdev->flags & RADEON_IS_IGP) {
738
		a.full = dfixed_const(16);
739
		/* core_bandwidth = sclk(Mhz) * 16 */
740
		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
741
	}
742
}
743
 
2997 Serge 744
/**
745
 * radeon_boot_test_post_card - check and possibly initialize the hw
746
 *
747
 * @rdev: radeon_device pointer
748
 *
749
 * Check if the asic is initialized and if not, attempt to initialize
750
 * it (all asics).
751
 * Returns true if initialized or false if not.
752
 */
1321 serge 753
bool radeon_boot_test_post_card(struct radeon_device *rdev)
754
{
755
	if (radeon_card_posted(rdev))
756
		return true;
757
 
758
	if (rdev->bios) {
759
		DRM_INFO("GPU not posted. posting now...\n");
760
		if (rdev->is_atom_bios)
761
			atom_asic_init(rdev->mode_info.atom_context);
762
		else
763
			radeon_combios_asic_init(rdev->ddev);
764
		return true;
765
	} else {
766
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
767
		return false;
768
	}
769
}
770
 
2997 Serge 771
/**
772
 * radeon_dummy_page_init - init dummy page used by the driver
773
 *
774
 * @rdev: radeon_device pointer
775
 *
776
 * Allocate the dummy page used by the driver (all asics).
777
 * This dummy page is used by the driver as a filler for gart entries
778
 * when pages are taken out of the GART
779
 * Returns 0 on sucess, -ENOMEM on failure.
780
 */
1233 serge 781
int radeon_dummy_page_init(struct radeon_device *rdev)
782
{
1430 serge 783
	if (rdev->dummy_page.page)
784
		return 0;
5078 serge 785
	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
1233 serge 786
	if (rdev->dummy_page.page == NULL)
787
		return -ENOMEM;
5078 serge 788
	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
789
					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1233 serge 790
	return 0;
791
}
1117 serge 792
 
2997 Serge 793
/**
794
 * radeon_dummy_page_fini - free dummy page used by the driver
795
 *
796
 * @rdev: radeon_device pointer
797
 *
798
 * Frees the dummy page used by the driver (all asics).
799
 */
1233 serge 800
void radeon_dummy_page_fini(struct radeon_device *rdev)
801
{
802
	if (rdev->dummy_page.page == NULL)
803
		return;
5078 serge 804
 
1233 serge 805
	rdev->dummy_page.page = NULL;
806
}
807
 
808
 
1117 serge 809
/* ATOM accessor methods */
2997 Serge 810
/*
811
 * ATOM is an interpreted byte code stored in tables in the vbios.  The
812
 * driver registers callbacks to access registers and the interpreter
813
 * in the driver parses the tables and executes then to program specific
814
 * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
815
 * atombios.h, and atom.c
816
 */
817
 
818
/**
819
 * cail_pll_read - read PLL register
820
 *
821
 * @info: atom card_info pointer
822
 * @reg: PLL register offset
823
 *
824
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
825
 * Returns the value of the PLL register.
826
 */
1117 serge 827
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
828
{
829
    struct radeon_device *rdev = info->dev->dev_private;
830
    uint32_t r;
831
 
832
    r = rdev->pll_rreg(rdev, reg);
833
    return r;
834
}
835
 
2997 Serge 836
/**
837
 * cail_pll_write - write PLL register
838
 *
839
 * @info: atom card_info pointer
840
 * @reg: PLL register offset
841
 * @val: value to write to the pll register
842
 *
843
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
844
 */
1117 serge 845
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
846
{
847
    struct radeon_device *rdev = info->dev->dev_private;
848
 
849
    rdev->pll_wreg(rdev, reg, val);
850
}
851
 
2997 Serge 852
/**
853
 * cail_mc_read - read MC (Memory Controller) register
854
 *
855
 * @info: atom card_info pointer
856
 * @reg: MC register offset
857
 *
858
 * Provides an MC register accessor for the atom interpreter (r4xx+).
859
 * Returns the value of the MC register.
860
 */
1117 serge 861
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
862
{
863
    struct radeon_device *rdev = info->dev->dev_private;
864
    uint32_t r;
865
 
866
    r = rdev->mc_rreg(rdev, reg);
867
    return r;
868
}
869
 
2997 Serge 870
/**
871
 * cail_mc_write - write MC (Memory Controller) register
872
 *
873
 * @info: atom card_info pointer
874
 * @reg: MC register offset
875
 * @val: value to write to the pll register
876
 *
877
 * Provides a MC register accessor for the atom interpreter (r4xx+).
878
 */
1117 serge 879
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
880
{
881
    struct radeon_device *rdev = info->dev->dev_private;
882
 
883
    rdev->mc_wreg(rdev, reg, val);
884
}
885
 
2997 Serge 886
/**
887
 * cail_reg_write - write MMIO register
888
 *
889
 * @info: atom card_info pointer
890
 * @reg: MMIO register offset
891
 * @val: value to write to the pll register
892
 *
893
 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
894
 */
1117 serge 895
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
896
{
897
    struct radeon_device *rdev = info->dev->dev_private;
898
 
899
    WREG32(reg*4, val);
900
}
901
 
2997 Serge 902
/**
903
 * cail_reg_read - read MMIO register
904
 *
905
 * @info: atom card_info pointer
906
 * @reg: MMIO register offset
907
 *
908
 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
909
 * Returns the value of the MMIO register.
910
 */
1117 serge 911
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
912
{
913
    struct radeon_device *rdev = info->dev->dev_private;
914
    uint32_t r;
915
 
916
    r = RREG32(reg*4);
917
    return r;
918
}
919
 
2997 Serge 920
/**
921
 * cail_ioreg_write - write IO register
922
 *
923
 * @info: atom card_info pointer
924
 * @reg: IO register offset
925
 * @val: value to write to the pll register
926
 *
927
 * Provides a IO register accessor for the atom interpreter (r4xx+).
928
 */
1963 serge 929
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
930
{
931
	struct radeon_device *rdev = info->dev->dev_private;
932
 
933
	WREG32_IO(reg*4, val);
934
}
935
 
2997 Serge 936
/**
937
 * cail_ioreg_read - read IO register
938
 *
939
 * @info: atom card_info pointer
940
 * @reg: IO register offset
941
 *
942
 * Provides an IO register accessor for the atom interpreter (r4xx+).
943
 * Returns the value of the IO register.
944
 */
1963 serge 945
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
946
{
947
	struct radeon_device *rdev = info->dev->dev_private;
948
	uint32_t r;
949
 
950
	r = RREG32_IO(reg*4);
951
	return r;
952
}
953
 
2997 Serge 954
/**
955
 * radeon_atombios_init - init the driver info and callbacks for atombios
956
 *
957
 * @rdev: radeon_device pointer
958
 *
959
 * Initializes the driver info and register access callbacks for the
960
 * ATOM interpreter (r4xx+).
961
 * Returns 0 on sucess, -ENOMEM on failure.
962
 * Called at driver startup.
963
 */
1117 serge 964
int radeon_atombios_init(struct radeon_device *rdev)
965
{
1268 serge 966
	struct card_info *atom_card_info =
967
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
1117 serge 968
 
1268 serge 969
	if (!atom_card_info)
970
		return -ENOMEM;
971
 
972
	rdev->mode_info.atom_card_info = atom_card_info;
973
	atom_card_info->dev = rdev->ddev;
974
	atom_card_info->reg_read = cail_reg_read;
975
	atom_card_info->reg_write = cail_reg_write;
1963 serge 976
	/* needed for iio ops */
977
	if (rdev->rio_mem) {
978
		atom_card_info->ioreg_read = cail_ioreg_read;
979
		atom_card_info->ioreg_write = cail_ioreg_write;
980
	} else {
981
		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
982
		atom_card_info->ioreg_read = cail_reg_read;
983
		atom_card_info->ioreg_write = cail_reg_write;
984
	}
1268 serge 985
	atom_card_info->mc_read = cail_mc_read;
986
	atom_card_info->mc_write = cail_mc_write;
987
	atom_card_info->pll_read = cail_pll_read;
988
	atom_card_info->pll_write = cail_pll_write;
989
 
990
	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
3764 Serge 991
	if (!rdev->mode_info.atom_context) {
992
		radeon_atombios_fini(rdev);
993
		return -ENOMEM;
994
	}
995
 
1630 serge 996
	mutex_init(&rdev->mode_info.atom_context->mutex);
1117 serge 997
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1321 serge 998
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1117 serge 999
    return 0;
1000
}
1001
 
2997 Serge 1002
/**
1003
 * radeon_atombios_fini - free the driver info and callbacks for atombios
1004
 *
1005
 * @rdev: radeon_device pointer
1006
 *
1007
 * Frees the driver info and register access callbacks for the ATOM
1008
 * interpreter (r4xx+).
1009
 * Called at driver shutdown.
1010
 */
1117 serge 1011
void radeon_atombios_fini(struct radeon_device *rdev)
1012
{
1321 serge 1013
	if (rdev->mode_info.atom_context) {
1014
		kfree(rdev->mode_info.atom_context->scratch);
3764 Serge 1015
	}
1119 serge 1016
	kfree(rdev->mode_info.atom_context);
3764 Serge 1017
	rdev->mode_info.atom_context = NULL;
1268 serge 1018
	kfree(rdev->mode_info.atom_card_info);
3764 Serge 1019
	rdev->mode_info.atom_card_info = NULL;
1117 serge 1020
}
1021
 
2997 Serge 1022
/* COMBIOS */
1023
/*
1024
 * COMBIOS is the bios format prior to ATOM. It provides
1025
 * command tables similar to ATOM, but doesn't have a unified
1026
 * parser.  See radeon_combios.c
1027
 */
1028
 
1029
/**
1030
 * radeon_combios_init - init the driver info for combios
1031
 *
1032
 * @rdev: radeon_device pointer
1033
 *
1034
 * Initializes the driver info for combios (r1xx-r3xx).
1035
 * Returns 0 on sucess.
1036
 * Called at driver startup.
1037
 */
1117 serge 1038
int radeon_combios_init(struct radeon_device *rdev)
1039
{
1128 serge 1040
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117 serge 1041
	return 0;
1042
}
1043
 
2997 Serge 1044
/**
1045
 * radeon_combios_fini - free the driver info for combios
1046
 *
1047
 * @rdev: radeon_device pointer
1048
 *
1049
 * Frees the driver info for combios (r1xx-r3xx).
1050
 * Called at driver shutdown.
1051
 */
1117 serge 1052
void radeon_combios_fini(struct radeon_device *rdev)
1053
{
1054
}
1055
 
2997 Serge 1056
/* if we get transitioned to only one device, take VGA back */
1057
/**
1058
 * radeon_vga_set_decode - enable/disable vga decode
1059
 *
1060
 * @cookie: radeon_device pointer
1061
 * @state: enable/disable vga decode
1062
 *
1063
 * Enable/disable vga decode (all asics).
1064
 * Returns VGA resource flags.
1065
 */
1233 serge 1066
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1067
{
1068
	struct radeon_device *rdev = cookie;
1069
	radeon_vga_set_state(rdev, state);
1070
	if (state)
1071
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1072
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1073
	else
1074
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1075
}
1117 serge 1076
 
2997 Serge 1077
/**
1078
 * radeon_check_pot_argument - check that argument is a power of two
1079
 *
1080
 * @arg: value to check
1081
 *
1082
 * Validates that a certain argument is a power of two (all asics).
1083
 * Returns true if argument is valid.
1084
 */
1085
static bool radeon_check_pot_argument(int arg)
1404 serge 1086
{
2997 Serge 1087
	return (arg & (arg - 1)) == 0;
1088
}
1089
 
1090
/**
1091
 * radeon_check_arguments - validate module params
1092
 *
1093
 * @rdev: radeon_device pointer
1094
 *
1095
 * Validates certain module parameters and updates
1096
 * the associated values used by the driver (all asics).
1097
 */
1098
static void radeon_check_arguments(struct radeon_device *rdev)
1099
{
1404 serge 1100
	/* vramlimit must be a power of two */
2997 Serge 1101
	if (!radeon_check_pot_argument(radeon_vram_limit)) {
1404 serge 1102
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1103
				radeon_vram_limit);
1104
		radeon_vram_limit = 0;
1105
	}
2997 Serge 1106
 
5078 serge 1107
	if (radeon_gart_size == -1) {
1108
		/* default to a larger gart size on newer asics */
1109
		if (rdev->family >= CHIP_RV770)
1110
			radeon_gart_size = 1024;
1111
		else
1112
			radeon_gart_size = 512;
1113
	}
1404 serge 1114
	/* gtt size must be power of two and greater or equal to 32M */
2997 Serge 1115
	if (radeon_gart_size < 32) {
5078 serge 1116
		dev_warn(rdev->dev, "gart size (%d) too small\n",
1404 serge 1117
				radeon_gart_size);
5078 serge 1118
		if (rdev->family >= CHIP_RV770)
1119
			radeon_gart_size = 1024;
1120
		else
1404 serge 1121
		radeon_gart_size = 512;
2997 Serge 1122
	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
1404 serge 1123
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1124
				radeon_gart_size);
5078 serge 1125
		if (rdev->family >= CHIP_RV770)
1126
			radeon_gart_size = 1024;
1127
		else
1404 serge 1128
		radeon_gart_size = 512;
1129
	}
2997 Serge 1130
	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1131
 
1404 serge 1132
	/* AGP mode can only be -1, 1, 2, 4, 8 */
1133
	switch (radeon_agpmode) {
1134
	case -1:
1135
	case 0:
1136
	case 1:
1137
	case 2:
1138
	case 4:
1139
	case 8:
1140
		break;
1141
	default:
1142
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1143
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1144
		radeon_agpmode = 0;
1145
		break;
1146
	}
5078 serge 1147
 
1148
	if (!radeon_check_pot_argument(radeon_vm_size)) {
1149
		dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1150
			 radeon_vm_size);
1151
		radeon_vm_size = 4;
1152
	}
1153
 
1154
	if (radeon_vm_size < 1) {
1155
		dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
1156
			 radeon_vm_size);
1157
		radeon_vm_size = 4;
1158
	}
1159
 
1160
       /*
1161
        * Max GPUVM size for Cayman, SI and CI are 40 bits.
1162
        */
1163
	if (radeon_vm_size > 1024) {
1164
		dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1165
			 radeon_vm_size);
1166
		radeon_vm_size = 4;
1167
	}
1168
 
1169
	/* defines number of bits in page table versus page directory,
1170
	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1171
	 * page table and the remaining bits are in the page directory */
1172
	if (radeon_vm_block_size == -1) {
1173
 
1174
		/* Total bits covered by PD + PTs */
1175
		unsigned bits = ilog2(radeon_vm_size) + 17;
1176
 
1177
		/* Make sure the PD is 4K in size up to 8GB address space.
1178
		   Above that split equal between PD and PTs */
1179
		if (radeon_vm_size <= 8)
1180
			radeon_vm_block_size = bits - 9;
1181
		else
1182
			radeon_vm_block_size = (bits + 3) / 2;
1183
 
1184
	} else if (radeon_vm_block_size < 9) {
1185
		dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1186
			 radeon_vm_block_size);
1187
		radeon_vm_block_size = 9;
1188
	}
1189
 
1190
	if (radeon_vm_block_size > 24 ||
1191
	    (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1192
		dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1193
			 radeon_vm_block_size);
1194
		radeon_vm_block_size = 9;
1195
	}
1404 serge 1196
}
1197
 
5078 serge 1198
/**
1199
 * radeon_device_init - initialize the driver
1200
 *
1201
 * @rdev: radeon_device pointer
1202
 * @pdev: drm dev pointer
1203
 * @pdev: pci dev pointer
1204
 * @flags: driver flags
1205
 *
1206
 * Initializes the driver info and hw (all asics).
1207
 * Returns 0 for success or an error on failure.
1208
 * Called at driver startup.
1209
 */
1117 serge 1210
int radeon_device_init(struct radeon_device *rdev,
1211
               struct drm_device *ddev,
1212
               struct pci_dev *pdev,
1213
               uint32_t flags)
1214
{
1963 serge 1215
	int r, i;
1179 serge 1216
	int dma_bits;
5078 serge 1217
	bool runtime = false;
1117 serge 1218
 
1219
    rdev->shutdown = false;
5078 serge 1220
	rdev->dev = &pdev->dev;
1117 serge 1221
    rdev->ddev = ddev;
1222
    rdev->pdev = pdev;
1223
    rdev->flags = flags;
1224
    rdev->family = flags & RADEON_FAMILY_MASK;
1225
    rdev->is_atom_bios = false;
1226
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
5078 serge 1227
	rdev->mc.gtt_size = 512 * 1024 * 1024;
1221 serge 1228
	rdev->accel_working = false;
2997 Serge 1229
	/* set up ring ids */
1230
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
1231
		rdev->ring[i].idx = i;
1232
	}
1963 serge 1233
 
2997 Serge 1234
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1235
		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1236
		pdev->subsystem_vendor, pdev->subsystem_device);
1963 serge 1237
 
1117 serge 1238
    /* mutex initialization are all done here so we
1239
     * can recall function without having locking issues */
2997 Serge 1240
	mutex_init(&rdev->ring_lock);
1630 serge 1241
	mutex_init(&rdev->dc_hw_i2c_mutex);
2997 Serge 1242
	atomic_set(&rdev->ih.lock, 0);
1630 serge 1243
	mutex_init(&rdev->gem.mutex);
1244
	mutex_init(&rdev->pm.mutex);
2997 Serge 1245
	mutex_init(&rdev->gpu_clock_mutex);
5078 serge 1246
	mutex_init(&rdev->srbm_mutex);
3764 Serge 1247
//   init_rwsem(&rdev->pm.mclk_lock);
1248
//   init_rwsem(&rdev->exclusive_lock);
2997 Serge 1249
	init_waitqueue_head(&rdev->irq.vblank_queue);
1250
	r = radeon_gem_init(rdev);
1251
	if (r)
1252
		return r;
5078 serge 1253
 
1254
	radeon_check_arguments(rdev);
2997 Serge 1255
	/* Adjust VM size here.
5078 serge 1256
	 * Max GPUVM size for cayman+ is 40 bits.
2997 Serge 1257
	 */
5078 serge 1258
	rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1117 serge 1259
 
1179 serge 1260
	/* Set asic functions */
1261
	r = radeon_asic_init(rdev);
1404 serge 1262
	if (r)
1179 serge 1263
		return r;
1264
 
1963 serge 1265
	/* all of the newer IGP chips have an internal gart
1266
	 * However some rs4xx report as AGP, so remove that here.
1267
	 */
1268
	if ((rdev->family >= CHIP_RS400) &&
1269
	    (rdev->flags & RADEON_IS_IGP)) {
1270
		rdev->flags &= ~RADEON_IS_AGP;
1271
	}
1272
 
1321 serge 1273
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1221 serge 1274
		radeon_agp_disable(rdev);
1117 serge 1275
    }
1276
 
3764 Serge 1277
	/* Set the internal MC address mask
1278
	 * This is the max address of the GPU's
1279
	 * internal address space.
1280
	 */
1281
	if (rdev->family >= CHIP_CAYMAN)
1282
		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1283
	else if (rdev->family >= CHIP_CEDAR)
1284
		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1285
	else
1286
		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1287
 
1179 serge 1288
	/* set DMA mask + need_dma32 flags.
1289
	 * PCIE - can handle 40-bits.
2997 Serge 1290
	 * IGP - can handle 40-bits
1179 serge 1291
	 * AGP - generally dma32 is safest
2997 Serge 1292
	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1179 serge 1293
	 */
1294
	rdev->need_dma32 = false;
1295
	if (rdev->flags & RADEON_IS_AGP)
1296
		rdev->need_dma32 = true;
2997 Serge 1297
	if ((rdev->flags & RADEON_IS_PCI) &&
1298
	    (rdev->family <= CHIP_RS740))
1179 serge 1299
		rdev->need_dma32 = true;
1117 serge 1300
 
1179 serge 1301
	dma_bits = rdev->need_dma32 ? 32 : 40;
1302
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117 serge 1303
    if (r) {
1986 serge 1304
		rdev->need_dma32 = true;
2997 Serge 1305
		dma_bits = 32;
1119 serge 1306
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1307
    }
1117 serge 1308
 
1309
    /* Registers mapping */
1310
    /* TODO: block userspace mapping of io register */
3192 Serge 1311
	spin_lock_init(&rdev->mmio_idx_lock);
5078 serge 1312
	spin_lock_init(&rdev->smc_idx_lock);
1313
	spin_lock_init(&rdev->pll_idx_lock);
1314
	spin_lock_init(&rdev->mc_idx_lock);
1315
	spin_lock_init(&rdev->pcie_idx_lock);
1316
	spin_lock_init(&rdev->pciep_idx_lock);
1317
	spin_lock_init(&rdev->pif_idx_lock);
1318
	spin_lock_init(&rdev->cg_idx_lock);
1319
	spin_lock_init(&rdev->uvd_idx_lock);
1320
	spin_lock_init(&rdev->rcu_idx_lock);
1321
	spin_lock_init(&rdev->didt_idx_lock);
1322
	spin_lock_init(&rdev->end_idx_lock);
1323
	if (rdev->family >= CHIP_BONAIRE) {
1324
		rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1325
		rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1326
	} else {
1117 serge 1327
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1328
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
5078 serge 1329
	}
2997 Serge 1330
	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1117 serge 1331
    if (rdev->rmmio == NULL) {
1332
        return -ENOMEM;
1333
    }
1334
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1335
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1336
 
5078 serge 1337
	/* doorbell bar mapping */
1338
	if (rdev->family >= CHIP_BONAIRE)
1339
		radeon_doorbell_init(rdev);
1340
 
2997 Serge 1341
	/* io port mapping */
1342
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1343
		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1344
			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1345
			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1346
			break;
1347
		}
1348
	}
1349
	if (rdev->rio_mem == NULL)
1350
		DRM_ERROR("Unable to find PCI I/O BAR\n");
1351
 
5078 serge 1352
	if (rdev->flags & RADEON_IS_PX)
1353
		radeon_device_handle_px_quirks(rdev);
1354
	if (rdev->flags & RADEON_IS_PX)
1355
		runtime = true;
2997 Serge 1356
 
1179 serge 1357
	r = radeon_init(rdev);
1221 serge 1358
	if (r)
1963 serge 1359
        return r;
1117 serge 1360
 
5078 serge 1361
	r = radeon_ib_ring_tests(rdev);
1362
	if (r)
1363
		DRM_ERROR("ib ring test failed (%d).\n", r);
3192 Serge 1364
 
5078 serge 1365
 
1221 serge 1366
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1367
		/* Acceleration not working on AGP card try again
1368
		 * with fallback to PCI or PCIE GART
1369
		 */
1963 serge 1370
		radeon_asic_reset(rdev);
1221 serge 1371
		radeon_fini(rdev);
1372
		radeon_agp_disable(rdev);
1373
		r = radeon_init(rdev);
1374
		if (r)
1179 serge 1375
		return r;
1126 serge 1376
	}
5078 serge 1377
 
1378
	if ((radeon_testing & 1)) {
1379
		if (rdev->accel_working)
1380
			radeon_test_moves(rdev);
1381
		else
1382
			DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1383
	}
1384
	if ((radeon_testing & 2)) {
1385
		if (rdev->accel_working)
1386
			radeon_test_syncing(rdev);
1387
		else
1388
			DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1389
	}
2005 serge 1390
   if (radeon_benchmarking) {
5078 serge 1391
		if (rdev->accel_working)
2997 Serge 1392
		radeon_benchmark(rdev, radeon_benchmarking);
5078 serge 1393
		else
1394
			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
2005 serge 1395
    }
1179 serge 1396
	return 0;
1117 serge 1397
}
1398
 
2997 Serge 1399
/**
1400
 * radeon_gpu_reset - reset the asic
1401
 *
1402
 * @rdev: radeon device pointer
1403
 *
1404
 * Attempt the reset the GPU if it has hung (all asics).
1405
 * Returns 0 for success or an error on failure.
1406
 */
1407
int radeon_gpu_reset(struct radeon_device *rdev)
1408
{
1409
    unsigned ring_sizes[RADEON_NUM_RINGS];
1410
    uint32_t *ring_data[RADEON_NUM_RINGS];
1179 serge 1411
 
2997 Serge 1412
    bool saved = false;
1413
 
1414
    int i, r;
1415
    int resched;
1416
 
1417
//    down_write(&rdev->exclusive_lock);
5078 serge 1418
	rdev->needs_reset = false;
1419
 
2997 Serge 1420
    radeon_save_bios_scratch_regs(rdev);
1421
    /* block TTM */
1422
//    resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1423
    radeon_suspend(rdev);
1424
 
1425
    for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1426
        ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1427
                           &ring_data[i]);
1428
        if (ring_sizes[i]) {
1429
            saved = true;
1430
            dev_info(rdev->dev, "Saved %d dwords of commands "
1431
                 "on ring %d.\n", ring_sizes[i], i);
1432
        }
1433
    }
1434
 
1435
retry:
1436
    r = radeon_asic_reset(rdev);
1437
    if (!r) {
1438
        dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1439
        radeon_resume(rdev);
1440
    }
1441
 
1442
    radeon_restore_bios_scratch_regs(rdev);
1443
 
1444
    if (!r) {
1445
        for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1446
            radeon_ring_restore(rdev, &rdev->ring[i],
1447
                        ring_sizes[i], ring_data[i]);
1448
            ring_sizes[i] = 0;
1449
            ring_data[i] = NULL;
1450
        }
1451
 
3192 Serge 1452
//        r = radeon_ib_ring_tests(rdev);
1453
//        if (r) {
1454
//            dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1455
//            if (saved) {
1456
//                saved = false;
1457
//                radeon_suspend(rdev);
1458
//                goto retry;
1459
//            }
1460
//        }
2997 Serge 1461
    } else {
1462
        for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1463
            kfree(ring_data[i]);
1464
        }
1465
    }
1466
 
1467
//    ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1468
    if (r) {
1469
        /* bad news, how to tell it to userspace ? */
1470
        dev_info(rdev->dev, "GPU reset failed\n");
1471
    }
1472
 
1473
//    up_write(&rdev->exclusive_lock);
1474
    return r;
1475
}
1476
 
1477
 
1117 serge 1478
/*
1479
 * Driver load/unload
1480
 */
1481
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
1482
{
1483
    struct radeon_device *rdev;
1484
    int r;
1485
 
1486
 
1120 serge 1487
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117 serge 1488
    if (rdev == NULL) {
1489
        return -ENOMEM;
1490
    };
1491
 
1492
    dev->dev_private = (void *)rdev;
1493
 
1494
    /* update BUS flag */
5097 serge 1495
    if (drm_pci_device_is_agp(dev)) {
1117 serge 1496
        flags |= RADEON_IS_AGP;
1239 serge 1497
    } else if (drm_device_is_pcie(dev)) {
1498
        flags |= RADEON_IS_PCIE;
1499
    } else {
1500
        flags |= RADEON_IS_PCI;
1501
    }
1117 serge 1502
 
1182 serge 1503
    /* radeon_device_init should report only fatal error
1504
     * like memory allocation failure or iomapping failure,
1505
     * or memory manager initialization failure, it must
1506
     * properly initialize the GPU MC controller and permit
1507
     * VRAM allocation
1508
     */
1117 serge 1509
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
1510
    if (r) {
1182 serge 1511
        DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117 serge 1512
        return r;
1513
    }
1182 serge 1514
    /* Again modeset_init should fail only on fatal error
1515
     * otherwise it should provide enough functionalities
1516
     * for shadowfb to run
1517
     */
5078 serge 1518
    main_device = dev;
1519
 
1246 serge 1520
    if( radeon_modeset )
1521
    {
1268 serge 1522
        r = radeon_modeset_init(rdev);
1523
        if (r) {
1524
            return r;
1525
        }
5078 serge 1526
        init_display_kms(dev, &usermode);
1527
    }
1986 serge 1528
    else
5078 serge 1529
        init_display(rdev, &usermode);
1126 serge 1530
 
1117 serge 1531
    return 0;
5078 serge 1532
}
1117 serge 1533
 
1534
 
1221 serge 1535
 
1117 serge 1536
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
1537
{
1538
    return pci_resource_start(dev->pdev, resource);
1539
}
1540
 
1541
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
1542
{
1543
    return pci_resource_len(dev->pdev, resource);
1544
}
1545
 
1123 serge 1546
 
1547
uint32_t __div64_32(uint64_t *n, uint32_t base)
1548
{
1549
        uint64_t rem = *n;
1550
        uint64_t b = base;
1551
        uint64_t res, d = 1;
1552
        uint32_t high = rem >> 32;
1553
 
1554
        /* Reduce the thing a bit first */
1555
        res = 0;
1556
        if (high >= base) {
1557
                high /= base;
1558
                res = (uint64_t) high << 32;
1559
                rem -= (uint64_t) (high*base) << 32;
1560
        }
1561
 
1562
        while ((int64_t)b > 0 && b < rem) {
1563
                b = b+b;
1564
                d = d+d;
1565
        }
1566
 
1567
        do {
1568
                if (rem >= b) {
1569
                        rem -= b;
1570
                        res += d;
1571
                }
1572
                b >>= 1;
1573
                d >>= 1;
1574
        } while (d);
1575
 
1576
        *n = res;
1577
        return rem;
1578
}
1579
 
1239 serge 1580
static struct pci_device_id pciidlist[] = {
1581
    radeon_PCI_IDS
1582
};
1583
 
5078 serge 1584
void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
1585
int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
1586
void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
1587
irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
1239 serge 1588
 
1589
 
5078 serge 1590
static struct drm_driver kms_driver = {
1591
    .driver_features =
1592
        DRIVER_USE_AGP |
1593
        DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
1594
        DRIVER_PRIME | DRIVER_RENDER,
1595
    .load = radeon_driver_load_kms,
1596
//    .open = radeon_driver_open_kms,
1597
//    .preclose = radeon_driver_preclose_kms,
1598
//    .postclose = radeon_driver_postclose_kms,
1599
//    .lastclose = radeon_driver_lastclose_kms,
1600
//    .unload = radeon_driver_unload_kms,
1601
//    .get_vblank_counter = radeon_get_vblank_counter_kms,
1602
//    .enable_vblank = radeon_enable_vblank_kms,
1603
//    .disable_vblank = radeon_disable_vblank_kms,
1604
//    .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
1605
//    .get_scanout_position = radeon_get_crtc_scanoutpos,
1606
#if defined(CONFIG_DEBUG_FS)
1607
    .debugfs_init = radeon_debugfs_init,
1608
    .debugfs_cleanup = radeon_debugfs_cleanup,
1609
#endif
1610
    .irq_preinstall = radeon_driver_irq_preinstall_kms,
1611
    .irq_postinstall = radeon_driver_irq_postinstall_kms,
1612
    .irq_uninstall = radeon_driver_irq_uninstall_kms,
1613
    .irq_handler = radeon_driver_irq_handler_kms,
1614
//    .ioctls = radeon_ioctls_kms,
1615
//    .gem_free_object = radeon_gem_object_free,
1616
//    .gem_open_object = radeon_gem_object_open,
1617
//    .gem_close_object = radeon_gem_object_close,
1618
//    .dumb_create = radeon_mode_dumb_create,
1619
//    .dumb_map_offset = radeon_mode_dumb_mmap,
1620
//    .dumb_destroy = drm_gem_dumb_destroy,
1621
//    .fops = &radeon_driver_kms_fops,
3120 serge 1622
 
5078 serge 1623
//    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1624
//    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1625
//    .gem_prime_export = drm_gem_prime_export,
1626
//    .gem_prime_import = drm_gem_prime_import,
1627
//    .gem_prime_pin = radeon_gem_prime_pin,
1628
//    .gem_prime_unpin = radeon_gem_prime_unpin,
1629
//    .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
1630
//    .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
1631
//    .gem_prime_vmap = radeon_gem_prime_vmap,
1632
//    .gem_prime_vunmap = radeon_gem_prime_vunmap,
1239 serge 1633
 
5078 serge 1634
};
2007 serge 1635
 
5078 serge 1636
int ati_init(void)
1239 serge 1637
{
5078 serge 1638
    static pci_dev_t device;
2997 Serge 1639
    const struct pci_device_id  *ent;
5078 serge 1640
    int  err;
1239 serge 1641
 
1642
    ent = find_pci_device(&device, pciidlist);
1643
    if( unlikely(ent == NULL) )
1644
    {
1645
        dbgprintf("device not found\n");
5078 serge 1646
        return -ENODEV;
1239 serge 1647
    };
1648
 
5078 serge 1649
    drm_core_init();
1650
 
1651
    DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
1239 serge 1652
                                device.pci_dev.device);
1653
 
5078 serge 1654
    kms_driver.driver_features |= DRIVER_MODESET;
3764 Serge 1655
 
5078 serge 1656
    err = drm_get_pci_dev(&device.pci_dev, ent, &kms_driver);
1239 serge 1657
 
1246 serge 1658
    return err;
5078 serge 1659
}
1430 serge 1660