WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_device.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
2997	Serge	29	#include
1179	serge	30	#include
		31	#include
1221	serge	32	#include
1117	serge	33	#include "radeon_reg.h"
		34	#include "radeon.h"
		35	#include "atom.h"
3120	serge	36
		37	#include "bitmap.h"
1428	serge	38	#include "display.h"
1117	serge	39
3120	serge	40
1221	serge	41	#include
		42
1117	serge	43
2160	serge	44	int radeon_no_wb = 1;
1430	serge	45	int radeon_modeset = -1;
		46	int radeon_dynclks = -1;
		47	int radeon_r4xx_atom = 0;
		48	int radeon_agpmode = 0;
		49	int radeon_vram_limit = 0;
		50	int radeon_gart_size = 512; /* default gart size */
		51	int radeon_benchmarking = 0;
		52	int radeon_testing = 0;
		53	int radeon_connector_table = 0;
		54	int radeon_tv = 1;
		55	int radeon_new_pll = -1;
		56	int radeon_dynpm = -1;
		57	int radeon_audio = 1;
1963	serge	58	int radeon_hw_i2c = 0;
		59	int radeon_pcie_gen2 = 0;
		60	int radeon_disp_priority = 0;
2997	Serge	61	int radeon_lockup_timeout = 10000;
3764	Serge	62	int radeon_fastfb = 0;
1117	serge	63
2160	serge	64	int irq_override = 0;
1430	serge	65
1963	serge	66
1428	serge	67	extern display_t *rdisplay;
3120	serge	68	struct drm_device *main_drm_device;
1246	serge	69
3120	serge	70
1404	serge	71	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);
		72	int init_display(struct radeon_device rdev, videomode_t mode);
		73	int init_display_kms(struct radeon_device rdev, videomode_t mode);
1117	serge	74
2997	Serge	75	int get_modes(videomode_t mode, u32_t count);
1404	serge	76	int set_user_mode(videomode_t *mode);
1428	serge	77	int r100_2D_test(struct radeon_device *rdev);
1239	serge	78
1404	serge	79
1233	serge	80	/* Legacy VGA regions */
		81	#define VGA_RSRC_NONE 0x00
		82	#define VGA_RSRC_LEGACY_IO 0x01
		83	#define VGA_RSRC_LEGACY_MEM 0x02
		84	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
		85	/* Non-legacy access */
		86	#define VGA_RSRC_NORMAL_IO 0x04
		87	#define VGA_RSRC_NORMAL_MEM 0x08
		88
		89
1963	serge	90	static const char radeon_family_name[][16] = {
		91	"R100",
		92	"RV100",
		93	"RS100",
		94	"RV200",
		95	"RS200",
		96	"R200",
		97	"RV250",
		98	"RS300",
		99	"RV280",
		100	"R300",
		101	"R350",
		102	"RV350",
		103	"RV380",
		104	"R420",
		105	"R423",
		106	"RV410",
		107	"RS400",
		108	"RS480",
		109	"RS600",
		110	"RS690",
		111	"RS740",
		112	"RV515",
		113	"R520",
		114	"RV530",
		115	"RV560",
		116	"RV570",
		117	"R580",
		118	"R600",
		119	"RV610",
		120	"RV630",
		121	"RV670",
		122	"RV620",
		123	"RV635",
		124	"RS780",
		125	"RS880",
		126	"RV770",
		127	"RV730",
		128	"RV710",
		129	"RV740",
		130	"CEDAR",
		131	"REDWOOD",
		132	"JUNIPER",
		133	"CYPRESS",
		134	"HEMLOCK",
		135	"PALM",
1986	serge	136	"SUMO",
		137	"SUMO2",
1963	serge	138	"BARTS",
		139	"TURKS",
		140	"CAICOS",
		141	"CAYMAN",
2997	Serge	142	"ARUBA",
		143	"TAHITI",
		144	"PITCAIRN",
		145	"VERDE",
3764	Serge	146	"OLAND",
		147	"HAINAN",
1963	serge	148	"LAST",
		149	};
1233	serge	150
2997	Serge	151	/**
3764	Serge	152	* radeon_program_register_sequence - program an array of registers.
		153	*
		154	* @rdev: radeon_device pointer
		155	* @registers: pointer to the register array
		156	* @array_size: size of the register array
		157	*
		158	* Programs an array or registers with and and or masks.
		159	* This is a helper for setting golden registers.
		160	*/
		161	void radeon_program_register_sequence(struct radeon_device *rdev,
		162	const u32 *registers,
		163	const u32 array_size)
		164	{
		165	u32 tmp, reg, and_mask, or_mask;
		166	int i;
		167
		168	if (array_size % 3)
		169	return;
		170
		171	for (i = 0; i < array_size; i +=3) {
		172	reg = registers[i + 0];
		173	and_mask = registers[i + 1];
		174	or_mask = registers[i + 2];
		175
		176	if (and_mask == 0xffffffff) {
		177	tmp = or_mask;
		178	} else {
		179	tmp = RREG32(reg);
		180	tmp &= ~and_mask;
		181	tmp \|= or_mask;
		182	}
		183	WREG32(reg, tmp);
		184	}
		185	}
		186
		187	/**
2997	Serge	188	* radeon_surface_init - Clear GPU surface registers.
		189	*
		190	* @rdev: radeon_device pointer
		191	*
		192	* Clear GPU surface registers (r1xx-r5xx).
1117	serge	193	*/
1179	serge	194	void radeon_surface_init(struct radeon_device *rdev)
1117	serge	195	{
		196	/* FIXME: check this out */
		197	if (rdev->family < CHIP_R600) {
		198	int i;
		199
1321	serge	200	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
1404	serge	201	radeon_clear_surface_reg(rdev, i);
1117	serge	202	}
1179	serge	203	/* enable surfaces */
		204	WREG32(RADEON_SURFACE_CNTL, 0);
1117	serge	205	}
		206	}
		207
		208	/*
		209	* GPU scratch registers helpers function.
		210	*/
2997	Serge	211	/**
		212	* radeon_scratch_init - Init scratch register driver information.
		213	*
		214	* @rdev: radeon_device pointer
		215	*
		216	* Init CP scratch register driver information (r1xx-r5xx)
		217	*/
1179	serge	218	void radeon_scratch_init(struct radeon_device *rdev)
1117	serge	219	{
		220	int i;
		221
		222	/* FIXME: check this out */
		223	if (rdev->family < CHIP_R300) {
		224	rdev->scratch.num_reg = 5;
		225	} else {
		226	rdev->scratch.num_reg = 7;
		227	}
1963	serge	228	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
1117	serge	229	for (i = 0; i < rdev->scratch.num_reg; i++) {
		230	rdev->scratch.free[i] = true;
1963	serge	231	rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1117	serge	232	}
		233	}
		234
2997	Serge	235	/**
		236	* radeon_scratch_get - Allocate a scratch register
		237	*
		238	* @rdev: radeon_device pointer
		239	* @reg: scratch register mmio offset
		240	*
		241	* Allocate a CP scratch register for use by the driver (all asics).
		242	* Returns 0 on success or -EINVAL on failure.
		243	*/
1117	serge	244	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
		245	{
		246	int i;
		247
		248	for (i = 0; i < rdev->scratch.num_reg; i++) {
		249	if (rdev->scratch.free[i]) {
		250	rdev->scratch.free[i] = false;
		251	*reg = rdev->scratch.reg[i];
		252	return 0;
		253	}
		254	}
		255	return -EINVAL;
		256	}
		257
2997	Serge	258	/**
		259	* radeon_scratch_free - Free a scratch register
		260	*
		261	* @rdev: radeon_device pointer
		262	* @reg: scratch register mmio offset
		263	*
		264	* Free a CP scratch register allocated for use by the driver (all asics)
		265	*/
1117	serge	266	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
		267	{
		268	int i;
		269
		270	for (i = 0; i < rdev->scratch.num_reg; i++) {
		271	if (rdev->scratch.reg[i] == reg) {
		272	rdev->scratch.free[i] = true;
		273	return;
		274	}
		275	}
		276	}
		277
2997	Serge	278	/*
		279	* radeon_wb_*()
		280	* Writeback is the the method by which the the GPU updates special pages
		281	* in memory with the status of certain GPU events (fences, ring pointers,
		282	* etc.).
		283	*/
		284
		285	/**
		286	* radeon_wb_disable - Disable Writeback
		287	*
		288	* @rdev: radeon_device pointer
		289	*
		290	* Disables Writeback (all asics). Used for suspend.
		291	*/
2004	serge	292	void radeon_wb_disable(struct radeon_device *rdev)
		293	{
		294	rdev->wb.enabled = false;
		295	}
		296
2997	Serge	297	/**
		298	* radeon_wb_fini - Disable Writeback and free memory
		299	*
		300	* @rdev: radeon_device pointer
		301	*
		302	* Disables Writeback and frees the Writeback memory (all asics).
		303	* Used at driver shutdown.
		304	*/
2004	serge	305	void radeon_wb_fini(struct radeon_device *rdev)
		306	{
		307	radeon_wb_disable(rdev);
		308	if (rdev->wb.wb_obj) {
		309	radeon_bo_unref(&rdev->wb.wb_obj);
		310	rdev->wb.wb = NULL;
		311	rdev->wb.wb_obj = NULL;
		312	}
		313	}
		314
2997	Serge	315	/**
		316	* radeon_wb_init- Init Writeback driver info and allocate memory
		317	*
		318	* @rdev: radeon_device pointer
		319	*
		320	* Disables Writeback and frees the Writeback memory (all asics).
		321	* Used at driver startup.
		322	* Returns 0 on success or an -error on failure.
		323	*/
2004	serge	324	int radeon_wb_init(struct radeon_device *rdev)
		325	{
		326	int r;
		327
		328	if (rdev->wb.wb_obj == NULL) {
		329	r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
2997	Serge	330	RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
2004	serge	331	if (r) {
		332	dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
		333	return r;
		334	}
		335	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		336	if (unlikely(r != 0)) {
		337	radeon_wb_fini(rdev);
		338	return r;
		339	}
		340	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
		341	&rdev->wb.gpu_addr);
		342	if (r) {
		343	radeon_bo_unreserve(rdev->wb.wb_obj);
		344	dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
		345	radeon_wb_fini(rdev);
		346	return r;
		347	}
		348	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
		349	radeon_bo_unreserve(rdev->wb.wb_obj);
		350	if (r) {
		351	dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
		352	radeon_wb_fini(rdev);
		353	return r;
		354	}
3764	Serge	355	}
2004	serge	356
		357	/* clear wb memory */
		358	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
		359	/* disable event_write fences */
		360	rdev->wb.use_event = false;
		361	/* disabled via module param */
2997	Serge	362	if (radeon_no_wb == 1) {
2004	serge	363	rdev->wb.enabled = false;
2997	Serge	364	} else {
		365	if (rdev->flags & RADEON_IS_AGP) {
2004	serge	366	/* often unreliable on AGP */
2997	Serge	367	rdev->wb.enabled = false;
		368	} else if (rdev->family < CHIP_R300) {
		369	/* often unreliable on pre-r300 */
		370	rdev->wb.enabled = false;
		371	} else {
2004	serge	372	rdev->wb.enabled = true;
		373	/* event_write fences are only available on r600+ */
2997	Serge	374	if (rdev->family >= CHIP_R600) {
2004	serge	375	rdev->wb.use_event = true;
		376	}
2997	Serge	377	}
		378	}
		379	/* always use writeback/events on NI, APUs */
		380	if (rdev->family >= CHIP_PALM) {
2004	serge	381	rdev->wb.enabled = true;
		382	rdev->wb.use_event = true;
		383	}
		384
		385	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
		386
		387	return 0;
		388	}
		389
1430	serge	390	/**
		391	* radeon_vram_location - try to find VRAM location
		392	* @rdev: radeon device structure holding all necessary informations
		393	* @mc: memory controller structure holding memory informations
		394	* @base: base address at which to put VRAM
		395	*
		396	* Function will place try to place VRAM at base address provided
		397	* as parameter (which is so far either PCI aperture address or
		398	* for IGP TOM base address).
		399	*
		400	* If there is not enough space to fit the unvisible VRAM in the 32bits
		401	* address space then we limit the VRAM size to the aperture.
		402	*
		403	* If we are using AGP and if the AGP aperture doesn't allow us to have
		404	* room for all the VRAM than we restrict the VRAM to the PCI aperture
		405	* size and print a warning.
		406	*
		407	* This function will never fails, worst case are limiting VRAM.
		408	*
		409	* Note: GTT start, end, size should be initialized before calling this
		410	* function on AGP platform.
		411	*
1963	serge	412	* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
1430	serge	413	* this shouldn't be a problem as we are using the PCI aperture as a reference.
		414	* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
		415	* not IGP.
		416	*
		417	* Note: we use mc_vram_size as on some board we need to program the mc to
		418	* cover the whole aperture even if VRAM size is inferior to aperture size
		419	* Novell bug 204882 + along with lots of ubuntu ones
		420	*
		421	* Note: when limiting vram it's safe to overwritte real_vram_size because
		422	* we are not in case where real_vram_size is inferior to mc_vram_size (ie
		423	* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
		424	* ones)
		425	*
		426	* Note: IGP TOM addr should be the same as the aperture addr, we don't
		427	* explicitly check for that thought.
		428	*
		429	* FIXME: when reducing VRAM size align new size on power of 2.
1117	serge	430	*/
1430	serge	431	void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base)
1117	serge	432	{
2997	Serge	433	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
		434
1430	serge	435	mc->vram_start = base;
3764	Serge	436	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
1430	serge	437	dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		438	mc->real_vram_size = mc->aper_size;
		439	mc->mc_vram_size = mc->aper_size;
		440	}
		441	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1963	serge	442	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
1430	serge	443	dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		444	mc->real_vram_size = mc->aper_size;
		445	mc->mc_vram_size = mc->aper_size;
		446	}
		447	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2997	Serge	448	if (limit && limit < mc->real_vram_size)
		449	mc->real_vram_size = limit;
1963	serge	450	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
1430	serge	451	mc->mc_vram_size >> 20, mc->vram_start,
		452	mc->vram_end, mc->real_vram_size >> 20);
		453	}
1117	serge	454
1430	serge	455	/**
		456	* radeon_gtt_location - try to find GTT location
		457	* @rdev: radeon device structure holding all necessary informations
		458	* @mc: memory controller structure holding memory informations
		459	*
		460	* Function will place try to place GTT before or after VRAM.
		461	*
		462	* If GTT size is bigger than space left then we ajust GTT size.
		463	* Thus function will never fails.
		464	*
		465	* FIXME: when reducing GTT size align new size on power of 2.
		466	*/
		467	void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc)
		468	{
		469	u64 size_af, size_bf;
		470
3764	Serge	471	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
1963	serge	472	size_bf = mc->vram_start & ~mc->gtt_base_align;
1430	serge	473	if (size_bf > size_af) {
		474	if (mc->gtt_size > size_bf) {
		475	dev_warn(rdev->dev, "limiting GTT\n");
		476	mc->gtt_size = size_bf;
1117	serge	477	}
1963	serge	478	mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
1430	serge	479	} else {
		480	if (mc->gtt_size > size_af) {
		481	dev_warn(rdev->dev, "limiting GTT\n");
		482	mc->gtt_size = size_af;
1117	serge	483	}
1963	serge	484	mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
1117	serge	485	}
1430	serge	486	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
1963	serge	487	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
1430	serge	488	mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
1117	serge	489	}
		490
		491	/*
		492	* GPU helpers function.
		493	*/
2997	Serge	494	/**
		495	* radeon_card_posted - check if the hw has already been initialized
		496	*
		497	* @rdev: radeon_device pointer
		498	*
		499	* Check if the asic has been initialized (all asics).
		500	* Used at driver startup.
		501	* Returns true if initialized or false if not.
		502	*/
1179	serge	503	bool radeon_card_posted(struct radeon_device *rdev)
1117	serge	504	{
		505	uint32_t reg;
		506
3764	Serge	507	if (ASIC_IS_NODCE(rdev))
		508	goto check_memsize;
		509
1117	serge	510	/* first check CRTCs */
3764	Serge	511	if (ASIC_IS_DCE4(rdev)) {
1430	serge	512	reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) \|
1963	serge	513	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
3764	Serge	514	if (rdev->num_crtc >= 4) {
		515	reg \|= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) \|
		516	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
		517	}
		518	if (rdev->num_crtc >= 6) {
		519	reg \|= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) \|
1430	serge	520	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
3764	Serge	521	}
1430	serge	522	if (reg & EVERGREEN_CRTC_MASTER_EN)
		523	return true;
		524	} else if (ASIC_IS_AVIVO(rdev)) {
1117	serge	525	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
		526	RREG32(AVIVO_D2CRTC_CONTROL);
		527	if (reg & AVIVO_CRTC_EN) {
		528	return true;
		529	}
		530	} else {
		531	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
		532	RREG32(RADEON_CRTC2_GEN_CNTL);
		533	if (reg & RADEON_CRTC_EN) {
		534	return true;
		535	}
		536	}
		537
3764	Serge	538	check_memsize:
1117	serge	539	/* then check MEM_SIZE, in case the crtcs are off */
		540	if (rdev->family >= CHIP_R600)
		541	reg = RREG32(R600_CONFIG_MEMSIZE);
		542	else
		543	reg = RREG32(RADEON_CONFIG_MEMSIZE);
		544
		545	if (reg)
		546	return true;
		547
		548	return false;
		549
		550	}
		551
2997	Serge	552	/**
		553	* radeon_update_bandwidth_info - update display bandwidth params
		554	*
		555	* @rdev: radeon_device pointer
		556	*
		557	* Used when sclk/mclk are switched or display modes are set.
		558	* params are used to calculate display watermarks (all asics)
		559	*/
1963	serge	560	void radeon_update_bandwidth_info(struct radeon_device *rdev)
		561	{
		562	fixed20_12 a;
		563	u32 sclk = rdev->pm.current_sclk;
		564	u32 mclk = rdev->pm.current_mclk;
		565
		566	/* sclk/mclk in Mhz */
		567	a.full = dfixed_const(100);
		568	rdev->pm.sclk.full = dfixed_const(sclk);
		569	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
		570	rdev->pm.mclk.full = dfixed_const(mclk);
		571	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
		572
		573	if (rdev->flags & RADEON_IS_IGP) {
		574	a.full = dfixed_const(16);
		575	/* core_bandwidth = sclk(Mhz) * 16 */
		576	rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
		577	}
		578	}
		579
2997	Serge	580	/**
		581	* radeon_boot_test_post_card - check and possibly initialize the hw
		582	*
		583	* @rdev: radeon_device pointer
		584	*
		585	* Check if the asic is initialized and if not, attempt to initialize
		586	* it (all asics).
		587	* Returns true if initialized or false if not.
		588	*/
1321	serge	589	bool radeon_boot_test_post_card(struct radeon_device *rdev)
		590	{
		591	if (radeon_card_posted(rdev))
		592	return true;
		593
		594	if (rdev->bios) {
		595	DRM_INFO("GPU not posted. posting now...\n");
		596	if (rdev->is_atom_bios)
		597	atom_asic_init(rdev->mode_info.atom_context);
		598	else
		599	radeon_combios_asic_init(rdev->ddev);
		600	return true;
		601	} else {
		602	dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		603	return false;
		604	}
		605	}
		606
2997	Serge	607	/**
		608	* radeon_dummy_page_init - init dummy page used by the driver
		609	*
		610	* @rdev: radeon_device pointer
		611	*
		612	* Allocate the dummy page used by the driver (all asics).
		613	* This dummy page is used by the driver as a filler for gart entries
		614	* when pages are taken out of the GART
		615	* Returns 0 on sucess, -ENOMEM on failure.
		616	*/
1233	serge	617	int radeon_dummy_page_init(struct radeon_device *rdev)
		618	{
1430	serge	619	if (rdev->dummy_page.page)
		620	return 0;
2997	Serge	621	rdev->dummy_page.page = (void*)AllocPage();
1233	serge	622	if (rdev->dummy_page.page == NULL)
		623	return -ENOMEM;
2997	Serge	624	rdev->dummy_page.addr = MapIoMem((addr_t)rdev->dummy_page.page, 4096, 3);
1233	serge	625	if (!rdev->dummy_page.addr) {
		626	// __free_page(rdev->dummy_page.page);
		627	rdev->dummy_page.page = NULL;
		628	return -ENOMEM;
		629	}
		630	return 0;
		631	}
1117	serge	632
2997	Serge	633	/**
		634	* radeon_dummy_page_fini - free dummy page used by the driver
		635	*
		636	* @rdev: radeon_device pointer
		637	*
		638	* Frees the dummy page used by the driver (all asics).
		639	*/
1233	serge	640	void radeon_dummy_page_fini(struct radeon_device *rdev)
		641	{
		642	if (rdev->dummy_page.page == NULL)
		643	return;
2997	Serge	644	KernelFree((void*)rdev->dummy_page.addr);
1233	serge	645	rdev->dummy_page.page = NULL;
		646	}
		647
		648
1117	serge	649	/* ATOM accessor methods */
2997	Serge	650	/*
		651	* ATOM is an interpreted byte code stored in tables in the vbios. The
		652	* driver registers callbacks to access registers and the interpreter
		653	* in the driver parses the tables and executes then to program specific
		654	* actions (set display modes, asic init, etc.). See radeon_atombios.c,
		655	* atombios.h, and atom.c
		656	*/
		657
		658	/**
		659	* cail_pll_read - read PLL register
		660	*
		661	* @info: atom card_info pointer
		662	* @reg: PLL register offset
		663	*
		664	* Provides a PLL register accessor for the atom interpreter (r4xx+).
		665	* Returns the value of the PLL register.
		666	*/
1117	serge	667	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
		668	{
		669	struct radeon_device *rdev = info->dev->dev_private;
		670	uint32_t r;
		671
		672	r = rdev->pll_rreg(rdev, reg);
		673	return r;
		674	}
		675
2997	Serge	676	/**
		677	* cail_pll_write - write PLL register
		678	*
		679	* @info: atom card_info pointer
		680	* @reg: PLL register offset
		681	* @val: value to write to the pll register
		682	*
		683	* Provides a PLL register accessor for the atom interpreter (r4xx+).
		684	*/
1117	serge	685	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
		686	{
		687	struct radeon_device *rdev = info->dev->dev_private;
		688
		689	rdev->pll_wreg(rdev, reg, val);
		690	}
		691
2997	Serge	692	/**
		693	* cail_mc_read - read MC (Memory Controller) register
		694	*
		695	* @info: atom card_info pointer
		696	* @reg: MC register offset
		697	*
		698	* Provides an MC register accessor for the atom interpreter (r4xx+).
		699	* Returns the value of the MC register.
		700	*/
1117	serge	701	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
		702	{
		703	struct radeon_device *rdev = info->dev->dev_private;
		704	uint32_t r;
		705
		706	r = rdev->mc_rreg(rdev, reg);
		707	return r;
		708	}
		709
2997	Serge	710	/**
		711	* cail_mc_write - write MC (Memory Controller) register
		712	*
		713	* @info: atom card_info pointer
		714	* @reg: MC register offset
		715	* @val: value to write to the pll register
		716	*
		717	* Provides a MC register accessor for the atom interpreter (r4xx+).
		718	*/
1117	serge	719	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
		720	{
		721	struct radeon_device *rdev = info->dev->dev_private;
		722
		723	rdev->mc_wreg(rdev, reg, val);
		724	}
		725
2997	Serge	726	/**
		727	* cail_reg_write - write MMIO register
		728	*
		729	* @info: atom card_info pointer
		730	* @reg: MMIO register offset
		731	* @val: value to write to the pll register
		732	*
		733	* Provides a MMIO register accessor for the atom interpreter (r4xx+).
		734	*/
1117	serge	735	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
		736	{
		737	struct radeon_device *rdev = info->dev->dev_private;
		738
		739	WREG32(reg*4, val);
		740	}
		741
2997	Serge	742	/**
		743	* cail_reg_read - read MMIO register
		744	*
		745	* @info: atom card_info pointer
		746	* @reg: MMIO register offset
		747	*
		748	* Provides an MMIO register accessor for the atom interpreter (r4xx+).
		749	* Returns the value of the MMIO register.
		750	*/
1117	serge	751	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
		752	{
		753	struct radeon_device *rdev = info->dev->dev_private;
		754	uint32_t r;
		755
		756	r = RREG32(reg*4);
		757	return r;
		758	}
		759
2997	Serge	760	/**
		761	* cail_ioreg_write - write IO register
		762	*
		763	* @info: atom card_info pointer
		764	* @reg: IO register offset
		765	* @val: value to write to the pll register
		766	*
		767	* Provides a IO register accessor for the atom interpreter (r4xx+).
		768	*/
1963	serge	769	static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
		770	{
		771	struct radeon_device *rdev = info->dev->dev_private;
		772
		773	WREG32_IO(reg*4, val);
		774	}
		775
2997	Serge	776	/**
		777	* cail_ioreg_read - read IO register
		778	*
		779	* @info: atom card_info pointer
		780	* @reg: IO register offset
		781	*
		782	* Provides an IO register accessor for the atom interpreter (r4xx+).
		783	* Returns the value of the IO register.
		784	*/
1963	serge	785	static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
		786	{
		787	struct radeon_device *rdev = info->dev->dev_private;
		788	uint32_t r;
		789
		790	r = RREG32_IO(reg*4);
		791	return r;
		792	}
		793
2997	Serge	794	/**
		795	* radeon_atombios_init - init the driver info and callbacks for atombios
		796	*
		797	* @rdev: radeon_device pointer
		798	*
		799	* Initializes the driver info and register access callbacks for the
		800	* ATOM interpreter (r4xx+).
		801	* Returns 0 on sucess, -ENOMEM on failure.
		802	* Called at driver startup.
		803	*/
1117	serge	804	int radeon_atombios_init(struct radeon_device *rdev)
		805	{
1268	serge	806	struct card_info *atom_card_info =
		807	kzalloc(sizeof(struct card_info), GFP_KERNEL);
1117	serge	808
1268	serge	809	if (!atom_card_info)
		810	return -ENOMEM;
		811
		812	rdev->mode_info.atom_card_info = atom_card_info;
		813	atom_card_info->dev = rdev->ddev;
		814	atom_card_info->reg_read = cail_reg_read;
		815	atom_card_info->reg_write = cail_reg_write;
1963	serge	816	/* needed for iio ops */
		817	if (rdev->rio_mem) {
		818	atom_card_info->ioreg_read = cail_ioreg_read;
		819	atom_card_info->ioreg_write = cail_ioreg_write;
		820	} else {
		821	DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
		822	atom_card_info->ioreg_read = cail_reg_read;
		823	atom_card_info->ioreg_write = cail_reg_write;
		824	}
1268	serge	825	atom_card_info->mc_read = cail_mc_read;
		826	atom_card_info->mc_write = cail_mc_write;
		827	atom_card_info->pll_read = cail_pll_read;
		828	atom_card_info->pll_write = cail_pll_write;
		829
		830	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
3764	Serge	831	if (!rdev->mode_info.atom_context) {
		832	radeon_atombios_fini(rdev);
		833	return -ENOMEM;
		834	}
		835
1630	serge	836	mutex_init(&rdev->mode_info.atom_context->mutex);
1117	serge	837	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1321	serge	838	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1117	serge	839	return 0;
		840	}
		841
2997	Serge	842	/**
		843	* radeon_atombios_fini - free the driver info and callbacks for atombios
		844	*
		845	* @rdev: radeon_device pointer
		846	*
		847	* Frees the driver info and register access callbacks for the ATOM
		848	* interpreter (r4xx+).
		849	* Called at driver shutdown.
		850	*/
1117	serge	851	void radeon_atombios_fini(struct radeon_device *rdev)
		852	{
1321	serge	853	if (rdev->mode_info.atom_context) {
		854	kfree(rdev->mode_info.atom_context->scratch);
3764	Serge	855	}
1119	serge	856	kfree(rdev->mode_info.atom_context);
3764	Serge	857	rdev->mode_info.atom_context = NULL;
1268	serge	858	kfree(rdev->mode_info.atom_card_info);
3764	Serge	859	rdev->mode_info.atom_card_info = NULL;
1117	serge	860	}
		861
2997	Serge	862	/* COMBIOS */
		863	/*
		864	* COMBIOS is the bios format prior to ATOM. It provides
		865	* command tables similar to ATOM, but doesn't have a unified
		866	* parser. See radeon_combios.c
		867	*/
		868
		869	/**
		870	* radeon_combios_init - init the driver info for combios
		871	*
		872	* @rdev: radeon_device pointer
		873	*
		874	* Initializes the driver info for combios (r1xx-r3xx).
		875	* Returns 0 on sucess.
		876	* Called at driver startup.
		877	*/
1117	serge	878	int radeon_combios_init(struct radeon_device *rdev)
		879	{
1128	serge	880	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117	serge	881	return 0;
		882	}
		883
2997	Serge	884	/**
		885	* radeon_combios_fini - free the driver info for combios
		886	*
		887	* @rdev: radeon_device pointer
		888	*
		889	* Frees the driver info for combios (r1xx-r3xx).
		890	* Called at driver shutdown.
		891	*/
1117	serge	892	void radeon_combios_fini(struct radeon_device *rdev)
		893	{
		894	}
		895
2997	Serge	896	/* if we get transitioned to only one device, take VGA back */
		897	/**
		898	* radeon_vga_set_decode - enable/disable vga decode
		899	*
		900	* @cookie: radeon_device pointer
		901	* @state: enable/disable vga decode
		902	*
		903	* Enable/disable vga decode (all asics).
		904	* Returns VGA resource flags.
		905	*/
1233	serge	906	static unsigned int radeon_vga_set_decode(void *cookie, bool state)
		907	{
		908	struct radeon_device *rdev = cookie;
		909	radeon_vga_set_state(rdev, state);
		910	if (state)
		911	return VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM \|
		912	VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		913	else
		914	return VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		915	}
1117	serge	916
2997	Serge	917	/**
		918	* radeon_check_pot_argument - check that argument is a power of two
		919	*
		920	* @arg: value to check
		921	*
		922	* Validates that a certain argument is a power of two (all asics).
		923	* Returns true if argument is valid.
		924	*/
		925	static bool radeon_check_pot_argument(int arg)
1404	serge	926	{
2997	Serge	927	return (arg & (arg - 1)) == 0;
		928	}
		929
		930	/**
		931	* radeon_check_arguments - validate module params
		932	*
		933	* @rdev: radeon_device pointer
		934	*
		935	* Validates certain module parameters and updates
		936	* the associated values used by the driver (all asics).
		937	*/
		938	static void radeon_check_arguments(struct radeon_device *rdev)
		939	{
1404	serge	940	/* vramlimit must be a power of two */
2997	Serge	941	if (!radeon_check_pot_argument(radeon_vram_limit)) {
1404	serge	942	dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
		943	radeon_vram_limit);
		944	radeon_vram_limit = 0;
		945	}
2997	Serge	946
1404	serge	947	/* gtt size must be power of two and greater or equal to 32M */
2997	Serge	948	if (radeon_gart_size < 32) {
1404	serge	949	dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
		950	radeon_gart_size);
		951	radeon_gart_size = 512;
2997	Serge	952
		953	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
1404	serge	954	dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
		955	radeon_gart_size);
		956	radeon_gart_size = 512;
		957	}
2997	Serge	958	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
		959
1404	serge	960	/* AGP mode can only be -1, 1, 2, 4, 8 */
		961	switch (radeon_agpmode) {
		962	case -1:
		963	case 0:
		964	case 1:
		965	case 2:
		966	case 4:
		967	case 8:
		968	break;
		969	default:
		970	dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
		971	"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		972	radeon_agpmode = 0;
		973	break;
		974	}
		975	}
		976
1117	serge	977	int radeon_device_init(struct radeon_device *rdev,
		978	struct drm_device *ddev,
		979	struct pci_dev *pdev,
		980	uint32_t flags)
		981	{
1963	serge	982	int r, i;
1179	serge	983	int dma_bits;
1117	serge	984
		985	rdev->shutdown = false;
		986	rdev->ddev = ddev;
		987	rdev->pdev = pdev;
		988	rdev->flags = flags;
		989	rdev->family = flags & RADEON_FAMILY_MASK;
		990	rdev->is_atom_bios = false;
		991	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
		992	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1221	serge	993	rdev->accel_working = false;
2997	Serge	994	/* set up ring ids */
		995	for (i = 0; i < RADEON_NUM_RINGS; i++) {
		996	rdev->ring[i].idx = i;
		997	}
1963	serge	998
2997	Serge	999	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
		1000	radeon_family_name[rdev->family], pdev->vendor, pdev->device,
		1001	pdev->subsystem_vendor, pdev->subsystem_device);
1963	serge	1002
1117	serge	1003	/* mutex initialization are all done here so we
		1004	* can recall function without having locking issues */
2997	Serge	1005	mutex_init(&rdev->ring_lock);
1630	serge	1006	mutex_init(&rdev->dc_hw_i2c_mutex);
2997	Serge	1007	atomic_set(&rdev->ih.lock, 0);
1630	serge	1008	mutex_init(&rdev->gem.mutex);
		1009	mutex_init(&rdev->pm.mutex);
2997	Serge	1010	mutex_init(&rdev->gpu_clock_mutex);
3764	Serge	1011	// init_rwsem(&rdev->pm.mclk_lock);
		1012	// init_rwsem(&rdev->exclusive_lock);
2997	Serge	1013	init_waitqueue_head(&rdev->irq.vblank_queue);
		1014	r = radeon_gem_init(rdev);
		1015	if (r)
		1016	return r;
		1017	/* initialize vm here */
		1018	mutex_init(&rdev->vm_manager.lock);
		1019	/* Adjust VM size here.
		1020	* Currently set to 4GB ((1 << 20) 4k pages).
		1021	* Max GPUVM size for cayman and SI is 40 bits.
		1022	*/
		1023	rdev->vm_manager.max_pfn = 1 << 20;
		1024	INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1117	serge	1025
1179	serge	1026	/* Set asic functions */
		1027	r = radeon_asic_init(rdev);
1404	serge	1028	if (r)
1179	serge	1029	return r;
1404	serge	1030	radeon_check_arguments(rdev);
1179	serge	1031
1963	serge	1032	/* all of the newer IGP chips have an internal gart
		1033	* However some rs4xx report as AGP, so remove that here.
		1034	*/
		1035	if ((rdev->family >= CHIP_RS400) &&
		1036	(rdev->flags & RADEON_IS_IGP)) {
		1037	rdev->flags &= ~RADEON_IS_AGP;
		1038	}
		1039
1321	serge	1040	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1221	serge	1041	radeon_agp_disable(rdev);
1117	serge	1042	}
		1043
3764	Serge	1044	/* Set the internal MC address mask
		1045	* This is the max address of the GPU's
		1046	* internal address space.
		1047	*/
		1048	if (rdev->family >= CHIP_CAYMAN)
		1049	rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
		1050	else if (rdev->family >= CHIP_CEDAR)
		1051	rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
		1052	else
		1053	rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
		1054
1179	serge	1055	/* set DMA mask + need_dma32 flags.
		1056	* PCIE - can handle 40-bits.
2997	Serge	1057	* IGP - can handle 40-bits
1179	serge	1058	* AGP - generally dma32 is safest
2997	Serge	1059	* PCI - dma32 for legacy pci gart, 40 bits on newer asics
1179	serge	1060	*/
		1061	rdev->need_dma32 = false;
		1062	if (rdev->flags & RADEON_IS_AGP)
		1063	rdev->need_dma32 = true;
2997	Serge	1064	if ((rdev->flags & RADEON_IS_PCI) &&
		1065	(rdev->family <= CHIP_RS740))
1179	serge	1066	rdev->need_dma32 = true;
1117	serge	1067
1179	serge	1068	dma_bits = rdev->need_dma32 ? 32 : 40;
		1069	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117	serge	1070	if (r) {
1986	serge	1071	rdev->need_dma32 = true;
2997	Serge	1072	dma_bits = 32;
1119	serge	1073	printk(KERN_WARNING "radeon: No suitable DMA available.\n");
		1074	}
1117	serge	1075
		1076	/* Registers mapping */
		1077	/* TODO: block userspace mapping of io register */
3192	Serge	1078	spin_lock_init(&rdev->mmio_idx_lock);
1117	serge	1079	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
		1080	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
2997	Serge	1081	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1117	serge	1082	if (rdev->rmmio == NULL) {
		1083	return -ENOMEM;
		1084	}
		1085	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
		1086	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
		1087
2997	Serge	1088	/* io port mapping */
		1089	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		1090	if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
		1091	rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
		1092	rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
		1093	break;
		1094	}
		1095	}
		1096	if (rdev->rio_mem == NULL)
		1097	DRM_ERROR("Unable to find PCI I/O BAR\n");
		1098
		1099
1179	serge	1100	r = radeon_init(rdev);
1221	serge	1101	if (r)
1963	serge	1102	return r;
1117	serge	1103
3192	Serge	1104	// r = radeon_ib_ring_tests(rdev);
		1105	// if (r)
		1106	// DRM_ERROR("ib ring test failed (%d).\n", r);
		1107
1221	serge	1108	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		1109	/* Acceleration not working on AGP card try again
		1110	* with fallback to PCI or PCIE GART
		1111	*/
1963	serge	1112	radeon_asic_reset(rdev);
1221	serge	1113	radeon_fini(rdev);
		1114	radeon_agp_disable(rdev);
		1115	r = radeon_init(rdev);
		1116	if (r)
1179	serge	1117	return r;
1126	serge	1118	}
1179	serge	1119	// if (radeon_testing) {
		1120	// radeon_test_moves(rdev);
1125	serge	1121	// }
2997	Serge	1122	// if ((radeon_testing & 2)) {
		1123	// radeon_test_syncing(rdev);
		1124	// }
2005	serge	1125	if (radeon_benchmarking) {
2997	Serge	1126	radeon_benchmark(rdev, radeon_benchmarking);
2005	serge	1127	}
1179	serge	1128	return 0;
1117	serge	1129	}
		1130
2997	Serge	1131	/**
		1132	* radeon_gpu_reset - reset the asic
		1133	*
		1134	* @rdev: radeon device pointer
		1135	*
		1136	* Attempt the reset the GPU if it has hung (all asics).
		1137	* Returns 0 for success or an error on failure.
		1138	*/
		1139	int radeon_gpu_reset(struct radeon_device *rdev)
		1140	{
		1141	unsigned ring_sizes[RADEON_NUM_RINGS];
		1142	uint32_t *ring_data[RADEON_NUM_RINGS];
1179	serge	1143
2997	Serge	1144	bool saved = false;
		1145
		1146	int i, r;
		1147	int resched;
		1148
		1149	// down_write(&rdev->exclusive_lock);
		1150	radeon_save_bios_scratch_regs(rdev);
		1151	/* block TTM */
		1152	// resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
		1153	radeon_suspend(rdev);
		1154
		1155	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		1156	ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
		1157	&ring_data[i]);
		1158	if (ring_sizes[i]) {
		1159	saved = true;
		1160	dev_info(rdev->dev, "Saved %d dwords of commands "
		1161	"on ring %d.\n", ring_sizes[i], i);
		1162	}
		1163	}
		1164
		1165	retry:
		1166	r = radeon_asic_reset(rdev);
		1167	if (!r) {
		1168	dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
		1169	radeon_resume(rdev);
		1170	}
		1171
		1172	radeon_restore_bios_scratch_regs(rdev);
		1173
		1174	if (!r) {
		1175	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		1176	radeon_ring_restore(rdev, &rdev->ring[i],
		1177	ring_sizes[i], ring_data[i]);
		1178	ring_sizes[i] = 0;
		1179	ring_data[i] = NULL;
		1180	}
		1181
3192	Serge	1182	// r = radeon_ib_ring_tests(rdev);
		1183	// if (r) {
		1184	// dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
		1185	// if (saved) {
		1186	// saved = false;
		1187	// radeon_suspend(rdev);
		1188	// goto retry;
		1189	// }
		1190	// }
2997	Serge	1191	} else {
		1192	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		1193	kfree(ring_data[i]);
		1194	}
		1195	}
		1196
		1197	// ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
		1198	if (r) {
		1199	/* bad news, how to tell it to userspace ? */
		1200	dev_info(rdev->dev, "GPU reset failed\n");
		1201	}
		1202
		1203	// up_write(&rdev->exclusive_lock);
		1204	return r;
		1205	}
		1206
		1207
1117	serge	1208	/*
		1209	* Driver load/unload
		1210	*/
		1211	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
		1212	{
		1213	struct radeon_device *rdev;
		1214	int r;
		1215
		1216
1120	serge	1217	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117	serge	1218	if (rdev == NULL) {
		1219	return -ENOMEM;
		1220	};
		1221
		1222	dev->dev_private = (void *)rdev;
		1223
		1224	/* update BUS flag */
1239	serge	1225	if (drm_device_is_agp(dev)) {
1117	serge	1226	flags \|= RADEON_IS_AGP;
1239	serge	1227	} else if (drm_device_is_pcie(dev)) {
		1228	flags \|= RADEON_IS_PCIE;
		1229	} else {
		1230	flags \|= RADEON_IS_PCI;
		1231	}
1117	serge	1232
1182	serge	1233	/* radeon_device_init should report only fatal error
		1234	* like memory allocation failure or iomapping failure,
		1235	* or memory manager initialization failure, it must
		1236	* properly initialize the GPU MC controller and permit
		1237	* VRAM allocation
		1238	*/
1117	serge	1239	r = radeon_device_init(rdev, dev, dev->pdev, flags);
		1240	if (r) {
1182	serge	1241	DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117	serge	1242	return r;
		1243	}
1182	serge	1244	/* Again modeset_init should fail only on fatal error
		1245	* otherwise it should provide enough functionalities
		1246	* for shadowfb to run
		1247	*/
1246	serge	1248	if( radeon_modeset )
		1249	{
1268	serge	1250	r = radeon_modeset_init(rdev);
		1251	if (r) {
		1252	return r;
		1253	}
1246	serge	1254	};
1117	serge	1255	return 0;
		1256	}
		1257
1404	serge	1258	videomode_t usermode;
1230	serge	1259
1239	serge	1260
1117	serge	1261	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		1262	{
1246	serge	1263	static struct drm_device *dev;
1117	serge	1264	int ret;
		1265
1246	serge	1266	dev = kzalloc(sizeof(*dev), 0);
1117	serge	1267	if (!dev)
		1268	return -ENOMEM;
		1269
		1270	// ret = pci_enable_device(pdev);
		1271	// if (ret)
		1272	// goto err_g1;
		1273
		1274	// pci_set_master(pdev);
		1275
		1276	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		1277	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		1278	// goto err_g2;
		1279	// }
		1280
		1281	dev->pdev = pdev;
		1282	dev->pci_device = pdev->device;
		1283	dev->pci_vendor = pdev->vendor;
		1284
1630	serge	1285	INIT_LIST_HEAD(&dev->filelist);
		1286	INIT_LIST_HEAD(&dev->ctxlist);
		1287	INIT_LIST_HEAD(&dev->vmalist);
		1288	INIT_LIST_HEAD(&dev->maplist);
		1289
		1290	spin_lock_init(&dev->count_lock);
		1291	mutex_init(&dev->struct_mutex);
		1292	mutex_init(&dev->ctxlist_mutex);
		1293
		1294
1221	serge	1295	ret = radeon_driver_load_kms(dev, ent->driver_data );
		1296	if (ret)
1117	serge	1297	goto err_g4;
		1298
3120	serge	1299	main_drm_device = dev;
		1300
1986	serge	1301	if( radeon_modeset )
		1302	init_display_kms(dev->dev_private, &usermode);
		1303	else
1268	serge	1304	init_display(dev->dev_private, &usermode);
1126	serge	1305
2160	serge	1306
1117	serge	1307	return 0;
		1308
		1309	err_g4:
		1310	// drm_put_minor(&dev->primary);
		1311	//err_g3:
		1312	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		1313	// drm_put_minor(&dev->control);
		1314	//err_g2:
		1315	// pci_disable_device(pdev);
		1316	//err_g1:
		1317	free(dev);
		1318
1221	serge	1319	LEAVE();
		1320
1117	serge	1321	return ret;
		1322	}
		1323
		1324	resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
		1325	{
		1326	return pci_resource_start(dev->pdev, resource);
		1327	}
		1328
		1329	resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
		1330	{
		1331	return pci_resource_len(dev->pdev, resource);
		1332	}
		1333
1123	serge	1334
		1335	uint32_t __div64_32(uint64_t *n, uint32_t base)
		1336	{
		1337	uint64_t rem = *n;
		1338	uint64_t b = base;
		1339	uint64_t res, d = 1;
		1340	uint32_t high = rem >> 32;
		1341
		1342	/* Reduce the thing a bit first */
		1343	res = 0;
		1344	if (high >= base) {
		1345	high /= base;
		1346	res = (uint64_t) high << 32;
		1347	rem -= (uint64_t) (high*base) << 32;
		1348	}
		1349
		1350	while ((int64_t)b > 0 && b < rem) {
		1351	b = b+b;
		1352	d = d+d;
		1353	}
		1354
		1355	do {
		1356	if (rem >= b) {
		1357	rem -= b;
		1358	res += d;
		1359	}
		1360	b >>= 1;
		1361	d >>= 1;
		1362	} while (d);
		1363
		1364	*n = res;
		1365	return rem;
		1366	}
		1367
1239	serge	1368
		1369	static struct pci_device_id pciidlist[] = {
		1370	radeon_PCI_IDS
		1371	};
		1372
		1373
3120	serge	1374	#define CURRENT_API 0x0200 /* 2.00 */
		1375	#define COMPATIBLE_API 0x0100 /* 1.00 */
1239	serge	1376
3120	serge	1377	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API
		1378
3764	Serge	1379	#define SRV_GETVERSION 0
		1380	#define SRV_ENUM_MODES 1
		1381	#define SRV_SET_MODE 2
3120	serge	1382	#define SRV_GET_CAPS 3
1239	serge	1383
3120	serge	1384	#define SRV_CREATE_SURFACE 10
		1385	#define SRV_DESTROY_SURFACE 11
		1386	#define SRV_LOCK_SURFACE 12
		1387	#define SRV_UNLOCK_SURFACE 13
		1388	#define SRV_RESIZE_SURFACE 14
		1389	#define SRV_BLIT_BITMAP 15
		1390	#define SRV_BLIT_TEXTURE 16
		1391	#define SRV_BLIT_VIDEO 17
2007	serge	1392
2175	serge	1393
3120	serge	1394
2007	serge	1395	int r600_video_blit(uint64_t src_offset, int x, int y,
		1396	int w, int h, int pitch);
		1397
2175	serge	1398	#define check_input(size) \
		1399	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \
		1400	break;
		1401
		1402	#define check_output(size) \
		1403	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \
		1404	break;
		1405
1239	serge	1406	int _stdcall display_handler(ioctl_t *io)
		1407	{
		1408	int retval = -1;
		1409	u32_t *inp;
		1410	u32_t *outp;
		1411
		1412	inp = io->input;
		1413	outp = io->output;
		1414
		1415	switch(io->io_code)
		1416	{
		1417	case SRV_GETVERSION:
2175	serge	1418	check_output(4);
2997	Serge	1419	*outp = API_VERSION;
		1420	retval = 0;
1239	serge	1421	break;
		1422
		1423	case SRV_ENUM_MODES:
		1424	dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
		1425	inp, io->inp_size, io->out_size );
2175	serge	1426	check_output(4);
		1427	if( radeon_modeset)
1404	serge	1428	retval = get_modes((videomode_t*)inp, outp);
1239	serge	1429	break;
		1430
		1431	case SRV_SET_MODE:
1246	serge	1432	dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
		1433	inp, io->inp_size);
2175	serge	1434	check_input(sizeof(videomode_t));
		1435	if( radeon_modeset )
1404	serge	1436	retval = set_user_mode((videomode_t*)inp);
1239	serge	1437	break;
3764	Serge	1438	/*
3120	serge	1439	case SRV_GET_CAPS:
		1440	retval = get_driver_caps((hwcaps_t*)inp);
2007	serge	1441	break;
		1442
3120	serge	1443	case SRV_CREATE_SURFACE:
		1444	// check_input(8);
		1445	retval = create_surface(main_drm_device, (struct io_call_10*)inp);
2007	serge	1446	break;
		1447
3120	serge	1448	case SRV_LOCK_SURFACE:
		1449	retval = lock_surface((struct io_call_12*)inp);
2175	serge	1450	break;
		1451
3120	serge	1452	case SRV_BLIT_BITMAP:
		1453	srv_blit_bitmap( inp[0], inp[1], inp[2],
		1454	inp[3], inp[4], inp[5], inp[6]);
3764	Serge	1455	*/
1239	serge	1456	};
		1457
		1458	return retval;
		1459	}
		1460
1246	serge	1461	static char log[256];
1404	serge	1462	static pci_dev_t device;
1246	serge	1463
2160	serge	1464	u32_t drvEntry(int action, char *cmdline)
1239	serge	1465	{
1428	serge	1466	struct radeon_device *rdev = NULL;
		1467
2997	Serge	1468	const struct pci_device_id *ent;
1239	serge	1469
		1470	int err;
		1471	u32_t retval = 0;
		1472
		1473	if(action != 1)
		1474	return 0;
		1475
		1476	if( GetService("DISPLAY") != 0 )
		1477	return 0;
		1478
		1479	if( cmdline && *cmdline )
1268	serge	1480	parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
1239	serge	1481
		1482	if(!dbg_open(log))
		1483	{
3764	Serge	1484	strcpy(log, "/TMP1/1/ati.log");
1239	serge	1485
		1486	if(!dbg_open(log))
		1487	{
		1488	printf("Can't open %s\nExit\n", log);
		1489	return 0;
		1490	};
		1491	}
3764	Serge	1492	dbgprintf("Radeon v3.10 preview-1 cmdline %s\n", cmdline);
1239	serge	1493
3764	Serge	1494	cpu_detect();
		1495
1239	serge	1496	enum_pci_devices();
1963	serge	1497
1239	serge	1498	ent = find_pci_device(&device, pciidlist);
		1499
		1500	if( unlikely(ent == NULL) )
		1501	{
		1502	dbgprintf("device not found\n");
		1503	return 0;
		1504	};
		1505
		1506	dbgprintf("device %x:%x\n", device.pci_dev.vendor,
		1507	device.pci_dev.device);
		1508
3764	Serge	1509	drm_global_init();
		1510
1239	serge	1511	err = drm_get_dev(&device.pci_dev, ent);
		1512
1428	serge	1513	rdev = rdisplay->ddev->dev_private;
		1514
1246	serge	1515	err = RegService("DISPLAY", display_handler);
1239	serge	1516
1246	serge	1517	if( err != 0)
		1518	dbgprintf("Set DISPLAY handler\n");
		1519
		1520	return err;
1239	serge	1521	};
1430	serge	1522
2997	Serge	1523	#define PCI_CLASS_REVISION 0x08
		1524	#define PCI_CLASS_DISPLAY_VGA 0x0300
		1525
		1526	int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
		1527	{
		1528	u16_t vendor, device;
		1529	u32_t class;
		1530	int ret = 0;
		1531
		1532	vendor = id & 0xffff;
		1533	device = (id >> 16) & 0xffff;
		1534
		1535	if(vendor == 0x1002)
		1536	{
		1537	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
		1538	class >>= 16;
		1539
		1540	if( class == PCI_CLASS_DISPLAY_VGA)
		1541	ret = 1;
		1542	}
		1543	return ret;
		1544	}
3192	Serge	1545

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c – Rev 3764