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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "atom.h" |
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1428 | serge | 36 | #include "display.h" |
1117 | serge | 37 | |
1221 | serge | 38 | #include |
39 | |||
1117 | serge | 40 | |
1430 | serge | 41 | int radeon_no_wb; |
42 | int radeon_modeset = -1; |
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43 | int radeon_dynclks = -1; |
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44 | int radeon_r4xx_atom = 0; |
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45 | int radeon_agpmode = 0; |
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46 | int radeon_vram_limit = 0; |
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47 | int radeon_gart_size = 512; /* default gart size */ |
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48 | int radeon_benchmarking = 0; |
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49 | int radeon_testing = 0; |
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50 | int radeon_connector_table = 0; |
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51 | int radeon_tv = 1; |
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52 | int radeon_new_pll = -1; |
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53 | int radeon_dynpm = -1; |
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54 | int radeon_audio = 1; |
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1963 | serge | 55 | int radeon_hw_i2c = 0; |
56 | int radeon_pcie_gen2 = 0; |
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57 | int radeon_disp_priority = 0; |
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1117 | serge | 58 | |
1430 | serge | 59 | |
1963 | serge | 60 | |
1428 | serge | 61 | extern display_t *rdisplay; |
1246 | serge | 62 | |
1404 | serge | 63 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
64 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
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65 | int init_display_kms(struct radeon_device *rdev, videomode_t *mode); |
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1117 | serge | 66 | |
1404 | serge | 67 | int get_modes(videomode_t *mode, int *count); |
68 | int set_user_mode(videomode_t *mode); |
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1428 | serge | 69 | int r100_2D_test(struct radeon_device *rdev); |
1239 | serge | 70 | |
1404 | serge | 71 | |
1233 | serge | 72 | /* Legacy VGA regions */ |
73 | #define VGA_RSRC_NONE 0x00 |
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74 | #define VGA_RSRC_LEGACY_IO 0x01 |
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75 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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76 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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77 | /* Non-legacy access */ |
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78 | #define VGA_RSRC_NORMAL_IO 0x04 |
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79 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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80 | |||
81 | |||
1963 | serge | 82 | static const char radeon_family_name[][16] = { |
83 | "R100", |
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84 | "RV100", |
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85 | "RS100", |
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86 | "RV200", |
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87 | "RS200", |
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88 | "R200", |
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89 | "RV250", |
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90 | "RS300", |
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91 | "RV280", |
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92 | "R300", |
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93 | "R350", |
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94 | "RV350", |
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95 | "RV380", |
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96 | "R420", |
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97 | "R423", |
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98 | "RV410", |
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99 | "RS400", |
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100 | "RS480", |
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101 | "RS600", |
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102 | "RS690", |
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103 | "RS740", |
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104 | "RV515", |
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105 | "R520", |
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106 | "RV530", |
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107 | "RV560", |
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108 | "RV570", |
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109 | "R580", |
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110 | "R600", |
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111 | "RV610", |
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112 | "RV630", |
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113 | "RV670", |
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114 | "RV620", |
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115 | "RV635", |
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116 | "RS780", |
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117 | "RS880", |
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118 | "RV770", |
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119 | "RV730", |
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120 | "RV710", |
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121 | "RV740", |
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122 | "CEDAR", |
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123 | "REDWOOD", |
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124 | "JUNIPER", |
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125 | "CYPRESS", |
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126 | "HEMLOCK", |
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127 | "PALM", |
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1986 | serge | 128 | "SUMO", |
129 | "SUMO2", |
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1963 | serge | 130 | "BARTS", |
131 | "TURKS", |
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132 | "CAICOS", |
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133 | "CAYMAN", |
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134 | "LAST", |
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135 | }; |
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1233 | serge | 136 | |
1117 | serge | 137 | /* |
138 | * Clear GPU surface registers. |
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139 | */ |
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1179 | serge | 140 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 141 | { |
142 | /* FIXME: check this out */ |
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143 | if (rdev->family < CHIP_R600) { |
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144 | int i; |
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145 | |||
1321 | serge | 146 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
1404 | serge | 147 | radeon_clear_surface_reg(rdev, i); |
1117 | serge | 148 | } |
1179 | serge | 149 | /* enable surfaces */ |
150 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 151 | } |
152 | } |
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153 | |||
154 | /* |
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155 | * GPU scratch registers helpers function. |
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156 | */ |
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1179 | serge | 157 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 158 | { |
159 | int i; |
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160 | |||
161 | /* FIXME: check this out */ |
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162 | if (rdev->family < CHIP_R300) { |
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163 | rdev->scratch.num_reg = 5; |
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164 | } else { |
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165 | rdev->scratch.num_reg = 7; |
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166 | } |
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1963 | serge | 167 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
1117 | serge | 168 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
169 | rdev->scratch.free[i] = true; |
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1963 | serge | 170 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1117 | serge | 171 | } |
172 | } |
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173 | |||
174 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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175 | { |
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176 | int i; |
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177 | |||
178 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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179 | if (rdev->scratch.free[i]) { |
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180 | rdev->scratch.free[i] = false; |
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181 | *reg = rdev->scratch.reg[i]; |
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182 | return 0; |
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183 | } |
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184 | } |
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185 | return -EINVAL; |
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186 | } |
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187 | |||
188 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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189 | { |
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190 | int i; |
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191 | |||
192 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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193 | if (rdev->scratch.reg[i] == reg) { |
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194 | rdev->scratch.free[i] = true; |
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195 | return; |
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196 | } |
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197 | } |
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198 | } |
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199 | |||
1430 | serge | 200 | /** |
201 | * radeon_vram_location - try to find VRAM location |
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202 | * @rdev: radeon device structure holding all necessary informations |
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203 | * @mc: memory controller structure holding memory informations |
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204 | * @base: base address at which to put VRAM |
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205 | * |
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206 | * Function will place try to place VRAM at base address provided |
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207 | * as parameter (which is so far either PCI aperture address or |
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208 | * for IGP TOM base address). |
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209 | * |
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210 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
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211 | * address space then we limit the VRAM size to the aperture. |
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212 | * |
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213 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
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214 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
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215 | * size and print a warning. |
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216 | * |
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217 | * This function will never fails, worst case are limiting VRAM. |
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218 | * |
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219 | * Note: GTT start, end, size should be initialized before calling this |
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220 | * function on AGP platform. |
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221 | * |
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1963 | serge | 222 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
1430 | serge | 223 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
224 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
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225 | * not IGP. |
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226 | * |
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227 | * Note: we use mc_vram_size as on some board we need to program the mc to |
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228 | * cover the whole aperture even if VRAM size is inferior to aperture size |
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229 | * Novell bug 204882 + along with lots of ubuntu ones |
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230 | * |
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231 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
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232 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
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233 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
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234 | * ones) |
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235 | * |
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236 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
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237 | * explicitly check for that thought. |
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238 | * |
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239 | * FIXME: when reducing VRAM size align new size on power of 2. |
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1117 | serge | 240 | */ |
1430 | serge | 241 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
1117 | serge | 242 | { |
1430 | serge | 243 | mc->vram_start = base; |
244 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
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245 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
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246 | mc->real_vram_size = mc->aper_size; |
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247 | mc->mc_vram_size = mc->aper_size; |
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248 | } |
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249 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 250 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
1430 | serge | 251 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
252 | mc->real_vram_size = mc->aper_size; |
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253 | mc->mc_vram_size = mc->aper_size; |
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254 | } |
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255 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 256 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
1430 | serge | 257 | mc->mc_vram_size >> 20, mc->vram_start, |
258 | mc->vram_end, mc->real_vram_size >> 20); |
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259 | } |
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1117 | serge | 260 | |
1430 | serge | 261 | /** |
262 | * radeon_gtt_location - try to find GTT location |
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263 | * @rdev: radeon device structure holding all necessary informations |
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264 | * @mc: memory controller structure holding memory informations |
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265 | * |
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266 | * Function will place try to place GTT before or after VRAM. |
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267 | * |
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268 | * If GTT size is bigger than space left then we ajust GTT size. |
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269 | * Thus function will never fails. |
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270 | * |
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271 | * FIXME: when reducing GTT size align new size on power of 2. |
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272 | */ |
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273 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
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274 | { |
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275 | u64 size_af, size_bf; |
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276 | |||
1963 | serge | 277 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
278 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
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1430 | serge | 279 | if (size_bf > size_af) { |
280 | if (mc->gtt_size > size_bf) { |
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281 | dev_warn(rdev->dev, "limiting GTT\n"); |
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282 | mc->gtt_size = size_bf; |
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1117 | serge | 283 | } |
1963 | serge | 284 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
1430 | serge | 285 | } else { |
286 | if (mc->gtt_size > size_af) { |
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287 | dev_warn(rdev->dev, "limiting GTT\n"); |
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288 | mc->gtt_size = size_af; |
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1117 | serge | 289 | } |
1963 | serge | 290 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
1117 | serge | 291 | } |
1430 | serge | 292 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
1963 | serge | 293 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
1430 | serge | 294 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
1117 | serge | 295 | } |
296 | |||
297 | /* |
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298 | * GPU helpers function. |
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299 | */ |
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1179 | serge | 300 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 301 | { |
302 | uint32_t reg; |
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303 | |||
304 | /* first check CRTCs */ |
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1963 | serge | 305 | if (ASIC_IS_DCE41(rdev)) { |
1430 | serge | 306 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
1963 | serge | 307 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
308 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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309 | return true; |
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310 | } else if (ASIC_IS_DCE4(rdev)) { |
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311 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
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1430 | serge | 312 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
313 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
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314 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
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315 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
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316 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
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317 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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318 | return true; |
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319 | } else if (ASIC_IS_AVIVO(rdev)) { |
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1117 | serge | 320 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
321 | RREG32(AVIVO_D2CRTC_CONTROL); |
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322 | if (reg & AVIVO_CRTC_EN) { |
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323 | return true; |
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324 | } |
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325 | } else { |
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326 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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327 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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328 | if (reg & RADEON_CRTC_EN) { |
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329 | return true; |
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330 | } |
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331 | } |
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332 | |||
333 | /* then check MEM_SIZE, in case the crtcs are off */ |
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334 | if (rdev->family >= CHIP_R600) |
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335 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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336 | else |
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337 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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338 | |||
339 | if (reg) |
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340 | return true; |
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341 | |||
342 | return false; |
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343 | |||
344 | } |
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345 | |||
1963 | serge | 346 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
347 | { |
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348 | fixed20_12 a; |
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349 | u32 sclk = rdev->pm.current_sclk; |
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350 | u32 mclk = rdev->pm.current_mclk; |
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351 | |||
352 | /* sclk/mclk in Mhz */ |
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353 | a.full = dfixed_const(100); |
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354 | rdev->pm.sclk.full = dfixed_const(sclk); |
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355 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
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356 | rdev->pm.mclk.full = dfixed_const(mclk); |
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357 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
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358 | |||
359 | if (rdev->flags & RADEON_IS_IGP) { |
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360 | a.full = dfixed_const(16); |
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361 | /* core_bandwidth = sclk(Mhz) * 16 */ |
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362 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
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363 | } |
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364 | } |
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365 | |||
1321 | serge | 366 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
367 | { |
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368 | if (radeon_card_posted(rdev)) |
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369 | return true; |
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370 | |||
371 | if (rdev->bios) { |
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372 | DRM_INFO("GPU not posted. posting now...\n"); |
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373 | if (rdev->is_atom_bios) |
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374 | atom_asic_init(rdev->mode_info.atom_context); |
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375 | else |
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376 | radeon_combios_asic_init(rdev->ddev); |
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377 | return true; |
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378 | } else { |
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379 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
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380 | return false; |
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381 | } |
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382 | } |
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383 | |||
1233 | serge | 384 | int radeon_dummy_page_init(struct radeon_device *rdev) |
385 | { |
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1430 | serge | 386 | if (rdev->dummy_page.page) |
387 | return 0; |
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1233 | serge | 388 | rdev->dummy_page.page = AllocPage(); |
389 | if (rdev->dummy_page.page == NULL) |
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390 | return -ENOMEM; |
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391 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
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392 | if (!rdev->dummy_page.addr) { |
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393 | // __free_page(rdev->dummy_page.page); |
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394 | rdev->dummy_page.page = NULL; |
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395 | return -ENOMEM; |
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396 | } |
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397 | return 0; |
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398 | } |
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1117 | serge | 399 | |
1233 | serge | 400 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
401 | { |
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402 | if (rdev->dummy_page.page == NULL) |
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403 | return; |
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404 | KernelFree(rdev->dummy_page.addr); |
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405 | rdev->dummy_page.page = NULL; |
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406 | } |
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407 | |||
408 | |||
1117 | serge | 409 | /* ATOM accessor methods */ |
410 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
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411 | { |
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412 | struct radeon_device *rdev = info->dev->dev_private; |
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413 | uint32_t r; |
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414 | |||
415 | r = rdev->pll_rreg(rdev, reg); |
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416 | return r; |
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417 | } |
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418 | |||
419 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
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420 | { |
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421 | struct radeon_device *rdev = info->dev->dev_private; |
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422 | |||
423 | rdev->pll_wreg(rdev, reg, val); |
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424 | } |
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425 | |||
426 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
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427 | { |
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428 | struct radeon_device *rdev = info->dev->dev_private; |
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429 | uint32_t r; |
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430 | |||
431 | r = rdev->mc_rreg(rdev, reg); |
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432 | return r; |
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433 | } |
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434 | |||
435 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
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436 | { |
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437 | struct radeon_device *rdev = info->dev->dev_private; |
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438 | |||
439 | rdev->mc_wreg(rdev, reg, val); |
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440 | } |
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441 | |||
442 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
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443 | { |
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444 | struct radeon_device *rdev = info->dev->dev_private; |
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445 | |||
446 | WREG32(reg*4, val); |
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447 | } |
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448 | |||
449 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
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450 | { |
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451 | struct radeon_device *rdev = info->dev->dev_private; |
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452 | uint32_t r; |
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453 | |||
454 | r = RREG32(reg*4); |
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455 | return r; |
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456 | } |
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457 | |||
1963 | serge | 458 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
459 | { |
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460 | struct radeon_device *rdev = info->dev->dev_private; |
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461 | |||
462 | WREG32_IO(reg*4, val); |
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463 | } |
||
464 | |||
465 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
||
466 | { |
||
467 | struct radeon_device *rdev = info->dev->dev_private; |
||
468 | uint32_t r; |
||
469 | |||
470 | r = RREG32_IO(reg*4); |
||
471 | return r; |
||
472 | } |
||
473 | |||
1117 | serge | 474 | int radeon_atombios_init(struct radeon_device *rdev) |
475 | { |
||
1268 | serge | 476 | struct card_info *atom_card_info = |
477 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 478 | |
1268 | serge | 479 | if (!atom_card_info) |
480 | return -ENOMEM; |
||
481 | |||
482 | rdev->mode_info.atom_card_info = atom_card_info; |
||
483 | atom_card_info->dev = rdev->ddev; |
||
484 | atom_card_info->reg_read = cail_reg_read; |
||
485 | atom_card_info->reg_write = cail_reg_write; |
||
1963 | serge | 486 | /* needed for iio ops */ |
487 | if (rdev->rio_mem) { |
||
488 | atom_card_info->ioreg_read = cail_ioreg_read; |
||
489 | atom_card_info->ioreg_write = cail_ioreg_write; |
||
490 | } else { |
||
491 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
||
492 | atom_card_info->ioreg_read = cail_reg_read; |
||
493 | atom_card_info->ioreg_write = cail_reg_write; |
||
494 | } |
||
1268 | serge | 495 | atom_card_info->mc_read = cail_mc_read; |
496 | atom_card_info->mc_write = cail_mc_write; |
||
497 | atom_card_info->pll_read = cail_pll_read; |
||
498 | atom_card_info->pll_write = cail_pll_write; |
||
499 | |||
500 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1630 | serge | 501 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1117 | serge | 502 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 503 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 504 | return 0; |
505 | } |
||
506 | |||
507 | void radeon_atombios_fini(struct radeon_device *rdev) |
||
508 | { |
||
1321 | serge | 509 | if (rdev->mode_info.atom_context) { |
510 | kfree(rdev->mode_info.atom_context->scratch); |
||
1119 | serge | 511 | kfree(rdev->mode_info.atom_context); |
1321 | serge | 512 | } |
1268 | serge | 513 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 514 | } |
515 | |||
516 | int radeon_combios_init(struct radeon_device *rdev) |
||
517 | { |
||
1128 | serge | 518 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 519 | return 0; |
520 | } |
||
521 | |||
522 | void radeon_combios_fini(struct radeon_device *rdev) |
||
523 | { |
||
524 | } |
||
525 | |||
1233 | serge | 526 | /* if we get transitioned to only one device, tak VGA back */ |
527 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
||
528 | { |
||
529 | struct radeon_device *rdev = cookie; |
||
530 | radeon_vga_set_state(rdev, state); |
||
531 | if (state) |
||
532 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
533 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
534 | else |
||
535 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
536 | } |
||
1117 | serge | 537 | |
1404 | serge | 538 | void radeon_check_arguments(struct radeon_device *rdev) |
539 | { |
||
540 | /* vramlimit must be a power of two */ |
||
541 | switch (radeon_vram_limit) { |
||
542 | case 0: |
||
543 | case 4: |
||
544 | case 8: |
||
545 | case 16: |
||
546 | case 32: |
||
547 | case 64: |
||
548 | case 128: |
||
549 | case 256: |
||
550 | case 512: |
||
551 | case 1024: |
||
552 | case 2048: |
||
553 | case 4096: |
||
554 | break; |
||
555 | default: |
||
556 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
||
557 | radeon_vram_limit); |
||
558 | radeon_vram_limit = 0; |
||
559 | break; |
||
560 | } |
||
561 | radeon_vram_limit = radeon_vram_limit << 20; |
||
562 | /* gtt size must be power of two and greater or equal to 32M */ |
||
563 | switch (radeon_gart_size) { |
||
564 | case 4: |
||
565 | case 8: |
||
566 | case 16: |
||
567 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
||
568 | radeon_gart_size); |
||
569 | radeon_gart_size = 512; |
||
570 | break; |
||
571 | case 32: |
||
572 | case 64: |
||
573 | case 128: |
||
574 | case 256: |
||
575 | case 512: |
||
576 | case 1024: |
||
577 | case 2048: |
||
578 | case 4096: |
||
579 | break; |
||
580 | default: |
||
581 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
||
582 | radeon_gart_size); |
||
583 | radeon_gart_size = 512; |
||
584 | break; |
||
585 | } |
||
586 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
587 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
||
588 | switch (radeon_agpmode) { |
||
589 | case -1: |
||
590 | case 0: |
||
591 | case 1: |
||
592 | case 2: |
||
593 | case 4: |
||
594 | case 8: |
||
595 | break; |
||
596 | default: |
||
597 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
||
598 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
||
599 | radeon_agpmode = 0; |
||
600 | break; |
||
601 | } |
||
602 | } |
||
603 | |||
1117 | serge | 604 | int radeon_device_init(struct radeon_device *rdev, |
605 | struct drm_device *ddev, |
||
606 | struct pci_dev *pdev, |
||
607 | uint32_t flags) |
||
608 | { |
||
1963 | serge | 609 | int r, i; |
1179 | serge | 610 | int dma_bits; |
1117 | serge | 611 | |
612 | rdev->shutdown = false; |
||
613 | rdev->ddev = ddev; |
||
614 | rdev->pdev = pdev; |
||
615 | rdev->flags = flags; |
||
616 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
617 | rdev->is_atom_bios = false; |
||
618 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
619 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
620 | rdev->gpu_lockup = false; |
||
1221 | serge | 621 | rdev->accel_working = false; |
1963 | serge | 622 | |
623 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", |
||
624 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); |
||
625 | |||
1117 | serge | 626 | /* mutex initialization are all done here so we |
627 | * can recall function without having locking issues */ |
||
1630 | serge | 628 | mutex_init(&rdev->cs_mutex); |
629 | mutex_init(&rdev->ib_pool.mutex); |
||
630 | mutex_init(&rdev->cp.mutex); |
||
631 | mutex_init(&rdev->dc_hw_i2c_mutex); |
||
1963 | serge | 632 | // if (rdev->family >= CHIP_R600) |
633 | // spin_lock_init(&rdev->ih.lock); |
||
1630 | serge | 634 | mutex_init(&rdev->gem.mutex); |
635 | mutex_init(&rdev->pm.mutex); |
||
1963 | serge | 636 | mutex_init(&rdev->vram_mutex); |
1117 | serge | 637 | // rwlock_init(&rdev->fence_drv.lock); |
1963 | serge | 638 | INIT_LIST_HEAD(&rdev->gem.objects); |
1117 | serge | 639 | |
1179 | serge | 640 | /* Set asic functions */ |
641 | r = radeon_asic_init(rdev); |
||
1404 | serge | 642 | if (r) |
1179 | serge | 643 | return r; |
1404 | serge | 644 | radeon_check_arguments(rdev); |
1179 | serge | 645 | |
1963 | serge | 646 | /* all of the newer IGP chips have an internal gart |
647 | * However some rs4xx report as AGP, so remove that here. |
||
648 | */ |
||
649 | if ((rdev->family >= CHIP_RS400) && |
||
650 | (rdev->flags & RADEON_IS_IGP)) { |
||
651 | rdev->flags &= ~RADEON_IS_AGP; |
||
652 | } |
||
653 | |||
1321 | serge | 654 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 655 | radeon_agp_disable(rdev); |
1117 | serge | 656 | } |
657 | |||
1179 | serge | 658 | /* set DMA mask + need_dma32 flags. |
659 | * PCIE - can handle 40-bits. |
||
660 | * IGP - can handle 40-bits (in theory) |
||
661 | * AGP - generally dma32 is safest |
||
662 | * PCI - only dma32 |
||
663 | */ |
||
664 | rdev->need_dma32 = false; |
||
665 | if (rdev->flags & RADEON_IS_AGP) |
||
666 | rdev->need_dma32 = true; |
||
667 | if (rdev->flags & RADEON_IS_PCI) |
||
668 | rdev->need_dma32 = true; |
||
1117 | serge | 669 | |
1179 | serge | 670 | dma_bits = rdev->need_dma32 ? 32 : 40; |
671 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 672 | if (r) { |
1986 | serge | 673 | rdev->need_dma32 = true; |
1119 | serge | 674 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
675 | } |
||
1117 | serge | 676 | |
677 | /* Registers mapping */ |
||
678 | /* TODO: block userspace mapping of io register */ |
||
679 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
680 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
681 | |||
682 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
683 | PG_SW+PG_NOCACHE); |
||
684 | |||
685 | if (rdev->rmmio == NULL) { |
||
686 | return -ENOMEM; |
||
687 | } |
||
688 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
689 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
690 | |||
1179 | serge | 691 | r = radeon_init(rdev); |
1221 | serge | 692 | if (r) |
1963 | serge | 693 | return r; |
1117 | serge | 694 | |
1221 | serge | 695 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
696 | /* Acceleration not working on AGP card try again |
||
697 | * with fallback to PCI or PCIE GART |
||
698 | */ |
||
1963 | serge | 699 | radeon_asic_reset(rdev); |
1221 | serge | 700 | radeon_fini(rdev); |
701 | radeon_agp_disable(rdev); |
||
702 | r = radeon_init(rdev); |
||
703 | if (r) |
||
1179 | serge | 704 | return r; |
1126 | serge | 705 | } |
1179 | serge | 706 | // if (radeon_testing) { |
707 | // radeon_test_moves(rdev); |
||
1125 | serge | 708 | // } |
1179 | serge | 709 | // if (radeon_benchmarking) { |
710 | // radeon_benchmark(rdev); |
||
711 | // } |
||
712 | return 0; |
||
1117 | serge | 713 | } |
714 | |||
1179 | serge | 715 | |
1117 | serge | 716 | /* |
717 | * Driver load/unload |
||
718 | */ |
||
719 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
720 | { |
||
721 | struct radeon_device *rdev; |
||
722 | int r; |
||
723 | |||
1182 | serge | 724 | ENTER(); |
1117 | serge | 725 | |
1120 | serge | 726 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 727 | if (rdev == NULL) { |
728 | return -ENOMEM; |
||
729 | }; |
||
730 | |||
731 | dev->dev_private = (void *)rdev; |
||
732 | |||
733 | /* update BUS flag */ |
||
1239 | serge | 734 | if (drm_device_is_agp(dev)) { |
1117 | serge | 735 | flags |= RADEON_IS_AGP; |
1239 | serge | 736 | } else if (drm_device_is_pcie(dev)) { |
737 | flags |= RADEON_IS_PCIE; |
||
738 | } else { |
||
739 | flags |= RADEON_IS_PCI; |
||
740 | } |
||
1117 | serge | 741 | |
1182 | serge | 742 | /* radeon_device_init should report only fatal error |
743 | * like memory allocation failure or iomapping failure, |
||
744 | * or memory manager initialization failure, it must |
||
745 | * properly initialize the GPU MC controller and permit |
||
746 | * VRAM allocation |
||
747 | */ |
||
1117 | serge | 748 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
749 | if (r) { |
||
1182 | serge | 750 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 751 | return r; |
752 | } |
||
1182 | serge | 753 | /* Again modeset_init should fail only on fatal error |
754 | * otherwise it should provide enough functionalities |
||
755 | * for shadowfb to run |
||
756 | */ |
||
1246 | serge | 757 | if( radeon_modeset ) |
758 | { |
||
1268 | serge | 759 | r = radeon_modeset_init(rdev); |
760 | if (r) { |
||
761 | return r; |
||
762 | } |
||
1246 | serge | 763 | }; |
1117 | serge | 764 | return 0; |
765 | } |
||
766 | |||
1404 | serge | 767 | videomode_t usermode; |
1230 | serge | 768 | |
1239 | serge | 769 | |
1117 | serge | 770 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
771 | { |
||
1246 | serge | 772 | static struct drm_device *dev; |
1117 | serge | 773 | int ret; |
774 | |||
1221 | serge | 775 | ENTER(); |
1117 | serge | 776 | |
1246 | serge | 777 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 778 | if (!dev) |
779 | return -ENOMEM; |
||
780 | |||
781 | // ret = pci_enable_device(pdev); |
||
782 | // if (ret) |
||
783 | // goto err_g1; |
||
784 | |||
785 | // pci_set_master(pdev); |
||
786 | |||
787 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
788 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
789 | // goto err_g2; |
||
790 | // } |
||
791 | |||
792 | dev->pdev = pdev; |
||
793 | dev->pci_device = pdev->device; |
||
794 | dev->pci_vendor = pdev->vendor; |
||
795 | |||
1630 | serge | 796 | INIT_LIST_HEAD(&dev->filelist); |
797 | INIT_LIST_HEAD(&dev->ctxlist); |
||
798 | INIT_LIST_HEAD(&dev->vmalist); |
||
799 | INIT_LIST_HEAD(&dev->maplist); |
||
800 | |||
801 | spin_lock_init(&dev->count_lock); |
||
802 | mutex_init(&dev->struct_mutex); |
||
803 | mutex_init(&dev->ctxlist_mutex); |
||
804 | |||
805 | |||
1221 | serge | 806 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
807 | if (ret) |
||
1117 | serge | 808 | goto err_g4; |
809 | |||
1986 | serge | 810 | if( radeon_modeset ) |
811 | init_display_kms(dev->dev_private, &usermode); |
||
812 | else |
||
1268 | serge | 813 | init_display(dev->dev_private, &usermode); |
1126 | serge | 814 | |
1221 | serge | 815 | LEAVE(); |
816 | |||
1117 | serge | 817 | return 0; |
818 | |||
819 | err_g4: |
||
820 | // drm_put_minor(&dev->primary); |
||
821 | //err_g3: |
||
822 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
823 | // drm_put_minor(&dev->control); |
||
824 | //err_g2: |
||
825 | // pci_disable_device(pdev); |
||
826 | //err_g1: |
||
827 | free(dev); |
||
828 | |||
1221 | serge | 829 | LEAVE(); |
830 | |||
1117 | serge | 831 | return ret; |
832 | } |
||
833 | |||
834 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
835 | { |
||
836 | return pci_resource_start(dev->pdev, resource); |
||
837 | } |
||
838 | |||
839 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
840 | { |
||
841 | return pci_resource_len(dev->pdev, resource); |
||
842 | } |
||
843 | |||
1123 | serge | 844 | |
845 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
846 | { |
||
847 | uint64_t rem = *n; |
||
848 | uint64_t b = base; |
||
849 | uint64_t res, d = 1; |
||
850 | uint32_t high = rem >> 32; |
||
851 | |||
852 | /* Reduce the thing a bit first */ |
||
853 | res = 0; |
||
854 | if (high >= base) { |
||
855 | high /= base; |
||
856 | res = (uint64_t) high << 32; |
||
857 | rem -= (uint64_t) (high*base) << 32; |
||
858 | } |
||
859 | |||
860 | while ((int64_t)b > 0 && b < rem) { |
||
861 | b = b+b; |
||
862 | d = d+d; |
||
863 | } |
||
864 | |||
865 | do { |
||
866 | if (rem >= b) { |
||
867 | rem -= b; |
||
868 | res += d; |
||
869 | } |
||
870 | b >>= 1; |
||
871 | d >>= 1; |
||
872 | } while (d); |
||
873 | |||
874 | *n = res; |
||
875 | return rem; |
||
876 | } |
||
877 | |||
1239 | serge | 878 | |
879 | static struct pci_device_id pciidlist[] = { |
||
880 | radeon_PCI_IDS |
||
881 | }; |
||
882 | |||
883 | |||
884 | #define API_VERSION 0x01000100 |
||
885 | |||
886 | #define SRV_GETVERSION 0 |
||
887 | #define SRV_ENUM_MODES 1 |
||
888 | #define SRV_SET_MODE 2 |
||
889 | |||
890 | int _stdcall display_handler(ioctl_t *io) |
||
891 | { |
||
892 | int retval = -1; |
||
893 | u32_t *inp; |
||
894 | u32_t *outp; |
||
895 | |||
896 | inp = io->input; |
||
897 | outp = io->output; |
||
898 | |||
899 | switch(io->io_code) |
||
900 | { |
||
901 | case SRV_GETVERSION: |
||
902 | if(io->out_size==4) |
||
903 | { |
||
904 | *outp = API_VERSION; |
||
905 | retval = 0; |
||
906 | } |
||
907 | break; |
||
908 | |||
909 | case SRV_ENUM_MODES: |
||
910 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
911 | inp, io->inp_size, io->out_size ); |
||
912 | |||
1246 | serge | 913 | if( radeon_modeset && |
914 | (outp != NULL) && (io->out_size == 4) && |
||
1404 | serge | 915 | (io->inp_size == *outp * sizeof(videomode_t)) ) |
1268 | serge | 916 | { |
1404 | serge | 917 | retval = get_modes((videomode_t*)inp, outp); |
1239 | serge | 918 | }; |
919 | break; |
||
920 | |||
921 | case SRV_SET_MODE: |
||
1246 | serge | 922 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
923 | inp, io->inp_size); |
||
924 | |||
925 | if( radeon_modeset && |
||
926 | (inp != NULL) && |
||
1404 | serge | 927 | (io->inp_size == sizeof(videomode_t)) ) |
1239 | serge | 928 | { |
1404 | serge | 929 | retval = set_user_mode((videomode_t*)inp); |
1239 | serge | 930 | }; |
931 | break; |
||
932 | }; |
||
933 | |||
934 | return retval; |
||
935 | } |
||
936 | |||
1246 | serge | 937 | static char log[256]; |
1404 | serge | 938 | static pci_dev_t device; |
1246 | serge | 939 | |
1963 | serge | 940 | u32_t drvEntry(int action, char *cmdline) |
1239 | serge | 941 | { |
1428 | serge | 942 | struct radeon_device *rdev = NULL; |
943 | |||
1239 | serge | 944 | struct pci_device_id *ent; |
945 | |||
946 | int err; |
||
947 | u32_t retval = 0; |
||
948 | |||
949 | if(action != 1) |
||
950 | return 0; |
||
951 | |||
952 | if( GetService("DISPLAY") != 0 ) |
||
953 | return 0; |
||
954 | |||
955 | if( cmdline && *cmdline ) |
||
1268 | serge | 956 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 957 | |
958 | if(!dbg_open(log)) |
||
959 | { |
||
1963 | serge | 960 | strcpy(log, "/hd2/1/atikms.log"); |
1239 | serge | 961 | |
962 | if(!dbg_open(log)) |
||
963 | { |
||
964 | printf("Can't open %s\nExit\n", log); |
||
965 | return 0; |
||
966 | }; |
||
967 | } |
||
1963 | serge | 968 | dbgprintf("Radeon RC11 cmdline %s\n", cmdline); |
1239 | serge | 969 | |
970 | enum_pci_devices(); |
||
1963 | serge | 971 | |
1239 | serge | 972 | ent = find_pci_device(&device, pciidlist); |
973 | |||
974 | if( unlikely(ent == NULL) ) |
||
975 | { |
||
976 | dbgprintf("device not found\n"); |
||
977 | return 0; |
||
978 | }; |
||
979 | |||
980 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
981 | device.pci_dev.device); |
||
982 | |||
983 | err = drm_get_dev(&device.pci_dev, ent); |
||
984 | |||
1428 | serge | 985 | rdev = rdisplay->ddev->dev_private; |
986 | |||
1963 | serge | 987 | // if( (rdev->asic == &r600_asic) || |
988 | // (rdev->asic == &rv770_asic)) |
||
989 | // r600_2D_test(rdev); |
||
990 | // else if (rdev->asic != &evergreen_asic) |
||
991 | // r100_2D_test(rdev); |
||
1428 | serge | 992 | |
1246 | serge | 993 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 994 | |
1246 | serge | 995 | if( err != 0) |
996 | dbgprintf("Set DISPLAY handler\n"); |
||
997 | |||
998 | return err; |
||
1239 | serge | 999 | }; |
1430 | serge | 1000 | |
1001 | void drm_vblank_post_modeset(struct drm_device *dev, int crtc) |
||
1002 | {}; |
||
1003 | |||
1004 | void drm_vblank_pre_modeset(struct drm_device *dev, int crtc) |
||
1005 | {};>><>><>><>=>>>>>>> |
||
1006 |