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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "atom.h" |
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1428 | serge | 36 | #include "display.h" |
1117 | serge | 37 | |
1221 | serge | 38 | #include |
39 | |||
1117 | serge | 40 | |
1430 | serge | 41 | int radeon_no_wb; |
42 | int radeon_modeset = -1; |
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43 | int radeon_dynclks = -1; |
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44 | int radeon_r4xx_atom = 0; |
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45 | int radeon_agpmode = 0; |
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46 | int radeon_vram_limit = 0; |
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47 | int radeon_gart_size = 512; /* default gart size */ |
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48 | int radeon_benchmarking = 0; |
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49 | int radeon_testing = 0; |
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50 | int radeon_connector_table = 0; |
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51 | int radeon_tv = 1; |
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52 | int radeon_new_pll = -1; |
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53 | int radeon_dynpm = -1; |
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54 | int radeon_audio = 1; |
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1963 | serge | 55 | int radeon_hw_i2c = 0; |
56 | int radeon_pcie_gen2 = 0; |
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57 | int radeon_disp_priority = 0; |
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1117 | serge | 58 | |
1430 | serge | 59 | |
1963 | serge | 60 | |
1428 | serge | 61 | extern display_t *rdisplay; |
1246 | serge | 62 | |
1404 | serge | 63 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
64 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
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65 | int init_display_kms(struct radeon_device *rdev, videomode_t *mode); |
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1117 | serge | 66 | |
1404 | serge | 67 | int get_modes(videomode_t *mode, int *count); |
68 | int set_user_mode(videomode_t *mode); |
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1428 | serge | 69 | int r100_2D_test(struct radeon_device *rdev); |
1239 | serge | 70 | |
1404 | serge | 71 | |
1233 | serge | 72 | /* Legacy VGA regions */ |
73 | #define VGA_RSRC_NONE 0x00 |
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74 | #define VGA_RSRC_LEGACY_IO 0x01 |
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75 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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76 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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77 | /* Non-legacy access */ |
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78 | #define VGA_RSRC_NORMAL_IO 0x04 |
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79 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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80 | |||
81 | |||
1963 | serge | 82 | static const char radeon_family_name[][16] = { |
83 | "R100", |
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84 | "RV100", |
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85 | "RS100", |
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86 | "RV200", |
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87 | "RS200", |
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88 | "R200", |
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89 | "RV250", |
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90 | "RS300", |
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91 | "RV280", |
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92 | "R300", |
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93 | "R350", |
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94 | "RV350", |
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95 | "RV380", |
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96 | "R420", |
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97 | "R423", |
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98 | "RV410", |
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99 | "RS400", |
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100 | "RS480", |
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101 | "RS600", |
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102 | "RS690", |
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103 | "RS740", |
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104 | "RV515", |
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105 | "R520", |
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106 | "RV530", |
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107 | "RV560", |
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108 | "RV570", |
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109 | "R580", |
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110 | "R600", |
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111 | "RV610", |
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112 | "RV630", |
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113 | "RV670", |
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114 | "RV620", |
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115 | "RV635", |
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116 | "RS780", |
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117 | "RS880", |
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118 | "RV770", |
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119 | "RV730", |
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120 | "RV710", |
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121 | "RV740", |
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122 | "CEDAR", |
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123 | "REDWOOD", |
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124 | "JUNIPER", |
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125 | "CYPRESS", |
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126 | "HEMLOCK", |
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127 | "PALM", |
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128 | "BARTS", |
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129 | "TURKS", |
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130 | "CAICOS", |
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131 | "CAYMAN", |
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132 | "LAST", |
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133 | }; |
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1233 | serge | 134 | |
1117 | serge | 135 | /* |
136 | * Clear GPU surface registers. |
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137 | */ |
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1179 | serge | 138 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 139 | { |
140 | /* FIXME: check this out */ |
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141 | if (rdev->family < CHIP_R600) { |
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142 | int i; |
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143 | |||
1321 | serge | 144 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
1404 | serge | 145 | radeon_clear_surface_reg(rdev, i); |
1117 | serge | 146 | } |
1179 | serge | 147 | /* enable surfaces */ |
148 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 149 | } |
150 | } |
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151 | |||
152 | /* |
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153 | * GPU scratch registers helpers function. |
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154 | */ |
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1179 | serge | 155 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 156 | { |
157 | int i; |
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158 | |||
159 | /* FIXME: check this out */ |
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160 | if (rdev->family < CHIP_R300) { |
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161 | rdev->scratch.num_reg = 5; |
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162 | } else { |
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163 | rdev->scratch.num_reg = 7; |
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164 | } |
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1963 | serge | 165 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
1117 | serge | 166 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
167 | rdev->scratch.free[i] = true; |
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1963 | serge | 168 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1117 | serge | 169 | } |
170 | } |
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171 | |||
172 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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173 | { |
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174 | int i; |
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175 | |||
176 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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177 | if (rdev->scratch.free[i]) { |
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178 | rdev->scratch.free[i] = false; |
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179 | *reg = rdev->scratch.reg[i]; |
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180 | return 0; |
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181 | } |
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182 | } |
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183 | return -EINVAL; |
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184 | } |
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185 | |||
186 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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187 | { |
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188 | int i; |
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189 | |||
190 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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191 | if (rdev->scratch.reg[i] == reg) { |
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192 | rdev->scratch.free[i] = true; |
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193 | return; |
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194 | } |
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195 | } |
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196 | } |
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197 | |||
1430 | serge | 198 | /** |
199 | * radeon_vram_location - try to find VRAM location |
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200 | * @rdev: radeon device structure holding all necessary informations |
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201 | * @mc: memory controller structure holding memory informations |
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202 | * @base: base address at which to put VRAM |
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203 | * |
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204 | * Function will place try to place VRAM at base address provided |
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205 | * as parameter (which is so far either PCI aperture address or |
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206 | * for IGP TOM base address). |
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207 | * |
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208 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
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209 | * address space then we limit the VRAM size to the aperture. |
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210 | * |
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211 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
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212 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
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213 | * size and print a warning. |
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214 | * |
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215 | * This function will never fails, worst case are limiting VRAM. |
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216 | * |
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217 | * Note: GTT start, end, size should be initialized before calling this |
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218 | * function on AGP platform. |
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219 | * |
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1963 | serge | 220 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
1430 | serge | 221 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
222 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
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223 | * not IGP. |
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224 | * |
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225 | * Note: we use mc_vram_size as on some board we need to program the mc to |
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226 | * cover the whole aperture even if VRAM size is inferior to aperture size |
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227 | * Novell bug 204882 + along with lots of ubuntu ones |
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228 | * |
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229 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
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230 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
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231 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
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232 | * ones) |
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233 | * |
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234 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
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235 | * explicitly check for that thought. |
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236 | * |
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237 | * FIXME: when reducing VRAM size align new size on power of 2. |
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1117 | serge | 238 | */ |
1430 | serge | 239 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
1117 | serge | 240 | { |
1430 | serge | 241 | mc->vram_start = base; |
242 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
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243 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
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244 | mc->real_vram_size = mc->aper_size; |
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245 | mc->mc_vram_size = mc->aper_size; |
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246 | } |
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247 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 248 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
1430 | serge | 249 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
250 | mc->real_vram_size = mc->aper_size; |
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251 | mc->mc_vram_size = mc->aper_size; |
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252 | } |
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253 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 254 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
1430 | serge | 255 | mc->mc_vram_size >> 20, mc->vram_start, |
256 | mc->vram_end, mc->real_vram_size >> 20); |
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257 | } |
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1117 | serge | 258 | |
1430 | serge | 259 | /** |
260 | * radeon_gtt_location - try to find GTT location |
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261 | * @rdev: radeon device structure holding all necessary informations |
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262 | * @mc: memory controller structure holding memory informations |
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263 | * |
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264 | * Function will place try to place GTT before or after VRAM. |
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265 | * |
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266 | * If GTT size is bigger than space left then we ajust GTT size. |
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267 | * Thus function will never fails. |
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268 | * |
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269 | * FIXME: when reducing GTT size align new size on power of 2. |
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270 | */ |
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271 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
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272 | { |
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273 | u64 size_af, size_bf; |
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274 | |||
1963 | serge | 275 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
276 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
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1430 | serge | 277 | if (size_bf > size_af) { |
278 | if (mc->gtt_size > size_bf) { |
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279 | dev_warn(rdev->dev, "limiting GTT\n"); |
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280 | mc->gtt_size = size_bf; |
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1117 | serge | 281 | } |
1963 | serge | 282 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
1430 | serge | 283 | } else { |
284 | if (mc->gtt_size > size_af) { |
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285 | dev_warn(rdev->dev, "limiting GTT\n"); |
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286 | mc->gtt_size = size_af; |
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1117 | serge | 287 | } |
1963 | serge | 288 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
1117 | serge | 289 | } |
1430 | serge | 290 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
1963 | serge | 291 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
1430 | serge | 292 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
1117 | serge | 293 | } |
294 | |||
295 | /* |
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296 | * GPU helpers function. |
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297 | */ |
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1179 | serge | 298 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 299 | { |
300 | uint32_t reg; |
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301 | |||
302 | /* first check CRTCs */ |
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1963 | serge | 303 | if (ASIC_IS_DCE41(rdev)) { |
1430 | serge | 304 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
1963 | serge | 305 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
306 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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307 | return true; |
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308 | } else if (ASIC_IS_DCE4(rdev)) { |
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309 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
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1430 | serge | 310 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
311 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
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312 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
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313 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
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314 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
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315 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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316 | return true; |
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317 | } else if (ASIC_IS_AVIVO(rdev)) { |
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1117 | serge | 318 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
319 | RREG32(AVIVO_D2CRTC_CONTROL); |
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320 | if (reg & AVIVO_CRTC_EN) { |
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321 | return true; |
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322 | } |
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323 | } else { |
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324 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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325 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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326 | if (reg & RADEON_CRTC_EN) { |
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327 | return true; |
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328 | } |
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329 | } |
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330 | |||
331 | /* then check MEM_SIZE, in case the crtcs are off */ |
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332 | if (rdev->family >= CHIP_R600) |
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333 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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334 | else |
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335 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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336 | |||
337 | if (reg) |
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338 | return true; |
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339 | |||
340 | return false; |
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341 | |||
342 | } |
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343 | |||
1963 | serge | 344 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
345 | { |
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346 | fixed20_12 a; |
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347 | u32 sclk = rdev->pm.current_sclk; |
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348 | u32 mclk = rdev->pm.current_mclk; |
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349 | |||
350 | /* sclk/mclk in Mhz */ |
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351 | a.full = dfixed_const(100); |
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352 | rdev->pm.sclk.full = dfixed_const(sclk); |
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353 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
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354 | rdev->pm.mclk.full = dfixed_const(mclk); |
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355 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
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356 | |||
357 | if (rdev->flags & RADEON_IS_IGP) { |
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358 | a.full = dfixed_const(16); |
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359 | /* core_bandwidth = sclk(Mhz) * 16 */ |
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360 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
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361 | } |
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362 | } |
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363 | |||
1321 | serge | 364 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
365 | { |
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366 | if (radeon_card_posted(rdev)) |
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367 | return true; |
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368 | |||
369 | if (rdev->bios) { |
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370 | DRM_INFO("GPU not posted. posting now...\n"); |
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371 | if (rdev->is_atom_bios) |
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372 | atom_asic_init(rdev->mode_info.atom_context); |
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373 | else |
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374 | radeon_combios_asic_init(rdev->ddev); |
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375 | return true; |
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376 | } else { |
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377 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
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378 | return false; |
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379 | } |
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380 | } |
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381 | |||
1233 | serge | 382 | int radeon_dummy_page_init(struct radeon_device *rdev) |
383 | { |
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1430 | serge | 384 | if (rdev->dummy_page.page) |
385 | return 0; |
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1233 | serge | 386 | rdev->dummy_page.page = AllocPage(); |
387 | if (rdev->dummy_page.page == NULL) |
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388 | return -ENOMEM; |
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389 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
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390 | if (!rdev->dummy_page.addr) { |
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391 | // __free_page(rdev->dummy_page.page); |
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392 | rdev->dummy_page.page = NULL; |
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393 | return -ENOMEM; |
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394 | } |
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395 | return 0; |
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396 | } |
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1117 | serge | 397 | |
1233 | serge | 398 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
399 | { |
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400 | if (rdev->dummy_page.page == NULL) |
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401 | return; |
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402 | KernelFree(rdev->dummy_page.addr); |
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403 | rdev->dummy_page.page = NULL; |
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404 | } |
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405 | |||
406 | |||
1117 | serge | 407 | /* ATOM accessor methods */ |
408 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
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409 | { |
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410 | struct radeon_device *rdev = info->dev->dev_private; |
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411 | uint32_t r; |
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412 | |||
413 | r = rdev->pll_rreg(rdev, reg); |
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414 | return r; |
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415 | } |
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416 | |||
417 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
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418 | { |
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419 | struct radeon_device *rdev = info->dev->dev_private; |
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420 | |||
421 | rdev->pll_wreg(rdev, reg, val); |
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422 | } |
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423 | |||
424 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
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425 | { |
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426 | struct radeon_device *rdev = info->dev->dev_private; |
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427 | uint32_t r; |
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428 | |||
429 | r = rdev->mc_rreg(rdev, reg); |
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430 | return r; |
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431 | } |
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432 | |||
433 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
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434 | { |
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435 | struct radeon_device *rdev = info->dev->dev_private; |
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436 | |||
437 | rdev->mc_wreg(rdev, reg, val); |
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438 | } |
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439 | |||
440 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
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441 | { |
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442 | struct radeon_device *rdev = info->dev->dev_private; |
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443 | |||
444 | WREG32(reg*4, val); |
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445 | } |
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446 | |||
447 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
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448 | { |
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449 | struct radeon_device *rdev = info->dev->dev_private; |
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450 | uint32_t r; |
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451 | |||
452 | r = RREG32(reg*4); |
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453 | return r; |
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454 | } |
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455 | |||
1963 | serge | 456 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
457 | { |
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458 | struct radeon_device *rdev = info->dev->dev_private; |
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459 | |||
460 | WREG32_IO(reg*4, val); |
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461 | } |
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462 | |||
463 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
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464 | { |
||
465 | struct radeon_device *rdev = info->dev->dev_private; |
||
466 | uint32_t r; |
||
467 | |||
468 | r = RREG32_IO(reg*4); |
||
469 | return r; |
||
470 | } |
||
471 | |||
1117 | serge | 472 | int radeon_atombios_init(struct radeon_device *rdev) |
473 | { |
||
1268 | serge | 474 | struct card_info *atom_card_info = |
475 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 476 | |
1268 | serge | 477 | if (!atom_card_info) |
478 | return -ENOMEM; |
||
479 | |||
480 | rdev->mode_info.atom_card_info = atom_card_info; |
||
481 | atom_card_info->dev = rdev->ddev; |
||
482 | atom_card_info->reg_read = cail_reg_read; |
||
483 | atom_card_info->reg_write = cail_reg_write; |
||
1963 | serge | 484 | /* needed for iio ops */ |
485 | if (rdev->rio_mem) { |
||
486 | atom_card_info->ioreg_read = cail_ioreg_read; |
||
487 | atom_card_info->ioreg_write = cail_ioreg_write; |
||
488 | } else { |
||
489 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
||
490 | atom_card_info->ioreg_read = cail_reg_read; |
||
491 | atom_card_info->ioreg_write = cail_reg_write; |
||
492 | } |
||
1268 | serge | 493 | atom_card_info->mc_read = cail_mc_read; |
494 | atom_card_info->mc_write = cail_mc_write; |
||
495 | atom_card_info->pll_read = cail_pll_read; |
||
496 | atom_card_info->pll_write = cail_pll_write; |
||
497 | |||
498 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1630 | serge | 499 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1117 | serge | 500 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 501 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 502 | return 0; |
503 | } |
||
504 | |||
505 | void radeon_atombios_fini(struct radeon_device *rdev) |
||
506 | { |
||
1321 | serge | 507 | if (rdev->mode_info.atom_context) { |
508 | kfree(rdev->mode_info.atom_context->scratch); |
||
1119 | serge | 509 | kfree(rdev->mode_info.atom_context); |
1321 | serge | 510 | } |
1268 | serge | 511 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 512 | } |
513 | |||
514 | int radeon_combios_init(struct radeon_device *rdev) |
||
515 | { |
||
1128 | serge | 516 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 517 | return 0; |
518 | } |
||
519 | |||
520 | void radeon_combios_fini(struct radeon_device *rdev) |
||
521 | { |
||
522 | } |
||
523 | |||
1233 | serge | 524 | /* if we get transitioned to only one device, tak VGA back */ |
525 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
||
526 | { |
||
527 | struct radeon_device *rdev = cookie; |
||
528 | radeon_vga_set_state(rdev, state); |
||
529 | if (state) |
||
530 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
531 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
532 | else |
||
533 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
534 | } |
||
1117 | serge | 535 | |
1404 | serge | 536 | void radeon_check_arguments(struct radeon_device *rdev) |
537 | { |
||
538 | /* vramlimit must be a power of two */ |
||
539 | switch (radeon_vram_limit) { |
||
540 | case 0: |
||
541 | case 4: |
||
542 | case 8: |
||
543 | case 16: |
||
544 | case 32: |
||
545 | case 64: |
||
546 | case 128: |
||
547 | case 256: |
||
548 | case 512: |
||
549 | case 1024: |
||
550 | case 2048: |
||
551 | case 4096: |
||
552 | break; |
||
553 | default: |
||
554 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
||
555 | radeon_vram_limit); |
||
556 | radeon_vram_limit = 0; |
||
557 | break; |
||
558 | } |
||
559 | radeon_vram_limit = radeon_vram_limit << 20; |
||
560 | /* gtt size must be power of two and greater or equal to 32M */ |
||
561 | switch (radeon_gart_size) { |
||
562 | case 4: |
||
563 | case 8: |
||
564 | case 16: |
||
565 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
||
566 | radeon_gart_size); |
||
567 | radeon_gart_size = 512; |
||
568 | break; |
||
569 | case 32: |
||
570 | case 64: |
||
571 | case 128: |
||
572 | case 256: |
||
573 | case 512: |
||
574 | case 1024: |
||
575 | case 2048: |
||
576 | case 4096: |
||
577 | break; |
||
578 | default: |
||
579 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
||
580 | radeon_gart_size); |
||
581 | radeon_gart_size = 512; |
||
582 | break; |
||
583 | } |
||
584 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
585 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
||
586 | switch (radeon_agpmode) { |
||
587 | case -1: |
||
588 | case 0: |
||
589 | case 1: |
||
590 | case 2: |
||
591 | case 4: |
||
592 | case 8: |
||
593 | break; |
||
594 | default: |
||
595 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
||
596 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
||
597 | radeon_agpmode = 0; |
||
598 | break; |
||
599 | } |
||
600 | } |
||
601 | |||
1117 | serge | 602 | int radeon_device_init(struct radeon_device *rdev, |
603 | struct drm_device *ddev, |
||
604 | struct pci_dev *pdev, |
||
605 | uint32_t flags) |
||
606 | { |
||
1963 | serge | 607 | int r, i; |
1179 | serge | 608 | int dma_bits; |
1117 | serge | 609 | |
610 | rdev->shutdown = false; |
||
611 | rdev->ddev = ddev; |
||
612 | rdev->pdev = pdev; |
||
613 | rdev->flags = flags; |
||
614 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
615 | rdev->is_atom_bios = false; |
||
616 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
617 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
618 | rdev->gpu_lockup = false; |
||
1221 | serge | 619 | rdev->accel_working = false; |
1963 | serge | 620 | |
621 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", |
||
622 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); |
||
623 | |||
1117 | serge | 624 | /* mutex initialization are all done here so we |
625 | * can recall function without having locking issues */ |
||
1630 | serge | 626 | mutex_init(&rdev->cs_mutex); |
627 | mutex_init(&rdev->ib_pool.mutex); |
||
628 | mutex_init(&rdev->cp.mutex); |
||
629 | mutex_init(&rdev->dc_hw_i2c_mutex); |
||
1963 | serge | 630 | // if (rdev->family >= CHIP_R600) |
631 | // spin_lock_init(&rdev->ih.lock); |
||
1630 | serge | 632 | mutex_init(&rdev->gem.mutex); |
633 | mutex_init(&rdev->pm.mutex); |
||
1963 | serge | 634 | mutex_init(&rdev->vram_mutex); |
1117 | serge | 635 | // rwlock_init(&rdev->fence_drv.lock); |
1963 | serge | 636 | INIT_LIST_HEAD(&rdev->gem.objects); |
1117 | serge | 637 | |
1179 | serge | 638 | /* Set asic functions */ |
639 | r = radeon_asic_init(rdev); |
||
1404 | serge | 640 | if (r) |
1179 | serge | 641 | return r; |
1404 | serge | 642 | radeon_check_arguments(rdev); |
1179 | serge | 643 | |
1963 | serge | 644 | /* all of the newer IGP chips have an internal gart |
645 | * However some rs4xx report as AGP, so remove that here. |
||
646 | */ |
||
647 | if ((rdev->family >= CHIP_RS400) && |
||
648 | (rdev->flags & RADEON_IS_IGP)) { |
||
649 | rdev->flags &= ~RADEON_IS_AGP; |
||
650 | } |
||
651 | |||
1321 | serge | 652 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 653 | radeon_agp_disable(rdev); |
1117 | serge | 654 | } |
655 | |||
1179 | serge | 656 | /* set DMA mask + need_dma32 flags. |
657 | * PCIE - can handle 40-bits. |
||
658 | * IGP - can handle 40-bits (in theory) |
||
659 | * AGP - generally dma32 is safest |
||
660 | * PCI - only dma32 |
||
661 | */ |
||
662 | rdev->need_dma32 = false; |
||
663 | if (rdev->flags & RADEON_IS_AGP) |
||
664 | rdev->need_dma32 = true; |
||
665 | if (rdev->flags & RADEON_IS_PCI) |
||
666 | rdev->need_dma32 = true; |
||
1117 | serge | 667 | |
1179 | serge | 668 | dma_bits = rdev->need_dma32 ? 32 : 40; |
669 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 670 | if (r) { |
1119 | serge | 671 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
672 | } |
||
1117 | serge | 673 | |
674 | /* Registers mapping */ |
||
675 | /* TODO: block userspace mapping of io register */ |
||
676 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
677 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
678 | |||
679 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
680 | PG_SW+PG_NOCACHE); |
||
681 | |||
682 | if (rdev->rmmio == NULL) { |
||
683 | return -ENOMEM; |
||
684 | } |
||
685 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
686 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
687 | |||
1179 | serge | 688 | r = radeon_init(rdev); |
1221 | serge | 689 | if (r) |
1963 | serge | 690 | return r; |
1117 | serge | 691 | |
1221 | serge | 692 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
693 | /* Acceleration not working on AGP card try again |
||
694 | * with fallback to PCI or PCIE GART |
||
695 | */ |
||
1963 | serge | 696 | radeon_asic_reset(rdev); |
1221 | serge | 697 | radeon_fini(rdev); |
698 | radeon_agp_disable(rdev); |
||
699 | r = radeon_init(rdev); |
||
700 | if (r) |
||
1179 | serge | 701 | return r; |
1126 | serge | 702 | } |
1179 | serge | 703 | // if (radeon_testing) { |
704 | // radeon_test_moves(rdev); |
||
1125 | serge | 705 | // } |
1179 | serge | 706 | // if (radeon_benchmarking) { |
707 | // radeon_benchmark(rdev); |
||
708 | // } |
||
709 | return 0; |
||
1117 | serge | 710 | } |
711 | |||
1179 | serge | 712 | |
1117 | serge | 713 | /* |
714 | * Driver load/unload |
||
715 | */ |
||
716 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
717 | { |
||
718 | struct radeon_device *rdev; |
||
719 | int r; |
||
720 | |||
1182 | serge | 721 | ENTER(); |
1117 | serge | 722 | |
1120 | serge | 723 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 724 | if (rdev == NULL) { |
725 | return -ENOMEM; |
||
726 | }; |
||
727 | |||
728 | dev->dev_private = (void *)rdev; |
||
729 | |||
730 | /* update BUS flag */ |
||
1239 | serge | 731 | if (drm_device_is_agp(dev)) { |
1117 | serge | 732 | flags |= RADEON_IS_AGP; |
1239 | serge | 733 | } else if (drm_device_is_pcie(dev)) { |
734 | flags |= RADEON_IS_PCIE; |
||
735 | } else { |
||
736 | flags |= RADEON_IS_PCI; |
||
737 | } |
||
1117 | serge | 738 | |
1182 | serge | 739 | /* radeon_device_init should report only fatal error |
740 | * like memory allocation failure or iomapping failure, |
||
741 | * or memory manager initialization failure, it must |
||
742 | * properly initialize the GPU MC controller and permit |
||
743 | * VRAM allocation |
||
744 | */ |
||
1117 | serge | 745 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
746 | if (r) { |
||
1182 | serge | 747 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 748 | return r; |
749 | } |
||
1182 | serge | 750 | /* Again modeset_init should fail only on fatal error |
751 | * otherwise it should provide enough functionalities |
||
752 | * for shadowfb to run |
||
753 | */ |
||
1246 | serge | 754 | if( radeon_modeset ) |
755 | { |
||
1268 | serge | 756 | r = radeon_modeset_init(rdev); |
757 | if (r) { |
||
758 | return r; |
||
759 | } |
||
1246 | serge | 760 | }; |
1117 | serge | 761 | return 0; |
762 | } |
||
763 | |||
1404 | serge | 764 | videomode_t usermode; |
1230 | serge | 765 | |
1239 | serge | 766 | |
1117 | serge | 767 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
768 | { |
||
1246 | serge | 769 | static struct drm_device *dev; |
1117 | serge | 770 | int ret; |
771 | |||
1221 | serge | 772 | ENTER(); |
1117 | serge | 773 | |
1246 | serge | 774 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 775 | if (!dev) |
776 | return -ENOMEM; |
||
777 | |||
778 | // ret = pci_enable_device(pdev); |
||
779 | // if (ret) |
||
780 | // goto err_g1; |
||
781 | |||
782 | // pci_set_master(pdev); |
||
783 | |||
784 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
785 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
786 | // goto err_g2; |
||
787 | // } |
||
788 | |||
789 | dev->pdev = pdev; |
||
790 | dev->pci_device = pdev->device; |
||
791 | dev->pci_vendor = pdev->vendor; |
||
792 | |||
1630 | serge | 793 | INIT_LIST_HEAD(&dev->filelist); |
794 | INIT_LIST_HEAD(&dev->ctxlist); |
||
795 | INIT_LIST_HEAD(&dev->vmalist); |
||
796 | INIT_LIST_HEAD(&dev->maplist); |
||
797 | |||
798 | spin_lock_init(&dev->count_lock); |
||
799 | mutex_init(&dev->struct_mutex); |
||
800 | mutex_init(&dev->ctxlist_mutex); |
||
801 | |||
802 | |||
1221 | serge | 803 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
804 | if (ret) |
||
1117 | serge | 805 | goto err_g4; |
806 | |||
1963 | serge | 807 | // if( radeon_modeset ) |
808 | // init_display_kms(dev->dev_private, &usermode); |
||
809 | // else |
||
1268 | serge | 810 | init_display(dev->dev_private, &usermode); |
1126 | serge | 811 | |
1221 | serge | 812 | LEAVE(); |
813 | |||
1117 | serge | 814 | return 0; |
815 | |||
816 | err_g4: |
||
817 | // drm_put_minor(&dev->primary); |
||
818 | //err_g3: |
||
819 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
820 | // drm_put_minor(&dev->control); |
||
821 | //err_g2: |
||
822 | // pci_disable_device(pdev); |
||
823 | //err_g1: |
||
824 | free(dev); |
||
825 | |||
1221 | serge | 826 | LEAVE(); |
827 | |||
1117 | serge | 828 | return ret; |
829 | } |
||
830 | |||
831 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
832 | { |
||
833 | return pci_resource_start(dev->pdev, resource); |
||
834 | } |
||
835 | |||
836 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
837 | { |
||
838 | return pci_resource_len(dev->pdev, resource); |
||
839 | } |
||
840 | |||
1123 | serge | 841 | |
842 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
843 | { |
||
844 | uint64_t rem = *n; |
||
845 | uint64_t b = base; |
||
846 | uint64_t res, d = 1; |
||
847 | uint32_t high = rem >> 32; |
||
848 | |||
849 | /* Reduce the thing a bit first */ |
||
850 | res = 0; |
||
851 | if (high >= base) { |
||
852 | high /= base; |
||
853 | res = (uint64_t) high << 32; |
||
854 | rem -= (uint64_t) (high*base) << 32; |
||
855 | } |
||
856 | |||
857 | while ((int64_t)b > 0 && b < rem) { |
||
858 | b = b+b; |
||
859 | d = d+d; |
||
860 | } |
||
861 | |||
862 | do { |
||
863 | if (rem >= b) { |
||
864 | rem -= b; |
||
865 | res += d; |
||
866 | } |
||
867 | b >>= 1; |
||
868 | d >>= 1; |
||
869 | } while (d); |
||
870 | |||
871 | *n = res; |
||
872 | return rem; |
||
873 | } |
||
874 | |||
1239 | serge | 875 | |
876 | static struct pci_device_id pciidlist[] = { |
||
877 | radeon_PCI_IDS |
||
878 | }; |
||
879 | |||
880 | |||
881 | #define API_VERSION 0x01000100 |
||
882 | |||
883 | #define SRV_GETVERSION 0 |
||
884 | #define SRV_ENUM_MODES 1 |
||
885 | #define SRV_SET_MODE 2 |
||
886 | |||
887 | int _stdcall display_handler(ioctl_t *io) |
||
888 | { |
||
889 | int retval = -1; |
||
890 | u32_t *inp; |
||
891 | u32_t *outp; |
||
892 | |||
893 | inp = io->input; |
||
894 | outp = io->output; |
||
895 | |||
896 | switch(io->io_code) |
||
897 | { |
||
898 | case SRV_GETVERSION: |
||
899 | if(io->out_size==4) |
||
900 | { |
||
901 | *outp = API_VERSION; |
||
902 | retval = 0; |
||
903 | } |
||
904 | break; |
||
905 | |||
906 | case SRV_ENUM_MODES: |
||
907 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
908 | inp, io->inp_size, io->out_size ); |
||
909 | |||
1246 | serge | 910 | if( radeon_modeset && |
911 | (outp != NULL) && (io->out_size == 4) && |
||
1404 | serge | 912 | (io->inp_size == *outp * sizeof(videomode_t)) ) |
1268 | serge | 913 | { |
1404 | serge | 914 | retval = get_modes((videomode_t*)inp, outp); |
1239 | serge | 915 | }; |
916 | break; |
||
917 | |||
918 | case SRV_SET_MODE: |
||
1246 | serge | 919 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
920 | inp, io->inp_size); |
||
921 | |||
922 | if( radeon_modeset && |
||
923 | (inp != NULL) && |
||
1404 | serge | 924 | (io->inp_size == sizeof(videomode_t)) ) |
1239 | serge | 925 | { |
1404 | serge | 926 | retval = set_user_mode((videomode_t*)inp); |
1239 | serge | 927 | }; |
928 | break; |
||
929 | }; |
||
930 | |||
931 | return retval; |
||
932 | } |
||
933 | |||
1246 | serge | 934 | static char log[256]; |
1404 | serge | 935 | static pci_dev_t device; |
1246 | serge | 936 | |
1963 | serge | 937 | u32_t drvEntry(int action, char *cmdline) |
1239 | serge | 938 | { |
1428 | serge | 939 | struct radeon_device *rdev = NULL; |
940 | |||
1239 | serge | 941 | struct pci_device_id *ent; |
942 | |||
943 | int err; |
||
944 | u32_t retval = 0; |
||
945 | |||
946 | if(action != 1) |
||
947 | return 0; |
||
948 | |||
949 | if( GetService("DISPLAY") != 0 ) |
||
950 | return 0; |
||
951 | |||
952 | if( cmdline && *cmdline ) |
||
1268 | serge | 953 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 954 | |
955 | if(!dbg_open(log)) |
||
956 | { |
||
1963 | serge | 957 | strcpy(log, "/hd2/1/atikms.log"); |
1239 | serge | 958 | |
959 | if(!dbg_open(log)) |
||
960 | { |
||
961 | printf("Can't open %s\nExit\n", log); |
||
962 | return 0; |
||
963 | }; |
||
964 | } |
||
1963 | serge | 965 | dbgprintf("Radeon RC11 cmdline %s\n", cmdline); |
1239 | serge | 966 | |
967 | enum_pci_devices(); |
||
1963 | serge | 968 | |
1239 | serge | 969 | ent = find_pci_device(&device, pciidlist); |
970 | |||
971 | if( unlikely(ent == NULL) ) |
||
972 | { |
||
973 | dbgprintf("device not found\n"); |
||
974 | return 0; |
||
975 | }; |
||
976 | |||
977 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
978 | device.pci_dev.device); |
||
979 | |||
980 | err = drm_get_dev(&device.pci_dev, ent); |
||
981 | |||
1428 | serge | 982 | rdev = rdisplay->ddev->dev_private; |
983 | |||
1963 | serge | 984 | // if( (rdev->asic == &r600_asic) || |
985 | // (rdev->asic == &rv770_asic)) |
||
986 | // r600_2D_test(rdev); |
||
987 | // else if (rdev->asic != &evergreen_asic) |
||
988 | // r100_2D_test(rdev); |
||
1428 | serge | 989 | |
1246 | serge | 990 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 991 | |
1246 | serge | 992 | if( err != 0) |
993 | dbgprintf("Set DISPLAY handler\n"); |
||
994 | |||
995 | return err; |
||
1239 | serge | 996 | }; |
1430 | serge | 997 | |
998 | void drm_vblank_post_modeset(struct drm_device *dev, int crtc) |
||
999 | {}; |
||
1000 | |||
1001 | void drm_vblank_pre_modeset(struct drm_device *dev, int crtc) |
||
1002 | {};>><>><>><>=>>>>>>> |
||
1003 |