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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "radeon_asic.h" |
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36 | #include "atom.h" |
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1428 | serge | 37 | #include "display.h" |
1117 | serge | 38 | |
1221 | serge | 39 | #include |
40 | |||
1117 | serge | 41 | |
1430 | serge | 42 | int radeon_no_wb; |
43 | int radeon_modeset = -1; |
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44 | int radeon_dynclks = -1; |
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45 | int radeon_r4xx_atom = 0; |
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46 | int radeon_agpmode = 0; |
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47 | int radeon_vram_limit = 0; |
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48 | int radeon_gart_size = 512; /* default gart size */ |
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49 | int radeon_benchmarking = 0; |
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50 | int radeon_testing = 0; |
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51 | int radeon_connector_table = 0; |
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52 | int radeon_tv = 1; |
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53 | int radeon_new_pll = -1; |
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54 | int radeon_dynpm = -1; |
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55 | int radeon_audio = 1; |
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1117 | serge | 56 | |
1430 | serge | 57 | |
1428 | serge | 58 | extern display_t *rdisplay; |
1246 | serge | 59 | |
1404 | serge | 60 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
61 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
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62 | int init_display_kms(struct radeon_device *rdev, videomode_t *mode); |
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1117 | serge | 63 | |
1404 | serge | 64 | int get_modes(videomode_t *mode, int *count); |
65 | int set_user_mode(videomode_t *mode); |
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1428 | serge | 66 | int r100_2D_test(struct radeon_device *rdev); |
1239 | serge | 67 | |
1404 | serge | 68 | |
1233 | serge | 69 | /* Legacy VGA regions */ |
70 | #define VGA_RSRC_NONE 0x00 |
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71 | #define VGA_RSRC_LEGACY_IO 0x01 |
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72 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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73 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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74 | /* Non-legacy access */ |
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75 | #define VGA_RSRC_NORMAL_IO 0x04 |
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76 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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77 | |||
78 | |||
79 | |||
1117 | serge | 80 | /* |
81 | * Clear GPU surface registers. |
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82 | */ |
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1179 | serge | 83 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 84 | { |
85 | /* FIXME: check this out */ |
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86 | if (rdev->family < CHIP_R600) { |
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87 | int i; |
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88 | |||
1321 | serge | 89 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
1404 | serge | 90 | radeon_clear_surface_reg(rdev, i); |
1117 | serge | 91 | } |
1179 | serge | 92 | /* enable surfaces */ |
93 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 94 | } |
95 | } |
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96 | |||
97 | /* |
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98 | * GPU scratch registers helpers function. |
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99 | */ |
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1179 | serge | 100 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 101 | { |
102 | int i; |
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103 | |||
104 | /* FIXME: check this out */ |
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105 | if (rdev->family < CHIP_R300) { |
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106 | rdev->scratch.num_reg = 5; |
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107 | } else { |
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108 | rdev->scratch.num_reg = 7; |
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109 | } |
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110 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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111 | rdev->scratch.free[i] = true; |
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112 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
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113 | } |
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114 | } |
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115 | |||
116 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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117 | { |
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118 | int i; |
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119 | |||
120 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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121 | if (rdev->scratch.free[i]) { |
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122 | rdev->scratch.free[i] = false; |
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123 | *reg = rdev->scratch.reg[i]; |
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124 | return 0; |
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125 | } |
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126 | } |
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127 | return -EINVAL; |
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128 | } |
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129 | |||
130 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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131 | { |
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132 | int i; |
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133 | |||
134 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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135 | if (rdev->scratch.reg[i] == reg) { |
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136 | rdev->scratch.free[i] = true; |
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137 | return; |
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138 | } |
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139 | } |
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140 | } |
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141 | |||
1430 | serge | 142 | /** |
143 | * radeon_vram_location - try to find VRAM location |
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144 | * @rdev: radeon device structure holding all necessary informations |
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145 | * @mc: memory controller structure holding memory informations |
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146 | * @base: base address at which to put VRAM |
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147 | * |
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148 | * Function will place try to place VRAM at base address provided |
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149 | * as parameter (which is so far either PCI aperture address or |
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150 | * for IGP TOM base address). |
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151 | * |
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152 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
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153 | * address space then we limit the VRAM size to the aperture. |
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154 | * |
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155 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
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156 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
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157 | * size and print a warning. |
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158 | * |
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159 | * This function will never fails, worst case are limiting VRAM. |
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160 | * |
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161 | * Note: GTT start, end, size should be initialized before calling this |
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162 | * function on AGP platform. |
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163 | * |
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164 | * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, |
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165 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
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166 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
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167 | * not IGP. |
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168 | * |
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169 | * Note: we use mc_vram_size as on some board we need to program the mc to |
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170 | * cover the whole aperture even if VRAM size is inferior to aperture size |
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171 | * Novell bug 204882 + along with lots of ubuntu ones |
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172 | * |
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173 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
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174 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
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175 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
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176 | * ones) |
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177 | * |
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178 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
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179 | * explicitly check for that thought. |
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180 | * |
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181 | * FIXME: when reducing VRAM size align new size on power of 2. |
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1117 | serge | 182 | */ |
1430 | serge | 183 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
1117 | serge | 184 | { |
1430 | serge | 185 | mc->vram_start = base; |
186 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
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187 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
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188 | mc->real_vram_size = mc->aper_size; |
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189 | mc->mc_vram_size = mc->aper_size; |
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190 | } |
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191 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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192 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { |
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193 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
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194 | mc->real_vram_size = mc->aper_size; |
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195 | mc->mc_vram_size = mc->aper_size; |
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196 | } |
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197 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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198 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
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199 | mc->mc_vram_size >> 20, mc->vram_start, |
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200 | mc->vram_end, mc->real_vram_size >> 20); |
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201 | } |
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1117 | serge | 202 | |
1430 | serge | 203 | /** |
204 | * radeon_gtt_location - try to find GTT location |
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205 | * @rdev: radeon device structure holding all necessary informations |
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206 | * @mc: memory controller structure holding memory informations |
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207 | * |
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208 | * Function will place try to place GTT before or after VRAM. |
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209 | * |
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210 | * If GTT size is bigger than space left then we ajust GTT size. |
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211 | * Thus function will never fails. |
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212 | * |
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213 | * FIXME: when reducing GTT size align new size on power of 2. |
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214 | */ |
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215 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
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216 | { |
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217 | u64 size_af, size_bf; |
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218 | |||
219 | size_af = 0xFFFFFFFF - mc->vram_end; |
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220 | size_bf = mc->vram_start; |
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221 | if (size_bf > size_af) { |
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222 | if (mc->gtt_size > size_bf) { |
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223 | dev_warn(rdev->dev, "limiting GTT\n"); |
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224 | mc->gtt_size = size_bf; |
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1117 | serge | 225 | } |
1430 | serge | 226 | mc->gtt_start = mc->vram_start - mc->gtt_size; |
227 | } else { |
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228 | if (mc->gtt_size > size_af) { |
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229 | dev_warn(rdev->dev, "limiting GTT\n"); |
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230 | mc->gtt_size = size_af; |
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1117 | serge | 231 | } |
1430 | serge | 232 | mc->gtt_start = mc->vram_end + 1; |
1117 | serge | 233 | } |
1430 | serge | 234 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
235 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", |
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236 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
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1117 | serge | 237 | } |
238 | |||
239 | /* |
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240 | * GPU helpers function. |
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241 | */ |
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1179 | serge | 242 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 243 | { |
244 | uint32_t reg; |
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245 | |||
246 | /* first check CRTCs */ |
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1430 | serge | 247 | if (ASIC_IS_DCE4(rdev)) { |
248 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
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249 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
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250 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
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251 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
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252 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
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253 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
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254 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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255 | return true; |
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256 | } else if (ASIC_IS_AVIVO(rdev)) { |
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1117 | serge | 257 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
258 | RREG32(AVIVO_D2CRTC_CONTROL); |
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259 | if (reg & AVIVO_CRTC_EN) { |
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260 | return true; |
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261 | } |
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262 | } else { |
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263 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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264 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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265 | if (reg & RADEON_CRTC_EN) { |
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266 | return true; |
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267 | } |
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268 | } |
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269 | |||
270 | /* then check MEM_SIZE, in case the crtcs are off */ |
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271 | if (rdev->family >= CHIP_R600) |
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272 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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273 | else |
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274 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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275 | |||
276 | if (reg) |
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277 | return true; |
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278 | |||
279 | return false; |
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280 | |||
281 | } |
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282 | |||
1321 | serge | 283 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
284 | { |
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285 | if (radeon_card_posted(rdev)) |
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286 | return true; |
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287 | |||
288 | if (rdev->bios) { |
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289 | DRM_INFO("GPU not posted. posting now...\n"); |
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290 | if (rdev->is_atom_bios) |
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291 | atom_asic_init(rdev->mode_info.atom_context); |
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292 | else |
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293 | radeon_combios_asic_init(rdev->ddev); |
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294 | return true; |
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295 | } else { |
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296 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
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297 | return false; |
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298 | } |
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299 | } |
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300 | |||
1233 | serge | 301 | int radeon_dummy_page_init(struct radeon_device *rdev) |
302 | { |
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1430 | serge | 303 | if (rdev->dummy_page.page) |
304 | return 0; |
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1233 | serge | 305 | rdev->dummy_page.page = AllocPage(); |
306 | if (rdev->dummy_page.page == NULL) |
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307 | return -ENOMEM; |
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308 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
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309 | if (!rdev->dummy_page.addr) { |
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310 | // __free_page(rdev->dummy_page.page); |
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311 | rdev->dummy_page.page = NULL; |
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312 | return -ENOMEM; |
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313 | } |
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314 | return 0; |
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315 | } |
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1117 | serge | 316 | |
1233 | serge | 317 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
318 | { |
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319 | if (rdev->dummy_page.page == NULL) |
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320 | return; |
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321 | KernelFree(rdev->dummy_page.addr); |
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322 | rdev->dummy_page.page = NULL; |
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323 | } |
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324 | |||
325 | |||
1117 | serge | 326 | /* |
327 | * Registers accessors functions. |
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328 | */ |
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329 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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330 | { |
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331 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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332 | BUG_ON(1); |
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333 | return 0; |
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334 | } |
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335 | |||
336 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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337 | { |
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338 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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339 | reg, v); |
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340 | BUG_ON(1); |
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341 | } |
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342 | |||
343 | void radeon_register_accessor_init(struct radeon_device *rdev) |
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344 | { |
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345 | rdev->mc_rreg = &radeon_invalid_rreg; |
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346 | rdev->mc_wreg = &radeon_invalid_wreg; |
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347 | rdev->pll_rreg = &radeon_invalid_rreg; |
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348 | rdev->pll_wreg = &radeon_invalid_wreg; |
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349 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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350 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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351 | |||
352 | /* Don't change order as we are overridding accessor. */ |
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353 | if (rdev->family < CHIP_RV515) { |
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1179 | serge | 354 | rdev->pcie_reg_mask = 0xff; |
355 | } else { |
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356 | rdev->pcie_reg_mask = 0x7ff; |
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1117 | serge | 357 | } |
358 | /* FIXME: not sure here */ |
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359 | if (rdev->family <= CHIP_R580) { |
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1119 | serge | 360 | rdev->pll_rreg = &r100_pll_rreg; |
361 | rdev->pll_wreg = &r100_pll_wreg; |
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1117 | serge | 362 | } |
1179 | serge | 363 | if (rdev->family >= CHIP_R420) { |
364 | rdev->mc_rreg = &r420_mc_rreg; |
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365 | rdev->mc_wreg = &r420_mc_wreg; |
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366 | } |
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1117 | serge | 367 | if (rdev->family >= CHIP_RV515) { |
368 | rdev->mc_rreg = &rv515_mc_rreg; |
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369 | rdev->mc_wreg = &rv515_mc_wreg; |
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370 | } |
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371 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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1128 | serge | 372 | rdev->mc_rreg = &rs400_mc_rreg; |
373 | rdev->mc_wreg = &rs400_mc_wreg; |
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1117 | serge | 374 | } |
1221 | serge | 375 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
376 | rdev->mc_rreg = &rs690_mc_rreg; |
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377 | rdev->mc_wreg = &rs690_mc_wreg; |
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378 | } |
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379 | if (rdev->family == CHIP_RS600) { |
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380 | rdev->mc_rreg = &rs600_mc_rreg; |
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381 | rdev->mc_wreg = &rs600_mc_wreg; |
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382 | } |
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1430 | serge | 383 | if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { |
1233 | serge | 384 | rdev->pciep_rreg = &r600_pciep_rreg; |
385 | rdev->pciep_wreg = &r600_pciep_wreg; |
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386 | } |
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1117 | serge | 387 | } |
388 | |||
389 | |||
390 | /* |
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391 | * ASIC |
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392 | */ |
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393 | int radeon_asic_init(struct radeon_device *rdev) |
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394 | { |
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395 | radeon_register_accessor_init(rdev); |
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396 | switch (rdev->family) { |
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397 | case CHIP_R100: |
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398 | case CHIP_RV100: |
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399 | case CHIP_RS100: |
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400 | case CHIP_RV200: |
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401 | case CHIP_RS200: |
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1430 | serge | 402 | rdev->asic = &r100_asic; |
403 | break; |
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1117 | serge | 404 | case CHIP_R200: |
405 | case CHIP_RV250: |
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406 | case CHIP_RS300: |
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407 | case CHIP_RV280: |
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1430 | serge | 408 | rdev->asic = &r200_asic; |
1117 | serge | 409 | break; |
410 | case CHIP_R300: |
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411 | case CHIP_R350: |
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412 | case CHIP_RV350: |
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413 | case CHIP_RV380: |
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1430 | serge | 414 | if (rdev->flags & RADEON_IS_PCIE) |
415 | rdev->asic = &r300_asic_pcie; |
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416 | else |
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1128 | serge | 417 | rdev->asic = &r300_asic; |
1117 | serge | 418 | break; |
419 | case CHIP_R420: |
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420 | case CHIP_R423: |
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421 | case CHIP_RV410: |
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1128 | serge | 422 | rdev->asic = &r420_asic; |
1117 | serge | 423 | break; |
424 | case CHIP_RS400: |
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425 | case CHIP_RS480: |
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1128 | serge | 426 | rdev->asic = &rs400_asic; |
1117 | serge | 427 | break; |
428 | case CHIP_RS600: |
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1221 | serge | 429 | rdev->asic = &rs600_asic; |
1117 | serge | 430 | break; |
431 | case CHIP_RS690: |
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432 | case CHIP_RS740: |
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1221 | serge | 433 | rdev->asic = &rs690_asic; |
1117 | serge | 434 | break; |
435 | case CHIP_RV515: |
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1128 | serge | 436 | rdev->asic = &rv515_asic; |
1117 | serge | 437 | break; |
438 | case CHIP_R520: |
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439 | case CHIP_RV530: |
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440 | case CHIP_RV560: |
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441 | case CHIP_RV570: |
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442 | case CHIP_R580: |
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443 | rdev->asic = &r520_asic; |
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444 | break; |
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445 | case CHIP_R600: |
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446 | case CHIP_RV610: |
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447 | case CHIP_RV630: |
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448 | case CHIP_RV620: |
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449 | case CHIP_RV635: |
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450 | case CHIP_RV670: |
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451 | case CHIP_RS780: |
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1221 | serge | 452 | case CHIP_RS880: |
1233 | serge | 453 | rdev->asic = &r600_asic; |
1221 | serge | 454 | break; |
1117 | serge | 455 | case CHIP_RV770: |
456 | case CHIP_RV730: |
||
457 | case CHIP_RV710: |
||
1221 | serge | 458 | case CHIP_RV740: |
1233 | serge | 459 | rdev->asic = &rv770_asic; |
1221 | serge | 460 | break; |
1430 | serge | 461 | case CHIP_CEDAR: |
462 | case CHIP_REDWOOD: |
||
463 | case CHIP_JUNIPER: |
||
464 | case CHIP_CYPRESS: |
||
465 | case CHIP_HEMLOCK: |
||
466 | rdev->asic = &evergreen_asic; |
||
467 | break; |
||
1117 | serge | 468 | default: |
469 | /* FIXME: not supported yet */ |
||
470 | return -EINVAL; |
||
471 | } |
||
1404 | serge | 472 | |
473 | if (rdev->flags & RADEON_IS_IGP) { |
||
474 | rdev->asic->get_memory_clock = NULL; |
||
475 | rdev->asic->set_memory_clock = NULL; |
||
476 | } |
||
477 | |||
1117 | serge | 478 | return 0; |
479 | } |
||
480 | |||
481 | |||
482 | /* |
||
483 | * Wrapper around modesetting bits. |
||
484 | */ |
||
485 | int radeon_clocks_init(struct radeon_device *rdev) |
||
486 | { |
||
487 | int r; |
||
488 | |||
489 | r = radeon_static_clocks_init(rdev->ddev); |
||
490 | if (r) { |
||
491 | return r; |
||
492 | } |
||
493 | DRM_INFO("Clocks initialized !\n"); |
||
494 | return 0; |
||
495 | } |
||
496 | |||
497 | void radeon_clocks_fini(struct radeon_device *rdev) |
||
498 | { |
||
499 | } |
||
500 | |||
501 | /* ATOM accessor methods */ |
||
502 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
||
503 | { |
||
504 | struct radeon_device *rdev = info->dev->dev_private; |
||
505 | uint32_t r; |
||
506 | |||
507 | r = rdev->pll_rreg(rdev, reg); |
||
508 | return r; |
||
509 | } |
||
510 | |||
511 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
512 | { |
||
513 | struct radeon_device *rdev = info->dev->dev_private; |
||
514 | |||
515 | rdev->pll_wreg(rdev, reg, val); |
||
516 | } |
||
517 | |||
518 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
||
519 | { |
||
520 | struct radeon_device *rdev = info->dev->dev_private; |
||
521 | uint32_t r; |
||
522 | |||
523 | r = rdev->mc_rreg(rdev, reg); |
||
524 | return r; |
||
525 | } |
||
526 | |||
527 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
528 | { |
||
529 | struct radeon_device *rdev = info->dev->dev_private; |
||
530 | |||
531 | rdev->mc_wreg(rdev, reg, val); |
||
532 | } |
||
533 | |||
534 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
535 | { |
||
536 | struct radeon_device *rdev = info->dev->dev_private; |
||
537 | |||
538 | WREG32(reg*4, val); |
||
539 | } |
||
540 | |||
541 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
||
542 | { |
||
543 | struct radeon_device *rdev = info->dev->dev_private; |
||
544 | uint32_t r; |
||
545 | |||
546 | r = RREG32(reg*4); |
||
547 | return r; |
||
548 | } |
||
549 | |||
550 | int radeon_atombios_init(struct radeon_device *rdev) |
||
551 | { |
||
1268 | serge | 552 | struct card_info *atom_card_info = |
553 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 554 | |
1268 | serge | 555 | if (!atom_card_info) |
556 | return -ENOMEM; |
||
557 | |||
558 | rdev->mode_info.atom_card_info = atom_card_info; |
||
559 | atom_card_info->dev = rdev->ddev; |
||
560 | atom_card_info->reg_read = cail_reg_read; |
||
561 | atom_card_info->reg_write = cail_reg_write; |
||
562 | atom_card_info->mc_read = cail_mc_read; |
||
563 | atom_card_info->mc_write = cail_mc_write; |
||
564 | atom_card_info->pll_read = cail_pll_read; |
||
565 | atom_card_info->pll_write = cail_pll_write; |
||
566 | |||
567 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1630 | serge | 568 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1117 | serge | 569 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 570 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 571 | return 0; |
572 | } |
||
573 | |||
574 | void radeon_atombios_fini(struct radeon_device *rdev) |
||
575 | { |
||
1321 | serge | 576 | if (rdev->mode_info.atom_context) { |
577 | kfree(rdev->mode_info.atom_context->scratch); |
||
1119 | serge | 578 | kfree(rdev->mode_info.atom_context); |
1321 | serge | 579 | } |
1268 | serge | 580 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 581 | } |
582 | |||
583 | int radeon_combios_init(struct radeon_device *rdev) |
||
584 | { |
||
1128 | serge | 585 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 586 | return 0; |
587 | } |
||
588 | |||
589 | void radeon_combios_fini(struct radeon_device *rdev) |
||
590 | { |
||
591 | } |
||
592 | |||
1233 | serge | 593 | /* if we get transitioned to only one device, tak VGA back */ |
594 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
||
595 | { |
||
596 | struct radeon_device *rdev = cookie; |
||
597 | radeon_vga_set_state(rdev, state); |
||
598 | if (state) |
||
599 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
600 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
601 | else |
||
602 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
603 | } |
||
1117 | serge | 604 | |
1221 | serge | 605 | void radeon_agp_disable(struct radeon_device *rdev) |
606 | { |
||
607 | rdev->flags &= ~RADEON_IS_AGP; |
||
608 | if (rdev->family >= CHIP_R600) { |
||
609 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
610 | rdev->flags |= RADEON_IS_PCIE; |
||
611 | } else if (rdev->family >= CHIP_RV515 || |
||
612 | rdev->family == CHIP_RV380 || |
||
613 | rdev->family == CHIP_RV410 || |
||
614 | rdev->family == CHIP_R423) { |
||
615 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
616 | rdev->flags |= RADEON_IS_PCIE; |
||
617 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
||
618 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
||
619 | } else { |
||
620 | DRM_INFO("Forcing AGP to PCI mode\n"); |
||
621 | rdev->flags |= RADEON_IS_PCI; |
||
622 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
||
623 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
||
624 | } |
||
1404 | serge | 625 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
1221 | serge | 626 | } |
1179 | serge | 627 | |
1404 | serge | 628 | void radeon_check_arguments(struct radeon_device *rdev) |
629 | { |
||
630 | /* vramlimit must be a power of two */ |
||
631 | switch (radeon_vram_limit) { |
||
632 | case 0: |
||
633 | case 4: |
||
634 | case 8: |
||
635 | case 16: |
||
636 | case 32: |
||
637 | case 64: |
||
638 | case 128: |
||
639 | case 256: |
||
640 | case 512: |
||
641 | case 1024: |
||
642 | case 2048: |
||
643 | case 4096: |
||
644 | break; |
||
645 | default: |
||
646 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
||
647 | radeon_vram_limit); |
||
648 | radeon_vram_limit = 0; |
||
649 | break; |
||
650 | } |
||
651 | radeon_vram_limit = radeon_vram_limit << 20; |
||
652 | /* gtt size must be power of two and greater or equal to 32M */ |
||
653 | switch (radeon_gart_size) { |
||
654 | case 4: |
||
655 | case 8: |
||
656 | case 16: |
||
657 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
||
658 | radeon_gart_size); |
||
659 | radeon_gart_size = 512; |
||
660 | break; |
||
661 | case 32: |
||
662 | case 64: |
||
663 | case 128: |
||
664 | case 256: |
||
665 | case 512: |
||
666 | case 1024: |
||
667 | case 2048: |
||
668 | case 4096: |
||
669 | break; |
||
670 | default: |
||
671 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
||
672 | radeon_gart_size); |
||
673 | radeon_gart_size = 512; |
||
674 | break; |
||
675 | } |
||
676 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
677 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
||
678 | switch (radeon_agpmode) { |
||
679 | case -1: |
||
680 | case 0: |
||
681 | case 1: |
||
682 | case 2: |
||
683 | case 4: |
||
684 | case 8: |
||
685 | break; |
||
686 | default: |
||
687 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
||
688 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
||
689 | radeon_agpmode = 0; |
||
690 | break; |
||
691 | } |
||
692 | } |
||
693 | |||
1117 | serge | 694 | int radeon_device_init(struct radeon_device *rdev, |
695 | struct drm_device *ddev, |
||
696 | struct pci_dev *pdev, |
||
697 | uint32_t flags) |
||
698 | { |
||
1221 | serge | 699 | int r; |
1179 | serge | 700 | int dma_bits; |
1117 | serge | 701 | |
702 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
||
703 | rdev->shutdown = false; |
||
704 | rdev->ddev = ddev; |
||
705 | rdev->pdev = pdev; |
||
706 | rdev->flags = flags; |
||
707 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
708 | rdev->is_atom_bios = false; |
||
709 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
710 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
711 | rdev->gpu_lockup = false; |
||
1221 | serge | 712 | rdev->accel_working = false; |
1117 | serge | 713 | /* mutex initialization are all done here so we |
714 | * can recall function without having locking issues */ |
||
1630 | serge | 715 | mutex_init(&rdev->cs_mutex); |
716 | mutex_init(&rdev->ib_pool.mutex); |
||
717 | mutex_init(&rdev->cp.mutex); |
||
718 | mutex_init(&rdev->dc_hw_i2c_mutex); |
||
719 | mutex_init(&rdev->gem.mutex); |
||
720 | mutex_init(&rdev->pm.mutex); |
||
1117 | serge | 721 | // rwlock_init(&rdev->fence_drv.lock); |
722 | |||
1179 | serge | 723 | /* Set asic functions */ |
724 | r = radeon_asic_init(rdev); |
||
1404 | serge | 725 | if (r) |
1179 | serge | 726 | return r; |
1404 | serge | 727 | radeon_check_arguments(rdev); |
1179 | serge | 728 | |
1321 | serge | 729 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 730 | radeon_agp_disable(rdev); |
1117 | serge | 731 | } |
732 | |||
1179 | serge | 733 | /* set DMA mask + need_dma32 flags. |
734 | * PCIE - can handle 40-bits. |
||
735 | * IGP - can handle 40-bits (in theory) |
||
736 | * AGP - generally dma32 is safest |
||
737 | * PCI - only dma32 |
||
738 | */ |
||
739 | rdev->need_dma32 = false; |
||
740 | if (rdev->flags & RADEON_IS_AGP) |
||
741 | rdev->need_dma32 = true; |
||
742 | if (rdev->flags & RADEON_IS_PCI) |
||
743 | rdev->need_dma32 = true; |
||
1117 | serge | 744 | |
1179 | serge | 745 | dma_bits = rdev->need_dma32 ? 32 : 40; |
746 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 747 | if (r) { |
1119 | serge | 748 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
749 | } |
||
1117 | serge | 750 | |
751 | /* Registers mapping */ |
||
752 | /* TODO: block userspace mapping of io register */ |
||
753 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
754 | |||
755 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
756 | |||
757 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
758 | PG_SW+PG_NOCACHE); |
||
759 | |||
760 | if (rdev->rmmio == NULL) { |
||
761 | return -ENOMEM; |
||
762 | } |
||
763 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
764 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
765 | |||
1179 | serge | 766 | r = radeon_init(rdev); |
1221 | serge | 767 | if (r) |
1117 | serge | 768 | return r; |
769 | |||
1221 | serge | 770 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
771 | /* Acceleration not working on AGP card try again |
||
772 | * with fallback to PCI or PCIE GART |
||
773 | */ |
||
774 | radeon_gpu_reset(rdev); |
||
775 | radeon_fini(rdev); |
||
776 | radeon_agp_disable(rdev); |
||
777 | r = radeon_init(rdev); |
||
778 | if (r) |
||
1179 | serge | 779 | return r; |
1126 | serge | 780 | } |
1179 | serge | 781 | // if (radeon_testing) { |
782 | // radeon_test_moves(rdev); |
||
1125 | serge | 783 | // } |
1179 | serge | 784 | // if (radeon_benchmarking) { |
785 | // radeon_benchmark(rdev); |
||
786 | // } |
||
787 | return 0; |
||
1117 | serge | 788 | } |
789 | |||
1179 | serge | 790 | |
1117 | serge | 791 | /* |
792 | * Driver load/unload |
||
793 | */ |
||
794 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
795 | { |
||
796 | struct radeon_device *rdev; |
||
797 | int r; |
||
798 | |||
1182 | serge | 799 | ENTER(); |
1117 | serge | 800 | |
1120 | serge | 801 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 802 | if (rdev == NULL) { |
803 | return -ENOMEM; |
||
804 | }; |
||
805 | |||
806 | dev->dev_private = (void *)rdev; |
||
807 | |||
808 | /* update BUS flag */ |
||
1239 | serge | 809 | if (drm_device_is_agp(dev)) { |
1117 | serge | 810 | flags |= RADEON_IS_AGP; |
1239 | serge | 811 | } else if (drm_device_is_pcie(dev)) { |
812 | flags |= RADEON_IS_PCIE; |
||
813 | } else { |
||
814 | flags |= RADEON_IS_PCI; |
||
815 | } |
||
1117 | serge | 816 | |
1182 | serge | 817 | /* radeon_device_init should report only fatal error |
818 | * like memory allocation failure or iomapping failure, |
||
819 | * or memory manager initialization failure, it must |
||
820 | * properly initialize the GPU MC controller and permit |
||
821 | * VRAM allocation |
||
822 | */ |
||
1117 | serge | 823 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
824 | if (r) { |
||
1182 | serge | 825 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 826 | return r; |
827 | } |
||
1182 | serge | 828 | /* Again modeset_init should fail only on fatal error |
829 | * otherwise it should provide enough functionalities |
||
830 | * for shadowfb to run |
||
831 | */ |
||
1246 | serge | 832 | if( radeon_modeset ) |
833 | { |
||
1268 | serge | 834 | r = radeon_modeset_init(rdev); |
835 | if (r) { |
||
836 | return r; |
||
837 | } |
||
1246 | serge | 838 | }; |
1117 | serge | 839 | return 0; |
840 | } |
||
841 | |||
1404 | serge | 842 | videomode_t usermode; |
1230 | serge | 843 | |
1239 | serge | 844 | |
1117 | serge | 845 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
846 | { |
||
1246 | serge | 847 | static struct drm_device *dev; |
1117 | serge | 848 | int ret; |
849 | |||
1221 | serge | 850 | ENTER(); |
1117 | serge | 851 | |
1246 | serge | 852 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 853 | if (!dev) |
854 | return -ENOMEM; |
||
855 | |||
856 | // ret = pci_enable_device(pdev); |
||
857 | // if (ret) |
||
858 | // goto err_g1; |
||
859 | |||
860 | // pci_set_master(pdev); |
||
861 | |||
862 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
863 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
864 | // goto err_g2; |
||
865 | // } |
||
866 | |||
867 | dev->pdev = pdev; |
||
868 | dev->pci_device = pdev->device; |
||
869 | dev->pci_vendor = pdev->vendor; |
||
870 | |||
1630 | serge | 871 | INIT_LIST_HEAD(&dev->filelist); |
872 | INIT_LIST_HEAD(&dev->ctxlist); |
||
873 | INIT_LIST_HEAD(&dev->vmalist); |
||
874 | INIT_LIST_HEAD(&dev->maplist); |
||
875 | |||
876 | spin_lock_init(&dev->count_lock); |
||
877 | spin_lock_init(&dev->drw_lock); |
||
878 | mutex_init(&dev->struct_mutex); |
||
879 | mutex_init(&dev->ctxlist_mutex); |
||
880 | |||
881 | |||
1221 | serge | 882 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
883 | if (ret) |
||
1117 | serge | 884 | goto err_g4; |
885 | |||
1246 | serge | 886 | if( radeon_modeset ) |
887 | init_display_kms(dev->dev_private, &usermode); |
||
888 | else |
||
1268 | serge | 889 | init_display(dev->dev_private, &usermode); |
1126 | serge | 890 | |
1221 | serge | 891 | LEAVE(); |
892 | |||
1117 | serge | 893 | return 0; |
894 | |||
895 | err_g4: |
||
896 | // drm_put_minor(&dev->primary); |
||
897 | //err_g3: |
||
898 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
899 | // drm_put_minor(&dev->control); |
||
900 | //err_g2: |
||
901 | // pci_disable_device(pdev); |
||
902 | //err_g1: |
||
903 | free(dev); |
||
904 | |||
1221 | serge | 905 | LEAVE(); |
906 | |||
1117 | serge | 907 | return ret; |
908 | } |
||
909 | |||
910 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
911 | { |
||
912 | return pci_resource_start(dev->pdev, resource); |
||
913 | } |
||
914 | |||
915 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
916 | { |
||
917 | return pci_resource_len(dev->pdev, resource); |
||
918 | } |
||
919 | |||
1123 | serge | 920 | |
921 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
922 | { |
||
923 | uint64_t rem = *n; |
||
924 | uint64_t b = base; |
||
925 | uint64_t res, d = 1; |
||
926 | uint32_t high = rem >> 32; |
||
927 | |||
928 | /* Reduce the thing a bit first */ |
||
929 | res = 0; |
||
930 | if (high >= base) { |
||
931 | high /= base; |
||
932 | res = (uint64_t) high << 32; |
||
933 | rem -= (uint64_t) (high*base) << 32; |
||
934 | } |
||
935 | |||
936 | while ((int64_t)b > 0 && b < rem) { |
||
937 | b = b+b; |
||
938 | d = d+d; |
||
939 | } |
||
940 | |||
941 | do { |
||
942 | if (rem >= b) { |
||
943 | rem -= b; |
||
944 | res += d; |
||
945 | } |
||
946 | b >>= 1; |
||
947 | d >>= 1; |
||
948 | } while (d); |
||
949 | |||
950 | *n = res; |
||
951 | return rem; |
||
952 | } |
||
953 | |||
1239 | serge | 954 | |
955 | static struct pci_device_id pciidlist[] = { |
||
956 | radeon_PCI_IDS |
||
957 | }; |
||
958 | |||
959 | |||
960 | #define API_VERSION 0x01000100 |
||
961 | |||
962 | #define SRV_GETVERSION 0 |
||
963 | #define SRV_ENUM_MODES 1 |
||
964 | #define SRV_SET_MODE 2 |
||
965 | |||
966 | int _stdcall display_handler(ioctl_t *io) |
||
967 | { |
||
968 | int retval = -1; |
||
969 | u32_t *inp; |
||
970 | u32_t *outp; |
||
971 | |||
972 | inp = io->input; |
||
973 | outp = io->output; |
||
974 | |||
975 | switch(io->io_code) |
||
976 | { |
||
977 | case SRV_GETVERSION: |
||
978 | if(io->out_size==4) |
||
979 | { |
||
980 | *outp = API_VERSION; |
||
981 | retval = 0; |
||
982 | } |
||
983 | break; |
||
984 | |||
985 | case SRV_ENUM_MODES: |
||
986 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
987 | inp, io->inp_size, io->out_size ); |
||
988 | |||
1246 | serge | 989 | if( radeon_modeset && |
990 | (outp != NULL) && (io->out_size == 4) && |
||
1404 | serge | 991 | (io->inp_size == *outp * sizeof(videomode_t)) ) |
1268 | serge | 992 | { |
1404 | serge | 993 | retval = get_modes((videomode_t*)inp, outp); |
1239 | serge | 994 | }; |
995 | break; |
||
996 | |||
997 | case SRV_SET_MODE: |
||
1246 | serge | 998 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
999 | inp, io->inp_size); |
||
1000 | |||
1001 | if( radeon_modeset && |
||
1002 | (inp != NULL) && |
||
1404 | serge | 1003 | (io->inp_size == sizeof(videomode_t)) ) |
1239 | serge | 1004 | { |
1404 | serge | 1005 | retval = set_user_mode((videomode_t*)inp); |
1239 | serge | 1006 | }; |
1007 | break; |
||
1008 | }; |
||
1009 | |||
1010 | return retval; |
||
1011 | } |
||
1012 | |||
1246 | serge | 1013 | static char log[256]; |
1404 | serge | 1014 | static pci_dev_t device; |
1246 | serge | 1015 | |
1239 | serge | 1016 | u32_t drvEntry(int action, char *cmdline) |
1017 | { |
||
1428 | serge | 1018 | struct radeon_device *rdev = NULL; |
1019 | |||
1239 | serge | 1020 | struct pci_device_id *ent; |
1021 | |||
1022 | int err; |
||
1023 | u32_t retval = 0; |
||
1024 | |||
1025 | if(action != 1) |
||
1026 | return 0; |
||
1027 | |||
1028 | if( GetService("DISPLAY") != 0 ) |
||
1029 | return 0; |
||
1030 | |||
1031 | if( cmdline && *cmdline ) |
||
1268 | serge | 1032 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 1033 | |
1034 | if(!dbg_open(log)) |
||
1035 | { |
||
1036 | strcpy(log, "/rd/1/drivers/atikms.log"); |
||
1037 | |||
1038 | if(!dbg_open(log)) |
||
1039 | { |
||
1040 | printf("Can't open %s\nExit\n", log); |
||
1041 | return 0; |
||
1042 | }; |
||
1043 | } |
||
1430 | serge | 1044 | dbgprintf("Radeon RC10 cmdline %s\n", cmdline); |
1239 | serge | 1045 | |
1046 | enum_pci_devices(); |
||
1047 | ent = find_pci_device(&device, pciidlist); |
||
1048 | |||
1049 | if( unlikely(ent == NULL) ) |
||
1050 | { |
||
1051 | dbgprintf("device not found\n"); |
||
1052 | return 0; |
||
1053 | }; |
||
1054 | |||
1055 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
1056 | device.pci_dev.device); |
||
1057 | |||
1058 | err = drm_get_dev(&device.pci_dev, ent); |
||
1059 | |||
1428 | serge | 1060 | rdev = rdisplay->ddev->dev_private; |
1061 | |||
1062 | if( (rdev->asic == &r600_asic) || |
||
1063 | (rdev->asic == &rv770_asic)) |
||
1064 | r600_2D_test(rdev); |
||
1430 | serge | 1065 | else if (rdev->asic != &evergreen_asic) |
1428 | serge | 1066 | r100_2D_test(rdev); |
1067 | |||
1246 | serge | 1068 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 1069 | |
1246 | serge | 1070 | if( err != 0) |
1071 | dbgprintf("Set DISPLAY handler\n"); |
||
1072 | |||
1073 | return err; |
||
1239 | serge | 1074 | }; |
1430 | serge | 1075 | |
1076 | void drm_vblank_post_modeset(struct drm_device *dev, int crtc) |
||
1077 | {}; |
||
1078 | |||
1079 | void drm_vblank_pre_modeset(struct drm_device *dev, int crtc) |
||
1080 | {};>><>><>><>=>=>>=>>>>>>> |
||
1081 |