WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_device.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
1123	serge	29
1179	serge	30	#include
		31	#include
1221	serge	32	#include
1117	serge	33	#include "radeon_reg.h"
		34	#include "radeon.h"
		35	#include "radeon_asic.h"
		36	#include "atom.h"
1428	serge	37	#include "display.h"
1117	serge	38
1221	serge	39	#include
		40
1117	serge	41
1268	serge	42	int radeon_dynclks = -1;
		43	int radeon_r4xx_atom = 0;
		44	int radeon_agpmode = -1;
		45	int radeon_gart_size = 512; /* default gart size */
		46	int radeon_benchmarking = 0;
		47	int radeon_connector_table = 0;
		48	int radeon_tv = 0;
1246	serge	49	int radeon_modeset = 1;
1404	serge	50	int radeon_new_pll = 1;
		51	int radeon_vram_limit = 0;
		52	int radeon_audio = 0;
1117	serge	53
1428	serge	54	extern display_t *rdisplay;
1246	serge	55
1404	serge	56	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);
		57	int init_display(struct radeon_device rdev, videomode_t mode);
		58	int init_display_kms(struct radeon_device rdev, videomode_t mode);
1117	serge	59
1404	serge	60	int get_modes(videomode_t mode, int count);
		61	int set_user_mode(videomode_t *mode);
1428	serge	62	int r100_2D_test(struct radeon_device *rdev);
1239	serge	63
1404	serge	64
1233	serge	65	/* Legacy VGA regions */
		66	#define VGA_RSRC_NONE 0x00
		67	#define VGA_RSRC_LEGACY_IO 0x01
		68	#define VGA_RSRC_LEGACY_MEM 0x02
		69	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
		70	/* Non-legacy access */
		71	#define VGA_RSRC_NORMAL_IO 0x04
		72	#define VGA_RSRC_NORMAL_MEM 0x08
		73
		74
		75
1117	serge	76	/*
		77	* Clear GPU surface registers.
		78	*/
1179	serge	79	void radeon_surface_init(struct radeon_device *rdev)
1117	serge	80	{
		81	/* FIXME: check this out */
		82	if (rdev->family < CHIP_R600) {
		83	int i;
		84
1321	serge	85	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
1404	serge	86	radeon_clear_surface_reg(rdev, i);
1117	serge	87	}
1179	serge	88	/* enable surfaces */
		89	WREG32(RADEON_SURFACE_CNTL, 0);
1117	serge	90	}
		91	}
		92
		93	/*
		94	* GPU scratch registers helpers function.
		95	*/
1179	serge	96	void radeon_scratch_init(struct radeon_device *rdev)
1117	serge	97	{
		98	int i;
		99
		100	/* FIXME: check this out */
		101	if (rdev->family < CHIP_R300) {
		102	rdev->scratch.num_reg = 5;
		103	} else {
		104	rdev->scratch.num_reg = 7;
		105	}
		106	for (i = 0; i < rdev->scratch.num_reg; i++) {
		107	rdev->scratch.free[i] = true;
		108	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
		109	}
		110	}
		111
		112	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
		113	{
		114	int i;
		115
		116	for (i = 0; i < rdev->scratch.num_reg; i++) {
		117	if (rdev->scratch.free[i]) {
		118	rdev->scratch.free[i] = false;
		119	*reg = rdev->scratch.reg[i];
		120	return 0;
		121	}
		122	}
		123	return -EINVAL;
		124	}
		125
		126	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
		127	{
		128	int i;
		129
		130	for (i = 0; i < rdev->scratch.num_reg; i++) {
		131	if (rdev->scratch.reg[i] == reg) {
		132	rdev->scratch.free[i] = true;
		133	return;
		134	}
		135	}
		136	}
		137
		138	/*
		139	* MC common functions
		140	*/
		141	int radeon_mc_setup(struct radeon_device *rdev)
		142	{
		143	uint32_t tmp;
		144
		145	/* Some chips have an "issue" with the memory controller, the
		146	* location must be aligned to the size. We just align it down,
		147	* too bad if we walk over the top of system memory, we don't
		148	* use DMA without a remapped anyway.
		149	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
		150	*/
		151	/* FGLRX seems to setup like this, VRAM a 0, then GART.
		152	*/
1126	serge	153	/*
1117	serge	154	* Note: from R6xx the address space is 40bits but here we only
		155	* use 32bits (still have to see a card which would exhaust 4G
		156	* address space).
		157	*/
		158	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		159	/* vram location was already setup try to put gtt after
		160	* if it fits */
1179	serge	161	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
1117	serge	162	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		163	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
		164	rdev->mc.gtt_location = tmp;
		165	} else {
		166	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
		167	printk(KERN_ERR "[drm] GTT too big to fit "
		168	"before or after vram location.\n");
		169	return -EINVAL;
		170	}
		171	rdev->mc.gtt_location = 0;
		172	}
		173	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		174	/* gtt location was already setup try to put vram before
		175	* if it fits */
1179	serge	176	if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
1117	serge	177	rdev->mc.vram_location = 0;
		178	} else {
		179	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
1179	serge	180	tmp += (rdev->mc.mc_vram_size - 1);
		181	tmp &= ~(rdev->mc.mc_vram_size - 1);
		182	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
1117	serge	183	rdev->mc.vram_location = tmp;
		184	} else {
		185	printk(KERN_ERR "[drm] vram too big to fit "
		186	"before or after GTT location.\n");
		187	return -EINVAL;
		188	}
		189	}
		190	} else {
		191	rdev->mc.vram_location = 0;
1179	serge	192	tmp = rdev->mc.mc_vram_size;
		193	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		194	rdev->mc.gtt_location = tmp;
1117	serge	195	}
1179	serge	196	rdev->mc.vram_start = rdev->mc.vram_location;
		197	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
		198	rdev->mc.gtt_start = rdev->mc.gtt_location;
		199	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		200	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
1117	serge	201	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
1179	serge	202	(unsigned)rdev->mc.vram_location,
		203	(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
		204	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
1117	serge	205	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
1179	serge	206	(unsigned)rdev->mc.gtt_location,
		207	(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
1117	serge	208	return 0;
		209	}
		210
		211
		212	/*
		213	* GPU helpers function.
		214	*/
1179	serge	215	bool radeon_card_posted(struct radeon_device *rdev)
1117	serge	216	{
		217	uint32_t reg;
		218
		219	/* first check CRTCs */
		220	if (ASIC_IS_AVIVO(rdev)) {
		221	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
		222	RREG32(AVIVO_D2CRTC_CONTROL);
		223	if (reg & AVIVO_CRTC_EN) {
		224	return true;
		225	}
		226	} else {
		227	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
		228	RREG32(RADEON_CRTC2_GEN_CNTL);
		229	if (reg & RADEON_CRTC_EN) {
		230	return true;
		231	}
		232	}
		233
		234	/* then check MEM_SIZE, in case the crtcs are off */
		235	if (rdev->family >= CHIP_R600)
		236	reg = RREG32(R600_CONFIG_MEMSIZE);
		237	else
		238	reg = RREG32(RADEON_CONFIG_MEMSIZE);
		239
		240	if (reg)
		241	return true;
		242
		243	return false;
		244
		245	}
		246
1321	serge	247	bool radeon_boot_test_post_card(struct radeon_device *rdev)
		248	{
		249	if (radeon_card_posted(rdev))
		250	return true;
		251
		252	if (rdev->bios) {
		253	DRM_INFO("GPU not posted. posting now...\n");
		254	if (rdev->is_atom_bios)
		255	atom_asic_init(rdev->mode_info.atom_context);
		256	else
		257	radeon_combios_asic_init(rdev->ddev);
		258	return true;
		259	} else {
		260	dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		261	return false;
		262	}
		263	}
		264
1233	serge	265	int radeon_dummy_page_init(struct radeon_device *rdev)
		266	{
		267	rdev->dummy_page.page = AllocPage();
		268	if (rdev->dummy_page.page == NULL)
		269	return -ENOMEM;
		270	rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
		271	if (!rdev->dummy_page.addr) {
		272	// __free_page(rdev->dummy_page.page);
		273	rdev->dummy_page.page = NULL;
		274	return -ENOMEM;
		275	}
		276	return 0;
		277	}
1117	serge	278
1233	serge	279	void radeon_dummy_page_fini(struct radeon_device *rdev)
		280	{
		281	if (rdev->dummy_page.page == NULL)
		282	return;
		283	KernelFree(rdev->dummy_page.addr);
		284	rdev->dummy_page.page = NULL;
		285	}
		286
		287
1117	serge	288	/*
		289	* Registers accessors functions.
		290	*/
		291	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		292	{
		293	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		294	BUG_ON(1);
		295	return 0;
		296	}
		297
		298	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		299	{
		300	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		301	reg, v);
		302	BUG_ON(1);
		303	}
		304
		305	void radeon_register_accessor_init(struct radeon_device *rdev)
		306	{
		307	rdev->mc_rreg = &radeon_invalid_rreg;
		308	rdev->mc_wreg = &radeon_invalid_wreg;
		309	rdev->pll_rreg = &radeon_invalid_rreg;
		310	rdev->pll_wreg = &radeon_invalid_wreg;
		311	rdev->pciep_rreg = &radeon_invalid_rreg;
		312	rdev->pciep_wreg = &radeon_invalid_wreg;
		313
		314	/* Don't change order as we are overridding accessor. */
		315	if (rdev->family < CHIP_RV515) {
1179	serge	316	rdev->pcie_reg_mask = 0xff;
		317	} else {
		318	rdev->pcie_reg_mask = 0x7ff;
1117	serge	319	}
		320	/* FIXME: not sure here */
		321	if (rdev->family <= CHIP_R580) {
1119	serge	322	rdev->pll_rreg = &r100_pll_rreg;
		323	rdev->pll_wreg = &r100_pll_wreg;
1117	serge	324	}
1179	serge	325	if (rdev->family >= CHIP_R420) {
		326	rdev->mc_rreg = &r420_mc_rreg;
		327	rdev->mc_wreg = &r420_mc_wreg;
		328	}
1117	serge	329	if (rdev->family >= CHIP_RV515) {
		330	rdev->mc_rreg = &rv515_mc_rreg;
		331	rdev->mc_wreg = &rv515_mc_wreg;
		332	}
		333	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
1128	serge	334	rdev->mc_rreg = &rs400_mc_rreg;
		335	rdev->mc_wreg = &rs400_mc_wreg;
1117	serge	336	}
1221	serge	337	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		338	rdev->mc_rreg = &rs690_mc_rreg;
		339	rdev->mc_wreg = &rs690_mc_wreg;
		340	}
		341	if (rdev->family == CHIP_RS600) {
		342	rdev->mc_rreg = &rs600_mc_rreg;
		343	rdev->mc_wreg = &rs600_mc_wreg;
		344	}
1233	serge	345	if (rdev->family >= CHIP_R600) {
		346	rdev->pciep_rreg = &r600_pciep_rreg;
		347	rdev->pciep_wreg = &r600_pciep_wreg;
		348	}
1117	serge	349	}
		350
		351
		352	/*
		353	* ASIC
		354	*/
		355	int radeon_asic_init(struct radeon_device *rdev)
		356	{
		357	radeon_register_accessor_init(rdev);
		358	switch (rdev->family) {
		359	case CHIP_R100:
		360	case CHIP_RV100:
		361	case CHIP_RS100:
		362	case CHIP_RV200:
		363	case CHIP_RS200:
		364	case CHIP_R200:
		365	case CHIP_RV250:
		366	case CHIP_RS300:
		367	case CHIP_RV280:
1128	serge	368	rdev->asic = &r100_asic;
1117	serge	369	break;
		370	case CHIP_R300:
		371	case CHIP_R350:
		372	case CHIP_RV350:
		373	case CHIP_RV380:
1128	serge	374	rdev->asic = &r300_asic;
1179	serge	375	if (rdev->flags & RADEON_IS_PCIE) {
		376	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		377	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		378	}
1117	serge	379	break;
		380	case CHIP_R420:
		381	case CHIP_R423:
		382	case CHIP_RV410:
1128	serge	383	rdev->asic = &r420_asic;
1117	serge	384	break;
		385	case CHIP_RS400:
		386	case CHIP_RS480:
1128	serge	387	rdev->asic = &rs400_asic;
1117	serge	388	break;
		389	case CHIP_RS600:
1221	serge	390	rdev->asic = &rs600_asic;
1117	serge	391	break;
		392	case CHIP_RS690:
		393	case CHIP_RS740:
1221	serge	394	rdev->asic = &rs690_asic;
1117	serge	395	break;
		396	case CHIP_RV515:
1128	serge	397	rdev->asic = &rv515_asic;
1117	serge	398	break;
		399	case CHIP_R520:
		400	case CHIP_RV530:
		401	case CHIP_RV560:
		402	case CHIP_RV570:
		403	case CHIP_R580:
		404	rdev->asic = &r520_asic;
		405	break;
		406	case CHIP_R600:
		407	case CHIP_RV610:
		408	case CHIP_RV630:
		409	case CHIP_RV620:
		410	case CHIP_RV635:
		411	case CHIP_RV670:
		412	case CHIP_RS780:
1221	serge	413	case CHIP_RS880:
1233	serge	414	rdev->asic = &r600_asic;
1221	serge	415	break;
1117	serge	416	case CHIP_RV770:
		417	case CHIP_RV730:
		418	case CHIP_RV710:
1221	serge	419	case CHIP_RV740:
1233	serge	420	rdev->asic = &rv770_asic;
1221	serge	421	break;
1117	serge	422	default:
		423	/* FIXME: not supported yet */
		424	return -EINVAL;
		425	}
1404	serge	426
		427	if (rdev->flags & RADEON_IS_IGP) {
		428	rdev->asic->get_memory_clock = NULL;
		429	rdev->asic->set_memory_clock = NULL;
		430	}
		431
1117	serge	432	return 0;
		433	}
		434
		435
		436	/*
		437	* Wrapper around modesetting bits.
		438	*/
		439	int radeon_clocks_init(struct radeon_device *rdev)
		440	{
		441	int r;
		442
		443	r = radeon_static_clocks_init(rdev->ddev);
		444	if (r) {
		445	return r;
		446	}
		447	DRM_INFO("Clocks initialized !\n");
		448	return 0;
		449	}
		450
		451	void radeon_clocks_fini(struct radeon_device *rdev)
		452	{
		453	}
		454
		455	/* ATOM accessor methods */
		456	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
		457	{
		458	struct radeon_device *rdev = info->dev->dev_private;
		459	uint32_t r;
		460
		461	r = rdev->pll_rreg(rdev, reg);
		462	return r;
		463	}
		464
		465	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
		466	{
		467	struct radeon_device *rdev = info->dev->dev_private;
		468
		469	rdev->pll_wreg(rdev, reg, val);
		470	}
		471
		472	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
		473	{
		474	struct radeon_device *rdev = info->dev->dev_private;
		475	uint32_t r;
		476
		477	r = rdev->mc_rreg(rdev, reg);
		478	return r;
		479	}
		480
		481	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
		482	{
		483	struct radeon_device *rdev = info->dev->dev_private;
		484
		485	rdev->mc_wreg(rdev, reg, val);
		486	}
		487
		488	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
		489	{
		490	struct radeon_device *rdev = info->dev->dev_private;
		491
		492	WREG32(reg*4, val);
		493	}
		494
		495	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
		496	{
		497	struct radeon_device *rdev = info->dev->dev_private;
		498	uint32_t r;
		499
		500	r = RREG32(reg*4);
		501	return r;
		502	}
		503
		504	int radeon_atombios_init(struct radeon_device *rdev)
		505	{
1268	serge	506	struct card_info *atom_card_info =
		507	kzalloc(sizeof(struct card_info), GFP_KERNEL);
1117	serge	508
1268	serge	509	if (!atom_card_info)
		510	return -ENOMEM;
		511
		512	rdev->mode_info.atom_card_info = atom_card_info;
		513	atom_card_info->dev = rdev->ddev;
		514	atom_card_info->reg_read = cail_reg_read;
		515	atom_card_info->reg_write = cail_reg_write;
		516	atom_card_info->mc_read = cail_mc_read;
		517	atom_card_info->mc_write = cail_mc_write;
		518	atom_card_info->pll_read = cail_pll_read;
		519	atom_card_info->pll_write = cail_pll_write;
		520
		521	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1117	serge	522	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1321	serge	523	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1117	serge	524	return 0;
		525	}
		526
		527	void radeon_atombios_fini(struct radeon_device *rdev)
		528	{
1321	serge	529	if (rdev->mode_info.atom_context) {
		530	kfree(rdev->mode_info.atom_context->scratch);
1119	serge	531	kfree(rdev->mode_info.atom_context);
1321	serge	532	}
1268	serge	533	kfree(rdev->mode_info.atom_card_info);
1117	serge	534	}
		535
		536	int radeon_combios_init(struct radeon_device *rdev)
		537	{
1128	serge	538	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117	serge	539	return 0;
		540	}
		541
		542	void radeon_combios_fini(struct radeon_device *rdev)
		543	{
		544	}
		545
1233	serge	546	/* if we get transitioned to only one device, tak VGA back */
		547	static unsigned int radeon_vga_set_decode(void *cookie, bool state)
		548	{
		549	struct radeon_device *rdev = cookie;
		550	radeon_vga_set_state(rdev, state);
		551	if (state)
		552	return VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM \|
		553	VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		554	else
		555	return VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		556	}
1117	serge	557
1221	serge	558	void radeon_agp_disable(struct radeon_device *rdev)
		559	{
		560	rdev->flags &= ~RADEON_IS_AGP;
		561	if (rdev->family >= CHIP_R600) {
		562	DRM_INFO("Forcing AGP to PCIE mode\n");
		563	rdev->flags \|= RADEON_IS_PCIE;
		564	} else if (rdev->family >= CHIP_RV515 \|\|
		565	rdev->family == CHIP_RV380 \|\|
		566	rdev->family == CHIP_RV410 \|\|
		567	rdev->family == CHIP_R423) {
		568	DRM_INFO("Forcing AGP to PCIE mode\n");
		569	rdev->flags \|= RADEON_IS_PCIE;
		570	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		571	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		572	} else {
		573	DRM_INFO("Forcing AGP to PCI mode\n");
		574	rdev->flags \|= RADEON_IS_PCI;
		575	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		576	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		577	}
1404	serge	578	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1221	serge	579	}
1179	serge	580
1404	serge	581	void radeon_check_arguments(struct radeon_device *rdev)
		582	{
		583	/* vramlimit must be a power of two */
		584	switch (radeon_vram_limit) {
		585	case 0:
		586	case 4:
		587	case 8:
		588	case 16:
		589	case 32:
		590	case 64:
		591	case 128:
		592	case 256:
		593	case 512:
		594	case 1024:
		595	case 2048:
		596	case 4096:
		597	break;
		598	default:
		599	dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
		600	radeon_vram_limit);
		601	radeon_vram_limit = 0;
		602	break;
		603	}
		604	radeon_vram_limit = radeon_vram_limit << 20;
		605	/* gtt size must be power of two and greater or equal to 32M */
		606	switch (radeon_gart_size) {
		607	case 4:
		608	case 8:
		609	case 16:
		610	dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
		611	radeon_gart_size);
		612	radeon_gart_size = 512;
		613	break;
		614	case 32:
		615	case 64:
		616	case 128:
		617	case 256:
		618	case 512:
		619	case 1024:
		620	case 2048:
		621	case 4096:
		622	break;
		623	default:
		624	dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
		625	radeon_gart_size);
		626	radeon_gart_size = 512;
		627	break;
		628	}
		629	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		630	/* AGP mode can only be -1, 1, 2, 4, 8 */
		631	switch (radeon_agpmode) {
		632	case -1:
		633	case 0:
		634	case 1:
		635	case 2:
		636	case 4:
		637	case 8:
		638	break;
		639	default:
		640	dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
		641	"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		642	radeon_agpmode = 0;
		643	break;
		644	}
		645	}
		646
1117	serge	647	int radeon_device_init(struct radeon_device *rdev,
		648	struct drm_device *ddev,
		649	struct pci_dev *pdev,
		650	uint32_t flags)
		651	{
1221	serge	652	int r;
1179	serge	653	int dma_bits;
1117	serge	654
		655	DRM_INFO("radeon: Initializing kernel modesetting.\n");
		656	rdev->shutdown = false;
		657	rdev->ddev = ddev;
		658	rdev->pdev = pdev;
		659	rdev->flags = flags;
		660	rdev->family = flags & RADEON_FAMILY_MASK;
		661	rdev->is_atom_bios = false;
		662	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
		663	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		664	rdev->gpu_lockup = false;
1221	serge	665	rdev->accel_working = false;
1117	serge	666	/* mutex initialization are all done here so we
		667	* can recall function without having locking issues */
		668	// mutex_init(&rdev->cs_mutex);
		669	// mutex_init(&rdev->ib_pool.mutex);
		670	// mutex_init(&rdev->cp.mutex);
		671	// rwlock_init(&rdev->fence_drv.lock);
		672
1179	serge	673	/* Set asic functions */
		674	r = radeon_asic_init(rdev);
1404	serge	675	if (r)
1179	serge	676	return r;
1404	serge	677	radeon_check_arguments(rdev);
1179	serge	678
1321	serge	679	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1221	serge	680	radeon_agp_disable(rdev);
1117	serge	681	}
		682
1179	serge	683	/* set DMA mask + need_dma32 flags.
		684	* PCIE - can handle 40-bits.
		685	* IGP - can handle 40-bits (in theory)
		686	* AGP - generally dma32 is safest
		687	* PCI - only dma32
		688	*/
		689	rdev->need_dma32 = false;
		690	if (rdev->flags & RADEON_IS_AGP)
		691	rdev->need_dma32 = true;
		692	if (rdev->flags & RADEON_IS_PCI)
		693	rdev->need_dma32 = true;
1117	serge	694
1179	serge	695	dma_bits = rdev->need_dma32 ? 32 : 40;
		696	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117	serge	697	if (r) {
1119	serge	698	printk(KERN_WARNING "radeon: No suitable DMA available.\n");
		699	}
1117	serge	700
		701	/* Registers mapping */
		702	/* TODO: block userspace mapping of io register */
		703	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
		704
		705	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
		706
		707	rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
		708	PG_SW+PG_NOCACHE);
		709
		710	if (rdev->rmmio == NULL) {
		711	return -ENOMEM;
		712	}
		713	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
		714	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
		715
1221	serge	716	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
		717	// r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
		718	// if (r) {
		719	// return -EINVAL;
		720	// }
		721
1179	serge	722	r = radeon_init(rdev);
1221	serge	723	if (r)
1117	serge	724	return r;
		725
1221	serge	726	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		727	/* Acceleration not working on AGP card try again
		728	* with fallback to PCI or PCIE GART
		729	*/
		730	radeon_gpu_reset(rdev);
		731	radeon_fini(rdev);
		732	radeon_agp_disable(rdev);
		733	r = radeon_init(rdev);
		734	if (r)
1179	serge	735	return r;
1126	serge	736	}
1179	serge	737	// if (radeon_testing) {
		738	// radeon_test_moves(rdev);
1125	serge	739	// }
1179	serge	740	// if (radeon_benchmarking) {
		741	// radeon_benchmark(rdev);
		742	// }
		743	return 0;
1117	serge	744	}
		745
1179	serge	746
1117	serge	747	/*
		748	* Driver load/unload
		749	*/
		750	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
		751	{
		752	struct radeon_device *rdev;
		753	int r;
		754
1182	serge	755	ENTER();
1117	serge	756
1120	serge	757	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117	serge	758	if (rdev == NULL) {
		759	return -ENOMEM;
		760	};
		761
		762	dev->dev_private = (void *)rdev;
		763
		764	/* update BUS flag */
1239	serge	765	if (drm_device_is_agp(dev)) {
1117	serge	766	flags \|= RADEON_IS_AGP;
1239	serge	767	} else if (drm_device_is_pcie(dev)) {
		768	flags \|= RADEON_IS_PCIE;
		769	} else {
		770	flags \|= RADEON_IS_PCI;
		771	}
1117	serge	772
1182	serge	773	/* radeon_device_init should report only fatal error
		774	* like memory allocation failure or iomapping failure,
		775	* or memory manager initialization failure, it must
		776	* properly initialize the GPU MC controller and permit
		777	* VRAM allocation
		778	*/
1117	serge	779	r = radeon_device_init(rdev, dev, dev->pdev, flags);
		780	if (r) {
1182	serge	781	DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117	serge	782	return r;
		783	}
1182	serge	784	/* Again modeset_init should fail only on fatal error
		785	* otherwise it should provide enough functionalities
		786	* for shadowfb to run
		787	*/
1246	serge	788	if( radeon_modeset )
		789	{
1268	serge	790	r = radeon_modeset_init(rdev);
		791	if (r) {
		792	return r;
		793	}
1246	serge	794	};
1117	serge	795	return 0;
		796	}
		797
1404	serge	798	videomode_t usermode;
1230	serge	799
1239	serge	800
1117	serge	801	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		802	{
1246	serge	803	static struct drm_device *dev;
1117	serge	804	int ret;
		805
1221	serge	806	ENTER();
1117	serge	807
1246	serge	808	dev = kzalloc(sizeof(*dev), 0);
1117	serge	809	if (!dev)
		810	return -ENOMEM;
		811
		812	// ret = pci_enable_device(pdev);
		813	// if (ret)
		814	// goto err_g1;
		815
		816	// pci_set_master(pdev);
		817
		818	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		819	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		820	// goto err_g2;
		821	// }
		822
		823	dev->pdev = pdev;
		824	dev->pci_device = pdev->device;
		825	dev->pci_vendor = pdev->vendor;
		826
1221	serge	827	ret = radeon_driver_load_kms(dev, ent->driver_data );
		828	if (ret)
1117	serge	829	goto err_g4;
		830
1246	serge	831	if( radeon_modeset )
		832	init_display_kms(dev->dev_private, &usermode);
		833	else
1268	serge	834	init_display(dev->dev_private, &usermode);
1126	serge	835
1221	serge	836	LEAVE();
		837
1117	serge	838	return 0;
		839
		840	err_g4:
		841	// drm_put_minor(&dev->primary);
		842	//err_g3:
		843	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		844	// drm_put_minor(&dev->control);
		845	//err_g2:
		846	// pci_disable_device(pdev);
		847	//err_g1:
		848	free(dev);
		849
1221	serge	850	LEAVE();
		851
1117	serge	852	return ret;
		853	}
		854
		855	resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
		856	{
		857	return pci_resource_start(dev->pdev, resource);
		858	}
		859
		860	resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
		861	{
		862	return pci_resource_len(dev->pdev, resource);
		863	}
		864
1123	serge	865
		866	uint32_t __div64_32(uint64_t *n, uint32_t base)
		867	{
		868	uint64_t rem = *n;
		869	uint64_t b = base;
		870	uint64_t res, d = 1;
		871	uint32_t high = rem >> 32;
		872
		873	/* Reduce the thing a bit first */
		874	res = 0;
		875	if (high >= base) {
		876	high /= base;
		877	res = (uint64_t) high << 32;
		878	rem -= (uint64_t) (high*base) << 32;
		879	}
		880
		881	while ((int64_t)b > 0 && b < rem) {
		882	b = b+b;
		883	d = d+d;
		884	}
		885
		886	do {
		887	if (rem >= b) {
		888	rem -= b;
		889	res += d;
		890	}
		891	b >>= 1;
		892	d >>= 1;
		893	} while (d);
		894
		895	*n = res;
		896	return rem;
		897	}
		898
1239	serge	899
		900	static struct pci_device_id pciidlist[] = {
		901	radeon_PCI_IDS
		902	};
		903
		904
		905	#define API_VERSION 0x01000100
		906
		907	#define SRV_GETVERSION 0
		908	#define SRV_ENUM_MODES 1
		909	#define SRV_SET_MODE 2
		910
		911	int _stdcall display_handler(ioctl_t *io)
		912	{
		913	int retval = -1;
		914	u32_t *inp;
		915	u32_t *outp;
		916
		917	inp = io->input;
		918	outp = io->output;
		919
		920	switch(io->io_code)
		921	{
		922	case SRV_GETVERSION:
		923	if(io->out_size==4)
		924	{
		925	*outp = API_VERSION;
		926	retval = 0;
		927	}
		928	break;
		929
		930	case SRV_ENUM_MODES:
		931	dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
		932	inp, io->inp_size, io->out_size );
		933
1246	serge	934	if( radeon_modeset &&
		935	(outp != NULL) && (io->out_size == 4) &&
1404	serge	936	(io->inp_size == outp sizeof(videomode_t)) )
1268	serge	937	{
1404	serge	938	retval = get_modes((videomode_t*)inp, outp);
1239	serge	939	};
		940	break;
		941
		942	case SRV_SET_MODE:
1246	serge	943	dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
		944	inp, io->inp_size);
		945
		946	if( radeon_modeset &&
		947	(inp != NULL) &&
1404	serge	948	(io->inp_size == sizeof(videomode_t)) )
1239	serge	949	{
1404	serge	950	retval = set_user_mode((videomode_t*)inp);
1239	serge	951	};
		952	break;
		953	};
		954
		955	return retval;
		956	}
		957
1246	serge	958	static char log[256];
1404	serge	959	static pci_dev_t device;
1246	serge	960
1239	serge	961	u32_t drvEntry(int action, char *cmdline)
		962	{
1428	serge	963	struct radeon_device *rdev = NULL;
		964
1239	serge	965	struct pci_device_id *ent;
		966
		967	int err;
		968	u32_t retval = 0;
		969
		970	if(action != 1)
		971	return 0;
		972
		973	if( GetService("DISPLAY") != 0 )
		974	return 0;
		975
		976	if( cmdline && *cmdline )
1268	serge	977	parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
1239	serge	978
		979	if(!dbg_open(log))
		980	{
		981	strcpy(log, "/rd/1/drivers/atikms.log");
		982
		983	if(!dbg_open(log))
		984	{
		985	printf("Can't open %s\nExit\n", log);
		986	return 0;
		987	};
		988	}
1404	serge	989	dbgprintf("Radeon RC9 cmdline %s\n", cmdline);
1239	serge	990
		991	enum_pci_devices();
		992
		993	ent = find_pci_device(&device, pciidlist);
		994
		995	if( unlikely(ent == NULL) )
		996	{
		997	dbgprintf("device not found\n");
		998	return 0;
		999	};
		1000
		1001	dbgprintf("device %x:%x\n", device.pci_dev.vendor,
		1002	device.pci_dev.device);
		1003
		1004	err = drm_get_dev(&device.pci_dev, ent);
		1005
1428	serge	1006	rdev = rdisplay->ddev->dev_private;
		1007
		1008	if( (rdev->asic == &r600_asic) \|\|
		1009	(rdev->asic == &rv770_asic))
		1010	r600_2D_test(rdev);
		1011	else
		1012	r100_2D_test(rdev);
		1013
1246	serge	1014	err = RegService("DISPLAY", display_handler);
1239	serge	1015
1246	serge	1016	if( err != 0)
		1017	dbgprintf("Set DISPLAY handler\n");
		1018
		1019	return err;
1239	serge	1020	};

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(root)/drivers/video/drm/radeon/radeon_device.c – Rev 1428