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1117 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
28
//#include 
1123 serge 29
 
1179 serge 30
#include 
31
#include 
1221 serge 32
#include 
1117 serge 33
#include "radeon_reg.h"
34
#include "radeon.h"
35
#include "radeon_asic.h"
36
#include "atom.h"
37
 
1221 serge 38
#include 
39
 
1117 serge 40
 
1268 serge 41
int radeon_dynclks          = -1;
42
int radeon_r4xx_atom        = 0;
43
int radeon_agpmode          = -1;
44
int radeon_gart_size        = 512; /* default gart size */
45
int radeon_benchmarking     = 0;
46
int radeon_connector_table  = 0;
47
int radeon_tv               = 0;
1246 serge 48
int radeon_modeset          = 1;
1404 serge 49
int radeon_new_pll          = 1;
50
int radeon_vram_limit       = 0;
51
int radeon_audio            = 0;
1117 serge 52
 
1246 serge 53
 
1404 serge 54
void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
55
int init_display(struct radeon_device *rdev, videomode_t *mode);
56
int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
1117 serge 57
 
1404 serge 58
int get_modes(videomode_t *mode, int *count);
59
int set_user_mode(videomode_t *mode);
1239 serge 60
 
1404 serge 61
 
1233 serge 62
 /* Legacy VGA regions */
63
#define VGA_RSRC_NONE          0x00
64
#define VGA_RSRC_LEGACY_IO     0x01
65
#define VGA_RSRC_LEGACY_MEM    0x02
66
#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
67
/* Non-legacy access */
68
#define VGA_RSRC_NORMAL_IO     0x04
69
#define VGA_RSRC_NORMAL_MEM    0x08
70
 
71
 
72
 
1117 serge 73
/*
74
 * Clear GPU surface registers.
75
 */
1179 serge 76
void radeon_surface_init(struct radeon_device *rdev)
1117 serge 77
{
78
    /* FIXME: check this out */
79
    if (rdev->family < CHIP_R600) {
80
        int i;
81
 
1321 serge 82
		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
1404 serge 83
           radeon_clear_surface_reg(rdev, i);
1117 serge 84
        }
1179 serge 85
		/* enable surfaces */
86
		WREG32(RADEON_SURFACE_CNTL, 0);
1117 serge 87
    }
88
}
89
 
90
/*
91
 * GPU scratch registers helpers function.
92
 */
1179 serge 93
void radeon_scratch_init(struct radeon_device *rdev)
1117 serge 94
{
95
    int i;
96
 
97
    /* FIXME: check this out */
98
    if (rdev->family < CHIP_R300) {
99
        rdev->scratch.num_reg = 5;
100
    } else {
101
        rdev->scratch.num_reg = 7;
102
    }
103
    for (i = 0; i < rdev->scratch.num_reg; i++) {
104
        rdev->scratch.free[i] = true;
105
        rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
106
    }
107
}
108
 
109
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
110
{
111
	int i;
112
 
113
	for (i = 0; i < rdev->scratch.num_reg; i++) {
114
		if (rdev->scratch.free[i]) {
115
			rdev->scratch.free[i] = false;
116
			*reg = rdev->scratch.reg[i];
117
			return 0;
118
		}
119
	}
120
	return -EINVAL;
121
}
122
 
123
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
124
{
125
	int i;
126
 
127
	for (i = 0; i < rdev->scratch.num_reg; i++) {
128
		if (rdev->scratch.reg[i] == reg) {
129
			rdev->scratch.free[i] = true;
130
			return;
131
		}
132
	}
133
}
134
 
135
/*
136
 * MC common functions
137
 */
138
int radeon_mc_setup(struct radeon_device *rdev)
139
{
140
	uint32_t tmp;
141
 
142
	/* Some chips have an "issue" with the memory controller, the
143
	 * location must be aligned to the size. We just align it down,
144
	 * too bad if we walk over the top of system memory, we don't
145
	 * use DMA without a remapped anyway.
146
	 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
147
	 */
148
	/* FGLRX seems to setup like this, VRAM a 0, then GART.
149
	 */
1126 serge 150
	/*
1117 serge 151
	 * Note: from R6xx the address space is 40bits but here we only
152
	 * use 32bits (still have to see a card which would exhaust 4G
153
	 * address space).
154
	 */
155
	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
156
		/* vram location was already setup try to put gtt after
157
		 * if it fits */
1179 serge 158
		tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
1117 serge 159
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
160
		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
161
			rdev->mc.gtt_location = tmp;
162
		} else {
163
			if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
164
				printk(KERN_ERR "[drm] GTT too big to fit "
165
				       "before or after vram location.\n");
166
				return -EINVAL;
167
			}
168
			rdev->mc.gtt_location = 0;
169
		}
170
	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
171
		/* gtt location was already setup try to put vram before
172
		 * if it fits */
1179 serge 173
		if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
1117 serge 174
			rdev->mc.vram_location = 0;
175
		} else {
176
			tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
1179 serge 177
			tmp += (rdev->mc.mc_vram_size - 1);
178
			tmp &= ~(rdev->mc.mc_vram_size - 1);
179
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
1117 serge 180
				rdev->mc.vram_location = tmp;
181
			} else {
182
				printk(KERN_ERR "[drm] vram too big to fit "
183
				       "before or after GTT location.\n");
184
				return -EINVAL;
185
			}
186
		}
187
	} else {
188
		rdev->mc.vram_location = 0;
1179 serge 189
		tmp = rdev->mc.mc_vram_size;
190
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
191
		rdev->mc.gtt_location = tmp;
1117 serge 192
	}
1179 serge 193
	rdev->mc.vram_start = rdev->mc.vram_location;
194
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
195
	rdev->mc.gtt_start = rdev->mc.gtt_location;
196
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
197
	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
1117 serge 198
	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
1179 serge 199
		 (unsigned)rdev->mc.vram_location,
200
		 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
201
	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
1117 serge 202
	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
1179 serge 203
		 (unsigned)rdev->mc.gtt_location,
204
		 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
1117 serge 205
	return 0;
206
}
207
 
208
 
209
/*
210
 * GPU helpers function.
211
 */
1179 serge 212
bool radeon_card_posted(struct radeon_device *rdev)
1117 serge 213
{
214
	uint32_t reg;
215
 
216
	/* first check CRTCs */
217
	if (ASIC_IS_AVIVO(rdev)) {
218
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
219
		      RREG32(AVIVO_D2CRTC_CONTROL);
220
		if (reg & AVIVO_CRTC_EN) {
221
			return true;
222
		}
223
	} else {
224
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
225
		      RREG32(RADEON_CRTC2_GEN_CNTL);
226
		if (reg & RADEON_CRTC_EN) {
227
			return true;
228
		}
229
	}
230
 
231
	/* then check MEM_SIZE, in case the crtcs are off */
232
	if (rdev->family >= CHIP_R600)
233
		reg = RREG32(R600_CONFIG_MEMSIZE);
234
	else
235
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
236
 
237
	if (reg)
238
		return true;
239
 
240
	return false;
241
 
242
}
243
 
1321 serge 244
bool radeon_boot_test_post_card(struct radeon_device *rdev)
245
{
246
	if (radeon_card_posted(rdev))
247
		return true;
248
 
249
	if (rdev->bios) {
250
		DRM_INFO("GPU not posted. posting now...\n");
251
		if (rdev->is_atom_bios)
252
			atom_asic_init(rdev->mode_info.atom_context);
253
		else
254
			radeon_combios_asic_init(rdev->ddev);
255
		return true;
256
	} else {
257
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
258
		return false;
259
	}
260
}
261
 
1233 serge 262
int radeon_dummy_page_init(struct radeon_device *rdev)
263
{
264
    rdev->dummy_page.page = AllocPage();
265
	if (rdev->dummy_page.page == NULL)
266
		return -ENOMEM;
267
    rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
268
	if (!rdev->dummy_page.addr) {
269
//       __free_page(rdev->dummy_page.page);
270
		rdev->dummy_page.page = NULL;
271
		return -ENOMEM;
272
	}
273
	return 0;
274
}
1117 serge 275
 
1233 serge 276
void radeon_dummy_page_fini(struct radeon_device *rdev)
277
{
278
	if (rdev->dummy_page.page == NULL)
279
		return;
280
    KernelFree(rdev->dummy_page.addr);
281
	rdev->dummy_page.page = NULL;
282
}
283
 
284
 
1117 serge 285
/*
286
 * Registers accessors functions.
287
 */
288
uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
289
{
290
    DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
291
    BUG_ON(1);
292
    return 0;
293
}
294
 
295
void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
296
{
297
    DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
298
          reg, v);
299
    BUG_ON(1);
300
}
301
 
302
void radeon_register_accessor_init(struct radeon_device *rdev)
303
{
304
    rdev->mc_rreg = &radeon_invalid_rreg;
305
    rdev->mc_wreg = &radeon_invalid_wreg;
306
    rdev->pll_rreg = &radeon_invalid_rreg;
307
    rdev->pll_wreg = &radeon_invalid_wreg;
308
    rdev->pciep_rreg = &radeon_invalid_rreg;
309
    rdev->pciep_wreg = &radeon_invalid_wreg;
310
 
311
    /* Don't change order as we are overridding accessor. */
312
    if (rdev->family < CHIP_RV515) {
1179 serge 313
		rdev->pcie_reg_mask = 0xff;
314
	} else {
315
		rdev->pcie_reg_mask = 0x7ff;
1117 serge 316
    }
317
    /* FIXME: not sure here */
318
    if (rdev->family <= CHIP_R580) {
1119 serge 319
        rdev->pll_rreg = &r100_pll_rreg;
320
        rdev->pll_wreg = &r100_pll_wreg;
1117 serge 321
    }
1179 serge 322
	if (rdev->family >= CHIP_R420) {
323
		rdev->mc_rreg = &r420_mc_rreg;
324
		rdev->mc_wreg = &r420_mc_wreg;
325
	}
1117 serge 326
    if (rdev->family >= CHIP_RV515) {
327
        rdev->mc_rreg = &rv515_mc_rreg;
328
        rdev->mc_wreg = &rv515_mc_wreg;
329
    }
330
    if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
1128 serge 331
        rdev->mc_rreg = &rs400_mc_rreg;
332
        rdev->mc_wreg = &rs400_mc_wreg;
1117 serge 333
    }
1221 serge 334
    if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
335
        rdev->mc_rreg = &rs690_mc_rreg;
336
        rdev->mc_wreg = &rs690_mc_wreg;
337
    }
338
    if (rdev->family == CHIP_RS600) {
339
        rdev->mc_rreg = &rs600_mc_rreg;
340
        rdev->mc_wreg = &rs600_mc_wreg;
341
    }
1233 serge 342
	if (rdev->family >= CHIP_R600) {
343
		rdev->pciep_rreg = &r600_pciep_rreg;
344
		rdev->pciep_wreg = &r600_pciep_wreg;
345
	}
1117 serge 346
}
347
 
348
 
349
/*
350
 * ASIC
351
 */
352
int radeon_asic_init(struct radeon_device *rdev)
353
{
354
    radeon_register_accessor_init(rdev);
355
	switch (rdev->family) {
356
	case CHIP_R100:
357
	case CHIP_RV100:
358
	case CHIP_RS100:
359
	case CHIP_RV200:
360
	case CHIP_RS200:
361
	case CHIP_R200:
362
	case CHIP_RV250:
363
	case CHIP_RS300:
364
	case CHIP_RV280:
1128 serge 365
        rdev->asic = &r100_asic;
1117 serge 366
		break;
367
	case CHIP_R300:
368
	case CHIP_R350:
369
	case CHIP_RV350:
370
	case CHIP_RV380:
1128 serge 371
        rdev->asic = &r300_asic;
1179 serge 372
		if (rdev->flags & RADEON_IS_PCIE) {
373
			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
374
			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
375
		}
1117 serge 376
		break;
377
	case CHIP_R420:
378
	case CHIP_R423:
379
	case CHIP_RV410:
1128 serge 380
        rdev->asic = &r420_asic;
1117 serge 381
		break;
382
	case CHIP_RS400:
383
	case CHIP_RS480:
1128 serge 384
       rdev->asic = &rs400_asic;
1117 serge 385
		break;
386
	case CHIP_RS600:
1221 serge 387
        rdev->asic = &rs600_asic;
1117 serge 388
		break;
389
	case CHIP_RS690:
390
	case CHIP_RS740:
1221 serge 391
        rdev->asic = &rs690_asic;
1117 serge 392
		break;
393
	case CHIP_RV515:
1128 serge 394
        rdev->asic = &rv515_asic;
1117 serge 395
		break;
396
	case CHIP_R520:
397
	case CHIP_RV530:
398
	case CHIP_RV560:
399
	case CHIP_RV570:
400
	case CHIP_R580:
401
        rdev->asic = &r520_asic;
402
		break;
403
	case CHIP_R600:
404
	case CHIP_RV610:
405
	case CHIP_RV630:
406
	case CHIP_RV620:
407
	case CHIP_RV635:
408
	case CHIP_RV670:
409
	case CHIP_RS780:
1221 serge 410
	case CHIP_RS880:
1233 serge 411
		rdev->asic = &r600_asic;
1221 serge 412
		break;
1117 serge 413
	case CHIP_RV770:
414
	case CHIP_RV730:
415
	case CHIP_RV710:
1221 serge 416
	case CHIP_RV740:
1233 serge 417
		rdev->asic = &rv770_asic;
1221 serge 418
		break;
1117 serge 419
	default:
420
		/* FIXME: not supported yet */
421
		return -EINVAL;
422
	}
1404 serge 423
 
424
	if (rdev->flags & RADEON_IS_IGP) {
425
		rdev->asic->get_memory_clock = NULL;
426
		rdev->asic->set_memory_clock = NULL;
427
	}
428
 
1117 serge 429
	return 0;
430
}
431
 
432
 
433
/*
434
 * Wrapper around modesetting bits.
435
 */
436
int radeon_clocks_init(struct radeon_device *rdev)
437
{
438
	int r;
439
 
440
    r = radeon_static_clocks_init(rdev->ddev);
441
	if (r) {
442
		return r;
443
	}
444
	DRM_INFO("Clocks initialized !\n");
445
	return 0;
446
}
447
 
448
void radeon_clocks_fini(struct radeon_device *rdev)
449
{
450
}
451
 
452
/* ATOM accessor methods */
453
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
454
{
455
    struct radeon_device *rdev = info->dev->dev_private;
456
    uint32_t r;
457
 
458
    r = rdev->pll_rreg(rdev, reg);
459
    return r;
460
}
461
 
462
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
463
{
464
    struct radeon_device *rdev = info->dev->dev_private;
465
 
466
    rdev->pll_wreg(rdev, reg, val);
467
}
468
 
469
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
470
{
471
    struct radeon_device *rdev = info->dev->dev_private;
472
    uint32_t r;
473
 
474
    r = rdev->mc_rreg(rdev, reg);
475
    return r;
476
}
477
 
478
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
479
{
480
    struct radeon_device *rdev = info->dev->dev_private;
481
 
482
    rdev->mc_wreg(rdev, reg, val);
483
}
484
 
485
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
486
{
487
    struct radeon_device *rdev = info->dev->dev_private;
488
 
489
    WREG32(reg*4, val);
490
}
491
 
492
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
493
{
494
    struct radeon_device *rdev = info->dev->dev_private;
495
    uint32_t r;
496
 
497
    r = RREG32(reg*4);
498
    return r;
499
}
500
 
501
int radeon_atombios_init(struct radeon_device *rdev)
502
{
1268 serge 503
	struct card_info *atom_card_info =
504
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
1117 serge 505
 
1268 serge 506
	if (!atom_card_info)
507
		return -ENOMEM;
508
 
509
	rdev->mode_info.atom_card_info = atom_card_info;
510
	atom_card_info->dev = rdev->ddev;
511
	atom_card_info->reg_read = cail_reg_read;
512
	atom_card_info->reg_write = cail_reg_write;
513
	atom_card_info->mc_read = cail_mc_read;
514
	atom_card_info->mc_write = cail_mc_write;
515
	atom_card_info->pll_read = cail_pll_read;
516
	atom_card_info->pll_write = cail_pll_write;
517
 
518
	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1117 serge 519
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1321 serge 520
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1117 serge 521
    return 0;
522
}
523
 
524
void radeon_atombios_fini(struct radeon_device *rdev)
525
{
1321 serge 526
	if (rdev->mode_info.atom_context) {
527
		kfree(rdev->mode_info.atom_context->scratch);
1119 serge 528
	kfree(rdev->mode_info.atom_context);
1321 serge 529
	}
1268 serge 530
	kfree(rdev->mode_info.atom_card_info);
1117 serge 531
}
532
 
533
int radeon_combios_init(struct radeon_device *rdev)
534
{
1128 serge 535
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117 serge 536
	return 0;
537
}
538
 
539
void radeon_combios_fini(struct radeon_device *rdev)
540
{
541
}
542
 
1233 serge 543
/* if we get transitioned to only one device, tak VGA back */
544
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
545
{
546
	struct radeon_device *rdev = cookie;
547
	radeon_vga_set_state(rdev, state);
548
	if (state)
549
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
550
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
551
	else
552
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
553
}
1117 serge 554
 
1221 serge 555
void radeon_agp_disable(struct radeon_device *rdev)
556
{
557
	rdev->flags &= ~RADEON_IS_AGP;
558
	if (rdev->family >= CHIP_R600) {
559
		DRM_INFO("Forcing AGP to PCIE mode\n");
560
		rdev->flags |= RADEON_IS_PCIE;
561
	} else if (rdev->family >= CHIP_RV515 ||
562
			rdev->family == CHIP_RV380 ||
563
			rdev->family == CHIP_RV410 ||
564
			rdev->family == CHIP_R423) {
565
		DRM_INFO("Forcing AGP to PCIE mode\n");
566
		rdev->flags |= RADEON_IS_PCIE;
567
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
568
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
569
	} else {
570
		DRM_INFO("Forcing AGP to PCI mode\n");
571
		rdev->flags |= RADEON_IS_PCI;
572
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
573
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
574
	}
1404 serge 575
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1221 serge 576
}
1179 serge 577
 
1404 serge 578
void radeon_check_arguments(struct radeon_device *rdev)
579
{
580
	/* vramlimit must be a power of two */
581
	switch (radeon_vram_limit) {
582
	case 0:
583
	case 4:
584
	case 8:
585
	case 16:
586
	case 32:
587
	case 64:
588
	case 128:
589
	case 256:
590
	case 512:
591
	case 1024:
592
	case 2048:
593
	case 4096:
594
		break;
595
	default:
596
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
597
				radeon_vram_limit);
598
		radeon_vram_limit = 0;
599
		break;
600
	}
601
	radeon_vram_limit = radeon_vram_limit << 20;
602
	/* gtt size must be power of two and greater or equal to 32M */
603
	switch (radeon_gart_size) {
604
	case 4:
605
	case 8:
606
	case 16:
607
		dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
608
				radeon_gart_size);
609
		radeon_gart_size = 512;
610
		break;
611
	case 32:
612
	case 64:
613
	case 128:
614
	case 256:
615
	case 512:
616
	case 1024:
617
	case 2048:
618
	case 4096:
619
		break;
620
	default:
621
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
622
				radeon_gart_size);
623
		radeon_gart_size = 512;
624
		break;
625
	}
626
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
627
	/* AGP mode can only be -1, 1, 2, 4, 8 */
628
	switch (radeon_agpmode) {
629
	case -1:
630
	case 0:
631
	case 1:
632
	case 2:
633
	case 4:
634
	case 8:
635
		break;
636
	default:
637
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
638
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
639
		radeon_agpmode = 0;
640
		break;
641
	}
642
}
643
 
1117 serge 644
int radeon_device_init(struct radeon_device *rdev,
645
               struct drm_device *ddev,
646
               struct pci_dev *pdev,
647
               uint32_t flags)
648
{
1221 serge 649
	int r;
1179 serge 650
	int dma_bits;
1117 serge 651
 
652
    DRM_INFO("radeon: Initializing kernel modesetting.\n");
653
    rdev->shutdown = false;
654
    rdev->ddev = ddev;
655
    rdev->pdev = pdev;
656
    rdev->flags = flags;
657
    rdev->family = flags & RADEON_FAMILY_MASK;
658
    rdev->is_atom_bios = false;
659
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
660
    rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
661
    rdev->gpu_lockup = false;
1221 serge 662
	rdev->accel_working = false;
1117 serge 663
    /* mutex initialization are all done here so we
664
     * can recall function without having locking issues */
665
 //   mutex_init(&rdev->cs_mutex);
666
 //   mutex_init(&rdev->ib_pool.mutex);
667
 //   mutex_init(&rdev->cp.mutex);
668
 //   rwlock_init(&rdev->fence_drv.lock);
669
 
1179 serge 670
	/* Set asic functions */
671
	r = radeon_asic_init(rdev);
1404 serge 672
	if (r)
1179 serge 673
		return r;
1404 serge 674
	radeon_check_arguments(rdev);
1179 serge 675
 
1321 serge 676
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1221 serge 677
		radeon_agp_disable(rdev);
1117 serge 678
    }
679
 
1179 serge 680
	/* set DMA mask + need_dma32 flags.
681
	 * PCIE - can handle 40-bits.
682
	 * IGP - can handle 40-bits (in theory)
683
	 * AGP - generally dma32 is safest
684
	 * PCI - only dma32
685
	 */
686
	rdev->need_dma32 = false;
687
	if (rdev->flags & RADEON_IS_AGP)
688
		rdev->need_dma32 = true;
689
	if (rdev->flags & RADEON_IS_PCI)
690
		rdev->need_dma32 = true;
1117 serge 691
 
1179 serge 692
	dma_bits = rdev->need_dma32 ? 32 : 40;
693
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117 serge 694
    if (r) {
1119 serge 695
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
696
    }
1117 serge 697
 
698
    /* Registers mapping */
699
    /* TODO: block userspace mapping of io register */
700
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
701
 
702
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
703
 
704
    rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
705
                                   PG_SW+PG_NOCACHE);
706
 
707
    if (rdev->rmmio == NULL) {
708
        return -ENOMEM;
709
    }
710
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
711
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
712
 
1221 serge 713
	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
714
//	r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
715
//	if (r) {
716
//		return -EINVAL;
717
//	}
718
 
1179 serge 719
	r = radeon_init(rdev);
1221 serge 720
	if (r)
1117 serge 721
            return r;
722
 
1221 serge 723
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
724
		/* Acceleration not working on AGP card try again
725
		 * with fallback to PCI or PCIE GART
726
		 */
727
		radeon_gpu_reset(rdev);
728
		radeon_fini(rdev);
729
		radeon_agp_disable(rdev);
730
		r = radeon_init(rdev);
731
		if (r)
1179 serge 732
		return r;
1126 serge 733
	}
1179 serge 734
//	if (radeon_testing) {
735
//		radeon_test_moves(rdev);
1125 serge 736
//    }
1179 serge 737
//	if (radeon_benchmarking) {
738
//		radeon_benchmark(rdev);
739
//    }
740
	return 0;
1117 serge 741
}
742
 
1179 serge 743
 
1117 serge 744
/*
745
 * Driver load/unload
746
 */
747
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
748
{
749
    struct radeon_device *rdev;
750
    int r;
751
 
1182 serge 752
    ENTER();
1117 serge 753
 
1120 serge 754
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117 serge 755
    if (rdev == NULL) {
756
        return -ENOMEM;
757
    };
758
 
759
    dev->dev_private = (void *)rdev;
760
 
761
    /* update BUS flag */
1239 serge 762
    if (drm_device_is_agp(dev)) {
1117 serge 763
        flags |= RADEON_IS_AGP;
1239 serge 764
    } else if (drm_device_is_pcie(dev)) {
765
        flags |= RADEON_IS_PCIE;
766
    } else {
767
        flags |= RADEON_IS_PCI;
768
    }
1117 serge 769
 
1182 serge 770
    /* radeon_device_init should report only fatal error
771
     * like memory allocation failure or iomapping failure,
772
     * or memory manager initialization failure, it must
773
     * properly initialize the GPU MC controller and permit
774
     * VRAM allocation
775
     */
1117 serge 776
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
777
    if (r) {
1182 serge 778
        DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117 serge 779
        return r;
780
    }
1182 serge 781
    /* Again modeset_init should fail only on fatal error
782
     * otherwise it should provide enough functionalities
783
     * for shadowfb to run
784
     */
1246 serge 785
    if( radeon_modeset )
786
    {
1268 serge 787
        r = radeon_modeset_init(rdev);
788
        if (r) {
789
            return r;
790
        }
1246 serge 791
    };
1117 serge 792
    return 0;
793
}
794
 
1404 serge 795
videomode_t usermode;
1230 serge 796
 
1239 serge 797
 
1117 serge 798
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
799
{
1246 serge 800
    static struct drm_device *dev;
1117 serge 801
    int ret;
802
 
1221 serge 803
    ENTER();
1117 serge 804
 
1246 serge 805
    dev = kzalloc(sizeof(*dev), 0);
1117 serge 806
    if (!dev)
807
        return -ENOMEM;
808
 
809
 //   ret = pci_enable_device(pdev);
810
 //   if (ret)
811
 //       goto err_g1;
812
 
813
 //   pci_set_master(pdev);
814
 
815
 //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
816
 //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
817
 //       goto err_g2;
818
 //   }
819
 
820
    dev->pdev = pdev;
821
    dev->pci_device = pdev->device;
822
    dev->pci_vendor = pdev->vendor;
823
 
1221 serge 824
    ret = radeon_driver_load_kms(dev, ent->driver_data );
825
    if (ret)
1117 serge 826
        goto err_g4;
827
 
828
 //   list_add_tail(&dev->driver_item, &driver->device_list);
829
 
830
 //   DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
831
 //        driver->name, driver->major, driver->minor, driver->patchlevel,
832
 //        driver->date, pci_name(pdev), dev->primary->index);
833
 
1246 serge 834
    if( radeon_modeset )
835
        init_display_kms(dev->dev_private, &usermode);
836
    else
1268 serge 837
        init_display(dev->dev_private, &usermode);
1126 serge 838
 
1221 serge 839
    LEAVE();
840
 
1117 serge 841
    return 0;
842
 
843
err_g4:
844
//    drm_put_minor(&dev->primary);
845
//err_g3:
846
//    if (drm_core_check_feature(dev, DRIVER_MODESET))
847
//        drm_put_minor(&dev->control);
848
//err_g2:
849
//    pci_disable_device(pdev);
850
//err_g1:
851
    free(dev);
852
 
1221 serge 853
    LEAVE();
854
 
1117 serge 855
    return ret;
856
}
857
 
858
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
859
{
860
    return pci_resource_start(dev->pdev, resource);
861
}
862
 
863
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
864
{
865
    return pci_resource_len(dev->pdev, resource);
866
}
867
 
1123 serge 868
 
869
uint32_t __div64_32(uint64_t *n, uint32_t base)
870
{
871
        uint64_t rem = *n;
872
        uint64_t b = base;
873
        uint64_t res, d = 1;
874
        uint32_t high = rem >> 32;
875
 
876
        /* Reduce the thing a bit first */
877
        res = 0;
878
        if (high >= base) {
879
                high /= base;
880
                res = (uint64_t) high << 32;
881
                rem -= (uint64_t) (high*base) << 32;
882
        }
883
 
884
        while ((int64_t)b > 0 && b < rem) {
885
                b = b+b;
886
                d = d+d;
887
        }
888
 
889
        do {
890
                if (rem >= b) {
891
                        rem -= b;
892
                        res += d;
893
                }
894
                b >>= 1;
895
                d >>= 1;
896
        } while (d);
897
 
898
        *n = res;
899
        return rem;
900
}
901
 
1239 serge 902
 
903
static struct pci_device_id pciidlist[] = {
904
    radeon_PCI_IDS
905
};
906
 
907
 
908
#define API_VERSION     0x01000100
909
 
910
#define SRV_GETVERSION  0
911
#define SRV_ENUM_MODES  1
912
#define SRV_SET_MODE    2
913
 
914
int _stdcall display_handler(ioctl_t *io)
915
{
916
    int    retval = -1;
917
    u32_t *inp;
918
    u32_t *outp;
919
 
920
    inp = io->input;
921
    outp = io->output;
922
 
923
    switch(io->io_code)
924
    {
925
        case SRV_GETVERSION:
926
            if(io->out_size==4)
927
            {
928
                *outp  = API_VERSION;
929
                retval = 0;
930
            }
931
            break;
932
 
933
        case SRV_ENUM_MODES:
934
            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
935
                       inp, io->inp_size, io->out_size );
936
 
1246 serge 937
            if( radeon_modeset &&
938
                (outp != NULL) && (io->out_size == 4) &&
1404 serge 939
                (io->inp_size == *outp * sizeof(videomode_t)) )
1268 serge 940
            {
1404 serge 941
                retval = get_modes((videomode_t*)inp, outp);
1239 serge 942
            };
943
            break;
944
 
945
        case SRV_SET_MODE:
1246 serge 946
            dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
947
                       inp, io->inp_size);
948
 
949
            if(  radeon_modeset   &&
950
                (inp != NULL) &&
1404 serge 951
                (io->inp_size == sizeof(videomode_t)) )
1239 serge 952
            {
1404 serge 953
                retval = set_user_mode((videomode_t*)inp);
1239 serge 954
            };
955
            break;
956
    };
957
 
958
    return retval;
959
}
960
 
1246 serge 961
static char  log[256];
1404 serge 962
static pci_dev_t device;
1246 serge 963
 
1239 serge 964
u32_t drvEntry(int action, char *cmdline)
965
{
966
    struct pci_device_id  *ent;
967
 
968
    int     err;
969
    u32_t   retval = 0;
970
 
971
    if(action != 1)
972
        return 0;
973
 
974
    if( GetService("DISPLAY") != 0 )
975
        return 0;
976
 
977
    if( cmdline && *cmdline )
1268 serge 978
        parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
1239 serge 979
 
980
    if(!dbg_open(log))
981
    {
982
        strcpy(log, "/rd/1/drivers/atikms.log");
983
 
984
        if(!dbg_open(log))
985
        {
986
            printf("Can't open %s\nExit\n", log);
987
            return 0;
988
        };
989
    }
1404 serge 990
    dbgprintf("Radeon RC9 cmdline %s\n", cmdline);
1239 serge 991
 
992
    enum_pci_devices();
993
 
994
    ent = find_pci_device(&device, pciidlist);
995
 
996
    if( unlikely(ent == NULL) )
997
    {
998
        dbgprintf("device not found\n");
999
        return 0;
1000
    };
1001
 
1002
    dbgprintf("device %x:%x\n", device.pci_dev.vendor,
1003
                                device.pci_dev.device);
1004
 
1005
    err = drm_get_dev(&device.pci_dev, ent);
1006
 
1246 serge 1007
    err = RegService("DISPLAY", display_handler);
1239 serge 1008
 
1246 serge 1009
    if( err != 0)
1010
        dbgprintf("Set DISPLAY handler\n");
1011
 
1012
    return err;
1239 serge 1013
};