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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "radeon_asic.h" |
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36 | #include "atom.h" |
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37 | |||
1221 | serge | 38 | #include |
39 | |||
1117 | serge | 40 | |
1268 | serge | 41 | int radeon_dynclks = -1; |
42 | int radeon_r4xx_atom = 0; |
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43 | int radeon_agpmode = -1; |
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44 | int radeon_gart_size = 512; /* default gart size */ |
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45 | int radeon_benchmarking = 0; |
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46 | int radeon_connector_table = 0; |
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47 | int radeon_tv = 0; |
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1246 | serge | 48 | int radeon_modeset = 1; |
1117 | serge | 49 | |
1268 | serge | 50 | void parse_cmdline(char *cmdline, mode_t *mode, char *log, int *kms); |
1233 | serge | 51 | int init_display(struct radeon_device *rdev, mode_t *mode); |
1246 | serge | 52 | int init_display_kms(struct radeon_device *rdev, mode_t *mode); |
53 | |||
1239 | serge | 54 | int get_modes(mode_t *mode, int *count); |
55 | int set_user_mode(mode_t *mode); |
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1117 | serge | 56 | |
1239 | serge | 57 | |
1233 | serge | 58 | /* Legacy VGA regions */ |
59 | #define VGA_RSRC_NONE 0x00 |
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60 | #define VGA_RSRC_LEGACY_IO 0x01 |
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61 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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62 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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63 | /* Non-legacy access */ |
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64 | #define VGA_RSRC_NORMAL_IO 0x04 |
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65 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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66 | |||
67 | |||
68 | |||
1117 | serge | 69 | /* |
70 | * Clear GPU surface registers. |
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71 | */ |
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1179 | serge | 72 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 73 | { |
1179 | serge | 74 | ENTER(); |
1117 | serge | 75 | |
76 | /* FIXME: check this out */ |
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77 | if (rdev->family < CHIP_R600) { |
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78 | int i; |
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79 | |||
1321 | serge | 80 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
81 | if (rdev->surface_regs[i].bo) |
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82 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
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83 | else |
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84 | radeon_clear_surface_reg(rdev, i); |
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1117 | serge | 85 | } |
1179 | serge | 86 | /* enable surfaces */ |
87 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 88 | } |
89 | } |
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90 | |||
91 | /* |
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92 | * GPU scratch registers helpers function. |
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93 | */ |
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1179 | serge | 94 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 95 | { |
96 | int i; |
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97 | |||
98 | /* FIXME: check this out */ |
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99 | if (rdev->family < CHIP_R300) { |
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100 | rdev->scratch.num_reg = 5; |
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101 | } else { |
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102 | rdev->scratch.num_reg = 7; |
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103 | } |
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104 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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105 | rdev->scratch.free[i] = true; |
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106 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
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107 | } |
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108 | } |
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109 | |||
110 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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111 | { |
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112 | int i; |
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113 | |||
114 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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115 | if (rdev->scratch.free[i]) { |
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116 | rdev->scratch.free[i] = false; |
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117 | *reg = rdev->scratch.reg[i]; |
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118 | return 0; |
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119 | } |
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120 | } |
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121 | return -EINVAL; |
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122 | } |
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123 | |||
124 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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125 | { |
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126 | int i; |
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127 | |||
128 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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129 | if (rdev->scratch.reg[i] == reg) { |
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130 | rdev->scratch.free[i] = true; |
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131 | return; |
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132 | } |
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133 | } |
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134 | } |
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135 | |||
136 | /* |
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137 | * MC common functions |
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138 | */ |
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139 | int radeon_mc_setup(struct radeon_device *rdev) |
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140 | { |
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141 | uint32_t tmp; |
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142 | |||
143 | /* Some chips have an "issue" with the memory controller, the |
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144 | * location must be aligned to the size. We just align it down, |
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145 | * too bad if we walk over the top of system memory, we don't |
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146 | * use DMA without a remapped anyway. |
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147 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
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148 | */ |
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149 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
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150 | */ |
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1126 | serge | 151 | /* |
1117 | serge | 152 | * Note: from R6xx the address space is 40bits but here we only |
153 | * use 32bits (still have to see a card which would exhaust 4G |
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154 | * address space). |
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155 | */ |
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156 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
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157 | /* vram location was already setup try to put gtt after |
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158 | * if it fits */ |
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1179 | serge | 159 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
1117 | serge | 160 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
161 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
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162 | rdev->mc.gtt_location = tmp; |
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163 | } else { |
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164 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
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165 | printk(KERN_ERR "[drm] GTT too big to fit " |
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166 | "before or after vram location.\n"); |
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167 | return -EINVAL; |
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168 | } |
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169 | rdev->mc.gtt_location = 0; |
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170 | } |
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171 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
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172 | /* gtt location was already setup try to put vram before |
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173 | * if it fits */ |
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1179 | serge | 174 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
1117 | serge | 175 | rdev->mc.vram_location = 0; |
176 | } else { |
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177 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
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1179 | serge | 178 | tmp += (rdev->mc.mc_vram_size - 1); |
179 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
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180 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
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1117 | serge | 181 | rdev->mc.vram_location = tmp; |
182 | } else { |
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183 | printk(KERN_ERR "[drm] vram too big to fit " |
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184 | "before or after GTT location.\n"); |
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185 | return -EINVAL; |
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186 | } |
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187 | } |
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188 | } else { |
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189 | rdev->mc.vram_location = 0; |
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1179 | serge | 190 | tmp = rdev->mc.mc_vram_size; |
191 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
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192 | rdev->mc.gtt_location = tmp; |
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1117 | serge | 193 | } |
1179 | serge | 194 | rdev->mc.vram_start = rdev->mc.vram_location; |
195 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
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196 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
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197 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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198 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
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1117 | serge | 199 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
1179 | serge | 200 | (unsigned)rdev->mc.vram_location, |
201 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); |
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202 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); |
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1117 | serge | 203 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
1179 | serge | 204 | (unsigned)rdev->mc.gtt_location, |
205 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); |
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1117 | serge | 206 | return 0; |
207 | } |
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208 | |||
209 | |||
210 | /* |
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211 | * GPU helpers function. |
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212 | */ |
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1179 | serge | 213 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 214 | { |
215 | uint32_t reg; |
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216 | |||
217 | /* first check CRTCs */ |
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218 | if (ASIC_IS_AVIVO(rdev)) { |
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219 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
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220 | RREG32(AVIVO_D2CRTC_CONTROL); |
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221 | if (reg & AVIVO_CRTC_EN) { |
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222 | return true; |
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223 | } |
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224 | } else { |
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225 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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226 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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227 | if (reg & RADEON_CRTC_EN) { |
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228 | return true; |
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229 | } |
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230 | } |
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231 | |||
232 | /* then check MEM_SIZE, in case the crtcs are off */ |
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233 | if (rdev->family >= CHIP_R600) |
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234 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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235 | else |
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236 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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237 | |||
238 | if (reg) |
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239 | return true; |
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240 | |||
241 | return false; |
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242 | |||
243 | } |
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244 | |||
1321 | serge | 245 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
246 | { |
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247 | if (radeon_card_posted(rdev)) |
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248 | return true; |
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249 | |||
250 | if (rdev->bios) { |
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251 | DRM_INFO("GPU not posted. posting now...\n"); |
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252 | if (rdev->is_atom_bios) |
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253 | atom_asic_init(rdev->mode_info.atom_context); |
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254 | else |
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255 | radeon_combios_asic_init(rdev->ddev); |
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256 | return true; |
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257 | } else { |
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258 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
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259 | return false; |
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260 | } |
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261 | } |
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262 | |||
1233 | serge | 263 | int radeon_dummy_page_init(struct radeon_device *rdev) |
264 | { |
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265 | rdev->dummy_page.page = AllocPage(); |
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266 | if (rdev->dummy_page.page == NULL) |
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267 | return -ENOMEM; |
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268 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
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269 | if (!rdev->dummy_page.addr) { |
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270 | // __free_page(rdev->dummy_page.page); |
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271 | rdev->dummy_page.page = NULL; |
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272 | return -ENOMEM; |
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273 | } |
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274 | return 0; |
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275 | } |
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1117 | serge | 276 | |
1233 | serge | 277 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
278 | { |
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279 | if (rdev->dummy_page.page == NULL) |
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280 | return; |
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281 | KernelFree(rdev->dummy_page.addr); |
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282 | rdev->dummy_page.page = NULL; |
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283 | } |
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284 | |||
285 | |||
1117 | serge | 286 | /* |
287 | * Registers accessors functions. |
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288 | */ |
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289 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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290 | { |
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291 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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292 | BUG_ON(1); |
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293 | return 0; |
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294 | } |
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295 | |||
296 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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297 | { |
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298 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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299 | reg, v); |
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300 | BUG_ON(1); |
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301 | } |
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302 | |||
303 | void radeon_register_accessor_init(struct radeon_device *rdev) |
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304 | { |
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305 | rdev->mc_rreg = &radeon_invalid_rreg; |
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306 | rdev->mc_wreg = &radeon_invalid_wreg; |
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307 | rdev->pll_rreg = &radeon_invalid_rreg; |
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308 | rdev->pll_wreg = &radeon_invalid_wreg; |
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309 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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310 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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311 | |||
312 | /* Don't change order as we are overridding accessor. */ |
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313 | if (rdev->family < CHIP_RV515) { |
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1179 | serge | 314 | rdev->pcie_reg_mask = 0xff; |
315 | } else { |
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316 | rdev->pcie_reg_mask = 0x7ff; |
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1117 | serge | 317 | } |
318 | /* FIXME: not sure here */ |
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319 | if (rdev->family <= CHIP_R580) { |
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1119 | serge | 320 | rdev->pll_rreg = &r100_pll_rreg; |
321 | rdev->pll_wreg = &r100_pll_wreg; |
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1117 | serge | 322 | } |
1179 | serge | 323 | if (rdev->family >= CHIP_R420) { |
324 | rdev->mc_rreg = &r420_mc_rreg; |
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325 | rdev->mc_wreg = &r420_mc_wreg; |
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326 | } |
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1117 | serge | 327 | if (rdev->family >= CHIP_RV515) { |
328 | rdev->mc_rreg = &rv515_mc_rreg; |
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329 | rdev->mc_wreg = &rv515_mc_wreg; |
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330 | } |
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331 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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1128 | serge | 332 | rdev->mc_rreg = &rs400_mc_rreg; |
333 | rdev->mc_wreg = &rs400_mc_wreg; |
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1117 | serge | 334 | } |
1221 | serge | 335 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
336 | rdev->mc_rreg = &rs690_mc_rreg; |
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337 | rdev->mc_wreg = &rs690_mc_wreg; |
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338 | } |
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339 | if (rdev->family == CHIP_RS600) { |
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340 | rdev->mc_rreg = &rs600_mc_rreg; |
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341 | rdev->mc_wreg = &rs600_mc_wreg; |
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342 | } |
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1233 | serge | 343 | if (rdev->family >= CHIP_R600) { |
344 | rdev->pciep_rreg = &r600_pciep_rreg; |
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345 | rdev->pciep_wreg = &r600_pciep_wreg; |
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346 | } |
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1117 | serge | 347 | } |
348 | |||
349 | |||
350 | /* |
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351 | * ASIC |
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352 | */ |
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353 | int radeon_asic_init(struct radeon_device *rdev) |
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354 | { |
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355 | radeon_register_accessor_init(rdev); |
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356 | switch (rdev->family) { |
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357 | case CHIP_R100: |
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358 | case CHIP_RV100: |
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359 | case CHIP_RS100: |
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360 | case CHIP_RV200: |
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361 | case CHIP_RS200: |
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362 | case CHIP_R200: |
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363 | case CHIP_RV250: |
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364 | case CHIP_RS300: |
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365 | case CHIP_RV280: |
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1128 | serge | 366 | rdev->asic = &r100_asic; |
1117 | serge | 367 | break; |
368 | case CHIP_R300: |
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369 | case CHIP_R350: |
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370 | case CHIP_RV350: |
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371 | case CHIP_RV380: |
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1128 | serge | 372 | rdev->asic = &r300_asic; |
1179 | serge | 373 | if (rdev->flags & RADEON_IS_PCIE) { |
374 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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375 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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376 | } |
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1117 | serge | 377 | break; |
378 | case CHIP_R420: |
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379 | case CHIP_R423: |
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380 | case CHIP_RV410: |
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1128 | serge | 381 | rdev->asic = &r420_asic; |
1117 | serge | 382 | break; |
383 | case CHIP_RS400: |
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384 | case CHIP_RS480: |
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1128 | serge | 385 | rdev->asic = &rs400_asic; |
1117 | serge | 386 | break; |
387 | case CHIP_RS600: |
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1221 | serge | 388 | rdev->asic = &rs600_asic; |
1117 | serge | 389 | break; |
390 | case CHIP_RS690: |
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391 | case CHIP_RS740: |
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1221 | serge | 392 | rdev->asic = &rs690_asic; |
1117 | serge | 393 | break; |
394 | case CHIP_RV515: |
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1128 | serge | 395 | rdev->asic = &rv515_asic; |
1117 | serge | 396 | break; |
397 | case CHIP_R520: |
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398 | case CHIP_RV530: |
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399 | case CHIP_RV560: |
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400 | case CHIP_RV570: |
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401 | case CHIP_R580: |
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402 | rdev->asic = &r520_asic; |
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403 | break; |
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404 | case CHIP_R600: |
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405 | case CHIP_RV610: |
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406 | case CHIP_RV630: |
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407 | case CHIP_RV620: |
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408 | case CHIP_RV635: |
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409 | case CHIP_RV670: |
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410 | case CHIP_RS780: |
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1221 | serge | 411 | case CHIP_RS880: |
1233 | serge | 412 | rdev->asic = &r600_asic; |
1221 | serge | 413 | break; |
1117 | serge | 414 | case CHIP_RV770: |
415 | case CHIP_RV730: |
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416 | case CHIP_RV710: |
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1221 | serge | 417 | case CHIP_RV740: |
1233 | serge | 418 | rdev->asic = &rv770_asic; |
1221 | serge | 419 | break; |
1117 | serge | 420 | default: |
421 | /* FIXME: not supported yet */ |
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422 | return -EINVAL; |
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423 | } |
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424 | return 0; |
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425 | } |
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426 | |||
427 | |||
428 | /* |
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429 | * Wrapper around modesetting bits. |
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430 | */ |
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431 | int radeon_clocks_init(struct radeon_device *rdev) |
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432 | { |
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433 | int r; |
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434 | |||
435 | r = radeon_static_clocks_init(rdev->ddev); |
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436 | if (r) { |
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437 | return r; |
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438 | } |
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439 | DRM_INFO("Clocks initialized !\n"); |
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440 | return 0; |
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441 | } |
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442 | |||
443 | void radeon_clocks_fini(struct radeon_device *rdev) |
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444 | { |
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445 | } |
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446 | |||
447 | /* ATOM accessor methods */ |
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448 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
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449 | { |
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450 | struct radeon_device *rdev = info->dev->dev_private; |
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451 | uint32_t r; |
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452 | |||
453 | r = rdev->pll_rreg(rdev, reg); |
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454 | return r; |
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455 | } |
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456 | |||
457 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
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458 | { |
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459 | struct radeon_device *rdev = info->dev->dev_private; |
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460 | |||
461 | rdev->pll_wreg(rdev, reg, val); |
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462 | } |
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463 | |||
464 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
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465 | { |
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466 | struct radeon_device *rdev = info->dev->dev_private; |
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467 | uint32_t r; |
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468 | |||
469 | r = rdev->mc_rreg(rdev, reg); |
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470 | return r; |
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471 | } |
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472 | |||
473 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
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474 | { |
||
475 | struct radeon_device *rdev = info->dev->dev_private; |
||
476 | |||
477 | rdev->mc_wreg(rdev, reg, val); |
||
478 | } |
||
479 | |||
480 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
481 | { |
||
482 | struct radeon_device *rdev = info->dev->dev_private; |
||
483 | |||
484 | WREG32(reg*4, val); |
||
485 | } |
||
486 | |||
487 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
||
488 | { |
||
489 | struct radeon_device *rdev = info->dev->dev_private; |
||
490 | uint32_t r; |
||
491 | |||
492 | r = RREG32(reg*4); |
||
493 | return r; |
||
494 | } |
||
495 | |||
496 | int radeon_atombios_init(struct radeon_device *rdev) |
||
497 | { |
||
1268 | serge | 498 | struct card_info *atom_card_info = |
499 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 500 | |
1268 | serge | 501 | if (!atom_card_info) |
502 | return -ENOMEM; |
||
503 | |||
504 | rdev->mode_info.atom_card_info = atom_card_info; |
||
505 | atom_card_info->dev = rdev->ddev; |
||
506 | atom_card_info->reg_read = cail_reg_read; |
||
507 | atom_card_info->reg_write = cail_reg_write; |
||
508 | atom_card_info->mc_read = cail_mc_read; |
||
509 | atom_card_info->mc_write = cail_mc_write; |
||
510 | atom_card_info->pll_read = cail_pll_read; |
||
511 | atom_card_info->pll_write = cail_pll_write; |
||
512 | |||
513 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1117 | serge | 514 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 515 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 516 | return 0; |
517 | } |
||
518 | |||
519 | void radeon_atombios_fini(struct radeon_device *rdev) |
||
520 | { |
||
1321 | serge | 521 | if (rdev->mode_info.atom_context) { |
522 | kfree(rdev->mode_info.atom_context->scratch); |
||
1119 | serge | 523 | kfree(rdev->mode_info.atom_context); |
1321 | serge | 524 | } |
1268 | serge | 525 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 526 | } |
527 | |||
528 | int radeon_combios_init(struct radeon_device *rdev) |
||
529 | { |
||
1128 | serge | 530 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 531 | return 0; |
532 | } |
||
533 | |||
534 | void radeon_combios_fini(struct radeon_device *rdev) |
||
535 | { |
||
536 | } |
||
537 | |||
1233 | serge | 538 | /* if we get transitioned to only one device, tak VGA back */ |
539 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
||
540 | { |
||
541 | struct radeon_device *rdev = cookie; |
||
542 | radeon_vga_set_state(rdev, state); |
||
543 | if (state) |
||
544 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
545 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
546 | else |
||
547 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
548 | } |
||
1117 | serge | 549 | |
1221 | serge | 550 | void radeon_agp_disable(struct radeon_device *rdev) |
551 | { |
||
552 | rdev->flags &= ~RADEON_IS_AGP; |
||
553 | if (rdev->family >= CHIP_R600) { |
||
554 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
555 | rdev->flags |= RADEON_IS_PCIE; |
||
556 | } else if (rdev->family >= CHIP_RV515 || |
||
557 | rdev->family == CHIP_RV380 || |
||
558 | rdev->family == CHIP_RV410 || |
||
559 | rdev->family == CHIP_R423) { |
||
560 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
561 | rdev->flags |= RADEON_IS_PCIE; |
||
562 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
||
563 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
||
564 | } else { |
||
565 | DRM_INFO("Forcing AGP to PCI mode\n"); |
||
566 | rdev->flags |= RADEON_IS_PCI; |
||
567 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
||
568 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
||
569 | } |
||
570 | } |
||
1179 | serge | 571 | |
1117 | serge | 572 | /* |
573 | * Radeon device. |
||
574 | */ |
||
575 | int radeon_device_init(struct radeon_device *rdev, |
||
576 | struct drm_device *ddev, |
||
577 | struct pci_dev *pdev, |
||
578 | uint32_t flags) |
||
579 | { |
||
1221 | serge | 580 | int r; |
1179 | serge | 581 | int dma_bits; |
1117 | serge | 582 | |
583 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
||
584 | rdev->shutdown = false; |
||
585 | rdev->ddev = ddev; |
||
586 | rdev->pdev = pdev; |
||
587 | rdev->flags = flags; |
||
588 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
589 | rdev->is_atom_bios = false; |
||
590 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
591 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
592 | rdev->gpu_lockup = false; |
||
1221 | serge | 593 | rdev->accel_working = false; |
1117 | serge | 594 | /* mutex initialization are all done here so we |
595 | * can recall function without having locking issues */ |
||
596 | // mutex_init(&rdev->cs_mutex); |
||
597 | // mutex_init(&rdev->ib_pool.mutex); |
||
598 | // mutex_init(&rdev->cp.mutex); |
||
599 | // rwlock_init(&rdev->fence_drv.lock); |
||
600 | |||
1179 | serge | 601 | /* Set asic functions */ |
602 | r = radeon_asic_init(rdev); |
||
603 | if (r) { |
||
604 | return r; |
||
605 | } |
||
606 | |||
1321 | serge | 607 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 608 | radeon_agp_disable(rdev); |
1117 | serge | 609 | } |
610 | |||
1179 | serge | 611 | /* set DMA mask + need_dma32 flags. |
612 | * PCIE - can handle 40-bits. |
||
613 | * IGP - can handle 40-bits (in theory) |
||
614 | * AGP - generally dma32 is safest |
||
615 | * PCI - only dma32 |
||
616 | */ |
||
617 | rdev->need_dma32 = false; |
||
618 | if (rdev->flags & RADEON_IS_AGP) |
||
619 | rdev->need_dma32 = true; |
||
620 | if (rdev->flags & RADEON_IS_PCI) |
||
621 | rdev->need_dma32 = true; |
||
1117 | serge | 622 | |
1179 | serge | 623 | dma_bits = rdev->need_dma32 ? 32 : 40; |
624 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 625 | if (r) { |
1119 | serge | 626 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
627 | } |
||
1117 | serge | 628 | |
629 | /* Registers mapping */ |
||
630 | /* TODO: block userspace mapping of io register */ |
||
631 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
632 | |||
633 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
634 | |||
635 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
636 | PG_SW+PG_NOCACHE); |
||
637 | |||
638 | if (rdev->rmmio == NULL) { |
||
639 | return -ENOMEM; |
||
640 | } |
||
641 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
642 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
643 | |||
1221 | serge | 644 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
645 | // r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
||
646 | // if (r) { |
||
647 | // return -EINVAL; |
||
648 | // } |
||
649 | |||
1179 | serge | 650 | r = radeon_init(rdev); |
1221 | serge | 651 | if (r) |
1117 | serge | 652 | return r; |
653 | |||
1221 | serge | 654 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
655 | /* Acceleration not working on AGP card try again |
||
656 | * with fallback to PCI or PCIE GART |
||
657 | */ |
||
658 | radeon_gpu_reset(rdev); |
||
659 | radeon_fini(rdev); |
||
660 | radeon_agp_disable(rdev); |
||
661 | r = radeon_init(rdev); |
||
662 | if (r) |
||
1179 | serge | 663 | return r; |
1126 | serge | 664 | } |
1179 | serge | 665 | // if (radeon_testing) { |
666 | // radeon_test_moves(rdev); |
||
1125 | serge | 667 | // } |
1179 | serge | 668 | // if (radeon_benchmarking) { |
669 | // radeon_benchmark(rdev); |
||
670 | // } |
||
671 | return 0; |
||
1117 | serge | 672 | } |
673 | |||
1179 | serge | 674 | |
1117 | serge | 675 | /* |
676 | * Driver load/unload |
||
677 | */ |
||
678 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
679 | { |
||
680 | struct radeon_device *rdev; |
||
681 | int r; |
||
682 | |||
1182 | serge | 683 | ENTER(); |
1117 | serge | 684 | |
1120 | serge | 685 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 686 | if (rdev == NULL) { |
687 | return -ENOMEM; |
||
688 | }; |
||
689 | |||
690 | dev->dev_private = (void *)rdev; |
||
691 | |||
692 | /* update BUS flag */ |
||
1239 | serge | 693 | if (drm_device_is_agp(dev)) { |
1117 | serge | 694 | flags |= RADEON_IS_AGP; |
1239 | serge | 695 | } else if (drm_device_is_pcie(dev)) { |
696 | flags |= RADEON_IS_PCIE; |
||
697 | } else { |
||
698 | flags |= RADEON_IS_PCI; |
||
699 | } |
||
1117 | serge | 700 | |
1182 | serge | 701 | /* radeon_device_init should report only fatal error |
702 | * like memory allocation failure or iomapping failure, |
||
703 | * or memory manager initialization failure, it must |
||
704 | * properly initialize the GPU MC controller and permit |
||
705 | * VRAM allocation |
||
706 | */ |
||
1117 | serge | 707 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
708 | if (r) { |
||
1182 | serge | 709 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 710 | return r; |
711 | } |
||
1182 | serge | 712 | /* Again modeset_init should fail only on fatal error |
713 | * otherwise it should provide enough functionalities |
||
714 | * for shadowfb to run |
||
715 | */ |
||
1246 | serge | 716 | if( radeon_modeset ) |
717 | { |
||
1268 | serge | 718 | r = radeon_modeset_init(rdev); |
719 | if (r) { |
||
720 | return r; |
||
721 | } |
||
1246 | serge | 722 | }; |
1117 | serge | 723 | return 0; |
724 | } |
||
725 | |||
1239 | serge | 726 | mode_t usermode; |
1230 | serge | 727 | |
1239 | serge | 728 | |
1117 | serge | 729 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
730 | { |
||
1246 | serge | 731 | static struct drm_device *dev; |
1117 | serge | 732 | int ret; |
733 | |||
1221 | serge | 734 | ENTER(); |
1117 | serge | 735 | |
1246 | serge | 736 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 737 | if (!dev) |
738 | return -ENOMEM; |
||
739 | |||
740 | // ret = pci_enable_device(pdev); |
||
741 | // if (ret) |
||
742 | // goto err_g1; |
||
743 | |||
744 | // pci_set_master(pdev); |
||
745 | |||
746 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
747 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
748 | // goto err_g2; |
||
749 | // } |
||
750 | |||
751 | dev->pdev = pdev; |
||
752 | dev->pci_device = pdev->device; |
||
753 | dev->pci_vendor = pdev->vendor; |
||
754 | |||
1221 | serge | 755 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
756 | if (ret) |
||
1117 | serge | 757 | goto err_g4; |
758 | |||
759 | // list_add_tail(&dev->driver_item, &driver->device_list); |
||
760 | |||
761 | // DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", |
||
762 | // driver->name, driver->major, driver->minor, driver->patchlevel, |
||
763 | // driver->date, pci_name(pdev), dev->primary->index); |
||
764 | |||
1246 | serge | 765 | if( radeon_modeset ) |
766 | init_display_kms(dev->dev_private, &usermode); |
||
767 | else |
||
1268 | serge | 768 | init_display(dev->dev_private, &usermode); |
1126 | serge | 769 | |
1221 | serge | 770 | LEAVE(); |
771 | |||
1117 | serge | 772 | return 0; |
773 | |||
774 | err_g4: |
||
775 | // drm_put_minor(&dev->primary); |
||
776 | //err_g3: |
||
777 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
778 | // drm_put_minor(&dev->control); |
||
779 | //err_g2: |
||
780 | // pci_disable_device(pdev); |
||
781 | //err_g1: |
||
782 | free(dev); |
||
783 | |||
1221 | serge | 784 | LEAVE(); |
785 | |||
1117 | serge | 786 | return ret; |
787 | } |
||
788 | |||
789 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
790 | { |
||
791 | return pci_resource_start(dev->pdev, resource); |
||
792 | } |
||
793 | |||
794 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
795 | { |
||
796 | return pci_resource_len(dev->pdev, resource); |
||
797 | } |
||
798 | |||
1123 | serge | 799 | |
800 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
801 | { |
||
802 | uint64_t rem = *n; |
||
803 | uint64_t b = base; |
||
804 | uint64_t res, d = 1; |
||
805 | uint32_t high = rem >> 32; |
||
806 | |||
807 | /* Reduce the thing a bit first */ |
||
808 | res = 0; |
||
809 | if (high >= base) { |
||
810 | high /= base; |
||
811 | res = (uint64_t) high << 32; |
||
812 | rem -= (uint64_t) (high*base) << 32; |
||
813 | } |
||
814 | |||
815 | while ((int64_t)b > 0 && b < rem) { |
||
816 | b = b+b; |
||
817 | d = d+d; |
||
818 | } |
||
819 | |||
820 | do { |
||
821 | if (rem >= b) { |
||
822 | rem -= b; |
||
823 | res += d; |
||
824 | } |
||
825 | b >>= 1; |
||
826 | d >>= 1; |
||
827 | } while (d); |
||
828 | |||
829 | *n = res; |
||
830 | return rem; |
||
831 | } |
||
832 | |||
1239 | serge | 833 | |
834 | static struct pci_device_id pciidlist[] = { |
||
835 | radeon_PCI_IDS |
||
836 | }; |
||
837 | |||
838 | |||
839 | #define API_VERSION 0x01000100 |
||
840 | |||
841 | #define SRV_GETVERSION 0 |
||
842 | #define SRV_ENUM_MODES 1 |
||
843 | #define SRV_SET_MODE 2 |
||
844 | |||
845 | int _stdcall display_handler(ioctl_t *io) |
||
846 | { |
||
847 | int retval = -1; |
||
848 | u32_t *inp; |
||
849 | u32_t *outp; |
||
850 | |||
851 | inp = io->input; |
||
852 | outp = io->output; |
||
853 | |||
854 | switch(io->io_code) |
||
855 | { |
||
856 | case SRV_GETVERSION: |
||
857 | if(io->out_size==4) |
||
858 | { |
||
859 | *outp = API_VERSION; |
||
860 | retval = 0; |
||
861 | } |
||
862 | break; |
||
863 | |||
864 | case SRV_ENUM_MODES: |
||
865 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
866 | inp, io->inp_size, io->out_size ); |
||
867 | |||
1246 | serge | 868 | if( radeon_modeset && |
869 | (outp != NULL) && (io->out_size == 4) && |
||
1239 | serge | 870 | (io->inp_size == *outp * sizeof(mode_t)) ) |
1268 | serge | 871 | { |
1239 | serge | 872 | retval = get_modes((mode_t*)inp, outp); |
873 | }; |
||
874 | break; |
||
875 | |||
876 | case SRV_SET_MODE: |
||
1246 | serge | 877 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
878 | inp, io->inp_size); |
||
879 | |||
880 | if( radeon_modeset && |
||
881 | (inp != NULL) && |
||
1239 | serge | 882 | (io->inp_size == sizeof(mode_t)) ) |
883 | { |
||
884 | retval = set_user_mode((mode_t*)inp); |
||
885 | }; |
||
886 | break; |
||
887 | }; |
||
888 | |||
889 | return retval; |
||
890 | } |
||
891 | |||
1246 | serge | 892 | static char log[256]; |
893 | static dev_t device; |
||
894 | |||
1239 | serge | 895 | u32_t drvEntry(int action, char *cmdline) |
896 | { |
||
897 | struct pci_device_id *ent; |
||
898 | |||
899 | int err; |
||
900 | u32_t retval = 0; |
||
901 | |||
902 | if(action != 1) |
||
903 | return 0; |
||
904 | |||
905 | if( GetService("DISPLAY") != 0 ) |
||
906 | return 0; |
||
907 | |||
908 | if( cmdline && *cmdline ) |
||
1268 | serge | 909 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 910 | |
911 | if(!dbg_open(log)) |
||
912 | { |
||
913 | strcpy(log, "/rd/1/drivers/atikms.log"); |
||
914 | |||
915 | if(!dbg_open(log)) |
||
916 | { |
||
917 | printf("Can't open %s\nExit\n", log); |
||
918 | return 0; |
||
919 | }; |
||
920 | } |
||
1321 | serge | 921 | dbgprintf("Radeon RC09 cmdline %s\n", cmdline); |
1239 | serge | 922 | |
923 | enum_pci_devices(); |
||
924 | |||
925 | ent = find_pci_device(&device, pciidlist); |
||
926 | |||
927 | if( unlikely(ent == NULL) ) |
||
928 | { |
||
929 | dbgprintf("device not found\n"); |
||
930 | return 0; |
||
931 | }; |
||
932 | |||
933 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
934 | device.pci_dev.device); |
||
935 | |||
936 | err = drm_get_dev(&device.pci_dev, ent); |
||
937 | |||
1246 | serge | 938 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 939 | |
1246 | serge | 940 | if( err != 0) |
941 | dbgprintf("Set DISPLAY handler\n"); |
||
942 | |||
943 | return err; |
||
1239 | serge | 944 | };>><>><>=>>>>>>>>> |