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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "radeon_asic.h" |
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36 | #include "atom.h" |
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37 | |||
1221 | serge | 38 | #include |
39 | |||
1117 | serge | 40 | |
1268 | serge | 41 | int radeon_dynclks = -1; |
42 | int radeon_r4xx_atom = 0; |
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43 | int radeon_agpmode = -1; |
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44 | int radeon_gart_size = 512; /* default gart size */ |
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45 | int radeon_benchmarking = 0; |
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46 | int radeon_connector_table = 0; |
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47 | int radeon_tv = 0; |
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1246 | serge | 48 | int radeon_modeset = 1; |
1117 | serge | 49 | |
1268 | serge | 50 | void parse_cmdline(char *cmdline, mode_t *mode, char *log, int *kms); |
1233 | serge | 51 | int init_display(struct radeon_device *rdev, mode_t *mode); |
1246 | serge | 52 | int init_display_kms(struct radeon_device *rdev, mode_t *mode); |
53 | |||
1239 | serge | 54 | int get_modes(mode_t *mode, int *count); |
55 | int set_user_mode(mode_t *mode); |
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1117 | serge | 56 | |
1239 | serge | 57 | |
1233 | serge | 58 | /* Legacy VGA regions */ |
59 | #define VGA_RSRC_NONE 0x00 |
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60 | #define VGA_RSRC_LEGACY_IO 0x01 |
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61 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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62 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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63 | /* Non-legacy access */ |
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64 | #define VGA_RSRC_NORMAL_IO 0x04 |
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65 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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66 | |||
67 | |||
68 | |||
1117 | serge | 69 | /* |
70 | * Clear GPU surface registers. |
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71 | */ |
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1179 | serge | 72 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 73 | { |
1179 | serge | 74 | ENTER(); |
1117 | serge | 75 | |
76 | /* FIXME: check this out */ |
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77 | if (rdev->family < CHIP_R600) { |
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78 | int i; |
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79 | |||
80 | for (i = 0; i < 8; i++) { |
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81 | WREG32(RADEON_SURFACE0_INFO + |
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82 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
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83 | 0); |
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84 | } |
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1179 | serge | 85 | /* enable surfaces */ |
86 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 87 | } |
88 | } |
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89 | |||
90 | /* |
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91 | * GPU scratch registers helpers function. |
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92 | */ |
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1179 | serge | 93 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 94 | { |
95 | int i; |
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96 | |||
97 | /* FIXME: check this out */ |
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98 | if (rdev->family < CHIP_R300) { |
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99 | rdev->scratch.num_reg = 5; |
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100 | } else { |
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101 | rdev->scratch.num_reg = 7; |
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102 | } |
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103 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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104 | rdev->scratch.free[i] = true; |
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105 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
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106 | } |
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107 | } |
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108 | |||
109 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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110 | { |
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111 | int i; |
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112 | |||
113 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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114 | if (rdev->scratch.free[i]) { |
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115 | rdev->scratch.free[i] = false; |
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116 | *reg = rdev->scratch.reg[i]; |
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117 | return 0; |
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118 | } |
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119 | } |
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120 | return -EINVAL; |
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121 | } |
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122 | |||
123 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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124 | { |
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125 | int i; |
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126 | |||
127 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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128 | if (rdev->scratch.reg[i] == reg) { |
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129 | rdev->scratch.free[i] = true; |
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130 | return; |
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131 | } |
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132 | } |
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133 | } |
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134 | |||
135 | /* |
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136 | * MC common functions |
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137 | */ |
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138 | int radeon_mc_setup(struct radeon_device *rdev) |
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139 | { |
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140 | uint32_t tmp; |
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141 | |||
142 | /* Some chips have an "issue" with the memory controller, the |
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143 | * location must be aligned to the size. We just align it down, |
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144 | * too bad if we walk over the top of system memory, we don't |
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145 | * use DMA without a remapped anyway. |
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146 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
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147 | */ |
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148 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
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149 | */ |
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1126 | serge | 150 | /* |
1117 | serge | 151 | * Note: from R6xx the address space is 40bits but here we only |
152 | * use 32bits (still have to see a card which would exhaust 4G |
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153 | * address space). |
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154 | */ |
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155 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
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156 | /* vram location was already setup try to put gtt after |
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157 | * if it fits */ |
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1179 | serge | 158 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
1117 | serge | 159 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
160 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
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161 | rdev->mc.gtt_location = tmp; |
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162 | } else { |
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163 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
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164 | printk(KERN_ERR "[drm] GTT too big to fit " |
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165 | "before or after vram location.\n"); |
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166 | return -EINVAL; |
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167 | } |
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168 | rdev->mc.gtt_location = 0; |
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169 | } |
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170 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
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171 | /* gtt location was already setup try to put vram before |
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172 | * if it fits */ |
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1179 | serge | 173 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
1117 | serge | 174 | rdev->mc.vram_location = 0; |
175 | } else { |
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176 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
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1179 | serge | 177 | tmp += (rdev->mc.mc_vram_size - 1); |
178 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
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179 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
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1117 | serge | 180 | rdev->mc.vram_location = tmp; |
181 | } else { |
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182 | printk(KERN_ERR "[drm] vram too big to fit " |
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183 | "before or after GTT location.\n"); |
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184 | return -EINVAL; |
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185 | } |
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186 | } |
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187 | } else { |
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188 | rdev->mc.vram_location = 0; |
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1179 | serge | 189 | tmp = rdev->mc.mc_vram_size; |
190 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
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191 | rdev->mc.gtt_location = tmp; |
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1117 | serge | 192 | } |
1179 | serge | 193 | rdev->mc.vram_start = rdev->mc.vram_location; |
194 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
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195 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
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196 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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197 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
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1117 | serge | 198 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
1179 | serge | 199 | (unsigned)rdev->mc.vram_location, |
200 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); |
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201 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); |
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1117 | serge | 202 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
1179 | serge | 203 | (unsigned)rdev->mc.gtt_location, |
204 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); |
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1117 | serge | 205 | return 0; |
206 | } |
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207 | |||
208 | |||
209 | /* |
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210 | * GPU helpers function. |
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211 | */ |
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1179 | serge | 212 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 213 | { |
214 | uint32_t reg; |
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215 | |||
1179 | serge | 216 | ENTER(); |
1117 | serge | 217 | |
218 | /* first check CRTCs */ |
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219 | if (ASIC_IS_AVIVO(rdev)) { |
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220 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
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221 | RREG32(AVIVO_D2CRTC_CONTROL); |
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222 | if (reg & AVIVO_CRTC_EN) { |
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223 | return true; |
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224 | } |
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225 | } else { |
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226 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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227 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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228 | if (reg & RADEON_CRTC_EN) { |
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229 | return true; |
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230 | } |
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231 | } |
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232 | |||
233 | /* then check MEM_SIZE, in case the crtcs are off */ |
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234 | if (rdev->family >= CHIP_R600) |
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235 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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236 | else |
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237 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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238 | |||
239 | if (reg) |
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240 | return true; |
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241 | |||
242 | return false; |
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243 | |||
244 | } |
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245 | |||
1233 | serge | 246 | int radeon_dummy_page_init(struct radeon_device *rdev) |
247 | { |
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248 | rdev->dummy_page.page = AllocPage(); |
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249 | if (rdev->dummy_page.page == NULL) |
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250 | return -ENOMEM; |
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251 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
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252 | if (!rdev->dummy_page.addr) { |
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253 | // __free_page(rdev->dummy_page.page); |
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254 | rdev->dummy_page.page = NULL; |
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255 | return -ENOMEM; |
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256 | } |
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257 | return 0; |
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258 | } |
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1117 | serge | 259 | |
1233 | serge | 260 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
261 | { |
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262 | if (rdev->dummy_page.page == NULL) |
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263 | return; |
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264 | KernelFree(rdev->dummy_page.addr); |
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265 | rdev->dummy_page.page = NULL; |
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266 | } |
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267 | |||
268 | |||
1117 | serge | 269 | /* |
270 | * Registers accessors functions. |
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271 | */ |
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272 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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273 | { |
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274 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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275 | BUG_ON(1); |
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276 | return 0; |
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277 | } |
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278 | |||
279 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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280 | { |
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281 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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282 | reg, v); |
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283 | BUG_ON(1); |
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284 | } |
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285 | |||
286 | void radeon_register_accessor_init(struct radeon_device *rdev) |
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287 | { |
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288 | rdev->mc_rreg = &radeon_invalid_rreg; |
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289 | rdev->mc_wreg = &radeon_invalid_wreg; |
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290 | rdev->pll_rreg = &radeon_invalid_rreg; |
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291 | rdev->pll_wreg = &radeon_invalid_wreg; |
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292 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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293 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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294 | |||
295 | /* Don't change order as we are overridding accessor. */ |
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296 | if (rdev->family < CHIP_RV515) { |
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1179 | serge | 297 | rdev->pcie_reg_mask = 0xff; |
298 | } else { |
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299 | rdev->pcie_reg_mask = 0x7ff; |
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1117 | serge | 300 | } |
301 | /* FIXME: not sure here */ |
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302 | if (rdev->family <= CHIP_R580) { |
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1119 | serge | 303 | rdev->pll_rreg = &r100_pll_rreg; |
304 | rdev->pll_wreg = &r100_pll_wreg; |
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1117 | serge | 305 | } |
1179 | serge | 306 | if (rdev->family >= CHIP_R420) { |
307 | rdev->mc_rreg = &r420_mc_rreg; |
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308 | rdev->mc_wreg = &r420_mc_wreg; |
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309 | } |
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1117 | serge | 310 | if (rdev->family >= CHIP_RV515) { |
311 | rdev->mc_rreg = &rv515_mc_rreg; |
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312 | rdev->mc_wreg = &rv515_mc_wreg; |
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313 | } |
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314 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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1128 | serge | 315 | rdev->mc_rreg = &rs400_mc_rreg; |
316 | rdev->mc_wreg = &rs400_mc_wreg; |
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1117 | serge | 317 | } |
1221 | serge | 318 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
319 | rdev->mc_rreg = &rs690_mc_rreg; |
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320 | rdev->mc_wreg = &rs690_mc_wreg; |
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321 | } |
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322 | if (rdev->family == CHIP_RS600) { |
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323 | rdev->mc_rreg = &rs600_mc_rreg; |
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324 | rdev->mc_wreg = &rs600_mc_wreg; |
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325 | } |
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1233 | serge | 326 | if (rdev->family >= CHIP_R600) { |
327 | rdev->pciep_rreg = &r600_pciep_rreg; |
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328 | rdev->pciep_wreg = &r600_pciep_wreg; |
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329 | } |
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1117 | serge | 330 | } |
331 | |||
332 | |||
333 | /* |
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334 | * ASIC |
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335 | */ |
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336 | int radeon_asic_init(struct radeon_device *rdev) |
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337 | { |
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338 | radeon_register_accessor_init(rdev); |
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339 | switch (rdev->family) { |
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340 | case CHIP_R100: |
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341 | case CHIP_RV100: |
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342 | case CHIP_RS100: |
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343 | case CHIP_RV200: |
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344 | case CHIP_RS200: |
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345 | case CHIP_R200: |
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346 | case CHIP_RV250: |
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347 | case CHIP_RS300: |
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348 | case CHIP_RV280: |
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1128 | serge | 349 | rdev->asic = &r100_asic; |
1117 | serge | 350 | break; |
351 | case CHIP_R300: |
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352 | case CHIP_R350: |
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353 | case CHIP_RV350: |
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354 | case CHIP_RV380: |
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1128 | serge | 355 | rdev->asic = &r300_asic; |
1179 | serge | 356 | if (rdev->flags & RADEON_IS_PCIE) { |
357 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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358 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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359 | } |
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1117 | serge | 360 | break; |
361 | case CHIP_R420: |
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362 | case CHIP_R423: |
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363 | case CHIP_RV410: |
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1128 | serge | 364 | rdev->asic = &r420_asic; |
1117 | serge | 365 | break; |
366 | case CHIP_RS400: |
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367 | case CHIP_RS480: |
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1128 | serge | 368 | rdev->asic = &rs400_asic; |
1117 | serge | 369 | break; |
370 | case CHIP_RS600: |
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1221 | serge | 371 | rdev->asic = &rs600_asic; |
1117 | serge | 372 | break; |
373 | case CHIP_RS690: |
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374 | case CHIP_RS740: |
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1221 | serge | 375 | rdev->asic = &rs690_asic; |
1117 | serge | 376 | break; |
377 | case CHIP_RV515: |
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1128 | serge | 378 | rdev->asic = &rv515_asic; |
1117 | serge | 379 | break; |
380 | case CHIP_R520: |
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381 | case CHIP_RV530: |
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382 | case CHIP_RV560: |
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383 | case CHIP_RV570: |
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384 | case CHIP_R580: |
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385 | rdev->asic = &r520_asic; |
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386 | break; |
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387 | case CHIP_R600: |
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388 | case CHIP_RV610: |
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389 | case CHIP_RV630: |
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390 | case CHIP_RV620: |
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391 | case CHIP_RV635: |
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392 | case CHIP_RV670: |
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393 | case CHIP_RS780: |
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1221 | serge | 394 | case CHIP_RS880: |
1233 | serge | 395 | rdev->asic = &r600_asic; |
1221 | serge | 396 | break; |
1117 | serge | 397 | case CHIP_RV770: |
398 | case CHIP_RV730: |
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399 | case CHIP_RV710: |
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1221 | serge | 400 | case CHIP_RV740: |
1233 | serge | 401 | rdev->asic = &rv770_asic; |
1221 | serge | 402 | break; |
1117 | serge | 403 | default: |
404 | /* FIXME: not supported yet */ |
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405 | return -EINVAL; |
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406 | } |
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407 | return 0; |
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408 | } |
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409 | |||
410 | |||
411 | /* |
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412 | * Wrapper around modesetting bits. |
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413 | */ |
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414 | int radeon_clocks_init(struct radeon_device *rdev) |
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415 | { |
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416 | int r; |
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417 | |||
1179 | serge | 418 | ENTER(); |
1117 | serge | 419 | |
420 | r = radeon_static_clocks_init(rdev->ddev); |
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421 | if (r) { |
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422 | return r; |
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423 | } |
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424 | DRM_INFO("Clocks initialized !\n"); |
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425 | return 0; |
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426 | } |
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427 | |||
428 | void radeon_clocks_fini(struct radeon_device *rdev) |
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429 | { |
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430 | } |
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431 | |||
432 | /* ATOM accessor methods */ |
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433 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
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434 | { |
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435 | struct radeon_device *rdev = info->dev->dev_private; |
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436 | uint32_t r; |
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437 | |||
438 | r = rdev->pll_rreg(rdev, reg); |
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439 | return r; |
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440 | } |
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441 | |||
442 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
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443 | { |
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444 | struct radeon_device *rdev = info->dev->dev_private; |
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445 | |||
446 | rdev->pll_wreg(rdev, reg, val); |
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447 | } |
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448 | |||
449 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
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450 | { |
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451 | struct radeon_device *rdev = info->dev->dev_private; |
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452 | uint32_t r; |
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453 | |||
454 | r = rdev->mc_rreg(rdev, reg); |
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455 | return r; |
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456 | } |
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457 | |||
458 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
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459 | { |
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460 | struct radeon_device *rdev = info->dev->dev_private; |
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461 | |||
462 | rdev->mc_wreg(rdev, reg, val); |
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463 | } |
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464 | |||
465 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
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466 | { |
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467 | struct radeon_device *rdev = info->dev->dev_private; |
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468 | |||
469 | WREG32(reg*4, val); |
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470 | } |
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471 | |||
472 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
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473 | { |
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474 | struct radeon_device *rdev = info->dev->dev_private; |
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475 | uint32_t r; |
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476 | |||
477 | r = RREG32(reg*4); |
||
478 | return r; |
||
479 | } |
||
480 | |||
481 | int radeon_atombios_init(struct radeon_device *rdev) |
||
482 | { |
||
1268 | serge | 483 | struct card_info *atom_card_info = |
484 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 485 | |
1268 | serge | 486 | if (!atom_card_info) |
487 | return -ENOMEM; |
||
488 | |||
489 | rdev->mode_info.atom_card_info = atom_card_info; |
||
490 | atom_card_info->dev = rdev->ddev; |
||
491 | atom_card_info->reg_read = cail_reg_read; |
||
492 | atom_card_info->reg_write = cail_reg_write; |
||
493 | atom_card_info->mc_read = cail_mc_read; |
||
494 | atom_card_info->mc_write = cail_mc_write; |
||
495 | atom_card_info->pll_read = cail_pll_read; |
||
496 | atom_card_info->pll_write = cail_pll_write; |
||
497 | |||
498 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1117 | serge | 499 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
500 | return 0; |
||
501 | } |
||
502 | |||
503 | void radeon_atombios_fini(struct radeon_device *rdev) |
||
504 | { |
||
1119 | serge | 505 | kfree(rdev->mode_info.atom_context); |
1268 | serge | 506 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 507 | } |
508 | |||
509 | int radeon_combios_init(struct radeon_device *rdev) |
||
510 | { |
||
1128 | serge | 511 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 512 | return 0; |
513 | } |
||
514 | |||
515 | void radeon_combios_fini(struct radeon_device *rdev) |
||
516 | { |
||
517 | } |
||
518 | |||
1233 | serge | 519 | /* if we get transitioned to only one device, tak VGA back */ |
520 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
||
521 | { |
||
522 | struct radeon_device *rdev = cookie; |
||
523 | radeon_vga_set_state(rdev, state); |
||
524 | if (state) |
||
525 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
526 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
527 | else |
||
528 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
529 | } |
||
1117 | serge | 530 | |
1221 | serge | 531 | void radeon_agp_disable(struct radeon_device *rdev) |
532 | { |
||
533 | rdev->flags &= ~RADEON_IS_AGP; |
||
534 | if (rdev->family >= CHIP_R600) { |
||
535 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
536 | rdev->flags |= RADEON_IS_PCIE; |
||
537 | } else if (rdev->family >= CHIP_RV515 || |
||
538 | rdev->family == CHIP_RV380 || |
||
539 | rdev->family == CHIP_RV410 || |
||
540 | rdev->family == CHIP_R423) { |
||
541 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
542 | rdev->flags |= RADEON_IS_PCIE; |
||
543 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
||
544 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
||
545 | } else { |
||
546 | DRM_INFO("Forcing AGP to PCI mode\n"); |
||
547 | rdev->flags |= RADEON_IS_PCI; |
||
548 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
||
549 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
||
550 | } |
||
551 | } |
||
1179 | serge | 552 | |
1117 | serge | 553 | /* |
554 | * Radeon device. |
||
555 | */ |
||
556 | int radeon_device_init(struct radeon_device *rdev, |
||
557 | struct drm_device *ddev, |
||
558 | struct pci_dev *pdev, |
||
559 | uint32_t flags) |
||
560 | { |
||
1221 | serge | 561 | int r; |
1179 | serge | 562 | int dma_bits; |
1117 | serge | 563 | |
1179 | serge | 564 | ENTER(); |
1117 | serge | 565 | |
566 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
||
567 | rdev->shutdown = false; |
||
568 | rdev->ddev = ddev; |
||
569 | rdev->pdev = pdev; |
||
570 | rdev->flags = flags; |
||
571 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
572 | rdev->is_atom_bios = false; |
||
573 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
574 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
575 | rdev->gpu_lockup = false; |
||
1221 | serge | 576 | rdev->accel_working = false; |
1117 | serge | 577 | /* mutex initialization are all done here so we |
578 | * can recall function without having locking issues */ |
||
579 | // mutex_init(&rdev->cs_mutex); |
||
580 | // mutex_init(&rdev->ib_pool.mutex); |
||
581 | // mutex_init(&rdev->cp.mutex); |
||
582 | // rwlock_init(&rdev->fence_drv.lock); |
||
583 | |||
1179 | serge | 584 | /* Set asic functions */ |
585 | r = radeon_asic_init(rdev); |
||
586 | if (r) { |
||
587 | return r; |
||
588 | } |
||
589 | |||
1117 | serge | 590 | if (radeon_agpmode == -1) { |
1221 | serge | 591 | radeon_agp_disable(rdev); |
1117 | serge | 592 | } |
593 | |||
1179 | serge | 594 | /* set DMA mask + need_dma32 flags. |
595 | * PCIE - can handle 40-bits. |
||
596 | * IGP - can handle 40-bits (in theory) |
||
597 | * AGP - generally dma32 is safest |
||
598 | * PCI - only dma32 |
||
599 | */ |
||
600 | rdev->need_dma32 = false; |
||
601 | if (rdev->flags & RADEON_IS_AGP) |
||
602 | rdev->need_dma32 = true; |
||
603 | if (rdev->flags & RADEON_IS_PCI) |
||
604 | rdev->need_dma32 = true; |
||
1117 | serge | 605 | |
1179 | serge | 606 | dma_bits = rdev->need_dma32 ? 32 : 40; |
607 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 608 | if (r) { |
1119 | serge | 609 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
610 | } |
||
1117 | serge | 611 | |
612 | /* Registers mapping */ |
||
613 | /* TODO: block userspace mapping of io register */ |
||
614 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
615 | |||
616 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
617 | |||
618 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
619 | PG_SW+PG_NOCACHE); |
||
620 | |||
621 | if (rdev->rmmio == NULL) { |
||
622 | return -ENOMEM; |
||
623 | } |
||
624 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
625 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
626 | |||
1221 | serge | 627 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
628 | // r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
||
629 | // if (r) { |
||
630 | // return -EINVAL; |
||
631 | // } |
||
632 | |||
1179 | serge | 633 | r = radeon_init(rdev); |
1221 | serge | 634 | if (r) |
1117 | serge | 635 | return r; |
636 | |||
1221 | serge | 637 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
638 | /* Acceleration not working on AGP card try again |
||
639 | * with fallback to PCI or PCIE GART |
||
640 | */ |
||
641 | radeon_gpu_reset(rdev); |
||
642 | radeon_fini(rdev); |
||
643 | radeon_agp_disable(rdev); |
||
644 | r = radeon_init(rdev); |
||
645 | if (r) |
||
1179 | serge | 646 | return r; |
1126 | serge | 647 | } |
1179 | serge | 648 | // if (radeon_testing) { |
649 | // radeon_test_moves(rdev); |
||
1125 | serge | 650 | // } |
1179 | serge | 651 | // if (radeon_benchmarking) { |
652 | // radeon_benchmark(rdev); |
||
653 | // } |
||
654 | return 0; |
||
1117 | serge | 655 | } |
656 | |||
1179 | serge | 657 | |
1117 | serge | 658 | /* |
659 | * Driver load/unload |
||
660 | */ |
||
661 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
662 | { |
||
663 | struct radeon_device *rdev; |
||
664 | int r; |
||
665 | |||
1182 | serge | 666 | ENTER(); |
1117 | serge | 667 | |
1120 | serge | 668 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 669 | if (rdev == NULL) { |
670 | return -ENOMEM; |
||
671 | }; |
||
672 | |||
673 | dev->dev_private = (void *)rdev; |
||
674 | |||
675 | /* update BUS flag */ |
||
1239 | serge | 676 | if (drm_device_is_agp(dev)) { |
1117 | serge | 677 | flags |= RADEON_IS_AGP; |
1239 | serge | 678 | } else if (drm_device_is_pcie(dev)) { |
679 | flags |= RADEON_IS_PCIE; |
||
680 | } else { |
||
681 | flags |= RADEON_IS_PCI; |
||
682 | } |
||
1117 | serge | 683 | |
1182 | serge | 684 | /* radeon_device_init should report only fatal error |
685 | * like memory allocation failure or iomapping failure, |
||
686 | * or memory manager initialization failure, it must |
||
687 | * properly initialize the GPU MC controller and permit |
||
688 | * VRAM allocation |
||
689 | */ |
||
1117 | serge | 690 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
691 | if (r) { |
||
1182 | serge | 692 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 693 | return r; |
694 | } |
||
1182 | serge | 695 | /* Again modeset_init should fail only on fatal error |
696 | * otherwise it should provide enough functionalities |
||
697 | * for shadowfb to run |
||
698 | */ |
||
1246 | serge | 699 | if( radeon_modeset ) |
700 | { |
||
1268 | serge | 701 | r = radeon_modeset_init(rdev); |
702 | if (r) { |
||
703 | return r; |
||
704 | } |
||
1246 | serge | 705 | }; |
1117 | serge | 706 | return 0; |
707 | } |
||
708 | |||
1239 | serge | 709 | mode_t usermode; |
1230 | serge | 710 | |
1239 | serge | 711 | |
1117 | serge | 712 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
713 | { |
||
1246 | serge | 714 | static struct drm_device *dev; |
1117 | serge | 715 | int ret; |
716 | |||
1221 | serge | 717 | ENTER(); |
1117 | serge | 718 | |
1246 | serge | 719 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 720 | if (!dev) |
721 | return -ENOMEM; |
||
722 | |||
723 | // ret = pci_enable_device(pdev); |
||
724 | // if (ret) |
||
725 | // goto err_g1; |
||
726 | |||
727 | // pci_set_master(pdev); |
||
728 | |||
729 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
730 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
731 | // goto err_g2; |
||
732 | // } |
||
733 | |||
734 | dev->pdev = pdev; |
||
735 | dev->pci_device = pdev->device; |
||
736 | dev->pci_vendor = pdev->vendor; |
||
737 | |||
1221 | serge | 738 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
739 | if (ret) |
||
1117 | serge | 740 | goto err_g4; |
741 | |||
742 | // list_add_tail(&dev->driver_item, &driver->device_list); |
||
743 | |||
744 | // DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", |
||
745 | // driver->name, driver->major, driver->minor, driver->patchlevel, |
||
746 | // driver->date, pci_name(pdev), dev->primary->index); |
||
747 | |||
1246 | serge | 748 | if( radeon_modeset ) |
749 | init_display_kms(dev->dev_private, &usermode); |
||
750 | else |
||
1268 | serge | 751 | init_display(dev->dev_private, &usermode); |
1126 | serge | 752 | |
1221 | serge | 753 | LEAVE(); |
754 | |||
1117 | serge | 755 | return 0; |
756 | |||
757 | err_g4: |
||
758 | // drm_put_minor(&dev->primary); |
||
759 | //err_g3: |
||
760 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
761 | // drm_put_minor(&dev->control); |
||
762 | //err_g2: |
||
763 | // pci_disable_device(pdev); |
||
764 | //err_g1: |
||
765 | free(dev); |
||
766 | |||
1221 | serge | 767 | LEAVE(); |
768 | |||
1117 | serge | 769 | return ret; |
770 | } |
||
771 | |||
772 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
773 | { |
||
774 | return pci_resource_start(dev->pdev, resource); |
||
775 | } |
||
776 | |||
777 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
778 | { |
||
779 | return pci_resource_len(dev->pdev, resource); |
||
780 | } |
||
781 | |||
1123 | serge | 782 | |
783 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
784 | { |
||
785 | uint64_t rem = *n; |
||
786 | uint64_t b = base; |
||
787 | uint64_t res, d = 1; |
||
788 | uint32_t high = rem >> 32; |
||
789 | |||
790 | /* Reduce the thing a bit first */ |
||
791 | res = 0; |
||
792 | if (high >= base) { |
||
793 | high /= base; |
||
794 | res = (uint64_t) high << 32; |
||
795 | rem -= (uint64_t) (high*base) << 32; |
||
796 | } |
||
797 | |||
798 | while ((int64_t)b > 0 && b < rem) { |
||
799 | b = b+b; |
||
800 | d = d+d; |
||
801 | } |
||
802 | |||
803 | do { |
||
804 | if (rem >= b) { |
||
805 | rem -= b; |
||
806 | res += d; |
||
807 | } |
||
808 | b >>= 1; |
||
809 | d >>= 1; |
||
810 | } while (d); |
||
811 | |||
812 | *n = res; |
||
813 | return rem; |
||
814 | } |
||
815 | |||
1239 | serge | 816 | |
817 | static struct pci_device_id pciidlist[] = { |
||
818 | radeon_PCI_IDS |
||
819 | }; |
||
820 | |||
821 | |||
822 | #define API_VERSION 0x01000100 |
||
823 | |||
824 | #define SRV_GETVERSION 0 |
||
825 | #define SRV_ENUM_MODES 1 |
||
826 | #define SRV_SET_MODE 2 |
||
827 | |||
828 | int _stdcall display_handler(ioctl_t *io) |
||
829 | { |
||
830 | int retval = -1; |
||
831 | u32_t *inp; |
||
832 | u32_t *outp; |
||
833 | |||
834 | inp = io->input; |
||
835 | outp = io->output; |
||
836 | |||
837 | switch(io->io_code) |
||
838 | { |
||
839 | case SRV_GETVERSION: |
||
840 | if(io->out_size==4) |
||
841 | { |
||
842 | *outp = API_VERSION; |
||
843 | retval = 0; |
||
844 | } |
||
845 | break; |
||
846 | |||
847 | case SRV_ENUM_MODES: |
||
848 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
849 | inp, io->inp_size, io->out_size ); |
||
850 | |||
1246 | serge | 851 | if( radeon_modeset && |
852 | (outp != NULL) && (io->out_size == 4) && |
||
1239 | serge | 853 | (io->inp_size == *outp * sizeof(mode_t)) ) |
1268 | serge | 854 | { |
1239 | serge | 855 | retval = get_modes((mode_t*)inp, outp); |
856 | }; |
||
857 | break; |
||
858 | |||
859 | case SRV_SET_MODE: |
||
1246 | serge | 860 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
861 | inp, io->inp_size); |
||
862 | |||
863 | if( radeon_modeset && |
||
864 | (inp != NULL) && |
||
1239 | serge | 865 | (io->inp_size == sizeof(mode_t)) ) |
866 | { |
||
867 | retval = set_user_mode((mode_t*)inp); |
||
868 | }; |
||
869 | break; |
||
870 | }; |
||
871 | |||
872 | return retval; |
||
873 | } |
||
874 | |||
1246 | serge | 875 | static char log[256]; |
876 | static dev_t device; |
||
877 | |||
1239 | serge | 878 | u32_t drvEntry(int action, char *cmdline) |
879 | { |
||
880 | struct pci_device_id *ent; |
||
881 | |||
882 | int err; |
||
883 | u32_t retval = 0; |
||
884 | |||
885 | if(action != 1) |
||
886 | return 0; |
||
887 | |||
888 | if( GetService("DISPLAY") != 0 ) |
||
889 | return 0; |
||
890 | |||
891 | if( cmdline && *cmdline ) |
||
1268 | serge | 892 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 893 | |
894 | if(!dbg_open(log)) |
||
895 | { |
||
896 | strcpy(log, "/rd/1/drivers/atikms.log"); |
||
897 | |||
898 | if(!dbg_open(log)) |
||
899 | { |
||
900 | printf("Can't open %s\nExit\n", log); |
||
901 | return 0; |
||
902 | }; |
||
903 | } |
||
1268 | serge | 904 | dbgprintf("Radeon RC06 cmdline %s\n", cmdline); |
1239 | serge | 905 | |
906 | enum_pci_devices(); |
||
907 | |||
908 | ent = find_pci_device(&device, pciidlist); |
||
909 | |||
910 | if( unlikely(ent == NULL) ) |
||
911 | { |
||
912 | dbgprintf("device not found\n"); |
||
913 | return 0; |
||
914 | }; |
||
915 | |||
916 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
917 | device.pci_dev.device); |
||
918 | |||
919 | err = drm_get_dev(&device.pci_dev, ent); |
||
920 | |||
1246 | serge | 921 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 922 | |
1246 | serge | 923 | if( err != 0) |
924 | dbgprintf("Set DISPLAY handler\n"); |
||
925 | |||
926 | return err; |
||
1239 | serge | 927 | };>><>><>=>>>>>>>>> |