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1117 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
28
//#include 
1123 serge 29
 
1179 serge 30
#include 
31
#include 
1221 serge 32
#include 
1117 serge 33
#include "radeon_reg.h"
34
#include "radeon.h"
35
#include "radeon_asic.h"
36
#include "atom.h"
37
 
1221 serge 38
#include 
39
 
1117 serge 40
 
41
int radeon_dynclks = -1;
1123 serge 42
int radeon_r4xx_atom = 0;
1125 serge 43
int radeon_agpmode   = -1;
1117 serge 44
int radeon_gart_size = 512; /* default gart size */
1123 serge 45
int radeon_benchmarking = 0;
46
int radeon_connector_table = 0;
1222 serge 47
int radeon_tv = 0;
1117 serge 48
 
1233 serge 49
void parse_cmdline(char *cmdline, mode_t *mode, char *log);
50
int init_display(struct radeon_device *rdev, mode_t *mode);
1239 serge 51
int get_modes(mode_t *mode, int *count);
52
int set_user_mode(mode_t *mode);
1117 serge 53
 
1239 serge 54
 
1233 serge 55
 /* Legacy VGA regions */
56
#define VGA_RSRC_NONE          0x00
57
#define VGA_RSRC_LEGACY_IO     0x01
58
#define VGA_RSRC_LEGACY_MEM    0x02
59
#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
60
/* Non-legacy access */
61
#define VGA_RSRC_NORMAL_IO     0x04
62
#define VGA_RSRC_NORMAL_MEM    0x08
63
 
64
 
65
 
1117 serge 66
/*
67
 * Clear GPU surface registers.
68
 */
1179 serge 69
void radeon_surface_init(struct radeon_device *rdev)
1117 serge 70
{
1179 serge 71
    ENTER();
1117 serge 72
 
73
    /* FIXME: check this out */
74
    if (rdev->family < CHIP_R600) {
75
        int i;
76
 
77
        for (i = 0; i < 8; i++) {
78
            WREG32(RADEON_SURFACE0_INFO +
79
                   i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
80
                   0);
81
        }
1179 serge 82
		/* enable surfaces */
83
		WREG32(RADEON_SURFACE_CNTL, 0);
1117 serge 84
    }
85
}
86
 
87
/*
88
 * GPU scratch registers helpers function.
89
 */
1179 serge 90
void radeon_scratch_init(struct radeon_device *rdev)
1117 serge 91
{
92
    int i;
93
 
94
    /* FIXME: check this out */
95
    if (rdev->family < CHIP_R300) {
96
        rdev->scratch.num_reg = 5;
97
    } else {
98
        rdev->scratch.num_reg = 7;
99
    }
100
    for (i = 0; i < rdev->scratch.num_reg; i++) {
101
        rdev->scratch.free[i] = true;
102
        rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
103
    }
104
}
105
 
106
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
107
{
108
	int i;
109
 
110
	for (i = 0; i < rdev->scratch.num_reg; i++) {
111
		if (rdev->scratch.free[i]) {
112
			rdev->scratch.free[i] = false;
113
			*reg = rdev->scratch.reg[i];
114
			return 0;
115
		}
116
	}
117
	return -EINVAL;
118
}
119
 
120
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
121
{
122
	int i;
123
 
124
	for (i = 0; i < rdev->scratch.num_reg; i++) {
125
		if (rdev->scratch.reg[i] == reg) {
126
			rdev->scratch.free[i] = true;
127
			return;
128
		}
129
	}
130
}
131
 
132
/*
133
 * MC common functions
134
 */
135
int radeon_mc_setup(struct radeon_device *rdev)
136
{
137
	uint32_t tmp;
138
 
139
	/* Some chips have an "issue" with the memory controller, the
140
	 * location must be aligned to the size. We just align it down,
141
	 * too bad if we walk over the top of system memory, we don't
142
	 * use DMA without a remapped anyway.
143
	 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
144
	 */
145
	/* FGLRX seems to setup like this, VRAM a 0, then GART.
146
	 */
1126 serge 147
	/*
1117 serge 148
	 * Note: from R6xx the address space is 40bits but here we only
149
	 * use 32bits (still have to see a card which would exhaust 4G
150
	 * address space).
151
	 */
152
	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
153
		/* vram location was already setup try to put gtt after
154
		 * if it fits */
1179 serge 155
		tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
1117 serge 156
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
157
		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
158
			rdev->mc.gtt_location = tmp;
159
		} else {
160
			if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
161
				printk(KERN_ERR "[drm] GTT too big to fit "
162
				       "before or after vram location.\n");
163
				return -EINVAL;
164
			}
165
			rdev->mc.gtt_location = 0;
166
		}
167
	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
168
		/* gtt location was already setup try to put vram before
169
		 * if it fits */
1179 serge 170
		if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
1117 serge 171
			rdev->mc.vram_location = 0;
172
		} else {
173
			tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
1179 serge 174
			tmp += (rdev->mc.mc_vram_size - 1);
175
			tmp &= ~(rdev->mc.mc_vram_size - 1);
176
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
1117 serge 177
				rdev->mc.vram_location = tmp;
178
			} else {
179
				printk(KERN_ERR "[drm] vram too big to fit "
180
				       "before or after GTT location.\n");
181
				return -EINVAL;
182
			}
183
		}
184
	} else {
185
		rdev->mc.vram_location = 0;
1179 serge 186
		tmp = rdev->mc.mc_vram_size;
187
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
188
		rdev->mc.gtt_location = tmp;
1117 serge 189
	}
1179 serge 190
	rdev->mc.vram_start = rdev->mc.vram_location;
191
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
192
	rdev->mc.gtt_start = rdev->mc.gtt_location;
193
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
194
	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
1117 serge 195
	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
1179 serge 196
		 (unsigned)rdev->mc.vram_location,
197
		 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
198
	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
1117 serge 199
	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
1179 serge 200
		 (unsigned)rdev->mc.gtt_location,
201
		 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
1117 serge 202
	return 0;
203
}
204
 
205
 
206
/*
207
 * GPU helpers function.
208
 */
1179 serge 209
bool radeon_card_posted(struct radeon_device *rdev)
1117 serge 210
{
211
	uint32_t reg;
212
 
1179 serge 213
    ENTER();
1117 serge 214
 
215
	/* first check CRTCs */
216
	if (ASIC_IS_AVIVO(rdev)) {
217
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
218
		      RREG32(AVIVO_D2CRTC_CONTROL);
219
		if (reg & AVIVO_CRTC_EN) {
220
			return true;
221
		}
222
	} else {
223
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
224
		      RREG32(RADEON_CRTC2_GEN_CNTL);
225
		if (reg & RADEON_CRTC_EN) {
226
			return true;
227
		}
228
	}
229
 
230
	/* then check MEM_SIZE, in case the crtcs are off */
231
	if (rdev->family >= CHIP_R600)
232
		reg = RREG32(R600_CONFIG_MEMSIZE);
233
	else
234
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
235
 
236
	if (reg)
237
		return true;
238
 
239
	return false;
240
 
241
}
242
 
1233 serge 243
int radeon_dummy_page_init(struct radeon_device *rdev)
244
{
245
    rdev->dummy_page.page = AllocPage();
246
	if (rdev->dummy_page.page == NULL)
247
		return -ENOMEM;
248
    rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
249
	if (!rdev->dummy_page.addr) {
250
//       __free_page(rdev->dummy_page.page);
251
		rdev->dummy_page.page = NULL;
252
		return -ENOMEM;
253
	}
254
	return 0;
255
}
1117 serge 256
 
1233 serge 257
void radeon_dummy_page_fini(struct radeon_device *rdev)
258
{
259
	if (rdev->dummy_page.page == NULL)
260
		return;
261
    KernelFree(rdev->dummy_page.addr);
262
	rdev->dummy_page.page = NULL;
263
}
264
 
265
 
1117 serge 266
/*
267
 * Registers accessors functions.
268
 */
269
uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
270
{
271
    DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
272
    BUG_ON(1);
273
    return 0;
274
}
275
 
276
void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
277
{
278
    DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
279
          reg, v);
280
    BUG_ON(1);
281
}
282
 
283
void radeon_register_accessor_init(struct radeon_device *rdev)
284
{
285
    rdev->mc_rreg = &radeon_invalid_rreg;
286
    rdev->mc_wreg = &radeon_invalid_wreg;
287
    rdev->pll_rreg = &radeon_invalid_rreg;
288
    rdev->pll_wreg = &radeon_invalid_wreg;
289
    rdev->pciep_rreg = &radeon_invalid_rreg;
290
    rdev->pciep_wreg = &radeon_invalid_wreg;
291
 
292
    /* Don't change order as we are overridding accessor. */
293
    if (rdev->family < CHIP_RV515) {
1179 serge 294
		rdev->pcie_reg_mask = 0xff;
295
	} else {
296
		rdev->pcie_reg_mask = 0x7ff;
1117 serge 297
    }
298
    /* FIXME: not sure here */
299
    if (rdev->family <= CHIP_R580) {
1119 serge 300
        rdev->pll_rreg = &r100_pll_rreg;
301
        rdev->pll_wreg = &r100_pll_wreg;
1117 serge 302
    }
1179 serge 303
	if (rdev->family >= CHIP_R420) {
304
		rdev->mc_rreg = &r420_mc_rreg;
305
		rdev->mc_wreg = &r420_mc_wreg;
306
	}
1117 serge 307
    if (rdev->family >= CHIP_RV515) {
308
        rdev->mc_rreg = &rv515_mc_rreg;
309
        rdev->mc_wreg = &rv515_mc_wreg;
310
    }
311
    if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
1128 serge 312
        rdev->mc_rreg = &rs400_mc_rreg;
313
        rdev->mc_wreg = &rs400_mc_wreg;
1117 serge 314
    }
1221 serge 315
    if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
316
        rdev->mc_rreg = &rs690_mc_rreg;
317
        rdev->mc_wreg = &rs690_mc_wreg;
318
    }
319
    if (rdev->family == CHIP_RS600) {
320
        rdev->mc_rreg = &rs600_mc_rreg;
321
        rdev->mc_wreg = &rs600_mc_wreg;
322
    }
1233 serge 323
	if (rdev->family >= CHIP_R600) {
324
		rdev->pciep_rreg = &r600_pciep_rreg;
325
		rdev->pciep_wreg = &r600_pciep_wreg;
326
	}
1117 serge 327
}
328
 
329
 
330
/*
331
 * ASIC
332
 */
333
int radeon_asic_init(struct radeon_device *rdev)
334
{
335
    radeon_register_accessor_init(rdev);
336
	switch (rdev->family) {
337
	case CHIP_R100:
338
	case CHIP_RV100:
339
	case CHIP_RS100:
340
	case CHIP_RV200:
341
	case CHIP_RS200:
342
	case CHIP_R200:
343
	case CHIP_RV250:
344
	case CHIP_RS300:
345
	case CHIP_RV280:
1128 serge 346
        rdev->asic = &r100_asic;
1117 serge 347
		break;
348
	case CHIP_R300:
349
	case CHIP_R350:
350
	case CHIP_RV350:
351
	case CHIP_RV380:
1128 serge 352
        rdev->asic = &r300_asic;
1179 serge 353
		if (rdev->flags & RADEON_IS_PCIE) {
354
			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
355
			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
356
		}
1117 serge 357
		break;
358
	case CHIP_R420:
359
	case CHIP_R423:
360
	case CHIP_RV410:
1128 serge 361
        rdev->asic = &r420_asic;
1117 serge 362
		break;
363
	case CHIP_RS400:
364
	case CHIP_RS480:
1128 serge 365
       rdev->asic = &rs400_asic;
1117 serge 366
		break;
367
	case CHIP_RS600:
1221 serge 368
        rdev->asic = &rs600_asic;
1117 serge 369
		break;
370
	case CHIP_RS690:
371
	case CHIP_RS740:
1221 serge 372
        rdev->asic = &rs690_asic;
1117 serge 373
		break;
374
	case CHIP_RV515:
1128 serge 375
        rdev->asic = &rv515_asic;
1117 serge 376
		break;
377
	case CHIP_R520:
378
	case CHIP_RV530:
379
	case CHIP_RV560:
380
	case CHIP_RV570:
381
	case CHIP_R580:
382
        rdev->asic = &r520_asic;
383
		break;
384
	case CHIP_R600:
385
	case CHIP_RV610:
386
	case CHIP_RV630:
387
	case CHIP_RV620:
388
	case CHIP_RV635:
389
	case CHIP_RV670:
390
	case CHIP_RS780:
1221 serge 391
	case CHIP_RS880:
1233 serge 392
		rdev->asic = &r600_asic;
1221 serge 393
		break;
1117 serge 394
	case CHIP_RV770:
395
	case CHIP_RV730:
396
	case CHIP_RV710:
1221 serge 397
	case CHIP_RV740:
1233 serge 398
		rdev->asic = &rv770_asic;
1221 serge 399
		break;
1117 serge 400
	default:
401
		/* FIXME: not supported yet */
402
		return -EINVAL;
403
	}
404
	return 0;
405
}
406
 
407
 
408
/*
409
 * Wrapper around modesetting bits.
410
 */
411
int radeon_clocks_init(struct radeon_device *rdev)
412
{
413
	int r;
414
 
1179 serge 415
    ENTER();
1117 serge 416
 
417
    r = radeon_static_clocks_init(rdev->ddev);
418
	if (r) {
419
		return r;
420
	}
421
	DRM_INFO("Clocks initialized !\n");
422
	return 0;
423
}
424
 
425
void radeon_clocks_fini(struct radeon_device *rdev)
426
{
427
}
428
 
429
/* ATOM accessor methods */
430
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
431
{
432
    struct radeon_device *rdev = info->dev->dev_private;
433
    uint32_t r;
434
 
435
    r = rdev->pll_rreg(rdev, reg);
436
    return r;
437
}
438
 
439
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
440
{
441
    struct radeon_device *rdev = info->dev->dev_private;
442
 
443
    rdev->pll_wreg(rdev, reg, val);
444
}
445
 
446
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
447
{
448
    struct radeon_device *rdev = info->dev->dev_private;
449
    uint32_t r;
450
 
451
    r = rdev->mc_rreg(rdev, reg);
452
    return r;
453
}
454
 
455
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
456
{
457
    struct radeon_device *rdev = info->dev->dev_private;
458
 
459
    rdev->mc_wreg(rdev, reg, val);
460
}
461
 
462
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
463
{
464
    struct radeon_device *rdev = info->dev->dev_private;
465
 
466
    WREG32(reg*4, val);
467
}
468
 
469
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
470
{
471
    struct radeon_device *rdev = info->dev->dev_private;
472
    uint32_t r;
473
 
474
    r = RREG32(reg*4);
475
    return r;
476
}
477
 
478
static struct card_info atom_card_info = {
479
    .dev = NULL,
480
    .reg_read = cail_reg_read,
481
    .reg_write = cail_reg_write,
482
    .mc_read = cail_mc_read,
483
    .mc_write = cail_mc_write,
484
    .pll_read = cail_pll_read,
485
    .pll_write = cail_pll_write,
486
};
487
 
488
int radeon_atombios_init(struct radeon_device *rdev)
489
{
1179 serge 490
    ENTER();
1117 serge 491
 
492
    atom_card_info.dev = rdev->ddev;
493
    rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
494
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
495
    return 0;
496
}
497
 
498
void radeon_atombios_fini(struct radeon_device *rdev)
499
{
1119 serge 500
	kfree(rdev->mode_info.atom_context);
1117 serge 501
}
502
 
503
int radeon_combios_init(struct radeon_device *rdev)
504
{
1128 serge 505
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117 serge 506
	return 0;
507
}
508
 
509
void radeon_combios_fini(struct radeon_device *rdev)
510
{
511
}
512
 
1233 serge 513
/* if we get transitioned to only one device, tak VGA back */
514
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
515
{
516
	struct radeon_device *rdev = cookie;
517
	radeon_vga_set_state(rdev, state);
518
	if (state)
519
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
520
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
521
	else
522
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
523
}
1117 serge 524
 
1221 serge 525
void radeon_agp_disable(struct radeon_device *rdev)
526
{
527
	rdev->flags &= ~RADEON_IS_AGP;
528
	if (rdev->family >= CHIP_R600) {
529
		DRM_INFO("Forcing AGP to PCIE mode\n");
530
		rdev->flags |= RADEON_IS_PCIE;
531
	} else if (rdev->family >= CHIP_RV515 ||
532
			rdev->family == CHIP_RV380 ||
533
			rdev->family == CHIP_RV410 ||
534
			rdev->family == CHIP_R423) {
535
		DRM_INFO("Forcing AGP to PCIE mode\n");
536
		rdev->flags |= RADEON_IS_PCIE;
537
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
538
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
539
	} else {
540
		DRM_INFO("Forcing AGP to PCI mode\n");
541
		rdev->flags |= RADEON_IS_PCI;
542
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
543
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
544
	}
545
}
1179 serge 546
 
1117 serge 547
/*
548
 * Radeon device.
549
 */
550
int radeon_device_init(struct radeon_device *rdev,
551
               struct drm_device *ddev,
552
               struct pci_dev *pdev,
553
               uint32_t flags)
554
{
1221 serge 555
	int r;
1179 serge 556
	int dma_bits;
1117 serge 557
 
1179 serge 558
    ENTER();
1117 serge 559
 
560
    DRM_INFO("radeon: Initializing kernel modesetting.\n");
561
    rdev->shutdown = false;
562
    rdev->ddev = ddev;
563
    rdev->pdev = pdev;
564
    rdev->flags = flags;
565
    rdev->family = flags & RADEON_FAMILY_MASK;
566
    rdev->is_atom_bios = false;
567
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
568
    rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
569
    rdev->gpu_lockup = false;
1221 serge 570
	rdev->accel_working = false;
1117 serge 571
    /* mutex initialization are all done here so we
572
     * can recall function without having locking issues */
573
 //   mutex_init(&rdev->cs_mutex);
574
 //   mutex_init(&rdev->ib_pool.mutex);
575
 //   mutex_init(&rdev->cp.mutex);
576
 //   rwlock_init(&rdev->fence_drv.lock);
577
 
1179 serge 578
	/* Set asic functions */
579
	r = radeon_asic_init(rdev);
580
	if (r) {
581
		return r;
582
	}
583
 
1117 serge 584
    if (radeon_agpmode == -1) {
1221 serge 585
		radeon_agp_disable(rdev);
1117 serge 586
    }
587
 
1179 serge 588
	/* set DMA mask + need_dma32 flags.
589
	 * PCIE - can handle 40-bits.
590
	 * IGP - can handle 40-bits (in theory)
591
	 * AGP - generally dma32 is safest
592
	 * PCI - only dma32
593
	 */
594
	rdev->need_dma32 = false;
595
	if (rdev->flags & RADEON_IS_AGP)
596
		rdev->need_dma32 = true;
597
	if (rdev->flags & RADEON_IS_PCI)
598
		rdev->need_dma32 = true;
1117 serge 599
 
1179 serge 600
	dma_bits = rdev->need_dma32 ? 32 : 40;
601
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117 serge 602
    if (r) {
1119 serge 603
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
604
    }
1117 serge 605
 
606
    /* Registers mapping */
607
    /* TODO: block userspace mapping of io register */
608
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
609
 
610
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
611
 
612
    rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
613
                                   PG_SW+PG_NOCACHE);
614
 
615
    if (rdev->rmmio == NULL) {
616
        return -ENOMEM;
617
    }
618
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
619
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
620
 
1221 serge 621
	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
622
//	r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
623
//	if (r) {
624
//		return -EINVAL;
625
//	}
626
 
1179 serge 627
	r = radeon_init(rdev);
1221 serge 628
	if (r)
1117 serge 629
            return r;
630
 
1221 serge 631
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
632
		/* Acceleration not working on AGP card try again
633
		 * with fallback to PCI or PCIE GART
634
		 */
635
		radeon_gpu_reset(rdev);
636
		radeon_fini(rdev);
637
		radeon_agp_disable(rdev);
638
		r = radeon_init(rdev);
639
		if (r)
1179 serge 640
		return r;
1126 serge 641
	}
1179 serge 642
//	if (radeon_testing) {
643
//		radeon_test_moves(rdev);
1125 serge 644
//    }
1179 serge 645
//	if (radeon_benchmarking) {
646
//		radeon_benchmark(rdev);
647
//    }
648
	return 0;
1117 serge 649
}
650
 
1179 serge 651
 
1117 serge 652
/*
653
 * Driver load/unload
654
 */
655
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
656
{
657
    struct radeon_device *rdev;
658
    int r;
659
 
1182 serge 660
    ENTER();
1117 serge 661
 
1120 serge 662
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117 serge 663
    if (rdev == NULL) {
664
        return -ENOMEM;
665
    };
666
 
667
    dev->dev_private = (void *)rdev;
668
 
669
    /* update BUS flag */
1239 serge 670
    if (drm_device_is_agp(dev)) {
1117 serge 671
        flags |= RADEON_IS_AGP;
1239 serge 672
    } else if (drm_device_is_pcie(dev)) {
673
        flags |= RADEON_IS_PCIE;
674
    } else {
675
        flags |= RADEON_IS_PCI;
676
    }
1117 serge 677
 
1182 serge 678
    /* radeon_device_init should report only fatal error
679
     * like memory allocation failure or iomapping failure,
680
     * or memory manager initialization failure, it must
681
     * properly initialize the GPU MC controller and permit
682
     * VRAM allocation
683
     */
1117 serge 684
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
685
    if (r) {
1182 serge 686
        DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117 serge 687
        return r;
688
    }
1182 serge 689
    /* Again modeset_init should fail only on fatal error
690
     * otherwise it should provide enough functionalities
691
     * for shadowfb to run
692
     */
693
    r = radeon_modeset_init(rdev);
694
    if (r) {
695
        return r;
696
    }
1117 serge 697
    return 0;
698
}
699
 
1239 serge 700
mode_t usermode;
1230 serge 701
 
1239 serge 702
 
1117 serge 703
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
704
{
705
    struct drm_device *dev;
706
    int ret;
707
 
1221 serge 708
    ENTER();
1117 serge 709
 
710
    dev = malloc(sizeof(*dev));
711
    if (!dev)
712
        return -ENOMEM;
713
 
714
 //   ret = pci_enable_device(pdev);
715
 //   if (ret)
716
 //       goto err_g1;
717
 
718
 //   pci_set_master(pdev);
719
 
720
 //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
721
 //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
722
 //       goto err_g2;
723
 //   }
724
 
725
    dev->pdev = pdev;
726
    dev->pci_device = pdev->device;
727
    dev->pci_vendor = pdev->vendor;
728
 
1221 serge 729
    ret = radeon_driver_load_kms(dev, ent->driver_data );
730
    if (ret)
1117 serge 731
        goto err_g4;
732
 
733
 //   list_add_tail(&dev->driver_item, &driver->device_list);
734
 
735
 //   DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
736
 //        driver->name, driver->major, driver->minor, driver->patchlevel,
737
 //        driver->date, pci_name(pdev), dev->primary->index);
738
 
1233 serge 739
    init_display(dev->dev_private, &usermode);
1126 serge 740
 
1221 serge 741
    LEAVE();
742
 
1117 serge 743
    return 0;
744
 
745
err_g4:
746
//    drm_put_minor(&dev->primary);
747
//err_g3:
748
//    if (drm_core_check_feature(dev, DRIVER_MODESET))
749
//        drm_put_minor(&dev->control);
750
//err_g2:
751
//    pci_disable_device(pdev);
752
//err_g1:
753
    free(dev);
754
 
1221 serge 755
    LEAVE();
756
 
1117 serge 757
    return ret;
758
}
759
 
760
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
761
{
762
    return pci_resource_start(dev->pdev, resource);
763
}
764
 
765
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
766
{
767
    return pci_resource_len(dev->pdev, resource);
768
}
769
 
1123 serge 770
 
771
uint32_t __div64_32(uint64_t *n, uint32_t base)
772
{
773
        uint64_t rem = *n;
774
        uint64_t b = base;
775
        uint64_t res, d = 1;
776
        uint32_t high = rem >> 32;
777
 
778
        /* Reduce the thing a bit first */
779
        res = 0;
780
        if (high >= base) {
781
                high /= base;
782
                res = (uint64_t) high << 32;
783
                rem -= (uint64_t) (high*base) << 32;
784
        }
785
 
786
        while ((int64_t)b > 0 && b < rem) {
787
                b = b+b;
788
                d = d+d;
789
        }
790
 
791
        do {
792
                if (rem >= b) {
793
                        rem -= b;
794
                        res += d;
795
                }
796
                b >>= 1;
797
                d >>= 1;
798
        } while (d);
799
 
800
        *n = res;
801
        return rem;
802
}
803
 
1239 serge 804
 
805
static struct pci_device_id pciidlist[] = {
806
    radeon_PCI_IDS
807
};
808
 
809
 
810
#define API_VERSION     0x01000100
811
 
812
#define SRV_GETVERSION  0
813
#define SRV_ENUM_MODES  1
814
#define SRV_SET_MODE    2
815
 
816
int _stdcall display_handler(ioctl_t *io)
817
{
818
    int    retval = -1;
819
    u32_t *inp;
820
    u32_t *outp;
821
 
822
    inp = io->input;
823
    outp = io->output;
824
 
825
    switch(io->io_code)
826
    {
827
        case SRV_GETVERSION:
828
            if(io->out_size==4)
829
            {
830
                *outp  = API_VERSION;
831
                retval = 0;
832
            }
833
            break;
834
 
835
        case SRV_ENUM_MODES:
836
            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
837
                       inp, io->inp_size, io->out_size );
838
 
839
            if( (outp != NULL) && (io->out_size == 4) &&
840
                (io->inp_size == *outp * sizeof(mode_t)) )
841
                {
842
                retval = get_modes((mode_t*)inp, outp);
843
            };
844
            break;
845
 
846
        case SRV_SET_MODE:
847
            if( (inp != NULL) &&
848
                (io->inp_size == sizeof(mode_t)) )
849
            {
850
                retval = set_user_mode((mode_t*)inp);
851
            };
852
            break;
853
 
854
    };
855
 
856
    return retval;
857
}
858
 
859
u32_t drvEntry(int action, char *cmdline)
860
{
861
    static char log[256];
862
 
863
    struct pci_device_id  *ent;
864
 
865
    dev_t   device;
866
    int     err;
867
    u32_t   retval = 0;
868
 
869
    if(action != 1)
870
        return 0;
871
 
872
    if( GetService("DISPLAY") != 0 )
873
        return 0;
874
 
875
    if( cmdline && *cmdline )
876
        parse_cmdline(cmdline, &usermode, log);
877
 
878
    if(!dbg_open(log))
879
    {
880
        strcpy(log, "/rd/1/drivers/atikms.log");
881
 
882
        if(!dbg_open(log))
883
        {
884
            printf("Can't open %s\nExit\n", log);
885
            return 0;
886
        };
887
    }
888
 
889
    enum_pci_devices();
890
 
891
    ent = find_pci_device(&device, pciidlist);
892
 
893
    if( unlikely(ent == NULL) )
894
    {
895
        dbgprintf("device not found\n");
896
        return 0;
897
    };
898
 
899
    dbgprintf("device %x:%x\n", device.pci_dev.vendor,
900
                                device.pci_dev.device);
901
 
902
    err = drm_get_dev(&device.pci_dev, ent);
903
 
904
    return RegService("DISPLAY", display_handler);
905
 
906
};