WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_device.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
1123	serge	29
1179	serge	30	#include
		31	#include
1221	serge	32	#include
1117	serge	33	#include "radeon_reg.h"
		34	#include "radeon.h"
		35	#include "radeon_asic.h"
		36	#include "atom.h"
		37
1221	serge	38	#include
		39
1117	serge	40
		41	int radeon_dynclks = -1;
1123	serge	42	int radeon_r4xx_atom = 0;
1125	serge	43	int radeon_agpmode = -1;
1117	serge	44	int radeon_gart_size = 512; /* default gart size */
1123	serge	45	int radeon_benchmarking = 0;
		46	int radeon_connector_table = 0;
1222	serge	47	int radeon_tv = 0;
1117	serge	48
1233	serge	49	void parse_cmdline(char cmdline, mode_t mode, char *log);
		50	int init_display(struct radeon_device rdev, mode_t mode);
1117	serge	51
1233	serge	52	/* Legacy VGA regions */
		53	#define VGA_RSRC_NONE 0x00
		54	#define VGA_RSRC_LEGACY_IO 0x01
		55	#define VGA_RSRC_LEGACY_MEM 0x02
		56	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
		57	/* Non-legacy access */
		58	#define VGA_RSRC_NORMAL_IO 0x04
		59	#define VGA_RSRC_NORMAL_MEM 0x08
		60
		61
		62
1117	serge	63	/*
		64	* Clear GPU surface registers.
		65	*/
1179	serge	66	void radeon_surface_init(struct radeon_device *rdev)
1117	serge	67	{
1179	serge	68	ENTER();
1117	serge	69
		70	/* FIXME: check this out */
		71	if (rdev->family < CHIP_R600) {
		72	int i;
		73
		74	for (i = 0; i < 8; i++) {
		75	WREG32(RADEON_SURFACE0_INFO +
		76	i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
		77	0);
		78	}
1179	serge	79	/* enable surfaces */
		80	WREG32(RADEON_SURFACE_CNTL, 0);
1117	serge	81	}
		82	}
		83
		84	/*
		85	* GPU scratch registers helpers function.
		86	*/
1179	serge	87	void radeon_scratch_init(struct radeon_device *rdev)
1117	serge	88	{
		89	int i;
		90
		91	/* FIXME: check this out */
		92	if (rdev->family < CHIP_R300) {
		93	rdev->scratch.num_reg = 5;
		94	} else {
		95	rdev->scratch.num_reg = 7;
		96	}
		97	for (i = 0; i < rdev->scratch.num_reg; i++) {
		98	rdev->scratch.free[i] = true;
		99	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
		100	}
		101	}
		102
		103	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
		104	{
		105	int i;
		106
		107	for (i = 0; i < rdev->scratch.num_reg; i++) {
		108	if (rdev->scratch.free[i]) {
		109	rdev->scratch.free[i] = false;
		110	*reg = rdev->scratch.reg[i];
		111	return 0;
		112	}
		113	}
		114	return -EINVAL;
		115	}
		116
		117	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
		118	{
		119	int i;
		120
		121	for (i = 0; i < rdev->scratch.num_reg; i++) {
		122	if (rdev->scratch.reg[i] == reg) {
		123	rdev->scratch.free[i] = true;
		124	return;
		125	}
		126	}
		127	}
		128
		129	/*
		130	* MC common functions
		131	*/
		132	int radeon_mc_setup(struct radeon_device *rdev)
		133	{
		134	uint32_t tmp;
		135
		136	/* Some chips have an "issue" with the memory controller, the
		137	* location must be aligned to the size. We just align it down,
		138	* too bad if we walk over the top of system memory, we don't
		139	* use DMA without a remapped anyway.
		140	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
		141	*/
		142	/* FGLRX seems to setup like this, VRAM a 0, then GART.
		143	*/
1126	serge	144	/*
1117	serge	145	* Note: from R6xx the address space is 40bits but here we only
		146	* use 32bits (still have to see a card which would exhaust 4G
		147	* address space).
		148	*/
		149	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		150	/* vram location was already setup try to put gtt after
		151	* if it fits */
1179	serge	152	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
1117	serge	153	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		154	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
		155	rdev->mc.gtt_location = tmp;
		156	} else {
		157	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
		158	printk(KERN_ERR "[drm] GTT too big to fit "
		159	"before or after vram location.\n");
		160	return -EINVAL;
		161	}
		162	rdev->mc.gtt_location = 0;
		163	}
		164	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		165	/* gtt location was already setup try to put vram before
		166	* if it fits */
1179	serge	167	if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
1117	serge	168	rdev->mc.vram_location = 0;
		169	} else {
		170	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
1179	serge	171	tmp += (rdev->mc.mc_vram_size - 1);
		172	tmp &= ~(rdev->mc.mc_vram_size - 1);
		173	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
1117	serge	174	rdev->mc.vram_location = tmp;
		175	} else {
		176	printk(KERN_ERR "[drm] vram too big to fit "
		177	"before or after GTT location.\n");
		178	return -EINVAL;
		179	}
		180	}
		181	} else {
		182	rdev->mc.vram_location = 0;
1179	serge	183	tmp = rdev->mc.mc_vram_size;
		184	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		185	rdev->mc.gtt_location = tmp;
1117	serge	186	}
1179	serge	187	rdev->mc.vram_start = rdev->mc.vram_location;
		188	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
		189	rdev->mc.gtt_start = rdev->mc.gtt_location;
		190	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		191	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
1117	serge	192	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
1179	serge	193	(unsigned)rdev->mc.vram_location,
		194	(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
		195	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
1117	serge	196	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
1179	serge	197	(unsigned)rdev->mc.gtt_location,
		198	(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
1117	serge	199	return 0;
		200	}
		201
		202
		203	/*
		204	* GPU helpers function.
		205	*/
1179	serge	206	bool radeon_card_posted(struct radeon_device *rdev)
1117	serge	207	{
		208	uint32_t reg;
		209
1179	serge	210	ENTER();
1117	serge	211
		212	/* first check CRTCs */
		213	if (ASIC_IS_AVIVO(rdev)) {
		214	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
		215	RREG32(AVIVO_D2CRTC_CONTROL);
		216	if (reg & AVIVO_CRTC_EN) {
		217	return true;
		218	}
		219	} else {
		220	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
		221	RREG32(RADEON_CRTC2_GEN_CNTL);
		222	if (reg & RADEON_CRTC_EN) {
		223	return true;
		224	}
		225	}
		226
		227	/* then check MEM_SIZE, in case the crtcs are off */
		228	if (rdev->family >= CHIP_R600)
		229	reg = RREG32(R600_CONFIG_MEMSIZE);
		230	else
		231	reg = RREG32(RADEON_CONFIG_MEMSIZE);
		232
		233	if (reg)
		234	return true;
		235
		236	return false;
		237
		238	}
		239
1233	serge	240	int radeon_dummy_page_init(struct radeon_device *rdev)
		241	{
		242	rdev->dummy_page.page = AllocPage();
		243	if (rdev->dummy_page.page == NULL)
		244	return -ENOMEM;
		245	rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
		246	if (!rdev->dummy_page.addr) {
		247	// __free_page(rdev->dummy_page.page);
		248	rdev->dummy_page.page = NULL;
		249	return -ENOMEM;
		250	}
		251	return 0;
		252	}
1117	serge	253
1233	serge	254	void radeon_dummy_page_fini(struct radeon_device *rdev)
		255	{
		256	if (rdev->dummy_page.page == NULL)
		257	return;
		258	KernelFree(rdev->dummy_page.addr);
		259	rdev->dummy_page.page = NULL;
		260	}
		261
		262
1117	serge	263	/*
		264	* Registers accessors functions.
		265	*/
		266	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		267	{
		268	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		269	BUG_ON(1);
		270	return 0;
		271	}
		272
		273	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		274	{
		275	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		276	reg, v);
		277	BUG_ON(1);
		278	}
		279
		280	void radeon_register_accessor_init(struct radeon_device *rdev)
		281	{
		282	rdev->mc_rreg = &radeon_invalid_rreg;
		283	rdev->mc_wreg = &radeon_invalid_wreg;
		284	rdev->pll_rreg = &radeon_invalid_rreg;
		285	rdev->pll_wreg = &radeon_invalid_wreg;
		286	rdev->pciep_rreg = &radeon_invalid_rreg;
		287	rdev->pciep_wreg = &radeon_invalid_wreg;
		288
		289	/* Don't change order as we are overridding accessor. */
		290	if (rdev->family < CHIP_RV515) {
1179	serge	291	rdev->pcie_reg_mask = 0xff;
		292	} else {
		293	rdev->pcie_reg_mask = 0x7ff;
1117	serge	294	}
		295	/* FIXME: not sure here */
		296	if (rdev->family <= CHIP_R580) {
1119	serge	297	rdev->pll_rreg = &r100_pll_rreg;
		298	rdev->pll_wreg = &r100_pll_wreg;
1117	serge	299	}
1179	serge	300	if (rdev->family >= CHIP_R420) {
		301	rdev->mc_rreg = &r420_mc_rreg;
		302	rdev->mc_wreg = &r420_mc_wreg;
		303	}
1117	serge	304	if (rdev->family >= CHIP_RV515) {
		305	rdev->mc_rreg = &rv515_mc_rreg;
		306	rdev->mc_wreg = &rv515_mc_wreg;
		307	}
		308	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
1128	serge	309	rdev->mc_rreg = &rs400_mc_rreg;
		310	rdev->mc_wreg = &rs400_mc_wreg;
1117	serge	311	}
1221	serge	312	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		313	rdev->mc_rreg = &rs690_mc_rreg;
		314	rdev->mc_wreg = &rs690_mc_wreg;
		315	}
		316	if (rdev->family == CHIP_RS600) {
		317	rdev->mc_rreg = &rs600_mc_rreg;
		318	rdev->mc_wreg = &rs600_mc_wreg;
		319	}
1233	serge	320	if (rdev->family >= CHIP_R600) {
		321	rdev->pciep_rreg = &r600_pciep_rreg;
		322	rdev->pciep_wreg = &r600_pciep_wreg;
		323	}
1117	serge	324	}
		325
		326
		327	/*
		328	* ASIC
		329	*/
		330	int radeon_asic_init(struct radeon_device *rdev)
		331	{
		332	radeon_register_accessor_init(rdev);
		333	switch (rdev->family) {
		334	case CHIP_R100:
		335	case CHIP_RV100:
		336	case CHIP_RS100:
		337	case CHIP_RV200:
		338	case CHIP_RS200:
		339	case CHIP_R200:
		340	case CHIP_RV250:
		341	case CHIP_RS300:
		342	case CHIP_RV280:
1128	serge	343	rdev->asic = &r100_asic;
1117	serge	344	break;
		345	case CHIP_R300:
		346	case CHIP_R350:
		347	case CHIP_RV350:
		348	case CHIP_RV380:
1128	serge	349	rdev->asic = &r300_asic;
1179	serge	350	if (rdev->flags & RADEON_IS_PCIE) {
		351	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		352	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		353	}
1117	serge	354	break;
		355	case CHIP_R420:
		356	case CHIP_R423:
		357	case CHIP_RV410:
1128	serge	358	rdev->asic = &r420_asic;
1117	serge	359	break;
		360	case CHIP_RS400:
		361	case CHIP_RS480:
1128	serge	362	rdev->asic = &rs400_asic;
1117	serge	363	break;
		364	case CHIP_RS600:
1221	serge	365	rdev->asic = &rs600_asic;
1117	serge	366	break;
		367	case CHIP_RS690:
		368	case CHIP_RS740:
1221	serge	369	rdev->asic = &rs690_asic;
1117	serge	370	break;
		371	case CHIP_RV515:
1128	serge	372	rdev->asic = &rv515_asic;
1117	serge	373	break;
		374	case CHIP_R520:
		375	case CHIP_RV530:
		376	case CHIP_RV560:
		377	case CHIP_RV570:
		378	case CHIP_R580:
		379	rdev->asic = &r520_asic;
		380	break;
		381	case CHIP_R600:
		382	case CHIP_RV610:
		383	case CHIP_RV630:
		384	case CHIP_RV620:
		385	case CHIP_RV635:
		386	case CHIP_RV670:
		387	case CHIP_RS780:
1221	serge	388	case CHIP_RS880:
1233	serge	389	rdev->asic = &r600_asic;
1221	serge	390	break;
1117	serge	391	case CHIP_RV770:
		392	case CHIP_RV730:
		393	case CHIP_RV710:
1221	serge	394	case CHIP_RV740:
1233	serge	395	rdev->asic = &rv770_asic;
1221	serge	396	break;
1117	serge	397	default:
		398	/* FIXME: not supported yet */
		399	return -EINVAL;
		400	}
		401	return 0;
		402	}
		403
		404
		405	/*
		406	* Wrapper around modesetting bits.
		407	*/
		408	int radeon_clocks_init(struct radeon_device *rdev)
		409	{
		410	int r;
		411
1179	serge	412	ENTER();
1117	serge	413
		414	r = radeon_static_clocks_init(rdev->ddev);
		415	if (r) {
		416	return r;
		417	}
		418	DRM_INFO("Clocks initialized !\n");
		419	return 0;
		420	}
		421
		422	void radeon_clocks_fini(struct radeon_device *rdev)
		423	{
		424	}
		425
		426	/* ATOM accessor methods */
		427	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
		428	{
		429	struct radeon_device *rdev = info->dev->dev_private;
		430	uint32_t r;
		431
		432	r = rdev->pll_rreg(rdev, reg);
		433	return r;
		434	}
		435
		436	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
		437	{
		438	struct radeon_device *rdev = info->dev->dev_private;
		439
		440	rdev->pll_wreg(rdev, reg, val);
		441	}
		442
		443	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
		444	{
		445	struct radeon_device *rdev = info->dev->dev_private;
		446	uint32_t r;
		447
		448	r = rdev->mc_rreg(rdev, reg);
		449	return r;
		450	}
		451
		452	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
		453	{
		454	struct radeon_device *rdev = info->dev->dev_private;
		455
		456	rdev->mc_wreg(rdev, reg, val);
		457	}
		458
		459	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
		460	{
		461	struct radeon_device *rdev = info->dev->dev_private;
		462
		463	WREG32(reg*4, val);
		464	}
		465
		466	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
		467	{
		468	struct radeon_device *rdev = info->dev->dev_private;
		469	uint32_t r;
		470
		471	r = RREG32(reg*4);
		472	return r;
		473	}
		474
		475	static struct card_info atom_card_info = {
		476	.dev = NULL,
		477	.reg_read = cail_reg_read,
		478	.reg_write = cail_reg_write,
		479	.mc_read = cail_mc_read,
		480	.mc_write = cail_mc_write,
		481	.pll_read = cail_pll_read,
		482	.pll_write = cail_pll_write,
		483	};
		484
		485	int radeon_atombios_init(struct radeon_device *rdev)
		486	{
1179	serge	487	ENTER();
1117	serge	488
		489	atom_card_info.dev = rdev->ddev;
		490	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
		491	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
		492	return 0;
		493	}
		494
		495	void radeon_atombios_fini(struct radeon_device *rdev)
		496	{
1119	serge	497	kfree(rdev->mode_info.atom_context);
1117	serge	498	}
		499
		500	int radeon_combios_init(struct radeon_device *rdev)
		501	{
1128	serge	502	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117	serge	503	return 0;
		504	}
		505
		506	void radeon_combios_fini(struct radeon_device *rdev)
		507	{
		508	}
		509
1233	serge	510	/* if we get transitioned to only one device, tak VGA back */
		511	static unsigned int radeon_vga_set_decode(void *cookie, bool state)
		512	{
		513	struct radeon_device *rdev = cookie;
		514	radeon_vga_set_state(rdev, state);
		515	if (state)
		516	return VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM \|
		517	VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		518	else
		519	return VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		520	}
1117	serge	521
1221	serge	522	void radeon_agp_disable(struct radeon_device *rdev)
		523	{
		524	rdev->flags &= ~RADEON_IS_AGP;
		525	if (rdev->family >= CHIP_R600) {
		526	DRM_INFO("Forcing AGP to PCIE mode\n");
		527	rdev->flags \|= RADEON_IS_PCIE;
		528	} else if (rdev->family >= CHIP_RV515 \|\|
		529	rdev->family == CHIP_RV380 \|\|
		530	rdev->family == CHIP_RV410 \|\|
		531	rdev->family == CHIP_R423) {
		532	DRM_INFO("Forcing AGP to PCIE mode\n");
		533	rdev->flags \|= RADEON_IS_PCIE;
		534	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		535	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		536	} else {
		537	DRM_INFO("Forcing AGP to PCI mode\n");
		538	rdev->flags \|= RADEON_IS_PCI;
		539	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		540	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		541	}
		542	}
1179	serge	543
1117	serge	544	/*
		545	* Radeon device.
		546	*/
		547	int radeon_device_init(struct radeon_device *rdev,
		548	struct drm_device *ddev,
		549	struct pci_dev *pdev,
		550	uint32_t flags)
		551	{
1221	serge	552	int r;
1179	serge	553	int dma_bits;
1117	serge	554
1179	serge	555	ENTER();
1117	serge	556
		557	DRM_INFO("radeon: Initializing kernel modesetting.\n");
		558	rdev->shutdown = false;
		559	rdev->ddev = ddev;
		560	rdev->pdev = pdev;
		561	rdev->flags = flags;
		562	rdev->family = flags & RADEON_FAMILY_MASK;
		563	rdev->is_atom_bios = false;
		564	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
		565	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		566	rdev->gpu_lockup = false;
1221	serge	567	rdev->accel_working = false;
1117	serge	568	/* mutex initialization are all done here so we
		569	* can recall function without having locking issues */
		570	// mutex_init(&rdev->cs_mutex);
		571	// mutex_init(&rdev->ib_pool.mutex);
		572	// mutex_init(&rdev->cp.mutex);
		573	// rwlock_init(&rdev->fence_drv.lock);
		574
1179	serge	575	/* Set asic functions */
		576	r = radeon_asic_init(rdev);
		577	if (r) {
		578	return r;
		579	}
		580
1117	serge	581	if (radeon_agpmode == -1) {
1221	serge	582	radeon_agp_disable(rdev);
1117	serge	583	}
		584
1179	serge	585	/* set DMA mask + need_dma32 flags.
		586	* PCIE - can handle 40-bits.
		587	* IGP - can handle 40-bits (in theory)
		588	* AGP - generally dma32 is safest
		589	* PCI - only dma32
		590	*/
		591	rdev->need_dma32 = false;
		592	if (rdev->flags & RADEON_IS_AGP)
		593	rdev->need_dma32 = true;
		594	if (rdev->flags & RADEON_IS_PCI)
		595	rdev->need_dma32 = true;
1117	serge	596
1179	serge	597	dma_bits = rdev->need_dma32 ? 32 : 40;
		598	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117	serge	599	if (r) {
1119	serge	600	printk(KERN_WARNING "radeon: No suitable DMA available.\n");
		601	}
1117	serge	602
		603	/* Registers mapping */
		604	/* TODO: block userspace mapping of io register */
		605	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
		606
		607	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
		608
		609	rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
		610	PG_SW+PG_NOCACHE);
		611
		612	if (rdev->rmmio == NULL) {
		613	return -ENOMEM;
		614	}
		615	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
		616	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
		617
1221	serge	618	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
		619	// r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
		620	// if (r) {
		621	// return -EINVAL;
		622	// }
		623
1179	serge	624	r = radeon_init(rdev);
1221	serge	625	if (r)
1117	serge	626	return r;
		627
1221	serge	628	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		629	/* Acceleration not working on AGP card try again
		630	* with fallback to PCI or PCIE GART
		631	*/
		632	radeon_gpu_reset(rdev);
		633	radeon_fini(rdev);
		634	radeon_agp_disable(rdev);
		635	r = radeon_init(rdev);
		636	if (r)
1179	serge	637	return r;
1126	serge	638	}
1179	serge	639	// if (radeon_testing) {
		640	// radeon_test_moves(rdev);
1125	serge	641	// }
1179	serge	642	// if (radeon_benchmarking) {
		643	// radeon_benchmark(rdev);
		644	// }
		645	return 0;
1117	serge	646	}
		647
1179	serge	648
1117	serge	649	static struct pci_device_id pciidlist[] = {
		650	radeon_PCI_IDS
		651	};
		652
1233	serge	653	mode_t usermode;
		654	char log[256];
1117	serge	655
1179	serge	656	u32_t drvEntry(int action, char *cmdline)
1117	serge	657	{
		658	struct pci_device_id *ent;
		659
		660	dev_t device;
		661	int err;
		662	u32_t retval = 0;
		663
		664	if(action != 1)
		665	return 0;
		666
1233	serge	667	if( cmdline && *cmdline )
		668	parse_cmdline(cmdline, &usermode, log);
		669
		670	if(!dbg_open(log))
1117	serge	671	{
1233	serge	672	strcpy(log, "/rd/1/drivers/atikms.log");
		673
		674	if(!dbg_open(log))
		675	{
		676	printf("Can't open %s\nExit\n", log);
1117	serge	677	return 0;
1233	serge	678	};
1117	serge	679	}
		680
		681	enum_pci_devices();
		682
		683	ent = find_pci_device(&device, pciidlist);
		684
		685	if( unlikely(ent == NULL) )
		686	{
		687	dbgprintf("device not found\n");
		688	return 0;
		689	};
		690
		691	dbgprintf("device %x:%x\n", device.pci_dev.vendor,
		692	device.pci_dev.device);
		693
		694	err = drm_get_dev(&device.pci_dev, ent);
		695
		696	return retval;
		697	};
		698
		699
		700
		701	/*
		702	* Driver load/unload
		703	*/
		704	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
		705	{
		706	struct radeon_device *rdev;
		707	int r;
		708
1182	serge	709	ENTER();
1117	serge	710
1120	serge	711	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117	serge	712	if (rdev == NULL) {
		713	return -ENOMEM;
		714	};
		715
		716	dev->dev_private = (void *)rdev;
		717
		718	/* update BUS flag */
		719	// if (drm_device_is_agp(dev)) {
		720	flags \|= RADEON_IS_AGP;
		721	// } else if (drm_device_is_pcie(dev)) {
		722	// flags \|= RADEON_IS_PCIE;
		723	// } else {
		724	// flags \|= RADEON_IS_PCI;
		725	// }
		726
1182	serge	727	/* radeon_device_init should report only fatal error
		728	* like memory allocation failure or iomapping failure,
		729	* or memory manager initialization failure, it must
		730	* properly initialize the GPU MC controller and permit
		731	* VRAM allocation
		732	*/
1117	serge	733	r = radeon_device_init(rdev, dev, dev->pdev, flags);
		734	if (r) {
1182	serge	735	DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117	serge	736	return r;
		737	}
1182	serge	738	/* Again modeset_init should fail only on fatal error
		739	* otherwise it should provide enough functionalities
		740	* for shadowfb to run
		741	*/
		742	r = radeon_modeset_init(rdev);
		743	if (r) {
		744	return r;
		745	}
1117	serge	746	return 0;
		747	}
		748
1230	serge	749
1117	serge	750	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		751	{
		752	struct drm_device *dev;
		753	int ret;
		754
1221	serge	755	ENTER();
1117	serge	756
		757	dev = malloc(sizeof(*dev));
		758	if (!dev)
		759	return -ENOMEM;
		760
		761	// ret = pci_enable_device(pdev);
		762	// if (ret)
		763	// goto err_g1;
		764
		765	// pci_set_master(pdev);
		766
		767	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		768	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		769	// goto err_g2;
		770	// }
		771
		772	dev->pdev = pdev;
		773	dev->pci_device = pdev->device;
		774	dev->pci_vendor = pdev->vendor;
		775
1221	serge	776	ret = radeon_driver_load_kms(dev, ent->driver_data );
		777	if (ret)
1117	serge	778	goto err_g4;
		779
		780	// list_add_tail(&dev->driver_item, &driver->device_list);
		781
		782	// DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
		783	// driver->name, driver->major, driver->minor, driver->patchlevel,
		784	// driver->date, pci_name(pdev), dev->primary->index);
		785
1233	serge	786	init_display(dev->dev_private, &usermode);
1126	serge	787
1221	serge	788	LEAVE();
		789
1117	serge	790	return 0;
		791
		792	err_g4:
		793	// drm_put_minor(&dev->primary);
		794	//err_g3:
		795	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		796	// drm_put_minor(&dev->control);
		797	//err_g2:
		798	// pci_disable_device(pdev);
		799	//err_g1:
		800	free(dev);
		801
1221	serge	802	LEAVE();
		803
1117	serge	804	return ret;
		805	}
		806
		807	resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
		808	{
		809	return pci_resource_start(dev->pdev, resource);
		810	}
		811
		812	resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
		813	{
		814	return pci_resource_len(dev->pdev, resource);
		815	}
		816
1123	serge	817
		818	uint32_t __div64_32(uint64_t *n, uint32_t base)
		819	{
		820	uint64_t rem = *n;
		821	uint64_t b = base;
		822	uint64_t res, d = 1;
		823	uint32_t high = rem >> 32;
		824
		825	/* Reduce the thing a bit first */
		826	res = 0;
		827	if (high >= base) {
		828	high /= base;
		829	res = (uint64_t) high << 32;
		830	rem -= (uint64_t) (high*base) << 32;
		831	}
		832
		833	while ((int64_t)b > 0 && b < rem) {
		834	b = b+b;
		835	d = d+d;
		836	}
		837
		838	do {
		839	if (rem >= b) {
		840	rem -= b;
		841	res += d;
		842	}
		843	b >>= 1;
		844	d >>= 1;
		845	} while (d);
		846
		847	*n = res;
		848	return rem;
		849	}
		850

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c – Rev 1233