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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
30 | #include |
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1117 | serge | 31 | //#include |
32 | #include "radeon_drm.h" |
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33 | #include "radeon_reg.h" |
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34 | #include "radeon.h" |
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35 | #include "radeon_asic.h" |
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36 | #include "atom.h" |
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37 | |||
38 | #include |
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39 | |||
40 | int radeon_dynclks = -1; |
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1123 | serge | 41 | int radeon_r4xx_atom = 0; |
1125 | serge | 42 | int radeon_agpmode = -1; |
1117 | serge | 43 | int radeon_gart_size = 512; /* default gart size */ |
1123 | serge | 44 | int radeon_benchmarking = 0; |
45 | int radeon_connector_table = 0; |
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1117 | serge | 46 | |
47 | |||
48 | /* |
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49 | * Clear GPU surface registers. |
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50 | */ |
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51 | static void radeon_surface_init(struct radeon_device *rdev) |
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52 | { |
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1120 | serge | 53 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 54 | |
55 | /* FIXME: check this out */ |
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56 | if (rdev->family < CHIP_R600) { |
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57 | int i; |
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58 | |||
59 | for (i = 0; i < 8; i++) { |
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60 | WREG32(RADEON_SURFACE0_INFO + |
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61 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
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62 | 0); |
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63 | } |
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64 | } |
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65 | } |
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66 | |||
67 | /* |
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68 | * GPU scratch registers helpers function. |
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69 | */ |
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70 | static void radeon_scratch_init(struct radeon_device *rdev) |
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71 | { |
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72 | int i; |
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73 | |||
74 | /* FIXME: check this out */ |
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75 | if (rdev->family < CHIP_R300) { |
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76 | rdev->scratch.num_reg = 5; |
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77 | } else { |
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78 | rdev->scratch.num_reg = 7; |
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79 | } |
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80 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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81 | rdev->scratch.free[i] = true; |
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82 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
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83 | } |
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84 | } |
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85 | |||
86 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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87 | { |
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88 | int i; |
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89 | |||
90 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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91 | if (rdev->scratch.free[i]) { |
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92 | rdev->scratch.free[i] = false; |
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93 | *reg = rdev->scratch.reg[i]; |
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94 | return 0; |
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95 | } |
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96 | } |
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97 | return -EINVAL; |
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98 | } |
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99 | |||
100 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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101 | { |
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102 | int i; |
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103 | |||
104 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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105 | if (rdev->scratch.reg[i] == reg) { |
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106 | rdev->scratch.free[i] = true; |
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107 | return; |
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108 | } |
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109 | } |
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110 | } |
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111 | |||
112 | /* |
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113 | * MC common functions |
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114 | */ |
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115 | int radeon_mc_setup(struct radeon_device *rdev) |
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116 | { |
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117 | uint32_t tmp; |
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118 | |||
119 | /* Some chips have an "issue" with the memory controller, the |
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120 | * location must be aligned to the size. We just align it down, |
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121 | * too bad if we walk over the top of system memory, we don't |
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122 | * use DMA without a remapped anyway. |
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123 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
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124 | */ |
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125 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
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126 | */ |
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127 | /* |
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128 | * Note: from R6xx the address space is 40bits but here we only |
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129 | * use 32bits (still have to see a card which would exhaust 4G |
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130 | * address space). |
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131 | */ |
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132 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
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133 | /* vram location was already setup try to put gtt after |
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134 | * if it fits */ |
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135 | tmp = rdev->mc.vram_location + rdev->mc.vram_size; |
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136 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
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137 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
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138 | rdev->mc.gtt_location = tmp; |
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139 | } else { |
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140 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
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141 | printk(KERN_ERR "[drm] GTT too big to fit " |
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142 | "before or after vram location.\n"); |
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143 | return -EINVAL; |
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144 | } |
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145 | rdev->mc.gtt_location = 0; |
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146 | } |
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147 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
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148 | /* gtt location was already setup try to put vram before |
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149 | * if it fits */ |
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150 | if (rdev->mc.vram_size < rdev->mc.gtt_location) { |
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151 | rdev->mc.vram_location = 0; |
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152 | } else { |
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153 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
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154 | tmp += (rdev->mc.vram_size - 1); |
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155 | tmp &= ~(rdev->mc.vram_size - 1); |
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156 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { |
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157 | rdev->mc.vram_location = tmp; |
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158 | } else { |
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159 | printk(KERN_ERR "[drm] vram too big to fit " |
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160 | "before or after GTT location.\n"); |
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161 | return -EINVAL; |
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162 | } |
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163 | } |
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164 | } else { |
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165 | rdev->mc.vram_location = 0; |
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166 | rdev->mc.gtt_location = rdev->mc.vram_size; |
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167 | } |
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168 | DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); |
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169 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
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170 | rdev->mc.vram_location, |
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171 | rdev->mc.vram_location + rdev->mc.vram_size - 1); |
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172 | DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); |
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173 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
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174 | rdev->mc.gtt_location, |
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175 | rdev->mc.gtt_location + rdev->mc.gtt_size - 1); |
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176 | return 0; |
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177 | } |
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178 | |||
179 | |||
180 | /* |
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181 | * GPU helpers function. |
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182 | */ |
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183 | static bool radeon_card_posted(struct radeon_device *rdev) |
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184 | { |
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185 | uint32_t reg; |
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186 | |||
1120 | serge | 187 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 188 | |
189 | /* first check CRTCs */ |
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190 | if (ASIC_IS_AVIVO(rdev)) { |
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191 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
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192 | RREG32(AVIVO_D2CRTC_CONTROL); |
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193 | if (reg & AVIVO_CRTC_EN) { |
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194 | return true; |
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195 | } |
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196 | } else { |
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197 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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198 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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199 | if (reg & RADEON_CRTC_EN) { |
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200 | return true; |
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201 | } |
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202 | } |
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203 | |||
204 | /* then check MEM_SIZE, in case the crtcs are off */ |
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205 | if (rdev->family >= CHIP_R600) |
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206 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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207 | else |
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208 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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209 | |||
210 | if (reg) |
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211 | return true; |
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212 | |||
213 | return false; |
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214 | |||
215 | } |
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216 | |||
217 | |||
218 | /* |
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219 | * Registers accessors functions. |
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220 | */ |
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221 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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222 | { |
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223 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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224 | BUG_ON(1); |
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225 | return 0; |
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226 | } |
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227 | |||
228 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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229 | { |
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230 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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231 | reg, v); |
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232 | BUG_ON(1); |
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233 | } |
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234 | |||
235 | void radeon_register_accessor_init(struct radeon_device *rdev) |
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236 | { |
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237 | |||
1120 | serge | 238 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 239 | |
240 | rdev->mm_rreg = &r100_mm_rreg; |
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241 | rdev->mm_wreg = &r100_mm_wreg; |
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242 | rdev->mc_rreg = &radeon_invalid_rreg; |
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243 | rdev->mc_wreg = &radeon_invalid_wreg; |
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244 | rdev->pll_rreg = &radeon_invalid_rreg; |
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245 | rdev->pll_wreg = &radeon_invalid_wreg; |
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246 | rdev->pcie_rreg = &radeon_invalid_rreg; |
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247 | rdev->pcie_wreg = &radeon_invalid_wreg; |
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248 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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249 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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250 | |||
251 | /* Don't change order as we are overridding accessor. */ |
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252 | if (rdev->family < CHIP_RV515) { |
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253 | // rdev->pcie_rreg = &rv370_pcie_rreg; |
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254 | // rdev->pcie_wreg = &rv370_pcie_wreg; |
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255 | } |
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256 | if (rdev->family >= CHIP_RV515) { |
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1119 | serge | 257 | rdev->pcie_rreg = &rv515_pcie_rreg; |
258 | rdev->pcie_wreg = &rv515_pcie_wreg; |
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1117 | serge | 259 | } |
260 | /* FIXME: not sure here */ |
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261 | if (rdev->family <= CHIP_R580) { |
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1119 | serge | 262 | rdev->pll_rreg = &r100_pll_rreg; |
263 | rdev->pll_wreg = &r100_pll_wreg; |
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1117 | serge | 264 | } |
265 | if (rdev->family >= CHIP_RV515) { |
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266 | rdev->mc_rreg = &rv515_mc_rreg; |
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267 | rdev->mc_wreg = &rv515_mc_wreg; |
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268 | } |
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269 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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270 | // rdev->mc_rreg = &rs400_mc_rreg; |
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271 | // rdev->mc_wreg = &rs400_mc_wreg; |
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272 | } |
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273 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
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274 | // rdev->mc_rreg = &rs690_mc_rreg; |
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275 | // rdev->mc_wreg = &rs690_mc_wreg; |
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276 | } |
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277 | if (rdev->family == CHIP_RS600) { |
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278 | // rdev->mc_rreg = &rs600_mc_rreg; |
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279 | // rdev->mc_wreg = &rs600_mc_wreg; |
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280 | } |
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281 | if (rdev->family >= CHIP_R600) { |
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282 | // rdev->pciep_rreg = &r600_pciep_rreg; |
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283 | // rdev->pciep_wreg = &r600_pciep_wreg; |
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284 | } |
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285 | } |
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286 | |||
287 | |||
288 | |||
289 | /* |
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290 | * ASIC |
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291 | */ |
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292 | int radeon_asic_init(struct radeon_device *rdev) |
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293 | { |
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294 | |||
1120 | serge | 295 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 296 | |
297 | radeon_register_accessor_init(rdev); |
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298 | switch (rdev->family) { |
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299 | case CHIP_R100: |
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300 | case CHIP_RV100: |
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301 | case CHIP_RS100: |
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302 | case CHIP_RV200: |
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303 | case CHIP_RS200: |
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304 | case CHIP_R200: |
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305 | case CHIP_RV250: |
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306 | case CHIP_RS300: |
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307 | case CHIP_RV280: |
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308 | // rdev->asic = &r100_asic; |
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309 | break; |
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310 | case CHIP_R300: |
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311 | case CHIP_R350: |
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312 | case CHIP_RV350: |
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313 | case CHIP_RV380: |
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314 | // rdev->asic = &r300_asic; |
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315 | break; |
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316 | case CHIP_R420: |
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317 | case CHIP_R423: |
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318 | case CHIP_RV410: |
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319 | // rdev->asic = &r420_asic; |
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320 | break; |
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321 | case CHIP_RS400: |
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322 | case CHIP_RS480: |
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323 | // rdev->asic = &rs400_asic; |
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324 | break; |
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325 | case CHIP_RS600: |
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326 | // rdev->asic = &rs600_asic; |
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327 | break; |
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328 | case CHIP_RS690: |
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329 | case CHIP_RS740: |
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330 | // rdev->asic = &rs690_asic; |
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331 | break; |
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332 | case CHIP_RV515: |
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333 | // rdev->asic = &rv515_asic; |
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334 | break; |
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335 | case CHIP_R520: |
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336 | case CHIP_RV530: |
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337 | case CHIP_RV560: |
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338 | case CHIP_RV570: |
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339 | case CHIP_R580: |
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340 | rdev->asic = &r520_asic; |
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341 | break; |
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342 | case CHIP_R600: |
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343 | case CHIP_RV610: |
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344 | case CHIP_RV630: |
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345 | case CHIP_RV620: |
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346 | case CHIP_RV635: |
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347 | case CHIP_RV670: |
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348 | case CHIP_RS780: |
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349 | case CHIP_RV770: |
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350 | case CHIP_RV730: |
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351 | case CHIP_RV710: |
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352 | default: |
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353 | /* FIXME: not supported yet */ |
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354 | return -EINVAL; |
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355 | } |
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356 | return 0; |
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357 | } |
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358 | |||
359 | |||
360 | /* |
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361 | * Wrapper around modesetting bits. |
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362 | */ |
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363 | int radeon_clocks_init(struct radeon_device *rdev) |
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364 | { |
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365 | int r; |
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366 | |||
1120 | serge | 367 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 368 | |
369 | radeon_get_clock_info(rdev->ddev); |
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370 | r = radeon_static_clocks_init(rdev->ddev); |
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371 | if (r) { |
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372 | return r; |
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373 | } |
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374 | DRM_INFO("Clocks initialized !\n"); |
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375 | return 0; |
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376 | } |
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377 | |||
378 | void radeon_clocks_fini(struct radeon_device *rdev) |
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379 | { |
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380 | } |
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381 | |||
382 | /* ATOM accessor methods */ |
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383 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
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384 | { |
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385 | struct radeon_device *rdev = info->dev->dev_private; |
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386 | uint32_t r; |
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387 | |||
388 | r = rdev->pll_rreg(rdev, reg); |
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389 | return r; |
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390 | } |
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391 | |||
392 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
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393 | { |
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394 | struct radeon_device *rdev = info->dev->dev_private; |
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395 | |||
396 | rdev->pll_wreg(rdev, reg, val); |
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397 | } |
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398 | |||
399 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
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400 | { |
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401 | struct radeon_device *rdev = info->dev->dev_private; |
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402 | uint32_t r; |
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403 | |||
404 | r = rdev->mc_rreg(rdev, reg); |
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405 | return r; |
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406 | } |
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407 | |||
408 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
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409 | { |
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410 | struct radeon_device *rdev = info->dev->dev_private; |
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411 | |||
412 | rdev->mc_wreg(rdev, reg, val); |
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413 | } |
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414 | |||
415 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
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416 | { |
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417 | struct radeon_device *rdev = info->dev->dev_private; |
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418 | |||
419 | WREG32(reg*4, val); |
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420 | } |
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421 | |||
422 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
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423 | { |
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424 | struct radeon_device *rdev = info->dev->dev_private; |
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425 | uint32_t r; |
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426 | |||
427 | r = RREG32(reg*4); |
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428 | return r; |
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429 | } |
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430 | |||
431 | static struct card_info atom_card_info = { |
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432 | .dev = NULL, |
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433 | .reg_read = cail_reg_read, |
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434 | .reg_write = cail_reg_write, |
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435 | .mc_read = cail_mc_read, |
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436 | .mc_write = cail_mc_write, |
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437 | .pll_read = cail_pll_read, |
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438 | .pll_write = cail_pll_write, |
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439 | }; |
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440 | |||
441 | int radeon_atombios_init(struct radeon_device *rdev) |
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442 | { |
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1120 | serge | 443 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 444 | |
445 | atom_card_info.dev = rdev->ddev; |
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446 | rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); |
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447 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
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448 | return 0; |
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449 | } |
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450 | |||
451 | void radeon_atombios_fini(struct radeon_device *rdev) |
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452 | { |
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1119 | serge | 453 | kfree(rdev->mode_info.atom_context); |
1117 | serge | 454 | } |
455 | |||
456 | int radeon_combios_init(struct radeon_device *rdev) |
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457 | { |
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458 | // radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
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459 | return 0; |
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460 | } |
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461 | |||
462 | void radeon_combios_fini(struct radeon_device *rdev) |
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463 | { |
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464 | } |
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465 | |||
466 | int radeon_modeset_init(struct radeon_device *rdev); |
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467 | void radeon_modeset_fini(struct radeon_device *rdev); |
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468 | |||
469 | /* |
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470 | * Radeon device. |
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471 | */ |
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472 | int radeon_device_init(struct radeon_device *rdev, |
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473 | struct drm_device *ddev, |
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474 | struct pci_dev *pdev, |
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475 | uint32_t flags) |
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476 | { |
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477 | int r, ret = -1; |
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478 | |||
1120 | serge | 479 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 480 | |
481 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
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482 | rdev->shutdown = false; |
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483 | rdev->ddev = ddev; |
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484 | rdev->pdev = pdev; |
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485 | rdev->flags = flags; |
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486 | rdev->family = flags & RADEON_FAMILY_MASK; |
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487 | rdev->is_atom_bios = false; |
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488 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
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489 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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490 | rdev->gpu_lockup = false; |
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491 | /* mutex initialization are all done here so we |
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492 | * can recall function without having locking issues */ |
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493 | // mutex_init(&rdev->cs_mutex); |
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494 | // mutex_init(&rdev->ib_pool.mutex); |
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495 | // mutex_init(&rdev->cp.mutex); |
||
496 | // rwlock_init(&rdev->fence_drv.lock); |
||
497 | |||
1119 | serge | 498 | |
1117 | serge | 499 | if (radeon_agpmode == -1) { |
500 | rdev->flags &= ~RADEON_IS_AGP; |
||
501 | if (rdev->family > CHIP_RV515 || |
||
502 | rdev->family == CHIP_RV380 || |
||
503 | rdev->family == CHIP_RV410 || |
||
504 | rdev->family == CHIP_R423) { |
||
505 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
506 | rdev->flags |= RADEON_IS_PCIE; |
||
507 | } else { |
||
508 | DRM_INFO("Forcing AGP to PCI mode\n"); |
||
509 | rdev->flags |= RADEON_IS_PCI; |
||
510 | } |
||
511 | } |
||
512 | |||
513 | /* Set asic functions */ |
||
514 | r = radeon_asic_init(rdev); |
||
515 | if (r) { |
||
516 | return r; |
||
517 | } |
||
518 | |||
519 | r = rdev->asic->init(rdev); |
||
520 | |||
521 | if (r) { |
||
522 | return r; |
||
523 | } |
||
524 | |||
525 | /* Report DMA addressing limitation */ |
||
1119 | serge | 526 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); |
527 | if (r) { |
||
528 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
||
529 | } |
||
1117 | serge | 530 | |
531 | /* Registers mapping */ |
||
532 | /* TODO: block userspace mapping of io register */ |
||
533 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
534 | |||
535 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
536 | |||
537 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
538 | PG_SW+PG_NOCACHE); |
||
539 | |||
540 | if (rdev->rmmio == NULL) { |
||
541 | return -ENOMEM; |
||
542 | } |
||
543 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
544 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
545 | |||
546 | /* Setup errata flags */ |
||
547 | radeon_errata(rdev); |
||
548 | /* Initialize scratch registers */ |
||
549 | radeon_scratch_init(rdev); |
||
550 | /* Initialize surface registers */ |
||
551 | radeon_surface_init(rdev); |
||
552 | |||
553 | /* TODO: disable VGA need to use VGA request */ |
||
554 | /* BIOS*/ |
||
555 | if (!radeon_get_bios(rdev)) { |
||
556 | if (ASIC_IS_AVIVO(rdev)) |
||
557 | return -EINVAL; |
||
558 | } |
||
559 | if (rdev->is_atom_bios) { |
||
560 | r = radeon_atombios_init(rdev); |
||
561 | if (r) { |
||
562 | return r; |
||
563 | } |
||
564 | } else { |
||
565 | r = radeon_combios_init(rdev); |
||
566 | if (r) { |
||
567 | return r; |
||
568 | } |
||
569 | } |
||
570 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
571 | if (radeon_gpu_reset(rdev)) { |
||
572 | /* FIXME: what do we want to do here ? */ |
||
573 | } |
||
574 | /* check if cards are posted or not */ |
||
575 | if (!radeon_card_posted(rdev) && rdev->bios) { |
||
576 | DRM_INFO("GPU not posted. posting now...\n"); |
||
577 | if (rdev->is_atom_bios) { |
||
578 | atom_asic_init(rdev->mode_info.atom_context); |
||
579 | } else { |
||
580 | // radeon_combios_asic_init(rdev->ddev); |
||
581 | } |
||
582 | } |
||
583 | |||
584 | /* Get vram informations */ |
||
585 | radeon_vram_info(rdev); |
||
586 | /* Device is severly broken if aper size > vram size. |
||
587 | * for RN50/M6/M7 - Novell bug 204882 ? |
||
588 | */ |
||
589 | if (rdev->mc.vram_size < rdev->mc.aper_size) { |
||
590 | rdev->mc.aper_size = rdev->mc.vram_size; |
||
591 | } |
||
592 | /* Add an MTRR for the VRAM */ |
||
593 | // rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
||
594 | // MTRR_TYPE_WRCOMB, 1); |
||
595 | DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", |
||
596 | rdev->mc.vram_size >> 20, |
||
597 | (unsigned)rdev->mc.aper_size >> 20); |
||
598 | DRM_INFO("RAM width %dbits %cDR\n", |
||
599 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
||
600 | |||
601 | /* Initialize clocks */ |
||
602 | r = radeon_clocks_init(rdev); |
||
603 | if (r) { |
||
604 | return r; |
||
605 | } |
||
606 | |||
607 | /* Initialize memory controller (also test AGP) */ |
||
608 | r = radeon_mc_init(rdev); |
||
609 | if (r) { |
||
610 | return r; |
||
1119 | serge | 611 | }; |
612 | |||
613 | |||
1117 | serge | 614 | /* Fence driver */ |
1119 | serge | 615 | // r = radeon_fence_driver_init(rdev); |
616 | // if (r) { |
||
617 | // return r; |
||
618 | // } |
||
619 | // r = radeon_irq_kms_init(rdev); |
||
620 | // if (r) { |
||
621 | // return r; |
||
622 | // } |
||
1117 | serge | 623 | /* Memory manager */ |
1120 | serge | 624 | r = radeon_object_init(rdev); |
625 | if (r) { |
||
626 | return r; |
||
627 | } |
||
1117 | serge | 628 | /* Initialize GART (initialize after TTM so we can allocate |
629 | * memory through TTM but finalize after TTM) */ |
||
630 | r = radeon_gart_enable(rdev); |
||
1119 | serge | 631 | // if (!r) { |
632 | // r = radeon_gem_init(rdev); |
||
633 | // } |
||
1117 | serge | 634 | |
635 | /* 1M ring buffer */ |
||
636 | if (!r) { |
||
637 | r = radeon_cp_init(rdev, 1024 * 1024); |
||
638 | } |
||
1125 | serge | 639 | // if (!r) { |
640 | // r = radeon_wb_init(rdev); |
||
641 | // if (r) { |
||
642 | // DRM_ERROR("radeon: failled initializing WB (%d).\n", r); |
||
643 | // return r; |
||
644 | // } |
||
645 | // } |
||
1119 | serge | 646 | |
1125 | serge | 647 | #if 0 |
1117 | serge | 648 | if (!r) { |
649 | r = radeon_ib_pool_init(rdev); |
||
650 | if (r) { |
||
651 | DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
||
652 | return r; |
||
653 | } |
||
654 | } |
||
655 | if (!r) { |
||
656 | r = radeon_ib_test(rdev); |
||
657 | if (r) { |
||
658 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
||
659 | return r; |
||
660 | } |
||
661 | } |
||
1125 | serge | 662 | #endif |
663 | |||
1117 | serge | 664 | ret = r; |
665 | r = radeon_modeset_init(rdev); |
||
666 | if (r) { |
||
667 | return r; |
||
668 | } |
||
1125 | serge | 669 | // if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) { |
670 | // rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private; |
||
671 | // } |
||
1117 | serge | 672 | if (!ret) { |
673 | DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
||
674 | } |
||
675 | // if (radeon_benchmarking) { |
||
676 | // radeon_benchmark(rdev); |
||
677 | // } |
||
678 | |||
1125 | serge | 679 | return -1; |
1117 | serge | 680 | } |
681 | |||
682 | static struct pci_device_id pciidlist[] = { |
||
683 | radeon_PCI_IDS |
||
684 | }; |
||
685 | |||
686 | |||
687 | u32_t __stdcall drvEntry(int action) |
||
688 | { |
||
689 | struct pci_device_id *ent; |
||
690 | |||
691 | dev_t device; |
||
692 | int err; |
||
693 | u32_t retval = 0; |
||
694 | |||
695 | if(action != 1) |
||
696 | return 0; |
||
697 | |||
1120 | serge | 698 | if(!dbg_open("/hd0/2/atikms.log")) |
1117 | serge | 699 | { |
1120 | serge | 700 | printf("Can't open /hd0/2/atikms.log\nExit\n"); |
1117 | serge | 701 | return 0; |
702 | } |
||
703 | |||
704 | enum_pci_devices(); |
||
705 | |||
706 | ent = find_pci_device(&device, pciidlist); |
||
707 | |||
708 | if( unlikely(ent == NULL) ) |
||
709 | { |
||
710 | dbgprintf("device not found\n"); |
||
711 | return 0; |
||
712 | }; |
||
713 | |||
714 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
715 | device.pci_dev.device); |
||
716 | |||
717 | err = drm_get_dev(&device.pci_dev, ent); |
||
718 | |||
719 | return retval; |
||
720 | }; |
||
721 | |||
722 | /* |
||
723 | static struct drm_driver kms_driver = { |
||
724 | .driver_features = |
||
725 | DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | |
||
726 | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM, |
||
727 | .dev_priv_size = 0, |
||
728 | .load = radeon_driver_load_kms, |
||
729 | .firstopen = radeon_driver_firstopen_kms, |
||
730 | .open = radeon_driver_open_kms, |
||
731 | .preclose = radeon_driver_preclose_kms, |
||
732 | .postclose = radeon_driver_postclose_kms, |
||
733 | .lastclose = radeon_driver_lastclose_kms, |
||
734 | .unload = radeon_driver_unload_kms, |
||
735 | .suspend = radeon_suspend_kms, |
||
736 | .resume = radeon_resume_kms, |
||
737 | .get_vblank_counter = radeon_get_vblank_counter_kms, |
||
738 | .enable_vblank = radeon_enable_vblank_kms, |
||
739 | .disable_vblank = radeon_disable_vblank_kms, |
||
740 | .master_create = radeon_master_create_kms, |
||
741 | .master_destroy = radeon_master_destroy_kms, |
||
742 | #if defined(CONFIG_DEBUG_FS) |
||
743 | .debugfs_init = radeon_debugfs_init, |
||
744 | .debugfs_cleanup = radeon_debugfs_cleanup, |
||
745 | #endif |
||
746 | .irq_preinstall = radeon_driver_irq_preinstall_kms, |
||
747 | .irq_postinstall = radeon_driver_irq_postinstall_kms, |
||
748 | .irq_uninstall = radeon_driver_irq_uninstall_kms, |
||
749 | .irq_handler = radeon_driver_irq_handler_kms, |
||
750 | .reclaim_buffers = drm_core_reclaim_buffers, |
||
751 | .get_map_ofs = drm_core_get_map_ofs, |
||
752 | .get_reg_ofs = drm_core_get_reg_ofs, |
||
753 | .ioctls = radeon_ioctls_kms, |
||
754 | .gem_init_object = radeon_gem_object_init, |
||
755 | .gem_free_object = radeon_gem_object_free, |
||
756 | .dma_ioctl = radeon_dma_ioctl_kms, |
||
757 | .fops = { |
||
758 | .owner = THIS_MODULE, |
||
759 | .open = drm_open, |
||
760 | .release = drm_release, |
||
761 | .ioctl = drm_ioctl, |
||
762 | .mmap = radeon_mmap, |
||
763 | .poll = drm_poll, |
||
764 | .fasync = drm_fasync, |
||
765 | #ifdef CONFIG_COMPAT |
||
766 | .compat_ioctl = NULL, |
||
767 | #endif |
||
768 | }, |
||
769 | |||
770 | .pci_driver = { |
||
771 | .name = DRIVER_NAME, |
||
772 | .id_table = pciidlist, |
||
773 | .probe = radeon_pci_probe, |
||
774 | .remove = radeon_pci_remove, |
||
775 | .suspend = radeon_pci_suspend, |
||
776 | .resume = radeon_pci_resume, |
||
777 | }, |
||
778 | |||
779 | .name = DRIVER_NAME, |
||
780 | .desc = DRIVER_DESC, |
||
781 | .date = DRIVER_DATE, |
||
782 | .major = KMS_DRIVER_MAJOR, |
||
783 | .minor = KMS_DRIVER_MINOR, |
||
784 | .patchlevel = KMS_DRIVER_PATCHLEVEL, |
||
785 | }; |
||
786 | */ |
||
787 | |||
788 | |||
789 | /* |
||
790 | * Driver load/unload |
||
791 | */ |
||
792 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
793 | { |
||
794 | struct radeon_device *rdev; |
||
795 | int r; |
||
796 | |||
1120 | serge | 797 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 798 | |
1120 | serge | 799 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 800 | if (rdev == NULL) { |
801 | return -ENOMEM; |
||
802 | }; |
||
803 | |||
804 | dev->dev_private = (void *)rdev; |
||
805 | |||
806 | /* update BUS flag */ |
||
807 | // if (drm_device_is_agp(dev)) { |
||
808 | flags |= RADEON_IS_AGP; |
||
809 | // } else if (drm_device_is_pcie(dev)) { |
||
810 | // flags |= RADEON_IS_PCIE; |
||
811 | // } else { |
||
812 | // flags |= RADEON_IS_PCI; |
||
813 | // } |
||
814 | |||
815 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
||
816 | if (r) { |
||
817 | dbgprintf("Failed to initialize Radeon, disabling IOCTL\n"); |
||
818 | // radeon_device_fini(rdev); |
||
819 | return r; |
||
820 | } |
||
821 | return 0; |
||
822 | } |
||
823 | |||
824 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
||
825 | { |
||
826 | struct drm_device *dev; |
||
827 | int ret; |
||
828 | |||
1120 | serge | 829 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 830 | |
831 | dev = malloc(sizeof(*dev)); |
||
832 | if (!dev) |
||
833 | return -ENOMEM; |
||
834 | |||
835 | // ret = pci_enable_device(pdev); |
||
836 | // if (ret) |
||
837 | // goto err_g1; |
||
838 | |||
839 | // pci_set_master(pdev); |
||
840 | |||
841 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
842 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
843 | // goto err_g2; |
||
844 | // } |
||
845 | |||
846 | dev->pdev = pdev; |
||
847 | dev->pci_device = pdev->device; |
||
848 | dev->pci_vendor = pdev->vendor; |
||
849 | |||
850 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
||
851 | // pci_set_drvdata(pdev, dev); |
||
852 | // ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL); |
||
853 | // if (ret) |
||
854 | // goto err_g2; |
||
855 | // } |
||
856 | |||
857 | // if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY))) |
||
858 | // goto err_g3; |
||
859 | |||
860 | // if (dev->driver->load) { |
||
861 | // ret = dev->driver->load(dev, ent->driver_data); |
||
862 | // if (ret) |
||
863 | // goto err_g4; |
||
864 | // } |
||
865 | |||
866 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
||
867 | if (ret) |
||
868 | goto err_g4; |
||
869 | |||
870 | // list_add_tail(&dev->driver_item, &driver->device_list); |
||
871 | |||
872 | // DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", |
||
873 | // driver->name, driver->major, driver->minor, driver->patchlevel, |
||
874 | // driver->date, pci_name(pdev), dev->primary->index); |
||
875 | |||
876 | return 0; |
||
877 | |||
878 | err_g4: |
||
879 | // drm_put_minor(&dev->primary); |
||
880 | //err_g3: |
||
881 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
882 | // drm_put_minor(&dev->control); |
||
883 | //err_g2: |
||
884 | // pci_disable_device(pdev); |
||
885 | //err_g1: |
||
886 | free(dev); |
||
887 | |||
888 | return ret; |
||
889 | } |
||
890 | |||
891 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
892 | { |
||
893 | return pci_resource_start(dev->pdev, resource); |
||
894 | } |
||
895 | |||
896 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
897 | { |
||
898 | return pci_resource_len(dev->pdev, resource); |
||
899 | } |
||
900 | |||
1123 | serge | 901 | |
902 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
903 | { |
||
904 | uint64_t rem = *n; |
||
905 | uint64_t b = base; |
||
906 | uint64_t res, d = 1; |
||
907 | uint32_t high = rem >> 32; |
||
908 | |||
909 | /* Reduce the thing a bit first */ |
||
910 | res = 0; |
||
911 | if (high >= base) { |
||
912 | high /= base; |
||
913 | res = (uint64_t) high << 32; |
||
914 | rem -= (uint64_t) (high*base) << 32; |
||
915 | } |
||
916 | |||
917 | while ((int64_t)b > 0 && b < rem) { |
||
918 | b = b+b; |
||
919 | d = d+d; |
||
920 | } |
||
921 | |||
922 | do { |
||
923 | if (rem >= b) { |
||
924 | rem -= b; |
||
925 | res += d; |
||
926 | } |
||
927 | b >>= 1; |
||
928 | d >>= 1; |
||
929 | } while (d); |
||
930 | |||
931 | *n = res; |
||
932 | return rem; |
||
933 | }>><>><>>=>>>>>>>>> |
||
934 |