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| Rev | Author | Line No. | Line |
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| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 28 | //#include |
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| 1123 | serge | 29 | |
| 30 | #include |
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| 1117 | serge | 31 | //#include |
| 32 | #include "radeon_drm.h" |
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| 33 | #include "radeon_reg.h" |
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| 34 | #include "radeon.h" |
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| 35 | #include "radeon_asic.h" |
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| 36 | #include "atom.h" |
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| 37 | |||
| 38 | #include |
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| 39 | |||
| 1123 | serge | 40 | int radeon_modeset = -1; |
| 1117 | serge | 41 | int radeon_dynclks = -1; |
| 1123 | serge | 42 | int radeon_r4xx_atom = 0; |
| 43 | int radeon_agpmode = 0; |
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| 44 | int radeon_vram_limit = 0; |
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| 1117 | serge | 45 | int radeon_gart_size = 512; /* default gart size */ |
| 1123 | serge | 46 | int radeon_benchmarking = 0; |
| 47 | int radeon_connector_table = 0; |
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| 1117 | serge | 48 | |
| 49 | |||
| 50 | /* |
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| 51 | * Clear GPU surface registers. |
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| 52 | */ |
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| 53 | static void radeon_surface_init(struct radeon_device *rdev) |
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| 54 | { |
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| 1120 | serge | 55 | dbgprintf("%s\n",__FUNCTION__); |
| 1117 | serge | 56 | |
| 57 | /* FIXME: check this out */ |
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| 58 | if (rdev->family < CHIP_R600) { |
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| 59 | int i; |
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| 60 | |||
| 61 | for (i = 0; i < 8; i++) { |
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| 62 | WREG32(RADEON_SURFACE0_INFO + |
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| 63 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
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| 64 | 0); |
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| 65 | } |
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| 66 | } |
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| 67 | } |
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| 68 | |||
| 69 | /* |
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| 70 | * GPU scratch registers helpers function. |
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| 71 | */ |
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| 72 | static void radeon_scratch_init(struct radeon_device *rdev) |
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| 73 | { |
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| 74 | int i; |
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| 75 | |||
| 76 | /* FIXME: check this out */ |
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| 77 | if (rdev->family < CHIP_R300) { |
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| 78 | rdev->scratch.num_reg = 5; |
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| 79 | } else { |
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| 80 | rdev->scratch.num_reg = 7; |
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| 81 | } |
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| 82 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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| 83 | rdev->scratch.free[i] = true; |
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| 84 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
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| 85 | } |
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| 86 | } |
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| 87 | |||
| 88 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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| 89 | { |
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| 90 | int i; |
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| 91 | |||
| 92 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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| 93 | if (rdev->scratch.free[i]) { |
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| 94 | rdev->scratch.free[i] = false; |
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| 95 | *reg = rdev->scratch.reg[i]; |
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| 96 | return 0; |
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| 97 | } |
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| 98 | } |
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| 99 | return -EINVAL; |
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| 100 | } |
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| 101 | |||
| 102 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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| 103 | { |
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| 104 | int i; |
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| 105 | |||
| 106 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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| 107 | if (rdev->scratch.reg[i] == reg) { |
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| 108 | rdev->scratch.free[i] = true; |
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| 109 | return; |
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| 110 | } |
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| 111 | } |
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| 112 | } |
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| 113 | |||
| 114 | /* |
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| 115 | * MC common functions |
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| 116 | */ |
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| 117 | int radeon_mc_setup(struct radeon_device *rdev) |
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| 118 | { |
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| 119 | uint32_t tmp; |
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| 120 | |||
| 121 | /* Some chips have an "issue" with the memory controller, the |
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| 122 | * location must be aligned to the size. We just align it down, |
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| 123 | * too bad if we walk over the top of system memory, we don't |
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| 124 | * use DMA without a remapped anyway. |
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| 125 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
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| 126 | */ |
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| 127 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
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| 128 | */ |
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| 129 | /* |
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| 130 | * Note: from R6xx the address space is 40bits but here we only |
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| 131 | * use 32bits (still have to see a card which would exhaust 4G |
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| 132 | * address space). |
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| 133 | */ |
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| 134 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
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| 135 | /* vram location was already setup try to put gtt after |
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| 136 | * if it fits */ |
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| 137 | tmp = rdev->mc.vram_location + rdev->mc.vram_size; |
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| 138 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
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| 139 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
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| 140 | rdev->mc.gtt_location = tmp; |
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| 141 | } else { |
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| 142 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
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| 143 | printk(KERN_ERR "[drm] GTT too big to fit " |
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| 144 | "before or after vram location.\n"); |
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| 145 | return -EINVAL; |
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| 146 | } |
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| 147 | rdev->mc.gtt_location = 0; |
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| 148 | } |
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| 149 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
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| 150 | /* gtt location was already setup try to put vram before |
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| 151 | * if it fits */ |
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| 152 | if (rdev->mc.vram_size < rdev->mc.gtt_location) { |
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| 153 | rdev->mc.vram_location = 0; |
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| 154 | } else { |
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| 155 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
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| 156 | tmp += (rdev->mc.vram_size - 1); |
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| 157 | tmp &= ~(rdev->mc.vram_size - 1); |
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| 158 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { |
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| 159 | rdev->mc.vram_location = tmp; |
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| 160 | } else { |
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| 161 | printk(KERN_ERR "[drm] vram too big to fit " |
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| 162 | "before or after GTT location.\n"); |
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| 163 | return -EINVAL; |
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| 164 | } |
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| 165 | } |
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| 166 | } else { |
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| 167 | rdev->mc.vram_location = 0; |
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| 168 | rdev->mc.gtt_location = rdev->mc.vram_size; |
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| 169 | } |
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| 170 | DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); |
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| 171 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
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| 172 | rdev->mc.vram_location, |
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| 173 | rdev->mc.vram_location + rdev->mc.vram_size - 1); |
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| 174 | DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); |
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| 175 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
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| 176 | rdev->mc.gtt_location, |
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| 177 | rdev->mc.gtt_location + rdev->mc.gtt_size - 1); |
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| 178 | return 0; |
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| 179 | } |
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| 180 | |||
| 181 | |||
| 182 | /* |
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| 183 | * GPU helpers function. |
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| 184 | */ |
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| 185 | static bool radeon_card_posted(struct radeon_device *rdev) |
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| 186 | { |
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| 187 | uint32_t reg; |
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| 188 | |||
| 1120 | serge | 189 | dbgprintf("%s\n",__FUNCTION__); |
| 1117 | serge | 190 | |
| 191 | /* first check CRTCs */ |
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| 192 | if (ASIC_IS_AVIVO(rdev)) { |
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| 193 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
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| 194 | RREG32(AVIVO_D2CRTC_CONTROL); |
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| 195 | if (reg & AVIVO_CRTC_EN) { |
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| 196 | return true; |
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| 197 | } |
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| 198 | } else { |
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| 199 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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| 200 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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| 201 | if (reg & RADEON_CRTC_EN) { |
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| 202 | return true; |
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| 203 | } |
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| 204 | } |
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| 205 | |||
| 206 | /* then check MEM_SIZE, in case the crtcs are off */ |
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| 207 | if (rdev->family >= CHIP_R600) |
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| 208 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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| 209 | else |
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| 210 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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| 211 | |||
| 212 | if (reg) |
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| 213 | return true; |
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| 214 | |||
| 215 | return false; |
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| 216 | |||
| 217 | } |
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| 218 | |||
| 219 | |||
| 220 | /* |
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| 221 | * Registers accessors functions. |
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| 222 | */ |
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| 223 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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| 224 | { |
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| 225 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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| 226 | BUG_ON(1); |
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| 227 | return 0; |
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| 228 | } |
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| 229 | |||
| 230 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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| 231 | { |
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| 232 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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| 233 | reg, v); |
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| 234 | BUG_ON(1); |
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| 235 | } |
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| 236 | |||
| 237 | void radeon_register_accessor_init(struct radeon_device *rdev) |
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| 238 | { |
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| 239 | |||
| 1120 | serge | 240 | dbgprintf("%s\n",__FUNCTION__); |
| 1117 | serge | 241 | |
| 242 | rdev->mm_rreg = &r100_mm_rreg; |
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| 243 | rdev->mm_wreg = &r100_mm_wreg; |
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| 244 | rdev->mc_rreg = &radeon_invalid_rreg; |
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| 245 | rdev->mc_wreg = &radeon_invalid_wreg; |
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| 246 | rdev->pll_rreg = &radeon_invalid_rreg; |
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| 247 | rdev->pll_wreg = &radeon_invalid_wreg; |
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| 248 | rdev->pcie_rreg = &radeon_invalid_rreg; |
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| 249 | rdev->pcie_wreg = &radeon_invalid_wreg; |
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| 250 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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| 251 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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| 252 | |||
| 253 | /* Don't change order as we are overridding accessor. */ |
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| 254 | if (rdev->family < CHIP_RV515) { |
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| 255 | // rdev->pcie_rreg = &rv370_pcie_rreg; |
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| 256 | // rdev->pcie_wreg = &rv370_pcie_wreg; |
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| 257 | } |
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| 258 | if (rdev->family >= CHIP_RV515) { |
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