WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_device.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
		29	//#include
		30	//#include
		31	#include "radeon_drm.h"
		32	#include "radeon_reg.h"
		33	#include "radeon.h"
		34	#include "radeon_asic.h"
		35	#include "atom.h"
		36
		37	#include
		38
		39	int radeon_dynclks = -1;
		40	int radeon_agpmode = -1;
		41	int radeon_gart_size = 512; /* default gart size */
		42
		43
		44	/*
		45	* Clear GPU surface registers.
		46	*/
		47	static void radeon_surface_init(struct radeon_device *rdev)
		48	{
		49	dbgprintf("%s\n\r",__FUNCTION__);
		50
		51	/* FIXME: check this out */
		52	if (rdev->family < CHIP_R600) {
		53	int i;
		54
		55	for (i = 0; i < 8; i++) {
		56	WREG32(RADEON_SURFACE0_INFO +
		57	i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
		58	0);
		59	}
		60	}
		61	}
		62
		63	/*
		64	* GPU scratch registers helpers function.
		65	*/
		66	static void radeon_scratch_init(struct radeon_device *rdev)
		67	{
		68	int i;
		69
		70	/* FIXME: check this out */
		71	if (rdev->family < CHIP_R300) {
		72	rdev->scratch.num_reg = 5;
		73	} else {
		74	rdev->scratch.num_reg = 7;
		75	}
		76	for (i = 0; i < rdev->scratch.num_reg; i++) {
		77	rdev->scratch.free[i] = true;
		78	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
		79	}
		80	}
		81
		82	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
		83	{
		84	int i;
		85
		86	for (i = 0; i < rdev->scratch.num_reg; i++) {
		87	if (rdev->scratch.free[i]) {
		88	rdev->scratch.free[i] = false;
		89	*reg = rdev->scratch.reg[i];
		90	return 0;
		91	}
		92	}
		93	return -EINVAL;
		94	}
		95
		96	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
		97	{
		98	int i;
		99
		100	for (i = 0; i < rdev->scratch.num_reg; i++) {
		101	if (rdev->scratch.reg[i] == reg) {
		102	rdev->scratch.free[i] = true;
		103	return;
		104	}
		105	}
		106	}
		107
		108	/*
		109	* MC common functions
		110	*/
		111	int radeon_mc_setup(struct radeon_device *rdev)
		112	{
		113	uint32_t tmp;
		114
		115	/* Some chips have an "issue" with the memory controller, the
		116	* location must be aligned to the size. We just align it down,
		117	* too bad if we walk over the top of system memory, we don't
		118	* use DMA without a remapped anyway.
		119	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
		120	*/
		121	/* FGLRX seems to setup like this, VRAM a 0, then GART.
		122	*/
		123	/*
		124	* Note: from R6xx the address space is 40bits but here we only
		125	* use 32bits (still have to see a card which would exhaust 4G
		126	* address space).
		127	*/
		128	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		129	/* vram location was already setup try to put gtt after
		130	* if it fits */
		131	tmp = rdev->mc.vram_location + rdev->mc.vram_size;
		132	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		133	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
		134	rdev->mc.gtt_location = tmp;
		135	} else {
		136	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
		137	printk(KERN_ERR "[drm] GTT too big to fit "
		138	"before or after vram location.\n");
		139	return -EINVAL;
		140	}
		141	rdev->mc.gtt_location = 0;
		142	}
		143	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		144	/* gtt location was already setup try to put vram before
		145	* if it fits */
		146	if (rdev->mc.vram_size < rdev->mc.gtt_location) {
		147	rdev->mc.vram_location = 0;
		148	} else {
		149	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
		150	tmp += (rdev->mc.vram_size - 1);
		151	tmp &= ~(rdev->mc.vram_size - 1);
		152	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
		153	rdev->mc.vram_location = tmp;
		154	} else {
		155	printk(KERN_ERR "[drm] vram too big to fit "
		156	"before or after GTT location.\n");
		157	return -EINVAL;
		158	}
		159	}
		160	} else {
		161	rdev->mc.vram_location = 0;
		162	rdev->mc.gtt_location = rdev->mc.vram_size;
		163	}
		164	DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
		165	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
		166	rdev->mc.vram_location,
		167	rdev->mc.vram_location + rdev->mc.vram_size - 1);
		168	DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
		169	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
		170	rdev->mc.gtt_location,
		171	rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
		172	return 0;
		173	}
		174
		175
		176	/*
		177	* GPU helpers function.
		178	*/
		179	static bool radeon_card_posted(struct radeon_device *rdev)
		180	{
		181	uint32_t reg;
		182
		183	dbgprintf("%s\n\r",__FUNCTION__);
		184
		185	/* first check CRTCs */
		186	if (ASIC_IS_AVIVO(rdev)) {
		187	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
		188	RREG32(AVIVO_D2CRTC_CONTROL);
		189	if (reg & AVIVO_CRTC_EN) {
		190	return true;
		191	}
		192	} else {
		193	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
		194	RREG32(RADEON_CRTC2_GEN_CNTL);
		195	if (reg & RADEON_CRTC_EN) {
		196	return true;
		197	}
		198	}
		199
		200	/* then check MEM_SIZE, in case the crtcs are off */
		201	if (rdev->family >= CHIP_R600)
		202	reg = RREG32(R600_CONFIG_MEMSIZE);
		203	else
		204	reg = RREG32(RADEON_CONFIG_MEMSIZE);
		205
		206	if (reg)
		207	return true;
		208
		209	return false;
		210
		211	}
		212
		213
		214	/*
		215	* Registers accessors functions.
		216	*/
		217	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		218	{
		219	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		220	BUG_ON(1);
		221	return 0;
		222	}
		223
		224	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		225	{
		226	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		227	reg, v);
		228	BUG_ON(1);
		229	}
		230
		231
		232	void radeon_register_accessor_init(struct radeon_device *rdev)
		233	{
		234
		235	dbgprintf("%s\n\r",__FUNCTION__);
		236
		237	rdev->mm_rreg = &r100_mm_rreg;
		238	rdev->mm_wreg = &r100_mm_wreg;
		239	rdev->mc_rreg = &radeon_invalid_rreg;
		240	rdev->mc_wreg = &radeon_invalid_wreg;
		241	rdev->pll_rreg = &radeon_invalid_rreg;
		242	rdev->pll_wreg = &radeon_invalid_wreg;
		243	rdev->pcie_rreg = &radeon_invalid_rreg;
		244	rdev->pcie_wreg = &radeon_invalid_wreg;
		245	rdev->pciep_rreg = &radeon_invalid_rreg;
		246	rdev->pciep_wreg = &radeon_invalid_wreg;
		247
		248	/* Don't change order as we are overridding accessor. */
		249	if (rdev->family < CHIP_RV515) {
		250	// rdev->pcie_rreg = &rv370_pcie_rreg;
		251	// rdev->pcie_wreg = &rv370_pcie_wreg;
		252	}
		253	if (rdev->family >= CHIP_RV515) {
		254	// rdev->pcie_rreg = &rv515_pcie_rreg;
		255	// rdev->pcie_wreg = &rv515_pcie_wreg;
		256	}
		257	/* FIXME: not sure here */
		258	if (rdev->family <= CHIP_R580) {
		259	// rdev->pll_rreg = &r100_pll_rreg;
		260	// rdev->pll_wreg = &r100_pll_wreg;
		261	}
		262	if (rdev->family >= CHIP_RV515) {
		263	rdev->mc_rreg = &rv515_mc_rreg;
		264	rdev->mc_wreg = &rv515_mc_wreg;
		265	}
		266	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		267	// rdev->mc_rreg = &rs400_mc_rreg;
		268	// rdev->mc_wreg = &rs400_mc_wreg;
		269	}
		270	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		271	// rdev->mc_rreg = &rs690_mc_rreg;
		272	// rdev->mc_wreg = &rs690_mc_wreg;
		273	}
		274	if (rdev->family == CHIP_RS600) {
		275	// rdev->mc_rreg = &rs600_mc_rreg;
		276	// rdev->mc_wreg = &rs600_mc_wreg;
		277	}
		278	if (rdev->family >= CHIP_R600) {
		279	// rdev->pciep_rreg = &r600_pciep_rreg;
		280	// rdev->pciep_wreg = &r600_pciep_wreg;
		281	}
		282	}
		283
		284
		285
		286	/*
		287	* ASIC
		288	*/
		289	int radeon_asic_init(struct radeon_device *rdev)
		290	{
		291
		292	dbgprintf("%s\n\r",__FUNCTION__);
		293
		294	radeon_register_accessor_init(rdev);
		295	switch (rdev->family) {
		296	case CHIP_R100:
		297	case CHIP_RV100:
		298	case CHIP_RS100:
		299	case CHIP_RV200:
		300	case CHIP_RS200:
		301	case CHIP_R200:
		302	case CHIP_RV250:
		303	case CHIP_RS300:
		304	case CHIP_RV280:
		305	// rdev->asic = &r100_asic;
		306	break;
		307	case CHIP_R300:
		308	case CHIP_R350:
		309	case CHIP_RV350:
		310	case CHIP_RV380:
		311	// rdev->asic = &r300_asic;
		312	break;
		313	case CHIP_R420:
		314	case CHIP_R423:
		315	case CHIP_RV410:
		316	// rdev->asic = &r420_asic;
		317	break;
		318	case CHIP_RS400:
		319	case CHIP_RS480:
		320	// rdev->asic = &rs400_asic;
		321	break;
		322	case CHIP_RS600:
		323	// rdev->asic = &rs600_asic;
		324	break;
		325	case CHIP_RS690:
		326	case CHIP_RS740:
		327	// rdev->asic = &rs690_asic;
		328	break;
		329	case CHIP_RV515:
		330	// rdev->asic = &rv515_asic;
		331	break;
		332	case CHIP_R520:
		333	case CHIP_RV530:
		334	case CHIP_RV560:
		335	case CHIP_RV570:
		336	case CHIP_R580:
		337	rdev->asic = &r520_asic;
		338	break;
		339	case CHIP_R600:
		340	case CHIP_RV610:
		341	case CHIP_RV630:
		342	case CHIP_RV620:
		343	case CHIP_RV635:
		344	case CHIP_RV670:
		345	case CHIP_RS780:
		346	case CHIP_RV770:
		347	case CHIP_RV730:
		348	case CHIP_RV710:
		349	default:
		350	/* FIXME: not supported yet */
		351	return -EINVAL;
		352	}
		353	return 0;
		354	}
		355
		356
		357	/*
		358	* Wrapper around modesetting bits.
		359	*/
		360	int radeon_clocks_init(struct radeon_device *rdev)
		361	{
		362	int r;
		363
		364	dbgprintf("%s\n\r",__FUNCTION__);
		365
		366	radeon_get_clock_info(rdev->ddev);
		367	r = radeon_static_clocks_init(rdev->ddev);
		368	if (r) {
		369	return r;
		370	}
		371	DRM_INFO("Clocks initialized !\n");
		372	return 0;
		373	}
		374
		375	void radeon_clocks_fini(struct radeon_device *rdev)
		376	{
		377	}
		378
		379	/* ATOM accessor methods */
		380	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
		381	{
		382	struct radeon_device *rdev = info->dev->dev_private;
		383	uint32_t r;
		384
		385	r = rdev->pll_rreg(rdev, reg);
		386	return r;
		387	}
		388
		389	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
		390	{
		391	struct radeon_device *rdev = info->dev->dev_private;
		392
		393	rdev->pll_wreg(rdev, reg, val);
		394	}
		395
		396	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
		397	{
		398	struct radeon_device *rdev = info->dev->dev_private;
		399	uint32_t r;
		400
		401	r = rdev->mc_rreg(rdev, reg);
		402	return r;
		403	}
		404
		405	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
		406	{
		407	struct radeon_device *rdev = info->dev->dev_private;
		408
		409	rdev->mc_wreg(rdev, reg, val);
		410	}
		411
		412	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
		413	{
		414	struct radeon_device *rdev = info->dev->dev_private;
		415
		416	WREG32(reg*4, val);
		417	}
		418
		419	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
		420	{
		421	struct radeon_device *rdev = info->dev->dev_private;
		422	uint32_t r;
		423
		424	r = RREG32(reg*4);
		425	return r;
		426	}
		427
		428	static struct card_info atom_card_info = {
		429	.dev = NULL,
		430	.reg_read = cail_reg_read,
		431	.reg_write = cail_reg_write,
		432	.mc_read = cail_mc_read,
		433	.mc_write = cail_mc_write,
		434	.pll_read = cail_pll_read,
		435	.pll_write = cail_pll_write,
		436	};
		437
		438	int radeon_atombios_init(struct radeon_device *rdev)
		439	{
		440	dbgprintf("%s\n\r",__FUNCTION__);
		441
		442	atom_card_info.dev = rdev->ddev;
		443	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
		444	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
		445	return 0;
		446	}
		447
		448	void radeon_atombios_fini(struct radeon_device *rdev)
		449	{
		450	free(rdev->mode_info.atom_context);
		451	}
		452
		453	int radeon_combios_init(struct radeon_device *rdev)
		454	{
		455	// radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
		456	return 0;
		457	}
		458
		459	void radeon_combios_fini(struct radeon_device *rdev)
		460	{
		461	}
		462
		463	int radeon_modeset_init(struct radeon_device *rdev);
		464	void radeon_modeset_fini(struct radeon_device *rdev);
		465
		466
		467	/*
		468	* Radeon device.
		469	*/
		470	int radeon_device_init(struct radeon_device *rdev,
		471	struct drm_device *ddev,
		472	struct pci_dev *pdev,
		473	uint32_t flags)
		474	{
		475	int r, ret = -1;
		476
		477	dbgprintf("%s\n\r",__FUNCTION__);
		478
		479	DRM_INFO("radeon: Initializing kernel modesetting.\n");
		480	rdev->shutdown = false;
		481	rdev->ddev = ddev;
		482	rdev->pdev = pdev;
		483	rdev->flags = flags;
		484	rdev->family = flags & RADEON_FAMILY_MASK;
		485	rdev->is_atom_bios = false;
		486	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
		487	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		488	rdev->gpu_lockup = false;
		489	/* mutex initialization are all done here so we
		490	* can recall function without having locking issues */
		491	// mutex_init(&rdev->cs_mutex);
		492	// mutex_init(&rdev->ib_pool.mutex);
		493	// mutex_init(&rdev->cp.mutex);
		494	// rwlock_init(&rdev->fence_drv.lock);
		495
		496	if (radeon_agpmode == -1) {
		497	rdev->flags &= ~RADEON_IS_AGP;
		498	if (rdev->family > CHIP_RV515 \|\|
		499	rdev->family == CHIP_RV380 \|\|
		500	rdev->family == CHIP_RV410 \|\|
		501	rdev->family == CHIP_R423) {
		502	DRM_INFO("Forcing AGP to PCIE mode\n");
		503	rdev->flags \|= RADEON_IS_PCIE;
		504	} else {
		505	DRM_INFO("Forcing AGP to PCI mode\n");
		506	rdev->flags \|= RADEON_IS_PCI;
		507	}
		508	}
		509
		510	/* Set asic functions */
		511	r = radeon_asic_init(rdev);
		512	if (r) {
		513	return r;
		514	}
		515	// r = radeon_init(rdev);
		516
		517	r = rdev->asic->init(rdev);
		518
		519	if (r) {
		520	return r;
		521	}
		522
		523	/* Report DMA addressing limitation */
		524	// r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
		525	// if (r) {
		526	// printk(KERN_WARNING "radeon: No suitable DMA available.\n");
		527	// }
		528
		529	/* Registers mapping */
		530	/* TODO: block userspace mapping of io register */
		531	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
		532
		533	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
		534
		535	rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
		536	PG_SW+PG_NOCACHE);
		537
		538	if (rdev->rmmio == NULL) {
		539	return -ENOMEM;
		540	}
		541	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
		542	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
		543
		544	/* Setup errata flags */
		545	radeon_errata(rdev);
		546	/* Initialize scratch registers */
		547	radeon_scratch_init(rdev);
		548	/* Initialize surface registers */
		549	radeon_surface_init(rdev);
		550
		551	/* TODO: disable VGA need to use VGA request */
		552	/* BIOS*/
		553	if (!radeon_get_bios(rdev)) {
		554	if (ASIC_IS_AVIVO(rdev))
		555	return -EINVAL;
		556	}
		557	if (rdev->is_atom_bios) {
		558	r = radeon_atombios_init(rdev);
		559	if (r) {
		560	return r;
		561	}
		562	} else {
		563	r = radeon_combios_init(rdev);
		564	if (r) {
		565	return r;
		566	}
		567	}
		568
		569
		570	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		571	if (radeon_gpu_reset(rdev)) {
		572	/* FIXME: what do we want to do here ? */
		573	}
		574
		575	/* check if cards are posted or not */
		576	if (!radeon_card_posted(rdev) && rdev->bios) {
		577	DRM_INFO("GPU not posted. posting now...\n");
		578	if (rdev->is_atom_bios) {
		579	atom_asic_init(rdev->mode_info.atom_context);
		580	} else {
		581	// radeon_combios_asic_init(rdev->ddev);
		582	}
		583	}
		584
		585	/* Get vram informations */
		586	radeon_vram_info(rdev);
		587	/* Device is severly broken if aper size > vram size.
		588	* for RN50/M6/M7 - Novell bug 204882 ?
		589	*/
		590	if (rdev->mc.vram_size < rdev->mc.aper_size) {
		591	rdev->mc.aper_size = rdev->mc.vram_size;
		592	}
		593	/* Add an MTRR for the VRAM */
		594	// rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
		595	// MTRR_TYPE_WRCOMB, 1);
		596	DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
		597	rdev->mc.vram_size >> 20,
		598	(unsigned)rdev->mc.aper_size >> 20);
		599	DRM_INFO("RAM width %dbits %cDR\n",
		600	rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
		601
		602	/* Initialize clocks */
		603	r = radeon_clocks_init(rdev);
		604	if (r) {
		605	return r;
		606	}
		607
		608	#if 0
		609
		610	/* Initialize memory controller (also test AGP) */
		611	r = radeon_mc_init(rdev);
		612	if (r) {
		613	return r;
		614	}
		615	/* Fence driver */
		616	r = radeon_fence_driver_init(rdev);
		617	if (r) {
		618	return r;
		619	}
		620	r = radeon_irq_kms_init(rdev);
		621	if (r) {
		622	return r;
		623	}
		624	/* Memory manager */
		625	r = radeon_object_init(rdev);
		626	if (r) {
		627	return r;
		628	}
		629	/* Initialize GART (initialize after TTM so we can allocate
		630	* memory through TTM but finalize after TTM) */
		631	r = radeon_gart_enable(rdev);
		632	if (!r) {
		633	r = radeon_gem_init(rdev);
		634	}
		635
		636	/* 1M ring buffer */
		637	if (!r) {
		638	r = radeon_cp_init(rdev, 1024 * 1024);
		639	}
		640	if (!r) {
		641	r = radeon_wb_init(rdev);
		642	if (r) {
		643	DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
		644	return r;
		645	}
		646	}
		647	if (!r) {
		648	r = radeon_ib_pool_init(rdev);
		649	if (r) {
		650	DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
		651	return r;
		652	}
		653	}
		654	if (!r) {
		655	r = radeon_ib_test(rdev);
		656	if (r) {
		657	DRM_ERROR("radeon: failled testing IB (%d).\n", r);
		658	return r;
		659	}
		660	}
		661	ret = r;
		662	r = radeon_modeset_init(rdev);
		663	if (r) {
		664	return r;
		665	}
		666	if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
		667	rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
		668	}
		669	if (!ret) {
		670	DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
		671	}
		672	// if (radeon_benchmarking) {
		673	// radeon_benchmark(rdev);
		674	// }
		675
		676	#endif
		677
		678	return ret;
		679	}
		680
		681	static struct pci_device_id pciidlist[] = {
		682	radeon_PCI_IDS
		683	};
		684
		685
		686	u32_t __stdcall drvEntry(int action)
		687	{
		688	struct pci_device_id *ent;
		689
		690	dev_t device;
		691	int err;
		692	u32_t retval = 0;
		693
		694	if(action != 1)
		695	return 0;
		696
		697	if(!dbg_open("/rd/1/drivers/atikms.log"))
		698	{
		699	printf("Can't open /rd/1/drivers/ati2d.log\nExit\n");
		700	return 0;
		701	}
		702
		703	enum_pci_devices();
		704
		705	ent = find_pci_device(&device, pciidlist);
		706
		707	if( unlikely(ent == NULL) )
		708	{
		709	dbgprintf("device not found\n");
		710	return 0;
		711	};
		712
		713	dbgprintf("device %x:%x\n", device.pci_dev.vendor,
		714	device.pci_dev.device);
		715
		716	err = drm_get_dev(&device.pci_dev, ent);
		717
		718	return retval;
		719	};
		720
		721	/*
		722	static struct drm_driver kms_driver = {
		723	.driver_features =
		724	DRIVER_USE_AGP \| DRIVER_USE_MTRR \| DRIVER_PCI_DMA \| DRIVER_SG \|
		725	DRIVER_HAVE_IRQ \| DRIVER_HAVE_DMA \| DRIVER_IRQ_SHARED \| DRIVER_GEM,
		726	.dev_priv_size = 0,
		727	.load = radeon_driver_load_kms,
		728	.firstopen = radeon_driver_firstopen_kms,
		729	.open = radeon_driver_open_kms,
		730	.preclose = radeon_driver_preclose_kms,
		731	.postclose = radeon_driver_postclose_kms,
		732	.lastclose = radeon_driver_lastclose_kms,
		733	.unload = radeon_driver_unload_kms,
		734	.suspend = radeon_suspend_kms,
		735	.resume = radeon_resume_kms,
		736	.get_vblank_counter = radeon_get_vblank_counter_kms,
		737	.enable_vblank = radeon_enable_vblank_kms,
		738	.disable_vblank = radeon_disable_vblank_kms,
		739	.master_create = radeon_master_create_kms,
		740	.master_destroy = radeon_master_destroy_kms,
		741	#if defined(CONFIG_DEBUG_FS)
		742	.debugfs_init = radeon_debugfs_init,
		743	.debugfs_cleanup = radeon_debugfs_cleanup,
		744	#endif
		745	.irq_preinstall = radeon_driver_irq_preinstall_kms,
		746	.irq_postinstall = radeon_driver_irq_postinstall_kms,
		747	.irq_uninstall = radeon_driver_irq_uninstall_kms,
		748	.irq_handler = radeon_driver_irq_handler_kms,
		749	.reclaim_buffers = drm_core_reclaim_buffers,
		750	.get_map_ofs = drm_core_get_map_ofs,
		751	.get_reg_ofs = drm_core_get_reg_ofs,
		752	.ioctls = radeon_ioctls_kms,
		753	.gem_init_object = radeon_gem_object_init,
		754	.gem_free_object = radeon_gem_object_free,
		755	.dma_ioctl = radeon_dma_ioctl_kms,
		756	.fops = {
		757	.owner = THIS_MODULE,
		758	.open = drm_open,
		759	.release = drm_release,
		760	.ioctl = drm_ioctl,
		761	.mmap = radeon_mmap,
		762	.poll = drm_poll,
		763	.fasync = drm_fasync,
		764	#ifdef CONFIG_COMPAT
		765	.compat_ioctl = NULL,
		766	#endif
		767	},
		768
		769	.pci_driver = {
		770	.name = DRIVER_NAME,
		771	.id_table = pciidlist,
		772	.probe = radeon_pci_probe,
		773	.remove = radeon_pci_remove,
		774	.suspend = radeon_pci_suspend,
		775	.resume = radeon_pci_resume,
		776	},
		777
		778	.name = DRIVER_NAME,
		779	.desc = DRIVER_DESC,
		780	.date = DRIVER_DATE,
		781	.major = KMS_DRIVER_MAJOR,
		782	.minor = KMS_DRIVER_MINOR,
		783	.patchlevel = KMS_DRIVER_PATCHLEVEL,
		784	};
		785	*/
		786
		787
		788	/*
		789	* Driver load/unload
		790	*/
		791	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
		792	{
		793	struct radeon_device *rdev;
		794	int r;
		795
		796	dbgprintf("%s\n\r",__FUNCTION__);
		797
		798	rdev = malloc(sizeof(struct radeon_device));
		799	if (rdev == NULL) {
		800	return -ENOMEM;
		801	};
		802
		803	dev->dev_private = (void *)rdev;
		804
		805	/* update BUS flag */
		806	// if (drm_device_is_agp(dev)) {
		807	flags \|= RADEON_IS_AGP;
		808	// } else if (drm_device_is_pcie(dev)) {
		809	// flags \|= RADEON_IS_PCIE;
		810	// } else {
		811	// flags \|= RADEON_IS_PCI;
		812	// }
		813
		814	r = radeon_device_init(rdev, dev, dev->pdev, flags);
		815	if (r) {
		816	dbgprintf("Failed to initialize Radeon, disabling IOCTL\n");
		817	// radeon_device_fini(rdev);
		818	return r;
		819	}
		820	return 0;
		821	}
		822
		823	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		824	{
		825	struct drm_device *dev;
		826	int ret;
		827
		828	dbgprintf("%s\n\r",__FUNCTION__);
		829
		830	dev = malloc(sizeof(*dev));
		831	if (!dev)
		832	return -ENOMEM;
		833
		834	// ret = pci_enable_device(pdev);
		835	// if (ret)
		836	// goto err_g1;
		837
		838	// pci_set_master(pdev);
		839
		840	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		841	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		842	// goto err_g2;
		843	// }
		844
		845	dev->pdev = pdev;
		846	dev->pci_device = pdev->device;
		847	dev->pci_vendor = pdev->vendor;
		848
		849	// if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		850	// pci_set_drvdata(pdev, dev);
		851	// ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
		852	// if (ret)
		853	// goto err_g2;
		854	// }
		855
		856	// if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
		857	// goto err_g3;
		858
		859	// if (dev->driver->load) {
		860	// ret = dev->driver->load(dev, ent->driver_data);
		861	// if (ret)
		862	// goto err_g4;
		863	// }
		864
		865	ret = radeon_driver_load_kms(dev, ent->driver_data );
		866	if (ret)
		867	goto err_g4;
		868
		869	// list_add_tail(&dev->driver_item, &driver->device_list);
		870
		871	// DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
		872	// driver->name, driver->major, driver->minor, driver->patchlevel,
		873	// driver->date, pci_name(pdev), dev->primary->index);
		874
		875	return 0;
		876
		877	err_g4:
		878	// drm_put_minor(&dev->primary);
		879	//err_g3:
		880	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		881	// drm_put_minor(&dev->control);
		882	//err_g2:
		883	// pci_disable_device(pdev);
		884	//err_g1:
		885	free(dev);
		886
		887	return ret;
		888	}
		889
		890	resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
		891	{
		892	return pci_resource_start(dev->pdev, resource);
		893	}
		894
		895	resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
		896	{
		897	return pci_resource_len(dev->pdev, resource);
		898	}
		899

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(root)/drivers/video/drm/radeon/radeon_device.c @ 2175 – Rev 1117