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| Rev | Author | Line No. | Line |
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| 5078 | serge | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: Dave Airlie |
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| 24 | * Alex Deucher |
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| 25 | */ |
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| 26 | #include |
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| 27 | #include |
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| 28 | #include "radeon.h" |
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| 29 | |||
| 30 | static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) |
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| 31 | { |
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| 32 | struct radeon_device *rdev = crtc->dev->dev_private; |
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| 33 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 34 | uint32_t cur_lock; |
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| 35 | |||
| 36 | if (ASIC_IS_DCE4(rdev)) { |
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| 37 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); |
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| 38 | if (lock) |
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| 39 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; |
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| 40 | else |
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| 41 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; |
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| 42 | WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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| 43 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 44 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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| 45 | if (lock) |
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| 46 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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| 47 | else |
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| 48 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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| 49 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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| 50 | } else { |
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| 51 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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| 52 | if (lock) |
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| 53 | cur_lock |= RADEON_CUR_LOCK; |
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| 54 | else |
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| 55 | cur_lock &= ~RADEON_CUR_LOCK; |
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| 56 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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| 57 | } |
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| 58 | } |
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| 59 | |||
| 60 | static void radeon_hide_cursor(struct drm_crtc *crtc) |
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| 61 | { |
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| 62 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 63 | struct radeon_device *rdev = crtc->dev->dev_private; |
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| 64 | |||
| 65 | if (ASIC_IS_DCE4(rdev)) { |
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| 66 | WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, |
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| 67 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | |
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| 68 | EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); |
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| 69 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 70 | WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, |
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| 71 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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| 72 | } else { |
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| 73 | u32 reg; |
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| 74 | switch (radeon_crtc->crtc_id) { |
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| 75 | case 0: |
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| 76 | reg = RADEON_CRTC_GEN_CNTL; |
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| 77 | break; |
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| 78 | case 1: |
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| 79 | reg = RADEON_CRTC2_GEN_CNTL; |
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| 80 | break; |
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| 81 | default: |
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| 82 | return; |
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| 83 | } |
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| 84 | WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); |
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| 85 | } |
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| 86 | } |
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| 87 | |||
| 88 | static void radeon_show_cursor(struct drm_crtc *crtc) |
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| 89 | { |
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| 90 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 91 | struct radeon_device *rdev = crtc->dev->dev_private; |
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| 92 | |||
| 93 | if (ASIC_IS_DCE4(rdev)) { |
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| 94 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); |
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| 95 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | |
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| 96 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | |
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| 97 | EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); |
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| 98 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 99 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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| 100 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
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| 101 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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| 102 | } else { |
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| 103 | switch (radeon_crtc->crtc_id) { |
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| 104 | case 0: |
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| 105 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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| 106 | break; |
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| 107 | case 1: |
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| 108 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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| 109 | break; |
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| 110 | default: |
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| 111 | return; |
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| 112 | } |
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| 113 | |||
| 114 | WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | |
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| 115 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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| 116 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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| 117 | } |
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| 118 | } |
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| 119 | |||
| 120 | static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, |
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| 121 | uint64_t gpu_addr) |
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| 122 | { |
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| 123 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 124 | struct radeon_device *rdev = crtc->dev->dev_private; |
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| 125 | |||
| 126 | if (ASIC_IS_DCE4(rdev)) { |
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| 127 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
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| 128 | upper_32_bits(gpu_addr)); |
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| 129 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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| 130 | gpu_addr & 0xffffffff); |
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| 131 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 132 | if (rdev->family >= CHIP_RV770) { |
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| 133 | if (radeon_crtc->crtc_id) |
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| 134 | WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); |
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| 135 | else |
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| 136 | WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); |
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| 137 | } |
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| 138 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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| 139 | gpu_addr & 0xffffffff); |
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| 140 | } else { |
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| 141 | radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; |
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| 142 | /* offset is from DISP(2)_BASE_ADDRESS */ |
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| 143 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
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| 144 | } |
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| 145 | } |
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| 146 | |||
| 147 | int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
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| 148 | struct drm_file *file_priv, |
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| 149 | uint32_t handle, |
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| 150 | uint32_t width, |
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| 151 | uint32_t height) |
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| 152 | { |
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| 153 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 154 | struct radeon_device *rdev = crtc->dev->dev_private; |
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| 155 | struct drm_gem_object *obj; |
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| 156 | struct radeon_bo *robj; |
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| 157 | uint64_t gpu_addr; |
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| 158 | int ret; |
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| 159 | |||
| 160 | if (!handle) { |
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| 161 | /* turn off cursor */ |
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| 162 | radeon_hide_cursor(crtc); |
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| 163 | obj = NULL; |
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| 164 | goto unpin; |
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| 165 | } |
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| 166 | |||
| 167 | if ((width > radeon_crtc->max_cursor_width) || |
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| 168 | (height > radeon_crtc->max_cursor_height)) { |
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| 169 | DRM_ERROR("bad cursor width or height %d x %d\n", width, height); |
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| 170 | return -EINVAL; |
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| 171 | } |
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| 172 | |||
| 173 | obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); |
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| 174 | if (!obj) { |
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| 175 | DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); |
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| 176 | return -ENOENT; |
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| 177 | } |
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| 178 | |||
| 179 | robj = gem_to_radeon_bo(obj); |
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| 180 | ret = radeon_bo_reserve(robj, false); |
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| 181 | if (unlikely(ret != 0)) |
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| 182 | goto fail; |
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| 183 | /* Only 27 bit offset for legacy cursor */ |
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| 184 | ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, |
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| 185 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, |
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| 186 | &gpu_addr); |
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| 187 | radeon_bo_unreserve(robj); |
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| 188 | if (ret) |
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| 189 | goto fail; |
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| 190 | |||
| 191 | radeon_crtc->cursor_width = width; |
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| 192 | radeon_crtc->cursor_height = height; |
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| 193 | |||
| 194 | radeon_lock_cursor(crtc, true); |
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| 195 | radeon_set_cursor(crtc, obj, gpu_addr); |
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| 196 | radeon_show_cursor(crtc); |
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| 197 | radeon_lock_cursor(crtc, false); |
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| 198 | |||
| 199 | unpin: |
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| 200 | if (radeon_crtc->cursor_bo) { |
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| 201 | robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); |
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| 202 | ret = radeon_bo_reserve(robj, false); |
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| 203 | if (likely(ret == 0)) { |
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| 204 | radeon_bo_unpin(robj); |
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| 205 | radeon_bo_unreserve(robj); |
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| 206 | } |
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| 207 | drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); |
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| 208 | } |
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| 209 | |||
| 210 | radeon_crtc->cursor_bo = obj; |
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| 211 | return 0; |
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| 212 | fail: |
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| 213 | drm_gem_object_unreference_unlocked(obj); |
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| 214 | |||
| 215 | return ret; |
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| 216 | } |
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| 217 | |||
| 218 | int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
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| 219 | int x, int y) |
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| 220 | { |
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| 221 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 222 | struct radeon_device *rdev = crtc->dev->dev_private; |
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| 223 | int xorigin = 0, yorigin = 0; |
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| 224 | int w = radeon_crtc->cursor_width; |
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| 225 | |||
| 226 | if (ASIC_IS_AVIVO(rdev)) { |
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| 227 | /* avivo cursor are offset into the total surface */ |
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| 228 | x += crtc->x; |
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| 229 | y += crtc->y; |
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| 230 | } |
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| 231 | DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); |
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| 232 | |||
| 233 | if (x < 0) { |
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| 234 | xorigin = min(-x, radeon_crtc->max_cursor_width - 1); |
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| 235 | x = 0; |
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| 236 | } |
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| 237 | if (y < 0) { |
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| 238 | yorigin = min(-y, radeon_crtc->max_cursor_height - 1); |
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| 239 | y = 0; |
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| 240 | } |
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| 241 | |||
| 242 | /* fixed on DCE6 and newer */ |
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| 243 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) { |
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| 244 | int i = 0; |
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| 245 | struct drm_crtc *crtc_p; |
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| 246 | |||
| 247 | /* |
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| 248 | * avivo cursor image can't end on 128 pixel boundary or |
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| 249 | * go past the end of the frame if both crtcs are enabled |
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| 250 | * |
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| 251 | * NOTE: It is safe to access crtc->enabled of other crtcs |
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| 252 | * without holding either the mode_config lock or the other |
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| 253 | * crtc's lock as long as write access to this flag _always_ |
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| 254 | * grabs all locks. |
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| 255 | */ |
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| 256 | list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { |
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| 257 | if (crtc_p->enabled) |
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| 258 | i++; |
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| 259 | } |
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| 260 | if (i > 1) { |
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| 261 | int cursor_end, frame_end; |
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| 262 | |||
| 263 | cursor_end = x - xorigin + w; |
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| 264 | frame_end = crtc->x + crtc->mode.crtc_hdisplay; |
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| 265 | if (cursor_end >= frame_end) { |
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| 266 | w = w - (cursor_end - frame_end); |
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| 267 | if (!(frame_end & 0x7f)) |
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| 268 | w--; |
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| 269 | } else { |
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| 270 | if (!(cursor_end & 0x7f)) |
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| 271 | w--; |
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| 272 | } |
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| 273 | if (w <= 0) { |
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| 274 | w = 1; |
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| 275 | cursor_end = x - xorigin + w; |
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| 276 | if (!(cursor_end & 0x7f)) { |
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| 277 | x--; |
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| 278 | WARN_ON_ONCE(x < 0); |
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| 279 | } |
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| 280 | } |
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| 281 | } |
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| 282 | } |
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| 283 | |||
| 284 | radeon_lock_cursor(crtc, true); |
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| 285 | if (ASIC_IS_DCE4(rdev)) { |
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| 286 | WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); |
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| 287 | WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); |
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| 288 | WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, |
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| 289 | ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); |
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| 290 | } else if (ASIC_IS_AVIVO(rdev)) { |
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| 291 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); |
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| 292 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); |
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| 293 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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| 294 | ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); |
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| 295 | } else { |
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| 296 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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| 297 | y *= 2; |
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| 298 | |||
| 299 | WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, |
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| 300 | (RADEON_CUR_LOCK |
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| 301 | | (xorigin << 16) |
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| 302 | | yorigin)); |
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| 303 | WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, |
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| 304 | (RADEON_CUR_LOCK |
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| 305 | | (x << 16) |
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| 306 | | y)); |
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| 307 | /* offset is from DISP(2)_BASE_ADDRESS */ |
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| 308 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + |
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| 309 | (yorigin * 256))); |
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| 310 | } |
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| 311 | radeon_lock_cursor(crtc, false); |
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| 312 | |||
| 313 | return 0; |
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| 314 | } |