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5078 | serge | 1 | /* |
2 | * Copyright 2008 Jerome Glisse. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Jerome Glisse |
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26 | */ |
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27 | #include |
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28 | #include |
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29 | #include |
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30 | #include "radeon_reg.h" |
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31 | #include "radeon.h" |
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32 | #include "radeon_trace.h" |
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33 | |||
34 | #define RADEON_CS_MAX_PRIORITY 32u |
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35 | #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1) |
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36 | |||
37 | static inline unsigned long |
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38 | copy_from_user(void *to, const void __user *from, unsigned long n) |
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39 | { |
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40 | memcpy(to, from, n); |
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41 | return n; |
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42 | } |
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43 | |||
44 | /* This is based on the bucket sort with O(n) time complexity. |
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45 | * An item with priority "i" is added to bucket[i]. The lists are then |
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46 | * concatenated in descending order. |
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47 | */ |
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48 | struct radeon_cs_buckets { |
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49 | struct list_head bucket[RADEON_CS_NUM_BUCKETS]; |
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50 | }; |
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51 | |||
52 | static void radeon_cs_buckets_init(struct radeon_cs_buckets *b) |
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53 | { |
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54 | unsigned i; |
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55 | |||
56 | for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) |
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57 | INIT_LIST_HEAD(&b->bucket[i]); |
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58 | } |
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59 | |||
60 | static void radeon_cs_buckets_add(struct radeon_cs_buckets *b, |
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61 | struct list_head *item, unsigned priority) |
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62 | { |
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63 | /* Since buffers which appear sooner in the relocation list are |
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64 | * likely to be used more often than buffers which appear later |
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65 | * in the list, the sort mustn't change the ordering of buffers |
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66 | * with the same priority, i.e. it must be stable. |
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67 | */ |
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68 | list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]); |
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69 | } |
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70 | |||
71 | static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b, |
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72 | struct list_head *out_list) |
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73 | { |
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74 | unsigned i; |
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75 | |||
76 | /* Connect the sorted buckets in the output list. */ |
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77 | for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) { |
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78 | list_splice(&b->bucket[i], out_list); |
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79 | } |
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80 | } |
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81 | |||
82 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
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83 | { |
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84 | struct drm_device *ddev = p->rdev->ddev; |
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85 | struct radeon_cs_chunk *chunk; |
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86 | struct radeon_cs_buckets buckets; |
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5271 | serge | 87 | unsigned i; |
88 | bool need_mmap_lock = false; |
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89 | int r; |
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5078 | serge | 90 | |
5271 | serge | 91 | if (p->chunk_relocs == NULL) { |
5078 | serge | 92 | return 0; |
93 | } |
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5271 | serge | 94 | chunk = p->chunk_relocs; |
5078 | serge | 95 | p->dma_reloc_idx = 0; |
96 | /* FIXME: we assume that each relocs use 4 dwords */ |
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97 | p->nrelocs = chunk->length_dw / 4; |
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5271 | serge | 98 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_bo_list), GFP_KERNEL); |
5078 | serge | 99 | if (p->relocs == NULL) { |
100 | return -ENOMEM; |
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101 | } |
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102 | |||
103 | radeon_cs_buckets_init(&buckets); |
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104 | |||
105 | for (i = 0; i < p->nrelocs; i++) { |
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106 | struct drm_radeon_cs_reloc *r; |
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5271 | serge | 107 | struct drm_gem_object *gobj; |
5078 | serge | 108 | unsigned priority; |
109 | |||
110 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; |
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5271 | serge | 111 | gobj = drm_gem_object_lookup(ddev, p->filp, r->handle); |
112 | if (gobj == NULL) { |
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5078 | serge | 113 | DRM_ERROR("gem object lookup failed 0x%x\n", |
114 | r->handle); |
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115 | return -ENOENT; |
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116 | } |
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5271 | serge | 117 | p->relocs[i].robj = gem_to_radeon_bo(gobj); |
5078 | serge | 118 | |
119 | /* The userspace buffer priorities are from 0 to 15. A higher |
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120 | * number means the buffer is more important. |
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121 | * Also, the buffers used for write have a higher priority than |
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122 | * the buffers used for read only, which doubles the range |
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123 | * to 0 to 31. 32 is reserved for the kernel driver. |
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124 | */ |
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125 | priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2 |
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126 | + !!r->write_domain; |
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127 | |||
128 | /* the first reloc of an UVD job is the msg and that must be in |
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5271 | serge | 129 | VRAM, also but everything into VRAM on AGP cards and older |
130 | IGP chips to avoid image corruptions */ |
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5078 | serge | 131 | if (p->ring == R600_RING_TYPE_UVD_INDEX && |
5271 | serge | 132 | (i == 0 || drm_pci_device_is_agp(p->rdev->ddev) || |
133 | p->rdev->family == CHIP_RS780 || |
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134 | p->rdev->family == CHIP_RS880)) { |
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135 | |||
5078 | serge | 136 | /* TODO: is this still needed for NI+ ? */ |
137 | p->relocs[i].prefered_domains = |
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138 | RADEON_GEM_DOMAIN_VRAM; |
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139 | |||
140 | p->relocs[i].allowed_domains = |
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141 | RADEON_GEM_DOMAIN_VRAM; |
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142 | |||
143 | /* prioritize this over any other relocation */ |
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144 | priority = RADEON_CS_MAX_PRIORITY; |
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145 | } else { |
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146 | uint32_t domain = r->write_domain ? |
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147 | r->write_domain : r->read_domains; |
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148 | |||
149 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
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150 | DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid " |
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151 | "for command submission\n"); |
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152 | return -EINVAL; |
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153 | } |
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154 | |||
155 | p->relocs[i].prefered_domains = domain; |
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156 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
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157 | domain |= RADEON_GEM_DOMAIN_GTT; |
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158 | p->relocs[i].allowed_domains = domain; |
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159 | } |
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5271 | serge | 160 | /* |
161 | if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) { |
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162 | uint32_t domain = p->relocs[i].prefered_domains; |
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163 | if (!(domain & RADEON_GEM_DOMAIN_GTT)) { |
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164 | DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is " |
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165 | "allowed for userptr BOs\n"); |
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166 | return -EINVAL; |
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167 | } |
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168 | need_mmap_lock = true; |
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169 | domain = RADEON_GEM_DOMAIN_GTT; |
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170 | p->relocs[i].prefered_domains = domain; |
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171 | p->relocs[i].allowed_domains = domain; |
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172 | } |
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173 | */ |
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5078 | serge | 174 | p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; |
5271 | serge | 175 | p->relocs[i].tv.shared = !r->write_domain; |
5078 | serge | 176 | |
177 | radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, |
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178 | priority); |
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179 | } |
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180 | |||
181 | radeon_cs_buckets_get_list(&buckets, &p->validated); |
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182 | |||
183 | if (p->cs_flags & RADEON_CS_USE_VM) |
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184 | p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm, |
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185 | &p->validated); |
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5271 | serge | 186 | // if (need_mmap_lock) |
187 | // down_read(¤t->mm->mmap_sem); |
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5078 | serge | 188 | |
5271 | serge | 189 | r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring); |
190 | |||
191 | // if (need_mmap_lock) |
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192 | // up_read(¤t->mm->mmap_sem); |
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193 | |||
194 | return r; |
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5078 | serge | 195 | } |
196 | |||
197 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
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198 | { |
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199 | p->priority = priority; |
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200 | |||
201 | switch (ring) { |
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202 | default: |
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203 | DRM_ERROR("unknown ring id: %d\n", ring); |
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204 | return -EINVAL; |
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205 | case RADEON_CS_RING_GFX: |
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206 | p->ring = RADEON_RING_TYPE_GFX_INDEX; |
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207 | break; |
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208 | case RADEON_CS_RING_COMPUTE: |
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209 | if (p->rdev->family >= CHIP_TAHITI) { |
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210 | if (p->priority > 0) |
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211 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX; |
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212 | else |
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213 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX; |
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214 | } else |
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215 | p->ring = RADEON_RING_TYPE_GFX_INDEX; |
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216 | break; |
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217 | case RADEON_CS_RING_DMA: |
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218 | if (p->rdev->family >= CHIP_CAYMAN) { |
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219 | if (p->priority > 0) |
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220 | p->ring = R600_RING_TYPE_DMA_INDEX; |
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221 | else |
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222 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; |
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223 | } else if (p->rdev->family >= CHIP_RV770) { |
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224 | p->ring = R600_RING_TYPE_DMA_INDEX; |
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225 | } else { |
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226 | return -EINVAL; |
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227 | } |
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228 | break; |
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229 | case RADEON_CS_RING_UVD: |
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230 | p->ring = R600_RING_TYPE_UVD_INDEX; |
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231 | break; |
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232 | case RADEON_CS_RING_VCE: |
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233 | /* TODO: only use the low priority ring for now */ |
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234 | p->ring = TN_RING_TYPE_VCE1_INDEX; |
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235 | break; |
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236 | } |
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237 | return 0; |
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238 | } |
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239 | |||
5271 | serge | 240 | static int radeon_cs_sync_rings(struct radeon_cs_parser *p) |
5078 | serge | 241 | { |
5271 | serge | 242 | struct radeon_bo_list *reloc; |
243 | int r; |
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5078 | serge | 244 | |
5271 | serge | 245 | list_for_each_entry(reloc, &p->validated, tv.head) { |
246 | struct reservation_object *resv; |
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5078 | serge | 247 | |
5271 | serge | 248 | resv = reloc->robj->tbo.resv; |
249 | r = radeon_sync_resv(p->rdev, &p->ib.sync, resv, |
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250 | reloc->tv.shared); |
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251 | if (r) |
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252 | return r; |
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5078 | serge | 253 | } |
5271 | serge | 254 | return 0; |
5078 | serge | 255 | } |
256 | |||
257 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
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258 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
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259 | { |
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260 | struct drm_radeon_cs *cs = data; |
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261 | uint64_t *chunk_array_ptr; |
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262 | unsigned size, i; |
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263 | u32 ring = RADEON_CS_RING_GFX; |
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264 | s32 priority = 0; |
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265 | |||
266 | if (!cs->num_chunks) { |
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267 | return 0; |
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268 | } |
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269 | /* get chunks */ |
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270 | INIT_LIST_HEAD(&p->validated); |
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271 | p->idx = 0; |
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272 | p->ib.sa_bo = NULL; |
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273 | p->const_ib.sa_bo = NULL; |
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5271 | serge | 274 | p->chunk_ib = NULL; |
275 | p->chunk_relocs = NULL; |
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276 | p->chunk_flags = NULL; |
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277 | p->chunk_const_ib = NULL; |
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5078 | serge | 278 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
279 | if (p->chunks_array == NULL) { |
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280 | return -ENOMEM; |
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281 | } |
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282 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); |
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283 | if (copy_from_user(p->chunks_array, chunk_array_ptr, |
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284 | sizeof(uint64_t)*cs->num_chunks)) { |
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285 | return -EFAULT; |
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286 | } |
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287 | p->cs_flags = 0; |
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288 | p->nchunks = cs->num_chunks; |
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289 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); |
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290 | if (p->chunks == NULL) { |
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291 | return -ENOMEM; |
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292 | } |
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293 | for (i = 0; i < p->nchunks; i++) { |
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294 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; |
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295 | struct drm_radeon_cs_chunk user_chunk; |
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296 | uint32_t __user *cdata; |
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297 | |||
298 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; |
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299 | if (copy_from_user(&user_chunk, chunk_ptr, |
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300 | sizeof(struct drm_radeon_cs_chunk))) { |
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301 | return -EFAULT; |
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302 | } |
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303 | p->chunks[i].length_dw = user_chunk.length_dw; |
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5271 | serge | 304 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) { |
305 | p->chunk_relocs = &p->chunks[i]; |
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5078 | serge | 306 | } |
5271 | serge | 307 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) { |
308 | p->chunk_ib = &p->chunks[i]; |
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5078 | serge | 309 | /* zero length IB isn't useful */ |
310 | if (p->chunks[i].length_dw == 0) |
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311 | return -EINVAL; |
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312 | } |
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5271 | serge | 313 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) { |
314 | p->chunk_const_ib = &p->chunks[i]; |
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5078 | serge | 315 | /* zero length CONST IB isn't useful */ |
316 | if (p->chunks[i].length_dw == 0) |
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317 | return -EINVAL; |
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318 | } |
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5271 | serge | 319 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) { |
320 | p->chunk_flags = &p->chunks[i]; |
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5078 | serge | 321 | /* zero length flags aren't useful */ |
322 | if (p->chunks[i].length_dw == 0) |
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323 | return -EINVAL; |
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324 | } |
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325 | |||
326 | size = p->chunks[i].length_dw; |
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327 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
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328 | p->chunks[i].user_ptr = cdata; |
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5271 | serge | 329 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) |
5078 | serge | 330 | continue; |
331 | |||
5271 | serge | 332 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) { |
5078 | serge | 333 | if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP)) |
334 | continue; |
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335 | } |
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336 | |||
337 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); |
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338 | size *= sizeof(uint32_t); |
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339 | if (p->chunks[i].kdata == NULL) { |
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340 | return -ENOMEM; |
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341 | } |
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342 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { |
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343 | return -EFAULT; |
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344 | } |
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5271 | serge | 345 | if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) { |
5078 | serge | 346 | p->cs_flags = p->chunks[i].kdata[0]; |
347 | if (p->chunks[i].length_dw > 1) |
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348 | ring = p->chunks[i].kdata[1]; |
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349 | if (p->chunks[i].length_dw > 2) |
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350 | priority = (s32)p->chunks[i].kdata[2]; |
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351 | } |
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352 | } |
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353 | |||
354 | /* these are KMS only */ |
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355 | if (p->rdev) { |
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356 | if ((p->cs_flags & RADEON_CS_USE_VM) && |
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357 | !p->rdev->vm_manager.enabled) { |
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358 | DRM_ERROR("VM not active on asic!\n"); |
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359 | return -EINVAL; |
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360 | } |
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361 | |||
362 | if (radeon_cs_get_ring(p, ring, priority)) |
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363 | return -EINVAL; |
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364 | |||
365 | /* we only support VM on some SI+ rings */ |
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366 | if ((p->cs_flags & RADEON_CS_USE_VM) == 0) { |
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367 | if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) { |
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368 | DRM_ERROR("Ring %d requires VM!\n", p->ring); |
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369 | return -EINVAL; |
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370 | } |
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371 | } else { |
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372 | if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) { |
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373 | DRM_ERROR("VM not supported on ring %d!\n", |
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374 | p->ring); |
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375 | return -EINVAL; |
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376 | } |
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377 | } |
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378 | } |
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379 | |||
380 | return 0; |
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381 | } |
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382 | |||
383 | static int cmp_size_smaller_first(void *priv, struct list_head *a, |
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384 | struct list_head *b) |
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385 | { |
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5271 | serge | 386 | struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head); |
387 | struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head); |
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5078 | serge | 388 | |
389 | /* Sort A before B if A is smaller. */ |
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390 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; |
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391 | } |
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392 | |||
393 | /** |
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394 | * cs_parser_fini() - clean parser states |
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395 | * @parser: parser structure holding parsing context. |
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396 | * @error: error number |
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397 | * |
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398 | * If error is set than unvalidate buffer, otherwise just free memory |
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399 | * used by parsing context. |
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400 | **/ |
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401 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) |
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402 | { |
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403 | unsigned i; |
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404 | |||
405 | if (!error) { |
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406 | /* Sort the buffer list from the smallest to largest buffer, |
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407 | * which affects the order of buffers in the LRU list. |
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408 | * This assures that the smallest buffers are added first |
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409 | * to the LRU list, so they are likely to be later evicted |
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410 | * first, instead of large buffers whose eviction is more |
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411 | * expensive. |
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412 | * |
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413 | * This slightly lowers the number of bytes moved by TTM |
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414 | * per frame under memory pressure. |
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415 | */ |
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416 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); |
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417 | |||
418 | ttm_eu_fence_buffer_objects(&parser->ticket, |
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419 | &parser->validated, |
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5271 | serge | 420 | &parser->ib.fence->base); |
5078 | serge | 421 | } else if (backoff) { |
422 | ttm_eu_backoff_reservation(&parser->ticket, |
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423 | &parser->validated); |
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424 | } |
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425 | |||
426 | if (parser->relocs != NULL) { |
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427 | for (i = 0; i < parser->nrelocs; i++) { |
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5271 | serge | 428 | struct radeon_bo *bo = parser->relocs[i].robj; |
429 | if (bo == NULL) |
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430 | continue; |
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431 | |||
432 | drm_gem_object_unreference_unlocked(&bo->gem_base); |
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5078 | serge | 433 | } |
434 | } |
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435 | kfree(parser->track); |
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436 | kfree(parser->relocs); |
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5271 | serge | 437 | drm_free_large(parser->vm_bos); |
5078 | serge | 438 | for (i = 0; i < parser->nchunks; i++) |
439 | drm_free_large(parser->chunks[i].kdata); |
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440 | kfree(parser->chunks); |
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441 | kfree(parser->chunks_array); |
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442 | radeon_ib_free(parser->rdev, &parser->ib); |
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443 | radeon_ib_free(parser->rdev, &parser->const_ib); |
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444 | } |
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445 | |||
446 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
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447 | struct radeon_cs_parser *parser) |
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448 | { |
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449 | int r; |
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450 | |||
5271 | serge | 451 | if (parser->chunk_ib == NULL) |
5078 | serge | 452 | return 0; |
453 | |||
454 | if (parser->cs_flags & RADEON_CS_USE_VM) |
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455 | return 0; |
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456 | |||
457 | r = radeon_cs_parse(rdev, parser->ring, parser); |
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458 | if (r || parser->parser_error) { |
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459 | DRM_ERROR("Invalid command stream !\n"); |
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460 | return r; |
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461 | } |
||
462 | |||
5271 | serge | 463 | r = radeon_cs_sync_rings(parser); |
464 | if (r) { |
||
465 | if (r != -ERESTARTSYS) |
||
466 | DRM_ERROR("Failed to sync rings: %i\n", r); |
||
467 | return r; |
||
468 | } |
||
469 | |||
5078 | serge | 470 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) |
471 | radeon_uvd_note_usage(rdev); |
||
472 | else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) || |
||
473 | (parser->ring == TN_RING_TYPE_VCE2_INDEX)) |
||
474 | radeon_vce_note_usage(rdev); |
||
475 | |||
476 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
||
477 | if (r) { |
||
478 | DRM_ERROR("Failed to schedule IB !\n"); |
||
479 | } |
||
480 | return r; |
||
481 | } |
||
482 | |||
483 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, |
||
484 | struct radeon_vm *vm) |
||
485 | { |
||
486 | struct radeon_device *rdev = p->rdev; |
||
487 | struct radeon_bo_va *bo_va; |
||
488 | int i, r; |
||
489 | |||
490 | r = radeon_vm_update_page_directory(rdev, vm); |
||
491 | if (r) |
||
492 | return r; |
||
493 | |||
494 | r = radeon_vm_clear_freed(rdev, vm); |
||
495 | if (r) |
||
496 | return r; |
||
497 | |||
498 | if (vm->ib_bo_va == NULL) { |
||
499 | DRM_ERROR("Tmp BO not in VM!\n"); |
||
500 | return -EINVAL; |
||
501 | } |
||
502 | |||
503 | r = radeon_vm_bo_update(rdev, vm->ib_bo_va, |
||
504 | &rdev->ring_tmp_bo.bo->tbo.mem); |
||
505 | if (r) |
||
506 | return r; |
||
507 | |||
508 | for (i = 0; i < p->nrelocs; i++) { |
||
509 | struct radeon_bo *bo; |
||
510 | |||
511 | bo = p->relocs[i].robj; |
||
512 | bo_va = radeon_vm_bo_find(vm, bo); |
||
513 | if (bo_va == NULL) { |
||
514 | dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); |
||
515 | return -EINVAL; |
||
516 | } |
||
517 | |||
518 | r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem); |
||
519 | if (r) |
||
520 | return r; |
||
5271 | serge | 521 | |
522 | radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update); |
||
5078 | serge | 523 | } |
524 | |||
525 | return radeon_vm_clear_invalids(rdev, vm); |
||
526 | } |
||
527 | |||
528 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, |
||
529 | struct radeon_cs_parser *parser) |
||
530 | { |
||
531 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; |
||
532 | struct radeon_vm *vm = &fpriv->vm; |
||
533 | int r; |
||
534 | |||
5271 | serge | 535 | if (parser->chunk_ib == NULL) |
5078 | serge | 536 | return 0; |
537 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) |
||
538 | return 0; |
||
539 | |||
540 | if (parser->const_ib.length_dw) { |
||
541 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); |
||
542 | if (r) { |
||
543 | return r; |
||
544 | } |
||
545 | } |
||
546 | |||
547 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); |
||
548 | if (r) { |
||
549 | return r; |
||
550 | } |
||
551 | |||
552 | if (parser->ring == R600_RING_TYPE_UVD_INDEX) |
||
553 | radeon_uvd_note_usage(rdev); |
||
554 | |||
555 | mutex_lock(&vm->mutex); |
||
556 | r = radeon_bo_vm_update_pte(parser, vm); |
||
557 | if (r) { |
||
558 | goto out; |
||
559 | } |
||
560 | |||
5271 | serge | 561 | r = radeon_cs_sync_rings(parser); |
562 | if (r) { |
||
563 | if (r != -ERESTARTSYS) |
||
564 | DRM_ERROR("Failed to sync rings: %i\n", r); |
||
565 | goto out; |
||
566 | } |
||
567 | |||
5078 | serge | 568 | if ((rdev->family >= CHIP_TAHITI) && |
5271 | serge | 569 | (parser->chunk_const_ib != NULL)) { |
5078 | serge | 570 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true); |
571 | } else { |
||
572 | r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); |
||
573 | } |
||
574 | |||
575 | out: |
||
576 | mutex_unlock(&vm->mutex); |
||
577 | return r; |
||
578 | } |
||
579 | |||
580 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
||
581 | { |
||
582 | if (r == -EDEADLK) { |
||
583 | r = radeon_gpu_reset(rdev); |
||
584 | if (!r) |
||
585 | r = -EAGAIN; |
||
586 | } |
||
587 | return r; |
||
588 | } |
||
589 | |||
590 | static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser) |
||
591 | { |
||
592 | struct radeon_cs_chunk *ib_chunk; |
||
593 | struct radeon_vm *vm = NULL; |
||
594 | int r; |
||
595 | |||
5271 | serge | 596 | if (parser->chunk_ib == NULL) |
5078 | serge | 597 | return 0; |
598 | |||
599 | if (parser->cs_flags & RADEON_CS_USE_VM) { |
||
600 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; |
||
601 | vm = &fpriv->vm; |
||
602 | |||
603 | if ((rdev->family >= CHIP_TAHITI) && |
||
5271 | serge | 604 | (parser->chunk_const_ib != NULL)) { |
605 | ib_chunk = parser->chunk_const_ib; |
||
5078 | serge | 606 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { |
607 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); |
||
608 | return -EINVAL; |
||
609 | } |
||
610 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, |
||
611 | vm, ib_chunk->length_dw * 4); |
||
612 | if (r) { |
||
613 | DRM_ERROR("Failed to get const ib !\n"); |
||
614 | return r; |
||
615 | } |
||
616 | parser->const_ib.is_const_ib = true; |
||
617 | parser->const_ib.length_dw = ib_chunk->length_dw; |
||
618 | if (copy_from_user(parser->const_ib.ptr, |
||
619 | ib_chunk->user_ptr, |
||
620 | ib_chunk->length_dw * 4)) |
||
621 | return -EFAULT; |
||
622 | } |
||
623 | |||
5271 | serge | 624 | ib_chunk = parser->chunk_ib; |
5078 | serge | 625 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { |
626 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); |
||
627 | return -EINVAL; |
||
628 | } |
||
629 | } |
||
5271 | serge | 630 | ib_chunk = parser->chunk_ib; |
5078 | serge | 631 | |
632 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, |
||
633 | vm, ib_chunk->length_dw * 4); |
||
634 | if (r) { |
||
635 | DRM_ERROR("Failed to get ib !\n"); |
||
636 | return r; |
||
637 | } |
||
638 | parser->ib.length_dw = ib_chunk->length_dw; |
||
639 | if (ib_chunk->kdata) |
||
640 | memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); |
||
641 | else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) |
||
642 | return -EFAULT; |
||
643 | return 0; |
||
644 | } |
||
645 | |||
646 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
||
647 | { |
||
648 | struct radeon_device *rdev = dev->dev_private; |
||
649 | struct radeon_cs_parser parser; |
||
650 | int r; |
||
651 | |||
652 | // down_read(&rdev->exclusive_lock); |
||
653 | if (!rdev->accel_working) { |
||
654 | // up_read(&rdev->exclusive_lock); |
||
655 | return -EBUSY; |
||
656 | } |
||
657 | /* initialize parser */ |
||
658 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); |
||
659 | parser.filp = filp; |
||
660 | parser.rdev = rdev; |
||
661 | parser.dev = rdev->dev; |
||
662 | parser.family = rdev->family; |
||
663 | r = radeon_cs_parser_init(&parser, data); |
||
664 | if (r) { |
||
665 | DRM_ERROR("Failed to initialize parser !\n"); |
||
666 | radeon_cs_parser_fini(&parser, r, false); |
||
667 | // up_read(&rdev->exclusive_lock); |
||
668 | r = radeon_cs_handle_lockup(rdev, r); |
||
669 | return r; |
||
670 | } |
||
671 | |||
672 | r = radeon_cs_ib_fill(rdev, &parser); |
||
673 | if (!r) { |
||
674 | r = radeon_cs_parser_relocs(&parser); |
||
675 | if (r && r != -ERESTARTSYS) |
||
676 | DRM_ERROR("Failed to parse relocation %d!\n", r); |
||
677 | } |
||
678 | |||
679 | if (r) { |
||
680 | radeon_cs_parser_fini(&parser, r, false); |
||
681 | // up_read(&rdev->exclusive_lock); |
||
682 | r = radeon_cs_handle_lockup(rdev, r); |
||
683 | return r; |
||
684 | } |
||
685 | |||
686 | trace_radeon_cs(&parser); |
||
687 | |||
688 | r = radeon_cs_ib_chunk(rdev, &parser); |
||
689 | if (r) { |
||
690 | goto out; |
||
691 | } |
||
692 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
||
693 | if (r) { |
||
694 | goto out; |
||
695 | } |
||
696 | out: |
||
697 | radeon_cs_parser_fini(&parser, r, true); |
||
698 | // up_read(&rdev->exclusive_lock); |
||
699 | r = radeon_cs_handle_lockup(rdev, r); |
||
700 | return r; |
||
701 | } |
||
702 | |||
703 | /** |
||
704 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet |
||
705 | * @parser: parser structure holding parsing context. |
||
706 | * @pkt: where to store packet information |
||
707 | * |
||
708 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
||
709 | * if packet is bigger than remaining ib size. or if packets is unknown. |
||
710 | **/ |
||
711 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
||
712 | struct radeon_cs_packet *pkt, |
||
713 | unsigned idx) |
||
714 | { |
||
5271 | serge | 715 | struct radeon_cs_chunk *ib_chunk = p->chunk_ib; |
5078 | serge | 716 | struct radeon_device *rdev = p->rdev; |
717 | uint32_t header; |
||
718 | |||
719 | if (idx >= ib_chunk->length_dw) { |
||
720 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
||
721 | idx, ib_chunk->length_dw); |
||
722 | return -EINVAL; |
||
723 | } |
||
724 | header = radeon_get_ib_value(p, idx); |
||
725 | pkt->idx = idx; |
||
726 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header); |
||
727 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header); |
||
728 | pkt->one_reg_wr = 0; |
||
729 | switch (pkt->type) { |
||
730 | case RADEON_PACKET_TYPE0: |
||
731 | if (rdev->family < CHIP_R600) { |
||
732 | pkt->reg = R100_CP_PACKET0_GET_REG(header); |
||
733 | pkt->one_reg_wr = |
||
734 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header); |
||
735 | } else |
||
736 | pkt->reg = R600_CP_PACKET0_GET_REG(header); |
||
737 | break; |
||
738 | case RADEON_PACKET_TYPE3: |
||
739 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); |
||
740 | break; |
||
741 | case RADEON_PACKET_TYPE2: |
||
742 | pkt->count = -1; |
||
743 | break; |
||
744 | default: |
||
745 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
||
746 | return -EINVAL; |
||
747 | } |
||
748 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
||
749 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
||
750 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
||
751 | return -EINVAL; |
||
752 | } |
||
753 | return 0; |
||
754 | } |
||
755 | |||
756 | /** |
||
757 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP |
||
758 | * @p: structure holding the parser context. |
||
759 | * |
||
760 | * Check if the next packet is NOP relocation packet3. |
||
761 | **/ |
||
762 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) |
||
763 | { |
||
764 | struct radeon_cs_packet p3reloc; |
||
765 | int r; |
||
766 | |||
767 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); |
||
768 | if (r) |
||
769 | return false; |
||
770 | if (p3reloc.type != RADEON_PACKET_TYPE3) |
||
771 | return false; |
||
772 | if (p3reloc.opcode != RADEON_PACKET3_NOP) |
||
773 | return false; |
||
774 | return true; |
||
775 | } |
||
776 | |||
777 | /** |
||
778 | * radeon_cs_dump_packet() - dump raw packet context |
||
779 | * @p: structure holding the parser context. |
||
780 | * @pkt: structure holding the packet. |
||
781 | * |
||
782 | * Used mostly for debugging and error reporting. |
||
783 | **/ |
||
784 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
||
785 | struct radeon_cs_packet *pkt) |
||
786 | { |
||
787 | volatile uint32_t *ib; |
||
788 | unsigned i; |
||
789 | unsigned idx; |
||
790 | |||
791 | ib = p->ib.ptr; |
||
792 | idx = pkt->idx; |
||
793 | for (i = 0; i <= (pkt->count + 1); i++, idx++) |
||
794 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
||
795 | } |
||
796 | |||
797 | /** |
||
798 | * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet |
||
799 | * @parser: parser structure holding parsing context. |
||
800 | * @data: pointer to relocation data |
||
801 | * @offset_start: starting offset |
||
802 | * @offset_mask: offset mask (to align start offset on) |
||
803 | * @reloc: reloc informations |
||
804 | * |
||
805 | * Check if next packet is relocation packet3, do bo validation and compute |
||
806 | * GPU offset using the provided start. |
||
807 | **/ |
||
808 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
||
5271 | serge | 809 | struct radeon_bo_list **cs_reloc, |
5078 | serge | 810 | int nomm) |
811 | { |
||
812 | struct radeon_cs_chunk *relocs_chunk; |
||
813 | struct radeon_cs_packet p3reloc; |
||
814 | unsigned idx; |
||
815 | int r; |
||
816 | |||
5271 | serge | 817 | if (p->chunk_relocs == NULL) { |
5078 | serge | 818 | DRM_ERROR("No relocation chunk !\n"); |
819 | return -EINVAL; |
||
820 | } |
||
821 | *cs_reloc = NULL; |
||
5271 | serge | 822 | relocs_chunk = p->chunk_relocs; |
5078 | serge | 823 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); |
824 | if (r) |
||
825 | return r; |
||
826 | p->idx += p3reloc.count + 2; |
||
827 | if (p3reloc.type != RADEON_PACKET_TYPE3 || |
||
828 | p3reloc.opcode != RADEON_PACKET3_NOP) { |
||
829 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
||
830 | p3reloc.idx); |
||
831 | radeon_cs_dump_packet(p, &p3reloc); |
||
832 | return -EINVAL; |
||
833 | } |
||
834 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
||
835 | if (idx >= relocs_chunk->length_dw) { |
||
836 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
||
837 | idx, relocs_chunk->length_dw); |
||
838 | radeon_cs_dump_packet(p, &p3reloc); |
||
839 | return -EINVAL; |
||
840 | } |
||
841 | /* FIXME: we assume reloc size is 4 dwords */ |
||
842 | if (nomm) { |
||
843 | *cs_reloc = p->relocs; |
||
844 | (*cs_reloc)->gpu_offset = |
||
845 | (u64)relocs_chunk->kdata[idx + 3] << 32; |
||
846 | (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; |
||
847 | } else |
||
5271 | serge | 848 | *cs_reloc = &p->relocs[(idx / 4)]; |
5078 | serge | 849 | return 0; |
850 | }><>=>>>>>>>>> |