WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_combios.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2004 ATI Technologies Inc., Markham, Ontario
		3	* Copyright 2007-8 Advanced Micro Devices, Inc.
		4	* Copyright 2008 Red Hat Inc.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	*/
2997	Serge	27	#include
		28	#include
1123	serge	29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	#ifdef CONFIG_PPC_PMAC
		33	/* not sure which of these are needed */
		34	#include
		35	#include
		36	#include
		37	#include
		38	#endif /* CONFIG_PPC_PMAC */
		39
		40	/* from radeon_encoder.c */
		41	extern uint32_t
1963	serge	42	radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
1123	serge	43	uint8_t dac);
		44	extern void radeon_link_encoder_connector(struct drm_device *dev);
		45
		46	/* from radeon_connector.c */
		47	extern void
		48	radeon_add_legacy_connector(struct drm_device *dev,
		49	uint32_t connector_id,
		50	uint32_t supported_device,
		51	int connector_type,
1268	serge	52	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	53	uint16_t connector_object_id,
		54	struct radeon_hpd *hpd);
1123	serge	55
		56	/* from radeon_legacy_encoder.c */
		57	extern void
1963	serge	58	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
1123	serge	59	uint32_t supported_device);
		60
		61	/* old legacy ATI BIOS routines */
		62
		63	/* COMBIOS table offsets */
		64	enum radeon_combios_table_offset {
		65	/* absolute offset tables */
		66	COMBIOS_ASIC_INIT_1_TABLE,
		67	COMBIOS_BIOS_SUPPORT_TABLE,
		68	COMBIOS_DAC_PROGRAMMING_TABLE,
		69	COMBIOS_MAX_COLOR_DEPTH_TABLE,
		70	COMBIOS_CRTC_INFO_TABLE,
		71	COMBIOS_PLL_INFO_TABLE,
		72	COMBIOS_TV_INFO_TABLE,
		73	COMBIOS_DFP_INFO_TABLE,
		74	COMBIOS_HW_CONFIG_INFO_TABLE,
		75	COMBIOS_MULTIMEDIA_INFO_TABLE,
		76	COMBIOS_TV_STD_PATCH_TABLE,
		77	COMBIOS_LCD_INFO_TABLE,
		78	COMBIOS_MOBILE_INFO_TABLE,
		79	COMBIOS_PLL_INIT_TABLE,
		80	COMBIOS_MEM_CONFIG_TABLE,
		81	COMBIOS_SAVE_MASK_TABLE,
		82	COMBIOS_HARDCODED_EDID_TABLE,
		83	COMBIOS_ASIC_INIT_2_TABLE,
		84	COMBIOS_CONNECTOR_INFO_TABLE,
		85	COMBIOS_DYN_CLK_1_TABLE,
		86	COMBIOS_RESERVED_MEM_TABLE,
		87	COMBIOS_EXT_TMDS_INFO_TABLE,
		88	COMBIOS_MEM_CLK_INFO_TABLE,
		89	COMBIOS_EXT_DAC_INFO_TABLE,
		90	COMBIOS_MISC_INFO_TABLE,
		91	COMBIOS_CRT_INFO_TABLE,
		92	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
		93	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
		94	COMBIOS_FAN_SPEED_INFO_TABLE,
		95	COMBIOS_OVERDRIVE_INFO_TABLE,
		96	COMBIOS_OEM_INFO_TABLE,
		97	COMBIOS_DYN_CLK_2_TABLE,
		98	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
		99	COMBIOS_I2C_INFO_TABLE,
		100	/* relative offset tables */
		101	COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
		102	COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
		103	COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
		104	COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
		105	COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
		106	COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
		107	COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
		108	COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
		109	COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
		110	COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
		111	COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
		112	};
		113
		114	enum radeon_combios_ddc {
		115	DDC_NONE_DETECTED,
		116	DDC_MONID,
		117	DDC_DVI,
		118	DDC_VGA,
		119	DDC_CRT2,
		120	DDC_LCD,
		121	DDC_GPIO,
		122	};
		123
		124	enum radeon_combios_connector {
		125	CONNECTOR_NONE_LEGACY,
		126	CONNECTOR_PROPRIETARY_LEGACY,
		127	CONNECTOR_CRT_LEGACY,
		128	CONNECTOR_DVI_I_LEGACY,
		129	CONNECTOR_DVI_D_LEGACY,
		130	CONNECTOR_CTV_LEGACY,
		131	CONNECTOR_STV_LEGACY,
		132	CONNECTOR_UNSUPPORTED_LEGACY
		133	};
		134
		135	const int legacy_connector_convert[] = {
		136	DRM_MODE_CONNECTOR_Unknown,
		137	DRM_MODE_CONNECTOR_DVID,
		138	DRM_MODE_CONNECTOR_VGA,
		139	DRM_MODE_CONNECTOR_DVII,
		140	DRM_MODE_CONNECTOR_DVID,
		141	DRM_MODE_CONNECTOR_Composite,
		142	DRM_MODE_CONNECTOR_SVIDEO,
		143	DRM_MODE_CONNECTOR_Unknown,
		144	};
		145
		146	static uint16_t combios_get_table_offset(struct drm_device *dev,
		147	enum radeon_combios_table_offset table)
		148	{
		149	struct radeon_device *rdev = dev->dev_private;
		150	int rev;
		151	uint16_t offset = 0, check_offset;
		152
1430	serge	153	if (!rdev->bios)
		154	return 0;
		155
1123	serge	156	switch (table) {
		157	/* absolute offset tables */
		158	case COMBIOS_ASIC_INIT_1_TABLE:
		159	check_offset = RBIOS16(rdev->bios_header_start + 0xc);
		160	if (check_offset)
		161	offset = check_offset;
		162	break;
		163	case COMBIOS_BIOS_SUPPORT_TABLE:
		164	check_offset = RBIOS16(rdev->bios_header_start + 0x14);
		165	if (check_offset)
		166	offset = check_offset;
		167	break;
		168	case COMBIOS_DAC_PROGRAMMING_TABLE:
		169	check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
		170	if (check_offset)
		171	offset = check_offset;
		172	break;
		173	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		174	check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
		175	if (check_offset)
		176	offset = check_offset;
		177	break;
		178	case COMBIOS_CRTC_INFO_TABLE:
		179	check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
		180	if (check_offset)
		181	offset = check_offset;
		182	break;
		183	case COMBIOS_PLL_INFO_TABLE:
		184	check_offset = RBIOS16(rdev->bios_header_start + 0x30);
		185	if (check_offset)
		186	offset = check_offset;
		187	break;
		188	case COMBIOS_TV_INFO_TABLE:
		189	check_offset = RBIOS16(rdev->bios_header_start + 0x32);
		190	if (check_offset)
		191	offset = check_offset;
		192	break;
		193	case COMBIOS_DFP_INFO_TABLE:
		194	check_offset = RBIOS16(rdev->bios_header_start + 0x34);
		195	if (check_offset)
		196	offset = check_offset;
		197	break;
		198	case COMBIOS_HW_CONFIG_INFO_TABLE:
		199	check_offset = RBIOS16(rdev->bios_header_start + 0x36);
		200	if (check_offset)
		201	offset = check_offset;
		202	break;
		203	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		204	check_offset = RBIOS16(rdev->bios_header_start + 0x38);
		205	if (check_offset)
		206	offset = check_offset;
		207	break;
		208	case COMBIOS_TV_STD_PATCH_TABLE:
		209	check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
		210	if (check_offset)
		211	offset = check_offset;
		212	break;
		213	case COMBIOS_LCD_INFO_TABLE:
		214	check_offset = RBIOS16(rdev->bios_header_start + 0x40);
		215	if (check_offset)
		216	offset = check_offset;
		217	break;
		218	case COMBIOS_MOBILE_INFO_TABLE:
		219	check_offset = RBIOS16(rdev->bios_header_start + 0x42);
		220	if (check_offset)
		221	offset = check_offset;
		222	break;
		223	case COMBIOS_PLL_INIT_TABLE:
		224	check_offset = RBIOS16(rdev->bios_header_start + 0x46);
		225	if (check_offset)
		226	offset = check_offset;
		227	break;
		228	case COMBIOS_MEM_CONFIG_TABLE:
		229	check_offset = RBIOS16(rdev->bios_header_start + 0x48);
		230	if (check_offset)
		231	offset = check_offset;
		232	break;
		233	case COMBIOS_SAVE_MASK_TABLE:
		234	check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
		235	if (check_offset)
		236	offset = check_offset;
		237	break;
		238	case COMBIOS_HARDCODED_EDID_TABLE:
		239	check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
		240	if (check_offset)
		241	offset = check_offset;
		242	break;
		243	case COMBIOS_ASIC_INIT_2_TABLE:
		244	check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
		245	if (check_offset)
		246	offset = check_offset;
		247	break;
		248	case COMBIOS_CONNECTOR_INFO_TABLE:
		249	check_offset = RBIOS16(rdev->bios_header_start + 0x50);
		250	if (check_offset)
		251	offset = check_offset;
		252	break;
		253	case COMBIOS_DYN_CLK_1_TABLE:
		254	check_offset = RBIOS16(rdev->bios_header_start + 0x52);
		255	if (check_offset)
		256	offset = check_offset;
		257	break;
		258	case COMBIOS_RESERVED_MEM_TABLE:
		259	check_offset = RBIOS16(rdev->bios_header_start + 0x54);
		260	if (check_offset)
		261	offset = check_offset;
		262	break;
		263	case COMBIOS_EXT_TMDS_INFO_TABLE:
		264	check_offset = RBIOS16(rdev->bios_header_start + 0x58);
		265	if (check_offset)
		266	offset = check_offset;
		267	break;
		268	case COMBIOS_MEM_CLK_INFO_TABLE:
		269	check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
		270	if (check_offset)
		271	offset = check_offset;
		272	break;
		273	case COMBIOS_EXT_DAC_INFO_TABLE:
		274	check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
		275	if (check_offset)
		276	offset = check_offset;
		277	break;
		278	case COMBIOS_MISC_INFO_TABLE:
		279	check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
		280	if (check_offset)
		281	offset = check_offset;
		282	break;
		283	case COMBIOS_CRT_INFO_TABLE:
		284	check_offset = RBIOS16(rdev->bios_header_start + 0x60);
		285	if (check_offset)
		286	offset = check_offset;
		287	break;
		288	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		289	check_offset = RBIOS16(rdev->bios_header_start + 0x62);
		290	if (check_offset)
		291	offset = check_offset;
		292	break;
		293	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		294	check_offset = RBIOS16(rdev->bios_header_start + 0x64);
		295	if (check_offset)
		296	offset = check_offset;
		297	break;
		298	case COMBIOS_FAN_SPEED_INFO_TABLE:
		299	check_offset = RBIOS16(rdev->bios_header_start + 0x66);
		300	if (check_offset)
		301	offset = check_offset;
		302	break;
		303	case COMBIOS_OVERDRIVE_INFO_TABLE:
		304	check_offset = RBIOS16(rdev->bios_header_start + 0x68);
		305	if (check_offset)
		306	offset = check_offset;
		307	break;
		308	case COMBIOS_OEM_INFO_TABLE:
		309	check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
		310	if (check_offset)
		311	offset = check_offset;
		312	break;
		313	case COMBIOS_DYN_CLK_2_TABLE:
		314	check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
		315	if (check_offset)
		316	offset = check_offset;
		317	break;
		318	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		319	check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
		320	if (check_offset)
		321	offset = check_offset;
		322	break;
		323	case COMBIOS_I2C_INFO_TABLE:
		324	check_offset = RBIOS16(rdev->bios_header_start + 0x70);
		325	if (check_offset)
		326	offset = check_offset;
		327	break;
		328	/* relative offset tables */
		329	case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
		330	check_offset =
		331	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		332	if (check_offset) {
		333	rev = RBIOS8(check_offset);
		334	if (rev > 0) {
		335	check_offset = RBIOS16(check_offset + 0x3);
		336	if (check_offset)
		337	offset = check_offset;
		338	}
		339	}
		340	break;
		341	case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
		342	check_offset =
		343	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		344	if (check_offset) {
		345	rev = RBIOS8(check_offset);
		346	if (rev > 0) {
		347	check_offset = RBIOS16(check_offset + 0x5);
		348	if (check_offset)
		349	offset = check_offset;
		350	}
		351	}
		352	break;
		353	case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
		354	check_offset =
		355	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		356	if (check_offset) {
		357	rev = RBIOS8(check_offset);
		358	if (rev > 0) {
		359	check_offset = RBIOS16(check_offset + 0x7);
		360	if (check_offset)
		361	offset = check_offset;
		362	}
		363	}
		364	break;
		365	case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
		366	check_offset =
		367	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		368	if (check_offset) {
		369	rev = RBIOS8(check_offset);
		370	if (rev == 2) {
		371	check_offset = RBIOS16(check_offset + 0x9);
		372	if (check_offset)
		373	offset = check_offset;
		374	}
		375	}
		376	break;
		377	case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
		378	check_offset =
		379	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		380	if (check_offset) {
		381	while (RBIOS8(check_offset++));
		382	check_offset += 2;
		383	if (check_offset)
		384	offset = check_offset;
		385	}
		386	break;
		387	case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
		388	check_offset =
		389	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		390	if (check_offset) {
		391	check_offset = RBIOS16(check_offset + 0x11);
		392	if (check_offset)
		393	offset = check_offset;
		394	}
		395	break;
		396	case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
		397	check_offset =
		398	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		399	if (check_offset) {
		400	check_offset = RBIOS16(check_offset + 0x13);
		401	if (check_offset)
		402	offset = check_offset;
		403	}
		404	break;
		405	case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
		406	check_offset =
		407	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		408	if (check_offset) {
		409	check_offset = RBIOS16(check_offset + 0x15);
		410	if (check_offset)
		411	offset = check_offset;
		412	}
		413	break;
		414	case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
		415	check_offset =
		416	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		417	if (check_offset) {
		418	check_offset = RBIOS16(check_offset + 0x17);
		419	if (check_offset)
		420	offset = check_offset;
		421	}
		422	break;
		423	case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
		424	check_offset =
		425	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		426	if (check_offset) {
		427	check_offset = RBIOS16(check_offset + 0x2);
		428	if (check_offset)
		429	offset = check_offset;
		430	}
		431	break;
		432	case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
		433	check_offset =
		434	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		435	if (check_offset) {
		436	check_offset = RBIOS16(check_offset + 0x4);
		437	if (check_offset)
		438	offset = check_offset;
		439	}
		440	break;
		441	default:
		442	break;
		443	}
		444
		445	return offset;
		446
		447	}
		448
1430	serge	449	bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
		450	{
1963	serge	451	int edid_info, size;
1430	serge	452	struct edid *edid;
1963	serge	453	unsigned char *raw;
1430	serge	454	edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
		455	if (!edid_info)
		456	return false;
		457
1963	serge	458	raw = rdev->bios + edid_info;
		459	size = EDID_LENGTH * (raw[0x7e] + 1);
		460	edid = kmalloc(size, GFP_KERNEL);
1430	serge	461	if (edid == NULL)
		462	return false;
		463
1963	serge	464	memcpy((unsigned char *)edid, raw, size);
1430	serge	465
		466	if (!drm_edid_is_valid(edid)) {
		467	kfree(edid);
		468	return false;
		469	}
		470
		471	rdev->mode_info.bios_hardcoded_edid = edid;
1963	serge	472	rdev->mode_info.bios_hardcoded_edid_size = size;
1430	serge	473	return true;
		474	}
		475
1963	serge	476	/* this is used for atom LCDs as well */
1430	serge	477	struct edid *
1963	serge	478	radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
1430	serge	479	{
1963	serge	480	struct edid *edid;
		481
		482	if (rdev->mode_info.bios_hardcoded_edid) {
		483	edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
		484	if (edid) {
		485	memcpy((unsigned char *)edid,
		486	(unsigned char *)rdev->mode_info.bios_hardcoded_edid,
		487	rdev->mode_info.bios_hardcoded_edid_size);
		488	return edid;
		489	}
		490	}
1430	serge	491	return NULL;
		492	}
		493
1321	serge	494	static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
1963	serge	495	enum radeon_combios_ddc ddc,
		496	u32 clk_mask,
		497	u32 data_mask)
1123	serge	498	{
		499	struct radeon_i2c_bus_rec i2c;
1963	serge	500	int ddc_line = 0;
1123	serge	501
1963	serge	502	/* ddc id = mask reg
		503	* DDC_NONE_DETECTED = none
		504	* DDC_DVI = RADEON_GPIO_DVI_DDC
		505	* DDC_VGA = RADEON_GPIO_VGA_DDC
		506	* DDC_LCD = RADEON_GPIOPAD_MASK
		507	* DDC_GPIO = RADEON_MDGPIO_MASK
		508	* r1xx
		509	* DDC_MONID = RADEON_GPIO_MONID
		510	* DDC_CRT2 = RADEON_GPIO_CRT2_DDC
		511	* r200
		512	* DDC_MONID = RADEON_GPIO_MONID
		513	* DDC_CRT2 = RADEON_GPIO_DVI_DDC
		514	* r300/r350
		515	* DDC_MONID = RADEON_GPIO_DVI_DDC
		516	* DDC_CRT2 = RADEON_GPIO_DVI_DDC
		517	* rv2xx/rv3xx
		518	* DDC_MONID = RADEON_GPIO_MONID
		519	* DDC_CRT2 = RADEON_GPIO_MONID
		520	* rs3xx/rs4xx
		521	* DDC_MONID = RADEON_GPIOPAD_MASK
		522	* DDC_CRT2 = RADEON_GPIO_MONID
		523	*/
		524	switch (ddc) {
		525	case DDC_NONE_DETECTED:
		526	default:
		527	ddc_line = 0;
		528	break;
		529	case DDC_DVI:
		530	ddc_line = RADEON_GPIO_DVI_DDC;
		531	break;
		532	case DDC_VGA:
		533	ddc_line = RADEON_GPIO_VGA_DDC;
		534	break;
		535	case DDC_LCD:
		536	ddc_line = RADEON_GPIOPAD_MASK;
		537	break;
		538	case DDC_GPIO:
		539	ddc_line = RADEON_MDGPIO_MASK;
		540	break;
		541	case DDC_MONID:
		542	if (rdev->family == CHIP_RS300 \|\|
		543	rdev->family == CHIP_RS400 \|\|
		544	rdev->family == CHIP_RS480)
		545	ddc_line = RADEON_GPIOPAD_MASK;
		546	else if (rdev->family == CHIP_R300 \|\|
		547	rdev->family == CHIP_R350) {
		548	ddc_line = RADEON_GPIO_DVI_DDC;
		549	ddc = DDC_DVI;
		550	} else
		551	ddc_line = RADEON_GPIO_MONID;
		552	break;
		553	case DDC_CRT2:
		554	if (rdev->family == CHIP_R200 \|\|
		555	rdev->family == CHIP_R300 \|\|
		556	rdev->family == CHIP_R350) {
		557	ddc_line = RADEON_GPIO_DVI_DDC;
		558	ddc = DDC_DVI;
		559	} else if (rdev->family == CHIP_RS300 \|\|
		560	rdev->family == CHIP_RS400 \|\|
		561	rdev->family == CHIP_RS480)
		562	ddc_line = RADEON_GPIO_MONID;
		563	else if (rdev->family >= CHIP_RV350) {
		564	ddc_line = RADEON_GPIO_MONID;
		565	ddc = DDC_MONID;
		566	} else
		567	ddc_line = RADEON_GPIO_CRT2_DDC;
		568	break;
		569	}
		570
1321	serge	571	if (ddc_line == RADEON_GPIOPAD_MASK) {
		572	i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
		573	i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
		574	i2c.a_clk_reg = RADEON_GPIOPAD_A;
		575	i2c.a_data_reg = RADEON_GPIOPAD_A;
		576	i2c.en_clk_reg = RADEON_GPIOPAD_EN;
		577	i2c.en_data_reg = RADEON_GPIOPAD_EN;
		578	i2c.y_clk_reg = RADEON_GPIOPAD_Y;
		579	i2c.y_data_reg = RADEON_GPIOPAD_Y;
		580	} else if (ddc_line == RADEON_MDGPIO_MASK) {
		581	i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
		582	i2c.mask_data_reg = RADEON_MDGPIO_MASK;
		583	i2c.a_clk_reg = RADEON_MDGPIO_A;
		584	i2c.a_data_reg = RADEON_MDGPIO_A;
		585	i2c.en_clk_reg = RADEON_MDGPIO_EN;
		586	i2c.en_data_reg = RADEON_MDGPIO_EN;
		587	i2c.y_clk_reg = RADEON_MDGPIO_Y;
		588	i2c.y_data_reg = RADEON_MDGPIO_Y;
		589	} else {
1123	serge	590	i2c.mask_clk_reg = ddc_line;
		591	i2c.mask_data_reg = ddc_line;
		592	i2c.a_clk_reg = ddc_line;
		593	i2c.a_data_reg = ddc_line;
1321	serge	594	i2c.en_clk_reg = ddc_line;
		595	i2c.en_data_reg = ddc_line;
		596	i2c.y_clk_reg = ddc_line;
		597	i2c.y_data_reg = ddc_line;
1123	serge	598	}
		599
1963	serge	600	if (clk_mask && data_mask) {
		601	/* system specific masks */
		602	i2c.mask_clk_mask = clk_mask;
		603	i2c.mask_data_mask = data_mask;
		604	i2c.a_clk_mask = clk_mask;
		605	i2c.a_data_mask = data_mask;
		606	i2c.en_clk_mask = clk_mask;
		607	i2c.en_data_mask = data_mask;
		608	i2c.y_clk_mask = clk_mask;
		609	i2c.y_data_mask = data_mask;
		610	} else if ((ddc_line == RADEON_GPIOPAD_MASK) \|\|
		611	(ddc_line == RADEON_MDGPIO_MASK)) {
		612	/* default gpiopad masks */
		613	i2c.mask_clk_mask = (0x20 << 8);
		614	i2c.mask_data_mask = 0x80;
		615	i2c.a_clk_mask = (0x20 << 8);
		616	i2c.a_data_mask = 0x80;
		617	i2c.en_clk_mask = (0x20 << 8);
		618	i2c.en_data_mask = 0x80;
		619	i2c.y_clk_mask = (0x20 << 8);
		620	i2c.y_data_mask = 0x80;
		621	} else {
		622	/* default masks for ddc pads */
2997	Serge	623	i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
		624	i2c.mask_data_mask = RADEON_GPIO_MASK_0;
1963	serge	625	i2c.a_clk_mask = RADEON_GPIO_A_1;
		626	i2c.a_data_mask = RADEON_GPIO_A_0;
		627	i2c.en_clk_mask = RADEON_GPIO_EN_1;
		628	i2c.en_data_mask = RADEON_GPIO_EN_0;
		629	i2c.y_clk_mask = RADEON_GPIO_Y_1;
		630	i2c.y_data_mask = RADEON_GPIO_Y_0;
		631	}
		632
1430	serge	633	switch (rdev->family) {
		634	case CHIP_R100:
		635	case CHIP_RV100:
		636	case CHIP_RS100:
		637	case CHIP_RV200:
		638	case CHIP_RS200:
		639	case CHIP_RS300:
		640	switch (ddc_line) {
		641	case RADEON_GPIO_DVI_DDC:
1963	serge	642	i2c.hw_capable = true;
1430	serge	643	break;
		644	default:
		645	i2c.hw_capable = false;
		646	break;
		647	}
		648	break;
		649	case CHIP_R200:
		650	switch (ddc_line) {
		651	case RADEON_GPIO_DVI_DDC:
		652	case RADEON_GPIO_MONID:
		653	i2c.hw_capable = true;
		654	break;
		655	default:
		656	i2c.hw_capable = false;
		657	break;
		658	}
		659	break;
		660	case CHIP_RV250:
		661	case CHIP_RV280:
		662	switch (ddc_line) {
		663	case RADEON_GPIO_VGA_DDC:
		664	case RADEON_GPIO_DVI_DDC:
		665	case RADEON_GPIO_CRT2_DDC:
		666	i2c.hw_capable = true;
		667	break;
		668	default:
		669	i2c.hw_capable = false;
		670	break;
		671	}
		672	break;
		673	case CHIP_R300:
		674	case CHIP_R350:
		675	switch (ddc_line) {
		676	case RADEON_GPIO_VGA_DDC:
		677	case RADEON_GPIO_DVI_DDC:
		678	i2c.hw_capable = true;
		679	break;
		680	default:
1321	serge	681	i2c.hw_capable = false;
1430	serge	682	break;
		683	}
		684	break;
		685	case CHIP_RV350:
		686	case CHIP_RV380:
		687	case CHIP_RS400:
		688	case CHIP_RS480:
1321	serge	689	switch (ddc_line) {
		690	case RADEON_GPIO_VGA_DDC:
		691	case RADEON_GPIO_DVI_DDC:
		692	i2c.hw_capable = true;
		693	break;
		694	case RADEON_GPIO_MONID:
		695	/* hw i2c on RADEON_GPIO_MONID doesn't seem to work
		696	* reliably on some pre-r4xx hardware; not sure why.
		697	*/
		698	i2c.hw_capable = false;
		699	break;
		700	default:
		701	i2c.hw_capable = false;
		702	break;
		703	}
1430	serge	704	break;
		705	default:
		706	i2c.hw_capable = false;
		707	break;
1321	serge	708	}
		709	i2c.mm_i2c = false;
		710
1963	serge	711	i2c.i2c_id = ddc;
		712	i2c.hpd = RADEON_HPD_NONE;
		713
1123	serge	714	if (ddc_line)
		715	i2c.valid = true;
		716	else
		717	i2c.valid = false;
		718
		719	return i2c;
		720	}
		721
2997	Serge	722	static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
		723	{
		724	struct drm_device *dev = rdev->ddev;
		725	struct radeon_i2c_bus_rec i2c;
		726	u16 offset;
		727	u8 id, blocks, clk, data;
		728	int i;
		729
		730	i2c.valid = false;
		731
		732	offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
		733	if (offset) {
		734	blocks = RBIOS8(offset + 2);
		735	for (i = 0; i < blocks; i++) {
		736	id = RBIOS8(offset + 3 + (i * 5) + 0);
		737	if (id == 136) {
		738	clk = RBIOS8(offset + 3 + (i * 5) + 3);
		739	data = RBIOS8(offset + 3 + (i * 5) + 4);
		740	/* gpiopad */
		741	i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
		742	(1 << clk), (1 << data));
		743	break;
		744	}
		745	}
		746	}
		747	return i2c;
		748	}
		749
1963	serge	750	void radeon_combios_i2c_init(struct radeon_device *rdev)
		751	{
		752	struct drm_device *dev = rdev->ddev;
		753	struct radeon_i2c_bus_rec i2c;
		754
		755	/* actual hw pads
		756	* r1xx/rs2xx/rs3xx
		757	* 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
		758	* r200
		759	* 0x60, 0x64, 0x68, mm
		760	* r300/r350
		761	* 0x60, 0x64, mm
		762	* rv2xx/rv3xx/rs4xx
		763	* 0x60, 0x64, 0x68, gpiopads, mm
		764	*/
		765
		766	/* 0x60 */
		767	i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		768	rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
		769	/* 0x64 */
		770	i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		771	rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
		772
		773	/* mm i2c */
		774	i2c.valid = true;
		775	i2c.hw_capable = true;
		776	i2c.mm_i2c = true;
		777	i2c.i2c_id = 0xa0;
		778	rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
		779
		780	if (rdev->family == CHIP_R300 \|\|
		781	rdev->family == CHIP_R350) {
		782	/* only 2 sw i2c pads */
		783	} else if (rdev->family == CHIP_RS300 \|\|
		784	rdev->family == CHIP_RS400 \|\|
		785	rdev->family == CHIP_RS480) {
		786	/* 0x68 */
		787	i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		788	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		789
		790	/* gpiopad */
2997	Serge	791	i2c = radeon_combios_get_i2c_info_from_table(rdev);
		792	if (i2c.valid)
1963	serge	793	rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
2160	serge	794	} else if ((rdev->family == CHIP_R200) \|\|
		795	(rdev->family >= CHIP_R300)) {
1963	serge	796	/* 0x68 */
		797	i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		798	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		799	} else {
		800	/* 0x68 */
		801	i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		802	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		803	/* 0x6c */
		804	i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		805	rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
		806	}
		807	}
		808
1123	serge	809	bool radeon_combios_get_clock_info(struct drm_device *dev)
		810	{
		811	struct radeon_device *rdev = dev->dev_private;
		812	uint16_t pll_info;
		813	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		814	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		815	struct radeon_pll *spll = &rdev->clock.spll;
		816	struct radeon_pll *mpll = &rdev->clock.mpll;
		817	int8_t rev;
		818	uint16_t sclk, mclk;
		819
		820	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
		821	if (pll_info) {
		822	rev = RBIOS8(pll_info);
		823
		824	/* pixel clocks */
		825	p1pll->reference_freq = RBIOS16(pll_info + 0xe);
		826	p1pll->reference_div = RBIOS16(pll_info + 0x10);
		827	p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
		828	p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
1963	serge	829	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		830	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1123	serge	831
		832	if (rev > 9) {
		833	p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
		834	p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
		835	} else {
		836	p1pll->pll_in_min = 40;
		837	p1pll->pll_in_max = 500;
		838	}
		839	p2pll = p1pll;
		840
		841	/* system clock */
		842	spll->reference_freq = RBIOS16(pll_info + 0x1a);
		843	spll->reference_div = RBIOS16(pll_info + 0x1c);
		844	spll->pll_out_min = RBIOS32(pll_info + 0x1e);
		845	spll->pll_out_max = RBIOS32(pll_info + 0x22);
		846
		847	if (rev > 10) {
		848	spll->pll_in_min = RBIOS32(pll_info + 0x48);
		849	spll->pll_in_max = RBIOS32(pll_info + 0x4c);
		850	} else {
		851	/* ??? */
		852	spll->pll_in_min = 40;
		853	spll->pll_in_max = 500;
		854	}
		855
		856	/* memory clock */
		857	mpll->reference_freq = RBIOS16(pll_info + 0x26);
		858	mpll->reference_div = RBIOS16(pll_info + 0x28);
		859	mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
		860	mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
		861
		862	if (rev > 10) {
		863	mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
		864	mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
		865	} else {
		866	/* ??? */
		867	mpll->pll_in_min = 40;
		868	mpll->pll_in_max = 500;
		869	}
		870
		871	/* default sclk/mclk */
		872	sclk = RBIOS16(pll_info + 0xa);
		873	mclk = RBIOS16(pll_info + 0x8);
		874	if (sclk == 0)
		875	sclk = 200 * 100;
		876	if (mclk == 0)
		877	mclk = 200 * 100;
		878
		879	rdev->clock.default_sclk = sclk;
		880	rdev->clock.default_mclk = mclk;
		881
1963	serge	882	if (RBIOS32(pll_info + 0x16))
		883	rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
		884	else
		885	rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
		886
1123	serge	887	return true;
		888	}
		889	return false;
		890	}
		891
1404	serge	892	bool radeon_combios_sideport_present(struct radeon_device *rdev)
		893	{
		894	struct drm_device *dev = rdev->ddev;
		895	u16 igp_info;
		896
1963	serge	897	/* sideport is AMD only */
		898	if (rdev->family == CHIP_RS400)
		899	return false;
		900
1404	serge	901	igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
		902
		903	if (igp_info) {
		904	if (RBIOS16(igp_info + 0x4))
		905	return true;
		906	}
		907	return false;
		908	}
		909
		910	static const uint32_t default_primarydac_adj[CHIP_LAST] = {
		911	0x00000808, /* r100 */
		912	0x00000808, /* rv100 */
		913	0x00000808, /* rs100 */
		914	0x00000808, /* rv200 */
		915	0x00000808, /* rs200 */
		916	0x00000808, /* r200 */
		917	0x00000808, /* rv250 */
		918	0x00000000, /* rs300 */
		919	0x00000808, /* rv280 */
		920	0x00000808, /* r300 */
		921	0x00000808, /* r350 */
		922	0x00000808, /* rv350 */
		923	0x00000808, /* rv380 */
		924	0x00000808, /* r420 */
		925	0x00000808, /* r423 */
		926	0x00000808, /* rv410 */
		927	0x00000000, /* rs400 */
		928	0x00000000, /* rs480 */
		929	};
		930
		931	static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
		932	struct radeon_encoder_primary_dac *p_dac)
		933	{
		934	p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
		935	return;
		936	}
		937
1123	serge	938	struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
		939	radeon_encoder
		940	*encoder)
		941	{
		942	struct drm_device *dev = encoder->base.dev;
		943	struct radeon_device *rdev = dev->dev_private;
		944	uint16_t dac_info;
		945	uint8_t rev, bg, dac;
		946	struct radeon_encoder_primary_dac *p_dac = NULL;
1404	serge	947	int found = 0;
1123	serge	948
1404	serge	949	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
		950	GFP_KERNEL);
		951
		952	if (!p_dac)
1123	serge	953	return NULL;
		954
		955	/* check CRT table */
		956	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		957	if (dac_info) {
		958	rev = RBIOS8(dac_info) & 0x3;
		959	if (rev < 2) {
		960	bg = RBIOS8(dac_info + 0x2) & 0xf;
		961	dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
		962	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		963	} else {
		964	bg = RBIOS8(dac_info + 0x2) & 0xf;
		965	dac = RBIOS8(dac_info + 0x3) & 0xf;
		966	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		967	}
1963	serge	968	/* if the values are all zeros, use the table */
		969	if (p_dac->ps2_pdac_adj)
1404	serge	970	found = 1;
1123	serge	971	}
		972
1404	serge	973	if (!found) /* fallback to defaults */
		974	radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
		975
1123	serge	976	return p_dac;
		977	}
		978
1404	serge	979	enum radeon_tv_std
		980	radeon_combios_get_tv_info(struct radeon_device *rdev)
1123	serge	981	{
1404	serge	982	struct drm_device *dev = rdev->ddev;
1123	serge	983	uint16_t tv_info;
		984	enum radeon_tv_std tv_std = TV_STD_NTSC;
		985
		986	tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		987	if (tv_info) {
		988	if (RBIOS8(tv_info + 6) == 'T') {
		989	switch (RBIOS8(tv_info + 7) & 0xf) {
		990	case 1:
		991	tv_std = TV_STD_NTSC;
1963	serge	992	DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1123	serge	993	break;
		994	case 2:
		995	tv_std = TV_STD_PAL;
1963	serge	996	DRM_DEBUG_KMS("Default TV standard: PAL\n");
1123	serge	997	break;
		998	case 3:
		999	tv_std = TV_STD_PAL_M;
1963	serge	1000	DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1123	serge	1001	break;
		1002	case 4:
		1003	tv_std = TV_STD_PAL_60;
1963	serge	1004	DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1123	serge	1005	break;
		1006	case 5:
		1007	tv_std = TV_STD_NTSC_J;
1963	serge	1008	DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1123	serge	1009	break;
		1010	case 6:
		1011	tv_std = TV_STD_SCART_PAL;
1963	serge	1012	DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1123	serge	1013	break;
		1014	default:
		1015	tv_std = TV_STD_NTSC;
1963	serge	1016	DRM_DEBUG_KMS
1123	serge	1017	("Unknown TV standard; defaulting to NTSC\n");
		1018	break;
		1019	}
		1020
		1021	switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
		1022	case 0:
1963	serge	1023	DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1123	serge	1024	break;
		1025	case 1:
1963	serge	1026	DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1123	serge	1027	break;
		1028	case 2:
1963	serge	1029	DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1123	serge	1030	break;
		1031	case 3:
1963	serge	1032	DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1123	serge	1033	break;
		1034	default:
		1035	break;
		1036	}
		1037	}
		1038	}
		1039	return tv_std;
		1040	}
		1041
		1042	static const uint32_t default_tvdac_adj[CHIP_LAST] = {
		1043	0x00000000, /* r100 */
		1044	0x00280000, /* rv100 */
		1045	0x00000000, /* rs100 */
		1046	0x00880000, /* rv200 */
		1047	0x00000000, /* rs200 */
		1048	0x00000000, /* r200 */
		1049	0x00770000, /* rv250 */
		1050	0x00290000, /* rs300 */
		1051	0x00560000, /* rv280 */
		1052	0x00780000, /* r300 */
		1053	0x00770000, /* r350 */
		1054	0x00780000, /* rv350 */
		1055	0x00780000, /* rv380 */
		1056	0x01080000, /* r420 */
		1057	0x01080000, /* r423 */
		1058	0x01080000, /* rv410 */
		1059	0x00780000, /* rs400 */
		1060	0x00780000, /* rs480 */
		1061	};
		1062
1179	serge	1063	static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
		1064	struct radeon_encoder_tv_dac *tv_dac)
1123	serge	1065	{
		1066	tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
		1067	if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
		1068	tv_dac->ps2_tvdac_adj = 0x00880000;
		1069	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1070	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	1071	return;
1123	serge	1072	}
		1073
		1074	struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
		1075	radeon_encoder
		1076	*encoder)
		1077	{
		1078	struct drm_device *dev = encoder->base.dev;
		1079	struct radeon_device *rdev = dev->dev_private;
		1080	uint16_t dac_info;
		1081	uint8_t rev, bg, dac;
		1082	struct radeon_encoder_tv_dac *tv_dac = NULL;
1179	serge	1083	int found = 0;
1123	serge	1084
1179	serge	1085	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1086	if (!tv_dac)
		1087	return NULL;
		1088
1123	serge	1089	/* first check TV table */
		1090	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		1091	if (dac_info) {
		1092	rev = RBIOS8(dac_info + 0x3);
		1093	if (rev > 4) {
		1094	bg = RBIOS8(dac_info + 0xc) & 0xf;
		1095	dac = RBIOS8(dac_info + 0xd) & 0xf;
		1096	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1097
		1098	bg = RBIOS8(dac_info + 0xe) & 0xf;
		1099	dac = RBIOS8(dac_info + 0xf) & 0xf;
		1100	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1101
		1102	bg = RBIOS8(dac_info + 0x10) & 0xf;
		1103	dac = RBIOS8(dac_info + 0x11) & 0xf;
		1104	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1963	serge	1105	/* if the values are all zeros, use the table */
		1106	if (tv_dac->ps2_tvdac_adj)
1179	serge	1107	found = 1;
1123	serge	1108	} else if (rev > 1) {
		1109	bg = RBIOS8(dac_info + 0xc) & 0xf;
		1110	dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
		1111	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1112
		1113	bg = RBIOS8(dac_info + 0xd) & 0xf;
		1114	dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
		1115	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1116
		1117	bg = RBIOS8(dac_info + 0xe) & 0xf;
		1118	dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
		1119	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1963	serge	1120	/* if the values are all zeros, use the table */
		1121	if (tv_dac->ps2_tvdac_adj)
1179	serge	1122	found = 1;
1123	serge	1123	}
1404	serge	1124	tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1179	serge	1125	}
		1126	if (!found) {
1123	serge	1127	/* then check CRT table */
		1128	dac_info =
		1129	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		1130	if (dac_info) {
		1131	rev = RBIOS8(dac_info) & 0x3;
		1132	if (rev < 2) {
		1133	bg = RBIOS8(dac_info + 0x3) & 0xf;
		1134	dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
		1135	tv_dac->ps2_tvdac_adj =
		1136	(bg << 16) \| (dac << 20);
		1137	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1138	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1963	serge	1139	/* if the values are all zeros, use the table */
		1140	if (tv_dac->ps2_tvdac_adj)
1179	serge	1141	found = 1;
1123	serge	1142	} else {
		1143	bg = RBIOS8(dac_info + 0x4) & 0xf;
		1144	dac = RBIOS8(dac_info + 0x5) & 0xf;
		1145	tv_dac->ps2_tvdac_adj =
		1146	(bg << 16) \| (dac << 20);
		1147	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1148	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1963	serge	1149	/* if the values are all zeros, use the table */
		1150	if (tv_dac->ps2_tvdac_adj)
1179	serge	1151	found = 1;
1123	serge	1152	}
		1153	} else {
		1154	DRM_INFO("No TV DAC info found in BIOS\n");
		1155	}
		1156	}
1221	serge	1157
1179	serge	1158	if (!found) /* fallback to defaults */
		1159	radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1123	serge	1160
		1161	return tv_dac;
		1162	}
		1163
		1164	static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
		1165	radeon_device
		1166	*rdev)
		1167	{
		1168	struct radeon_encoder_lvds *lvds = NULL;
		1169	uint32_t fp_vert_stretch, fp_horz_stretch;
		1170	uint32_t ppll_div_sel, ppll_val;
		1171	uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		1172
		1173	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		1174
		1175	if (!lvds)
		1176	return NULL;
		1177
		1178	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
		1179	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
		1180
		1181	/* These should be fail-safe defaults, fingers crossed */
		1182	lvds->panel_pwr_delay = 200;
		1183	lvds->panel_vcc_delay = 2000;
		1184
		1185	lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		1186	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
		1187	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
		1188
		1189	if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1268	serge	1190	lvds->native_mode.vdisplay =
1123	serge	1191	((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
		1192	RADEON_VERT_PANEL_SHIFT) + 1;
		1193	else
1268	serge	1194	lvds->native_mode.vdisplay =
1123	serge	1195	(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
		1196
		1197	if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1268	serge	1198	lvds->native_mode.hdisplay =
1123	serge	1199	(((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
		1200	RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
		1201	else
1268	serge	1202	lvds->native_mode.hdisplay =
1123	serge	1203	((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
		1204
1268	serge	1205	if ((lvds->native_mode.hdisplay < 640) \|\|
		1206	(lvds->native_mode.vdisplay < 480)) {
		1207	lvds->native_mode.hdisplay = 640;
		1208	lvds->native_mode.vdisplay = 480;
1123	serge	1209	}
		1210
		1211	ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
		1212	ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
		1213	if ((ppll_val & 0x000707ff) == 0x1bb)
		1214	lvds->use_bios_dividers = false;
		1215	else {
		1216	lvds->panel_ref_divider =
		1217	RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
		1218	lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
		1219	lvds->panel_fb_divider = ppll_val & 0x7ff;
		1220
		1221	if ((lvds->panel_ref_divider != 0) &&
		1222	(lvds->panel_fb_divider > 3))
		1223	lvds->use_bios_dividers = true;
		1224	}
		1225	lvds->panel_vcc_delay = 200;
		1226
		1227	DRM_INFO("Panel info derived from registers\n");
1268	serge	1228	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		1229	lvds->native_mode.vdisplay);
1123	serge	1230
		1231	return lvds;
		1232	}
		1233
		1234	struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
		1235	*encoder)
		1236	{
		1237	struct drm_device *dev = encoder->base.dev;
		1238	struct radeon_device *rdev = dev->dev_private;
		1239	uint16_t lcd_info;
		1240	uint32_t panel_setup;
		1241	char stmp[30];
		1242	int tmp, i;
		1243	struct radeon_encoder_lvds *lvds = NULL;
		1244
		1245	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		1246
		1247	if (lcd_info) {
		1248	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		1249
		1250	if (!lvds)
		1251	return NULL;
		1252
		1253	for (i = 0; i < 24; i++)
		1254	stmp[i] = RBIOS8(lcd_info + i + 1);
		1255	stmp[24] = 0;
		1256
		1257	DRM_INFO("Panel ID String: %s\n", stmp);
		1258
1268	serge	1259	lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
		1260	lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1123	serge	1261
1268	serge	1262	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		1263	lvds->native_mode.vdisplay);
1123	serge	1264
		1265	lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1404	serge	1266	lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1123	serge	1267
		1268	lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
		1269	lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
		1270	lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
		1271
		1272	lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
		1273	lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
		1274	lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
		1275	if ((lvds->panel_ref_divider != 0) &&
		1276	(lvds->panel_fb_divider > 3))
		1277	lvds->use_bios_dividers = true;
		1278
		1279	panel_setup = RBIOS32(lcd_info + 0x39);
		1280	lvds->lvds_gen_cntl = 0xff00;
		1281	if (panel_setup & 0x1)
		1282	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_FORMAT;
		1283
		1284	if ((panel_setup >> 4) & 0x1)
		1285	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_TYPE;
		1286
		1287	switch ((panel_setup >> 8) & 0x7) {
		1288	case 0:
		1289	lvds->lvds_gen_cntl \|= RADEON_LVDS_NO_FM;
		1290	break;
		1291	case 1:
		1292	lvds->lvds_gen_cntl \|= RADEON_LVDS_2_GREY;
		1293	break;
		1294	case 2:
		1295	lvds->lvds_gen_cntl \|= RADEON_LVDS_4_GREY;
		1296	break;
		1297	default:
		1298	break;
		1299	}
		1300
		1301	if ((panel_setup >> 16) & 0x1)
		1302	lvds->lvds_gen_cntl \|= RADEON_LVDS_FP_POL_LOW;
		1303
		1304	if ((panel_setup >> 17) & 0x1)
		1305	lvds->lvds_gen_cntl \|= RADEON_LVDS_LP_POL_LOW;
		1306
		1307	if ((panel_setup >> 18) & 0x1)
		1308	lvds->lvds_gen_cntl \|= RADEON_LVDS_DTM_POL_LOW;
		1309
		1310	if ((panel_setup >> 23) & 0x1)
		1311	lvds->lvds_gen_cntl \|= RADEON_LVDS_BL_CLK_SEL;
		1312
		1313	lvds->lvds_gen_cntl \|= (panel_setup & 0xf0000000);
		1314
		1315	for (i = 0; i < 32; i++) {
		1316	tmp = RBIOS16(lcd_info + 64 + i * 2);
		1317	if (tmp == 0)
		1318	break;
		1319
1268	serge	1320	if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1963	serge	1321	(RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
		1322	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
		1323	(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
		1324	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
		1325	(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
		1326	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
		1327	(RBIOS8(tmp + 23) * 8);
1123	serge	1328
1963	serge	1329	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
		1330	(RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
		1331	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
		1332	((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
		1333	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
		1334	((RBIOS16(tmp + 28) & 0xf800) >> 11);
1268	serge	1335
		1336	lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1123	serge	1337	lvds->native_mode.flags = 0;
1268	serge	1338	/* set crtc values */
		1339	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
		1340
1123	serge	1341	}
		1342	}
		1343	} else {
		1344	DRM_INFO("No panel info found in BIOS\n");
1179	serge	1345	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1123	serge	1346	}
1430	serge	1347
1179	serge	1348	if (lvds)
		1349	encoder->native_mode = lvds->native_mode;
1123	serge	1350	return lvds;
		1351	}
		1352
		1353	static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
		1354	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
		1355	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
		1356	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
		1357	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
		1358	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
		1359	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
		1360	{{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
		1361	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
		1362	{{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
		1363	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
		1364	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
		1365	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
		1366	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
		1367	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
		1368	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
		1369	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1321	serge	1370	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
		1371	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1123	serge	1372	};
		1373
1179	serge	1374	bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
		1375	struct radeon_encoder_int_tmds *tmds)
1123	serge	1376	{
1179	serge	1377	struct drm_device *dev = encoder->base.dev;
		1378	struct radeon_device *rdev = dev->dev_private;
1123	serge	1379	int i;
		1380
		1381	for (i = 0; i < 4; i++) {
		1382	tmds->tmds_pll[i].value =
		1383	default_tmds_pll[rdev->family][i].value;
		1384	tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
		1385	}
		1386
1179	serge	1387	return true;
1123	serge	1388	}
		1389
1179	serge	1390	bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
		1391	struct radeon_encoder_int_tmds *tmds)
1123	serge	1392	{
		1393	struct drm_device *dev = encoder->base.dev;
		1394	struct radeon_device *rdev = dev->dev_private;
		1395	uint16_t tmds_info;
		1396	int i, n;
		1397	uint8_t ver;
		1398
		1399	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		1400
		1401	if (tmds_info) {
		1402	ver = RBIOS8(tmds_info);
1963	serge	1403	DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1123	serge	1404	if (ver == 3) {
		1405	n = RBIOS8(tmds_info + 5) + 1;
		1406	if (n > 4)
		1407	n = 4;
		1408	for (i = 0; i < n; i++) {
		1409	tmds->tmds_pll[i].value =
		1410	RBIOS32(tmds_info + i * 10 + 0x08);
		1411	tmds->tmds_pll[i].freq =
		1412	RBIOS16(tmds_info + i * 10 + 0x10);
1963	serge	1413	DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1123	serge	1414	tmds->tmds_pll[i].freq,
		1415	tmds->tmds_pll[i].value);
		1416	}
		1417	} else if (ver == 4) {
		1418	int stride = 0;
		1419	n = RBIOS8(tmds_info + 5) + 1;
		1420	if (n > 4)
		1421	n = 4;
		1422	for (i = 0; i < n; i++) {
		1423	tmds->tmds_pll[i].value =
		1424	RBIOS32(tmds_info + stride + 0x08);
		1425	tmds->tmds_pll[i].freq =
		1426	RBIOS16(tmds_info + stride + 0x10);
		1427	if (i == 0)
		1428	stride += 10;
		1429	else
		1430	stride += 6;
1963	serge	1431	DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1123	serge	1432	tmds->tmds_pll[i].freq,
		1433	tmds->tmds_pll[i].value);
		1434	}
		1435	}
1321	serge	1436	} else {
1123	serge	1437	DRM_INFO("No TMDS info found in BIOS\n");
1321	serge	1438	return false;
		1439	}
1179	serge	1440	return true;
		1441	}
		1442
1321	serge	1443	bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
		1444	struct radeon_encoder_ext_tmds *tmds)
1179	serge	1445	{
1321	serge	1446	struct drm_device *dev = encoder->base.dev;
		1447	struct radeon_device *rdev = dev->dev_private;
		1448	struct radeon_i2c_bus_rec i2c_bus;
1179	serge	1449
1321	serge	1450	/* default for macs */
1963	serge	1451	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		1452	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1179	serge	1453
1321	serge	1454	/* XXX some macs have duallink chips */
		1455	switch (rdev->mode_info.connector_table) {
		1456	case CT_POWERBOOK_EXTERNAL:
		1457	case CT_MINI_EXTERNAL:
		1458	default:
		1459	tmds->dvo_chip = DVO_SIL164;
		1460	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1461	break;
		1462	}
1179	serge	1463
1321	serge	1464	return true;
1123	serge	1465	}
		1466
1321	serge	1467	bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
		1468	struct radeon_encoder_ext_tmds *tmds)
1123	serge	1469	{
		1470	struct drm_device *dev = encoder->base.dev;
		1471	struct radeon_device *rdev = dev->dev_private;
1321	serge	1472	uint16_t offset;
1963	serge	1473	uint8_t ver;
1321	serge	1474	enum radeon_combios_ddc gpio;
		1475	struct radeon_i2c_bus_rec i2c_bus;
1123	serge	1476
1321	serge	1477	tmds->i2c_bus = NULL;
		1478	if (rdev->flags & RADEON_IS_IGP) {
1963	serge	1479	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		1480	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1321	serge	1481	tmds->dvo_chip = DVO_SIL164;
		1482	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1483	} else {
		1484	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		1485	if (offset) {
		1486	ver = RBIOS8(offset);
1963	serge	1487	DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1321	serge	1488	tmds->slave_addr = RBIOS8(offset + 4 + 2);
		1489	tmds->slave_addr >>= 1; /* 7 bit addressing */
		1490	gpio = RBIOS8(offset + 4 + 3);
1963	serge	1491	if (gpio == DDC_LCD) {
		1492	/* MM i2c */
1430	serge	1493	i2c_bus.valid = true;
		1494	i2c_bus.hw_capable = true;
		1495	i2c_bus.mm_i2c = true;
1963	serge	1496	i2c_bus.i2c_id = 0xa0;
		1497	} else
		1498	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
		1499	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1321	serge	1500	}
		1501	}
		1502
		1503	if (!tmds->i2c_bus) {
		1504	DRM_INFO("No valid Ext TMDS info found in BIOS\n");
		1505	return false;
		1506	}
		1507
		1508	return true;
1123	serge	1509	}
		1510
		1511	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
		1512	{
		1513	struct radeon_device *rdev = dev->dev_private;
		1514	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	1515	struct radeon_hpd hpd;
1123	serge	1516
		1517	rdev->mode_info.connector_table = radeon_connector_table;
		1518	if (rdev->mode_info.connector_table == CT_NONE) {
		1519	#ifdef CONFIG_PPC_PMAC
1430	serge	1520	if (of_machine_is_compatible("PowerBook3,3")) {
1123	serge	1521	/* powerbook with VGA */
		1522	rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1430	serge	1523	} else if (of_machine_is_compatible("PowerBook3,4") \|\|
		1524	of_machine_is_compatible("PowerBook3,5")) {
1123	serge	1525	/* powerbook with internal tmds */
		1526	rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1430	serge	1527	} else if (of_machine_is_compatible("PowerBook5,1") \|\|
		1528	of_machine_is_compatible("PowerBook5,2") \|\|
		1529	of_machine_is_compatible("PowerBook5,3") \|\|
		1530	of_machine_is_compatible("PowerBook5,4") \|\|
		1531	of_machine_is_compatible("PowerBook5,5")) {
1123	serge	1532	/* powerbook with external single link tmds (sil164) */
		1533	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1534	} else if (of_machine_is_compatible("PowerBook5,6")) {
1123	serge	1535	/* powerbook with external dual or single link tmds */
		1536	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1537	} else if (of_machine_is_compatible("PowerBook5,7") \|\|
		1538	of_machine_is_compatible("PowerBook5,8") \|\|
		1539	of_machine_is_compatible("PowerBook5,9")) {
1123	serge	1540	/* PowerBook6,2 ? */
		1541	/* powerbook with external dual link tmds (sil1178?) */
		1542	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1543	} else if (of_machine_is_compatible("PowerBook4,1") \|\|
		1544	of_machine_is_compatible("PowerBook4,2") \|\|
		1545	of_machine_is_compatible("PowerBook4,3") \|\|
		1546	of_machine_is_compatible("PowerBook6,3") \|\|
		1547	of_machine_is_compatible("PowerBook6,5") \|\|
		1548	of_machine_is_compatible("PowerBook6,7")) {
1123	serge	1549	/* ibook */
		1550	rdev->mode_info.connector_table = CT_IBOOK;
3192	Serge	1551	} else if (of_machine_is_compatible("PowerMac3,5")) {
		1552	/* PowerMac G4 Silver radeon 7500 */
		1553	rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1430	serge	1554	} else if (of_machine_is_compatible("PowerMac4,4")) {
1123	serge	1555	/* emac */
		1556	rdev->mode_info.connector_table = CT_EMAC;
1430	serge	1557	} else if (of_machine_is_compatible("PowerMac10,1")) {
1123	serge	1558	/* mini with internal tmds */
		1559	rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1430	serge	1560	} else if (of_machine_is_compatible("PowerMac10,2")) {
1123	serge	1561	/* mini with external tmds */
		1562	rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1430	serge	1563	} else if (of_machine_is_compatible("PowerMac12,1")) {
1123	serge	1564	/* PowerMac8,1 ? */
		1565	/* imac g5 isight */
		1566	rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1963	serge	1567	} else if ((rdev->pdev->device == 0x4a48) &&
		1568	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1569	(rdev->pdev->subsystem_device == 0x4a48)) {
		1570	/* Mac X800 */
		1571	rdev->mode_info.connector_table = CT_MAC_X800;
1986	serge	1572	} else if ((of_machine_is_compatible("PowerMac7,2") \|\|
		1573	of_machine_is_compatible("PowerMac7,3")) &&
		1574	(rdev->pdev->device == 0x4150) &&
		1575	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1576	(rdev->pdev->subsystem_device == 0x4150)) {
		1577	/* Mac G5 tower 9600 */
1963	serge	1578	rdev->mode_info.connector_table = CT_MAC_G5_9600;
2997	Serge	1579	} else if ((rdev->pdev->device == 0x4c66) &&
		1580	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1581	(rdev->pdev->subsystem_device == 0x4c66)) {
		1582	/* SAM440ep RV250 embedded board */
		1583	rdev->mode_info.connector_table = CT_SAM440EP;
1123	serge	1584	} else
		1585	#endif /* CONFIG_PPC_PMAC */
1963	serge	1586	#ifdef CONFIG_PPC64
		1587	if (ASIC_IS_RN50(rdev))
		1588	rdev->mode_info.connector_table = CT_RN50_POWER;
		1589	else
		1590	#endif
1123	serge	1591	rdev->mode_info.connector_table = CT_GENERIC;
		1592	}
		1593
		1594	switch (rdev->mode_info.connector_table) {
		1595	case CT_GENERIC:
		1596	DRM_INFO("Connector Table: %d (generic)\n",
		1597	rdev->mode_info.connector_table);
		1598	/* these are the most common settings */
		1599	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1600	/* VGA - primary dac */
1963	serge	1601	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1602	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1603	radeon_add_legacy_encoder(dev,
1963	serge	1604	radeon_get_encoder_enum(dev,
1123	serge	1605	ATOM_DEVICE_CRT1_SUPPORT,
		1606	1),
		1607	ATOM_DEVICE_CRT1_SUPPORT);
		1608	radeon_add_legacy_connector(dev, 0,
		1609	ATOM_DEVICE_CRT1_SUPPORT,
		1610	DRM_MODE_CONNECTOR_VGA,
1268	serge	1611	&ddc_i2c,
1321	serge	1612	CONNECTOR_OBJECT_ID_VGA,
		1613	&hpd);
1123	serge	1614	} else if (rdev->flags & RADEON_IS_MOBILITY) {
		1615	/* LVDS */
1963	serge	1616	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1321	serge	1617	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1618	radeon_add_legacy_encoder(dev,
1963	serge	1619	radeon_get_encoder_enum(dev,
1123	serge	1620	ATOM_DEVICE_LCD1_SUPPORT,
		1621	0),
		1622	ATOM_DEVICE_LCD1_SUPPORT);
		1623	radeon_add_legacy_connector(dev, 0,
		1624	ATOM_DEVICE_LCD1_SUPPORT,
		1625	DRM_MODE_CONNECTOR_LVDS,
1268	serge	1626	&ddc_i2c,
1321	serge	1627	CONNECTOR_OBJECT_ID_LVDS,
		1628	&hpd);
1123	serge	1629
		1630	/* VGA - primary dac */
1963	serge	1631	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1632	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1633	radeon_add_legacy_encoder(dev,
1963	serge	1634	radeon_get_encoder_enum(dev,
1123	serge	1635	ATOM_DEVICE_CRT1_SUPPORT,
		1636	1),
		1637	ATOM_DEVICE_CRT1_SUPPORT);
		1638	radeon_add_legacy_connector(dev, 1,
		1639	ATOM_DEVICE_CRT1_SUPPORT,
		1640	DRM_MODE_CONNECTOR_VGA,
1268	serge	1641	&ddc_i2c,
1321	serge	1642	CONNECTOR_OBJECT_ID_VGA,
		1643	&hpd);
1123	serge	1644	} else {
		1645	/* DVI-I - tv dac, int tmds */
1963	serge	1646	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1647	hpd.hpd = RADEON_HPD_1;
1123	serge	1648	radeon_add_legacy_encoder(dev,
1963	serge	1649	radeon_get_encoder_enum(dev,
1123	serge	1650	ATOM_DEVICE_DFP1_SUPPORT,
		1651	0),
		1652	ATOM_DEVICE_DFP1_SUPPORT);
		1653	radeon_add_legacy_encoder(dev,
1963	serge	1654	radeon_get_encoder_enum(dev,
1123	serge	1655	ATOM_DEVICE_CRT2_SUPPORT,
		1656	2),
		1657	ATOM_DEVICE_CRT2_SUPPORT);
		1658	radeon_add_legacy_connector(dev, 0,
		1659	ATOM_DEVICE_DFP1_SUPPORT \|
		1660	ATOM_DEVICE_CRT2_SUPPORT,
		1661	DRM_MODE_CONNECTOR_DVII,
1268	serge	1662	&ddc_i2c,
1321	serge	1663	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1664	&hpd);
1123	serge	1665
		1666	/* VGA - primary dac */
1963	serge	1667	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1668	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1669	radeon_add_legacy_encoder(dev,
1963	serge	1670	radeon_get_encoder_enum(dev,
1123	serge	1671	ATOM_DEVICE_CRT1_SUPPORT,
		1672	1),
		1673	ATOM_DEVICE_CRT1_SUPPORT);
		1674	radeon_add_legacy_connector(dev, 1,
		1675	ATOM_DEVICE_CRT1_SUPPORT,
		1676	DRM_MODE_CONNECTOR_VGA,
1268	serge	1677	&ddc_i2c,
1321	serge	1678	CONNECTOR_OBJECT_ID_VGA,
		1679	&hpd);
1123	serge	1680	}
		1681
		1682	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		1683	/* TV - tv dac */
1321	serge	1684	ddc_i2c.valid = false;
		1685	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1686	radeon_add_legacy_encoder(dev,
1963	serge	1687	radeon_get_encoder_enum(dev,
1123	serge	1688	ATOM_DEVICE_TV1_SUPPORT,
		1689	2),
		1690	ATOM_DEVICE_TV1_SUPPORT);
		1691	radeon_add_legacy_connector(dev, 2,
		1692	ATOM_DEVICE_TV1_SUPPORT,
		1693	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1694	&ddc_i2c,
1321	serge	1695	CONNECTOR_OBJECT_ID_SVIDEO,
		1696	&hpd);
1123	serge	1697	}
		1698	break;
		1699	case CT_IBOOK:
		1700	DRM_INFO("Connector Table: %d (ibook)\n",
		1701	rdev->mode_info.connector_table);
		1702	/* LVDS */
1963	serge	1703	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1704	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1705	radeon_add_legacy_encoder(dev,
1963	serge	1706	radeon_get_encoder_enum(dev,
1123	serge	1707	ATOM_DEVICE_LCD1_SUPPORT,
		1708	0),
		1709	ATOM_DEVICE_LCD1_SUPPORT);
		1710	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1711	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1712	CONNECTOR_OBJECT_ID_LVDS,
		1713	&hpd);
1123	serge	1714	/* VGA - TV DAC */
1963	serge	1715	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1716	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1717	radeon_add_legacy_encoder(dev,
1963	serge	1718	radeon_get_encoder_enum(dev,
1123	serge	1719	ATOM_DEVICE_CRT2_SUPPORT,
		1720	2),
		1721	ATOM_DEVICE_CRT2_SUPPORT);
		1722	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1723	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1724	CONNECTOR_OBJECT_ID_VGA,
		1725	&hpd);
1123	serge	1726	/* TV - TV DAC */
1321	serge	1727	ddc_i2c.valid = false;
		1728	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1729	radeon_add_legacy_encoder(dev,
1963	serge	1730	radeon_get_encoder_enum(dev,
1123	serge	1731	ATOM_DEVICE_TV1_SUPPORT,
		1732	2),
		1733	ATOM_DEVICE_TV1_SUPPORT);
		1734	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1735	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1736	&ddc_i2c,
1321	serge	1737	CONNECTOR_OBJECT_ID_SVIDEO,
		1738	&hpd);
1123	serge	1739	break;
		1740	case CT_POWERBOOK_EXTERNAL:
		1741	DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
		1742	rdev->mode_info.connector_table);
		1743	/* LVDS */
1963	serge	1744	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1745	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1746	radeon_add_legacy_encoder(dev,
1963	serge	1747	radeon_get_encoder_enum(dev,
1123	serge	1748	ATOM_DEVICE_LCD1_SUPPORT,
		1749	0),
		1750	ATOM_DEVICE_LCD1_SUPPORT);
		1751	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1752	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1753	CONNECTOR_OBJECT_ID_LVDS,
		1754	&hpd);
1123	serge	1755	/* DVI-I - primary dac, ext tmds */
1963	serge	1756	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1757	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1758	radeon_add_legacy_encoder(dev,
1963	serge	1759	radeon_get_encoder_enum(dev,
1123	serge	1760	ATOM_DEVICE_DFP2_SUPPORT,
		1761	0),
		1762	ATOM_DEVICE_DFP2_SUPPORT);
		1763	radeon_add_legacy_encoder(dev,
1963	serge	1764	radeon_get_encoder_enum(dev,
1123	serge	1765	ATOM_DEVICE_CRT1_SUPPORT,
		1766	1),
		1767	ATOM_DEVICE_CRT1_SUPPORT);
1268	serge	1768	/* XXX some are SL */
1123	serge	1769	radeon_add_legacy_connector(dev, 1,
		1770	ATOM_DEVICE_DFP2_SUPPORT \|
		1771	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1772	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1773	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		1774	&hpd);
1123	serge	1775	/* TV - TV DAC */
1321	serge	1776	ddc_i2c.valid = false;
		1777	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1778	radeon_add_legacy_encoder(dev,
1963	serge	1779	radeon_get_encoder_enum(dev,
1123	serge	1780	ATOM_DEVICE_TV1_SUPPORT,
		1781	2),
		1782	ATOM_DEVICE_TV1_SUPPORT);
		1783	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1784	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1785	&ddc_i2c,
1321	serge	1786	CONNECTOR_OBJECT_ID_SVIDEO,
		1787	&hpd);
1123	serge	1788	break;
		1789	case CT_POWERBOOK_INTERNAL:
		1790	DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
		1791	rdev->mode_info.connector_table);
		1792	/* LVDS */
1963	serge	1793	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1794	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1795	radeon_add_legacy_encoder(dev,
1963	serge	1796	radeon_get_encoder_enum(dev,
1123	serge	1797	ATOM_DEVICE_LCD1_SUPPORT,
		1798	0),
		1799	ATOM_DEVICE_LCD1_SUPPORT);
		1800	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1801	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1802	CONNECTOR_OBJECT_ID_LVDS,
		1803	&hpd);
1123	serge	1804	/* DVI-I - primary dac, int tmds */
1963	serge	1805	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1806	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1807	radeon_add_legacy_encoder(dev,
1963	serge	1808	radeon_get_encoder_enum(dev,
1123	serge	1809	ATOM_DEVICE_DFP1_SUPPORT,
		1810	0),
		1811	ATOM_DEVICE_DFP1_SUPPORT);
		1812	radeon_add_legacy_encoder(dev,
1963	serge	1813	radeon_get_encoder_enum(dev,
1123	serge	1814	ATOM_DEVICE_CRT1_SUPPORT,
		1815	1),
		1816	ATOM_DEVICE_CRT1_SUPPORT);
		1817	radeon_add_legacy_connector(dev, 1,
		1818	ATOM_DEVICE_DFP1_SUPPORT \|
		1819	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1820	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1821	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1822	&hpd);
1123	serge	1823	/* TV - TV DAC */
1321	serge	1824	ddc_i2c.valid = false;
		1825	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1826	radeon_add_legacy_encoder(dev,
1963	serge	1827	radeon_get_encoder_enum(dev,
1123	serge	1828	ATOM_DEVICE_TV1_SUPPORT,
		1829	2),
		1830	ATOM_DEVICE_TV1_SUPPORT);
		1831	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1832	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1833	&ddc_i2c,
1321	serge	1834	CONNECTOR_OBJECT_ID_SVIDEO,
		1835	&hpd);
1123	serge	1836	break;
		1837	case CT_POWERBOOK_VGA:
		1838	DRM_INFO("Connector Table: %d (powerbook vga)\n",
		1839	rdev->mode_info.connector_table);
		1840	/* LVDS */
1963	serge	1841	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1842	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1843	radeon_add_legacy_encoder(dev,
1963	serge	1844	radeon_get_encoder_enum(dev,
1123	serge	1845	ATOM_DEVICE_LCD1_SUPPORT,
		1846	0),
		1847	ATOM_DEVICE_LCD1_SUPPORT);
		1848	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1849	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1850	CONNECTOR_OBJECT_ID_LVDS,
		1851	&hpd);
1123	serge	1852	/* VGA - primary dac */
1963	serge	1853	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1854	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1855	radeon_add_legacy_encoder(dev,
1963	serge	1856	radeon_get_encoder_enum(dev,
1123	serge	1857	ATOM_DEVICE_CRT1_SUPPORT,
		1858	1),
		1859	ATOM_DEVICE_CRT1_SUPPORT);
		1860	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1861	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1862	CONNECTOR_OBJECT_ID_VGA,
		1863	&hpd);
1123	serge	1864	/* TV - TV DAC */
1321	serge	1865	ddc_i2c.valid = false;
		1866	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1867	radeon_add_legacy_encoder(dev,
1963	serge	1868	radeon_get_encoder_enum(dev,
1123	serge	1869	ATOM_DEVICE_TV1_SUPPORT,
		1870	2),
		1871	ATOM_DEVICE_TV1_SUPPORT);
		1872	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1873	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1874	&ddc_i2c,
1321	serge	1875	CONNECTOR_OBJECT_ID_SVIDEO,
		1876	&hpd);
1123	serge	1877	break;
		1878	case CT_MINI_EXTERNAL:
		1879	DRM_INFO("Connector Table: %d (mini external tmds)\n",
		1880	rdev->mode_info.connector_table);
		1881	/* DVI-I - tv dac, ext tmds */
1963	serge	1882	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1883	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1884	radeon_add_legacy_encoder(dev,
1963	serge	1885	radeon_get_encoder_enum(dev,
1123	serge	1886	ATOM_DEVICE_DFP2_SUPPORT,
		1887	0),
		1888	ATOM_DEVICE_DFP2_SUPPORT);
		1889	radeon_add_legacy_encoder(dev,
1963	serge	1890	radeon_get_encoder_enum(dev,
1123	serge	1891	ATOM_DEVICE_CRT2_SUPPORT,
		1892	2),
		1893	ATOM_DEVICE_CRT2_SUPPORT);
1268	serge	1894	/* XXX are any DL? */
1123	serge	1895	radeon_add_legacy_connector(dev, 0,
		1896	ATOM_DEVICE_DFP2_SUPPORT \|
		1897	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1898	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1899	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1900	&hpd);
1123	serge	1901	/* TV - TV DAC */
1321	serge	1902	ddc_i2c.valid = false;
		1903	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1904	radeon_add_legacy_encoder(dev,
1963	serge	1905	radeon_get_encoder_enum(dev,
1123	serge	1906	ATOM_DEVICE_TV1_SUPPORT,
		1907	2),
		1908	ATOM_DEVICE_TV1_SUPPORT);
		1909	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1910	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1911	&ddc_i2c,
1321	serge	1912	CONNECTOR_OBJECT_ID_SVIDEO,
		1913	&hpd);
1123	serge	1914	break;
		1915	case CT_MINI_INTERNAL:
		1916	DRM_INFO("Connector Table: %d (mini internal tmds)\n",
		1917	rdev->mode_info.connector_table);
		1918	/* DVI-I - tv dac, int tmds */
1963	serge	1919	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1920	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1921	radeon_add_legacy_encoder(dev,
1963	serge	1922	radeon_get_encoder_enum(dev,
1123	serge	1923	ATOM_DEVICE_DFP1_SUPPORT,
		1924	0),
		1925	ATOM_DEVICE_DFP1_SUPPORT);
		1926	radeon_add_legacy_encoder(dev,
1963	serge	1927	radeon_get_encoder_enum(dev,
1123	serge	1928	ATOM_DEVICE_CRT2_SUPPORT,
		1929	2),
		1930	ATOM_DEVICE_CRT2_SUPPORT);
		1931	radeon_add_legacy_connector(dev, 0,
		1932	ATOM_DEVICE_DFP1_SUPPORT \|
		1933	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1934	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1935	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1936	&hpd);
1123	serge	1937	/* TV - TV DAC */
1321	serge	1938	ddc_i2c.valid = false;
		1939	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1940	radeon_add_legacy_encoder(dev,
1963	serge	1941	radeon_get_encoder_enum(dev,
1123	serge	1942	ATOM_DEVICE_TV1_SUPPORT,
		1943	2),
		1944	ATOM_DEVICE_TV1_SUPPORT);
		1945	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1946	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1947	&ddc_i2c,
1321	serge	1948	CONNECTOR_OBJECT_ID_SVIDEO,
		1949	&hpd);
1123	serge	1950	break;
		1951	case CT_IMAC_G5_ISIGHT:
		1952	DRM_INFO("Connector Table: %d (imac g5 isight)\n",
		1953	rdev->mode_info.connector_table);
		1954	/* DVI-D - int tmds */
1963	serge	1955	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1321	serge	1956	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1957	radeon_add_legacy_encoder(dev,
1963	serge	1958	radeon_get_encoder_enum(dev,
1123	serge	1959	ATOM_DEVICE_DFP1_SUPPORT,
		1960	0),
		1961	ATOM_DEVICE_DFP1_SUPPORT);
		1962	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1268	serge	1963	DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1321	serge	1964	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		1965	&hpd);
1123	serge	1966	/* VGA - tv dac */
1963	serge	1967	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1968	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1969	radeon_add_legacy_encoder(dev,
1963	serge	1970	radeon_get_encoder_enum(dev,
1123	serge	1971	ATOM_DEVICE_CRT2_SUPPORT,
		1972	2),
		1973	ATOM_DEVICE_CRT2_SUPPORT);
		1974	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1975	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1976	CONNECTOR_OBJECT_ID_VGA,
		1977	&hpd);
1123	serge	1978	/* TV - TV DAC */
1321	serge	1979	ddc_i2c.valid = false;
		1980	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1981	radeon_add_legacy_encoder(dev,
1963	serge	1982	radeon_get_encoder_enum(dev,
1123	serge	1983	ATOM_DEVICE_TV1_SUPPORT,
		1984	2),
		1985	ATOM_DEVICE_TV1_SUPPORT);
		1986	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1987	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1988	&ddc_i2c,
1321	serge	1989	CONNECTOR_OBJECT_ID_SVIDEO,
		1990	&hpd);
1123	serge	1991	break;
		1992	case CT_EMAC:
		1993	DRM_INFO("Connector Table: %d (emac)\n",
		1994	rdev->mode_info.connector_table);
		1995	/* VGA - primary dac */
1963	serge	1996	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1997	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1998	radeon_add_legacy_encoder(dev,
1963	serge	1999	radeon_get_encoder_enum(dev,
1123	serge	2000	ATOM_DEVICE_CRT1_SUPPORT,
		2001	1),
		2002	ATOM_DEVICE_CRT1_SUPPORT);
		2003	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	2004	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	2005	CONNECTOR_OBJECT_ID_VGA,
		2006	&hpd);
1123	serge	2007	/* VGA - tv dac */
1963	serge	2008	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	2009	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2010	radeon_add_legacy_encoder(dev,
1963	serge	2011	radeon_get_encoder_enum(dev,
1123	serge	2012	ATOM_DEVICE_CRT2_SUPPORT,
		2013	2),
		2014	ATOM_DEVICE_CRT2_SUPPORT);
		2015	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	2016	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	2017	CONNECTOR_OBJECT_ID_VGA,
		2018	&hpd);
1123	serge	2019	/* TV - TV DAC */
1321	serge	2020	ddc_i2c.valid = false;
		2021	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2022	radeon_add_legacy_encoder(dev,
1963	serge	2023	radeon_get_encoder_enum(dev,
1123	serge	2024	ATOM_DEVICE_TV1_SUPPORT,
		2025	2),
		2026	ATOM_DEVICE_TV1_SUPPORT);
		2027	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2028	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2029	&ddc_i2c,
1321	serge	2030	CONNECTOR_OBJECT_ID_SVIDEO,
		2031	&hpd);
1123	serge	2032	break;
1963	serge	2033	case CT_RN50_POWER:
		2034	DRM_INFO("Connector Table: %d (rn50-power)\n",
		2035	rdev->mode_info.connector_table);
		2036	/* VGA - primary dac */
		2037	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2038	hpd.hpd = RADEON_HPD_NONE;
		2039	radeon_add_legacy_encoder(dev,
		2040	radeon_get_encoder_enum(dev,
		2041	ATOM_DEVICE_CRT1_SUPPORT,
		2042	1),
		2043	ATOM_DEVICE_CRT1_SUPPORT);
		2044	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
		2045	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2046	CONNECTOR_OBJECT_ID_VGA,
		2047	&hpd);
		2048	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		2049	hpd.hpd = RADEON_HPD_NONE;
		2050	radeon_add_legacy_encoder(dev,
		2051	radeon_get_encoder_enum(dev,
		2052	ATOM_DEVICE_CRT2_SUPPORT,
		2053	2),
		2054	ATOM_DEVICE_CRT2_SUPPORT);
		2055	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
		2056	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2057	CONNECTOR_OBJECT_ID_VGA,
		2058	&hpd);
		2059	break;
		2060	case CT_MAC_X800:
		2061	DRM_INFO("Connector Table: %d (mac x800)\n",
		2062	rdev->mode_info.connector_table);
		2063	/* DVI - primary dac, internal tmds */
		2064	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2065	hpd.hpd = RADEON_HPD_1; /* ??? */
		2066	radeon_add_legacy_encoder(dev,
		2067	radeon_get_encoder_enum(dev,
		2068	ATOM_DEVICE_DFP1_SUPPORT,
		2069	0),
		2070	ATOM_DEVICE_DFP1_SUPPORT);
		2071	radeon_add_legacy_encoder(dev,
		2072	radeon_get_encoder_enum(dev,
		2073	ATOM_DEVICE_CRT1_SUPPORT,
		2074	1),
		2075	ATOM_DEVICE_CRT1_SUPPORT);
		2076	radeon_add_legacy_connector(dev, 0,
		2077	ATOM_DEVICE_DFP1_SUPPORT \|
		2078	ATOM_DEVICE_CRT1_SUPPORT,
		2079	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2080	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2081	&hpd);
		2082	/* DVI - tv dac, dvo */
		2083	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		2084	hpd.hpd = RADEON_HPD_2; /* ??? */
		2085	radeon_add_legacy_encoder(dev,
		2086	radeon_get_encoder_enum(dev,
		2087	ATOM_DEVICE_DFP2_SUPPORT,
		2088	0),
		2089	ATOM_DEVICE_DFP2_SUPPORT);
		2090	radeon_add_legacy_encoder(dev,
		2091	radeon_get_encoder_enum(dev,
		2092	ATOM_DEVICE_CRT2_SUPPORT,
		2093	2),
		2094	ATOM_DEVICE_CRT2_SUPPORT);
		2095	radeon_add_legacy_connector(dev, 1,
		2096	ATOM_DEVICE_DFP2_SUPPORT \|
		2097	ATOM_DEVICE_CRT2_SUPPORT,
		2098	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2099	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		2100	&hpd);
		2101	break;
		2102	case CT_MAC_G5_9600:
		2103	DRM_INFO("Connector Table: %d (mac g5 9600)\n",
		2104	rdev->mode_info.connector_table);
		2105	/* DVI - tv dac, dvo */
		2106	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2107	hpd.hpd = RADEON_HPD_1; /* ??? */
		2108	radeon_add_legacy_encoder(dev,
		2109	radeon_get_encoder_enum(dev,
		2110	ATOM_DEVICE_DFP2_SUPPORT,
		2111	0),
		2112	ATOM_DEVICE_DFP2_SUPPORT);
		2113	radeon_add_legacy_encoder(dev,
		2114	radeon_get_encoder_enum(dev,
		2115	ATOM_DEVICE_CRT2_SUPPORT,
		2116	2),
		2117	ATOM_DEVICE_CRT2_SUPPORT);
		2118	radeon_add_legacy_connector(dev, 0,
		2119	ATOM_DEVICE_DFP2_SUPPORT \|
		2120	ATOM_DEVICE_CRT2_SUPPORT,
		2121	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2122	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2123	&hpd);
		2124	/* ADC - primary dac, internal tmds */
		2125	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2126	hpd.hpd = RADEON_HPD_2; /* ??? */
		2127	radeon_add_legacy_encoder(dev,
		2128	radeon_get_encoder_enum(dev,
		2129	ATOM_DEVICE_DFP1_SUPPORT,
		2130	0),
		2131	ATOM_DEVICE_DFP1_SUPPORT);
		2132	radeon_add_legacy_encoder(dev,
		2133	radeon_get_encoder_enum(dev,
		2134	ATOM_DEVICE_CRT1_SUPPORT,
		2135	1),
		2136	ATOM_DEVICE_CRT1_SUPPORT);
		2137	radeon_add_legacy_connector(dev, 1,
		2138	ATOM_DEVICE_DFP1_SUPPORT \|
		2139	ATOM_DEVICE_CRT1_SUPPORT,
		2140	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2141	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2142	&hpd);
		2143	/* TV - TV DAC */
		2144	ddc_i2c.valid = false;
		2145	hpd.hpd = RADEON_HPD_NONE;
		2146	radeon_add_legacy_encoder(dev,
		2147	radeon_get_encoder_enum(dev,
		2148	ATOM_DEVICE_TV1_SUPPORT,
		2149	2),
		2150	ATOM_DEVICE_TV1_SUPPORT);
		2151	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2152	DRM_MODE_CONNECTOR_SVIDEO,
		2153	&ddc_i2c,
		2154	CONNECTOR_OBJECT_ID_SVIDEO,
		2155	&hpd);
		2156	break;
2997	Serge	2157	case CT_SAM440EP:
		2158	DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
		2159	rdev->mode_info.connector_table);
		2160	/* LVDS */
		2161	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
		2162	hpd.hpd = RADEON_HPD_NONE;
		2163	radeon_add_legacy_encoder(dev,
		2164	radeon_get_encoder_enum(dev,
		2165	ATOM_DEVICE_LCD1_SUPPORT,
		2166	0),
		2167	ATOM_DEVICE_LCD1_SUPPORT);
		2168	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
		2169	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
		2170	CONNECTOR_OBJECT_ID_LVDS,
		2171	&hpd);
		2172	/* DVI-I - secondary dac, int tmds */
		2173	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2174	hpd.hpd = RADEON_HPD_1; /* ??? */
		2175	radeon_add_legacy_encoder(dev,
		2176	radeon_get_encoder_enum(dev,
		2177	ATOM_DEVICE_DFP1_SUPPORT,
		2178	0),
		2179	ATOM_DEVICE_DFP1_SUPPORT);
		2180	radeon_add_legacy_encoder(dev,
		2181	radeon_get_encoder_enum(dev,
		2182	ATOM_DEVICE_CRT2_SUPPORT,
		2183	2),
		2184	ATOM_DEVICE_CRT2_SUPPORT);
		2185	radeon_add_legacy_connector(dev, 1,
		2186	ATOM_DEVICE_DFP1_SUPPORT \|
		2187	ATOM_DEVICE_CRT2_SUPPORT,
		2188	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2189	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2190	&hpd);
		2191	/* VGA - primary dac */
		2192	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2193	hpd.hpd = RADEON_HPD_NONE;
		2194	radeon_add_legacy_encoder(dev,
		2195	radeon_get_encoder_enum(dev,
		2196	ATOM_DEVICE_CRT1_SUPPORT,
		2197	1),
		2198	ATOM_DEVICE_CRT1_SUPPORT);
		2199	radeon_add_legacy_connector(dev, 2,
		2200	ATOM_DEVICE_CRT1_SUPPORT,
		2201	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2202	CONNECTOR_OBJECT_ID_VGA,
		2203	&hpd);
		2204	/* TV - TV DAC */
		2205	ddc_i2c.valid = false;
		2206	hpd.hpd = RADEON_HPD_NONE;
		2207	radeon_add_legacy_encoder(dev,
		2208	radeon_get_encoder_enum(dev,
		2209	ATOM_DEVICE_TV1_SUPPORT,
		2210	2),
		2211	ATOM_DEVICE_TV1_SUPPORT);
		2212	radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
		2213	DRM_MODE_CONNECTOR_SVIDEO,
		2214	&ddc_i2c,
		2215	CONNECTOR_OBJECT_ID_SVIDEO,
		2216	&hpd);
		2217	break;
3192	Serge	2218	case CT_MAC_G4_SILVER:
		2219	DRM_INFO("Connector Table: %d (mac g4 silver)\n",
		2220	rdev->mode_info.connector_table);
		2221	/* DVI-I - tv dac, int tmds */
		2222	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2223	hpd.hpd = RADEON_HPD_1; /* ??? */
		2224	radeon_add_legacy_encoder(dev,
		2225	radeon_get_encoder_enum(dev,
		2226	ATOM_DEVICE_DFP1_SUPPORT,
		2227	0),
		2228	ATOM_DEVICE_DFP1_SUPPORT);
		2229	radeon_add_legacy_encoder(dev,
		2230	radeon_get_encoder_enum(dev,
		2231	ATOM_DEVICE_CRT2_SUPPORT,
		2232	2),
		2233	ATOM_DEVICE_CRT2_SUPPORT);
		2234	radeon_add_legacy_connector(dev, 0,
		2235	ATOM_DEVICE_DFP1_SUPPORT \|
		2236	ATOM_DEVICE_CRT2_SUPPORT,
		2237	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2238	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2239	&hpd);
		2240	/* VGA - primary dac */
		2241	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2242	hpd.hpd = RADEON_HPD_NONE;
		2243	radeon_add_legacy_encoder(dev,
		2244	radeon_get_encoder_enum(dev,
		2245	ATOM_DEVICE_CRT1_SUPPORT,
		2246	1),
		2247	ATOM_DEVICE_CRT1_SUPPORT);
		2248	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
		2249	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2250	CONNECTOR_OBJECT_ID_VGA,
		2251	&hpd);
		2252	/* TV - TV DAC */
		2253	ddc_i2c.valid = false;
		2254	hpd.hpd = RADEON_HPD_NONE;
		2255	radeon_add_legacy_encoder(dev,
		2256	radeon_get_encoder_enum(dev,
		2257	ATOM_DEVICE_TV1_SUPPORT,
		2258	2),
		2259	ATOM_DEVICE_TV1_SUPPORT);
		2260	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2261	DRM_MODE_CONNECTOR_SVIDEO,
		2262	&ddc_i2c,
		2263	CONNECTOR_OBJECT_ID_SVIDEO,
		2264	&hpd);
		2265	break;
1123	serge	2266	default:
		2267	DRM_INFO("Connector table: %d (invalid)\n",
		2268	rdev->mode_info.connector_table);
		2269	return false;
		2270	}
		2271
		2272	radeon_link_encoder_connector(dev);
		2273
		2274	return true;
		2275	}
		2276
		2277	static bool radeon_apply_legacy_quirks(struct drm_device *dev,
		2278	int bios_index,
		2279	enum radeon_combios_connector
		2280	*legacy_connector,
1321	serge	2281	struct radeon_i2c_bus_rec *ddc_i2c,
		2282	struct radeon_hpd *hpd)
1123	serge	2283	{
		2284
		2285	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
		2286	one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
		2287	if (dev->pdev->device == 0x515e &&
		2288	dev->pdev->subsystem_vendor == 0x1014) {
		2289	if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
		2290	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		2291	return false;
		2292	}
		2293
		2294	/* X300 card with extra non-existent DVI port */
		2295	if (dev->pdev->device == 0x5B60 &&
		2296	dev->pdev->subsystem_vendor == 0x17af &&
		2297	dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
		2298	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		2299	return false;
		2300	}
		2301
		2302	return true;
		2303	}
		2304
1268	serge	2305	static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
		2306	{
		2307	/* Acer 5102 has non-existent TV port */
		2308	if (dev->pdev->device == 0x5975 &&
		2309	dev->pdev->subsystem_vendor == 0x1025 &&
		2310	dev->pdev->subsystem_device == 0x009f)
		2311	return false;
		2312
		2313	/* HP dc5750 has non-existent TV port */
		2314	if (dev->pdev->device == 0x5974 &&
		2315	dev->pdev->subsystem_vendor == 0x103c &&
		2316	dev->pdev->subsystem_device == 0x280a)
		2317	return false;
		2318
1321	serge	2319	/* MSI S270 has non-existent TV port */
		2320	if (dev->pdev->device == 0x5955 &&
		2321	dev->pdev->subsystem_vendor == 0x1462 &&
		2322	dev->pdev->subsystem_device == 0x0131)
		2323	return false;
		2324
1268	serge	2325	return true;
		2326	}
		2327
		2328	static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
		2329	{
		2330	struct radeon_device *rdev = dev->dev_private;
		2331	uint32_t ext_tmds_info;
		2332
		2333	if (rdev->flags & RADEON_IS_IGP) {
		2334	if (is_dvi_d)
		2335	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		2336	else
		2337	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2338	}
		2339	ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		2340	if (ext_tmds_info) {
		2341	uint8_t rev = RBIOS8(ext_tmds_info);
		2342	uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
		2343	if (rev >= 3) {
		2344	if (is_dvi_d)
		2345	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		2346	else
		2347	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		2348	} else {
		2349	if (flags & 1) {
		2350	if (is_dvi_d)
		2351	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		2352	else
		2353	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		2354	}
		2355	}
		2356	}
		2357	if (is_dvi_d)
		2358	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		2359	else
		2360	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2361	}
		2362
1123	serge	2363	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
		2364	{
		2365	struct radeon_device *rdev = dev->dev_private;
		2366	uint32_t conn_info, entry, devices;
1268	serge	2367	uint16_t tmp, connector_object_id;
1123	serge	2368	enum radeon_combios_ddc ddc_type;
		2369	enum radeon_combios_connector connector;
		2370	int i = 0;
		2371	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	2372	struct radeon_hpd hpd;
1123	serge	2373
		2374	conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
		2375	if (conn_info) {
		2376	for (i = 0; i < 4; i++) {
		2377	entry = conn_info + 2 + i * 2;
		2378
		2379	if (!RBIOS16(entry))
		2380	break;
		2381
		2382	tmp = RBIOS16(entry);
		2383
		2384	connector = (tmp >> 12) & 0xf;
		2385
		2386	ddc_type = (tmp >> 8) & 0xf;
2997	Serge	2387	if (ddc_type == 5)
		2388	ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
		2389	else
1963	serge	2390	ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
1123	serge	2391
1321	serge	2392	switch (connector) {
		2393	case CONNECTOR_PROPRIETARY_LEGACY:
		2394	case CONNECTOR_DVI_I_LEGACY:
		2395	case CONNECTOR_DVI_D_LEGACY:
		2396	if ((tmp >> 4) & 0x1)
		2397	hpd.hpd = RADEON_HPD_2;
		2398	else
		2399	hpd.hpd = RADEON_HPD_1;
		2400	break;
		2401	default:
		2402	hpd.hpd = RADEON_HPD_NONE;
		2403	break;
		2404	}
		2405
1268	serge	2406	if (!radeon_apply_legacy_quirks(dev, i, &connector,
1321	serge	2407	&ddc_i2c, &hpd))
1268	serge	2408	continue;
1123	serge	2409
		2410	switch (connector) {
		2411	case CONNECTOR_PROPRIETARY_LEGACY:
		2412	if ((tmp >> 4) & 0x1)
		2413	devices = ATOM_DEVICE_DFP2_SUPPORT;
		2414	else
		2415	devices = ATOM_DEVICE_DFP1_SUPPORT;
		2416	radeon_add_legacy_encoder(dev,
1963	serge	2417	radeon_get_encoder_enum
1123	serge	2418	(dev, devices, 0),
		2419	devices);
		2420	radeon_add_legacy_connector(dev, i, devices,
		2421	legacy_connector_convert
		2422	[connector],
1268	serge	2423	&ddc_i2c,
1321	serge	2424	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		2425	&hpd);
1123	serge	2426	break;
		2427	case CONNECTOR_CRT_LEGACY:
		2428	if (tmp & 0x1) {
		2429	devices = ATOM_DEVICE_CRT2_SUPPORT;
		2430	radeon_add_legacy_encoder(dev,
1963	serge	2431	radeon_get_encoder_enum
1123	serge	2432	(dev,
		2433	ATOM_DEVICE_CRT2_SUPPORT,
		2434	2),
		2435	ATOM_DEVICE_CRT2_SUPPORT);
		2436	} else {
		2437	devices = ATOM_DEVICE_CRT1_SUPPORT;
		2438	radeon_add_legacy_encoder(dev,
1963	serge	2439	radeon_get_encoder_enum
1123	serge	2440	(dev,
		2441	ATOM_DEVICE_CRT1_SUPPORT,
		2442	1),
		2443	ATOM_DEVICE_CRT1_SUPPORT);
		2444	}
		2445	radeon_add_legacy_connector(dev,
		2446	i,
		2447	devices,
		2448	legacy_connector_convert
		2449	[connector],
1268	serge	2450	&ddc_i2c,
1321	serge	2451	CONNECTOR_OBJECT_ID_VGA,
		2452	&hpd);
1123	serge	2453	break;
		2454	case CONNECTOR_DVI_I_LEGACY:
		2455	devices = 0;
		2456	if (tmp & 0x1) {
		2457	devices \|= ATOM_DEVICE_CRT2_SUPPORT;
		2458	radeon_add_legacy_encoder(dev,
1963	serge	2459	radeon_get_encoder_enum
1123	serge	2460	(dev,
		2461	ATOM_DEVICE_CRT2_SUPPORT,
		2462	2),
		2463	ATOM_DEVICE_CRT2_SUPPORT);
		2464	} else {
		2465	devices \|= ATOM_DEVICE_CRT1_SUPPORT;
		2466	radeon_add_legacy_encoder(dev,
1963	serge	2467	radeon_get_encoder_enum
1123	serge	2468	(dev,
		2469	ATOM_DEVICE_CRT1_SUPPORT,
		2470	1),
		2471	ATOM_DEVICE_CRT1_SUPPORT);
		2472	}
		2473	if ((tmp >> 4) & 0x1) {
		2474	devices \|= ATOM_DEVICE_DFP2_SUPPORT;
		2475	radeon_add_legacy_encoder(dev,
1963	serge	2476	radeon_get_encoder_enum
1123	serge	2477	(dev,
		2478	ATOM_DEVICE_DFP2_SUPPORT,
		2479	0),
		2480	ATOM_DEVICE_DFP2_SUPPORT);
1268	serge	2481	connector_object_id = combios_check_dl_dvi(dev, 0);
1123	serge	2482	} else {
		2483	devices \|= ATOM_DEVICE_DFP1_SUPPORT;
		2484	radeon_add_legacy_encoder(dev,
1963	serge	2485	radeon_get_encoder_enum
1123	serge	2486	(dev,
		2487	ATOM_DEVICE_DFP1_SUPPORT,
		2488	0),
		2489	ATOM_DEVICE_DFP1_SUPPORT);
1268	serge	2490	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1123	serge	2491	}
		2492	radeon_add_legacy_connector(dev,
		2493	i,
		2494	devices,
		2495	legacy_connector_convert
		2496	[connector],
1268	serge	2497	&ddc_i2c,
1321	serge	2498	connector_object_id,
		2499	&hpd);
1123	serge	2500	break;
		2501	case CONNECTOR_DVI_D_LEGACY:
1268	serge	2502	if ((tmp >> 4) & 0x1) {
1123	serge	2503	devices = ATOM_DEVICE_DFP2_SUPPORT;
1268	serge	2504	connector_object_id = combios_check_dl_dvi(dev, 1);
		2505	} else {
1123	serge	2506	devices = ATOM_DEVICE_DFP1_SUPPORT;
1268	serge	2507	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2508	}
1123	serge	2509	radeon_add_legacy_encoder(dev,
1963	serge	2510	radeon_get_encoder_enum
1123	serge	2511	(dev, devices, 0),
		2512	devices);
		2513	radeon_add_legacy_connector(dev, i, devices,
		2514	legacy_connector_convert
		2515	[connector],
1268	serge	2516	&ddc_i2c,
1321	serge	2517	connector_object_id,
		2518	&hpd);
1123	serge	2519	break;
		2520	case CONNECTOR_CTV_LEGACY:
		2521	case CONNECTOR_STV_LEGACY:
		2522	radeon_add_legacy_encoder(dev,
1963	serge	2523	radeon_get_encoder_enum
1123	serge	2524	(dev,
		2525	ATOM_DEVICE_TV1_SUPPORT,
		2526	2),
		2527	ATOM_DEVICE_TV1_SUPPORT);
		2528	radeon_add_legacy_connector(dev, i,
		2529	ATOM_DEVICE_TV1_SUPPORT,
		2530	legacy_connector_convert
		2531	[connector],
1268	serge	2532	&ddc_i2c,
1321	serge	2533	CONNECTOR_OBJECT_ID_SVIDEO,
		2534	&hpd);
1123	serge	2535	break;
		2536	default:
		2537	DRM_ERROR("Unknown connector type: %d\n",
		2538	connector);
		2539	continue;
		2540	}
		2541
		2542	}
		2543	} else {
		2544	uint16_t tmds_info =
		2545	combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		2546	if (tmds_info) {
1963	serge	2547	DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
1123	serge	2548
		2549	radeon_add_legacy_encoder(dev,
1963	serge	2550	radeon_get_encoder_enum(dev,
1123	serge	2551	ATOM_DEVICE_CRT1_SUPPORT,
		2552	1),
		2553	ATOM_DEVICE_CRT1_SUPPORT);
		2554	radeon_add_legacy_encoder(dev,
1963	serge	2555	radeon_get_encoder_enum(dev,
1123	serge	2556	ATOM_DEVICE_DFP1_SUPPORT,
		2557	0),
		2558	ATOM_DEVICE_DFP1_SUPPORT);
		2559
1963	serge	2560	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2561	hpd.hpd = RADEON_HPD_1;
1123	serge	2562	radeon_add_legacy_connector(dev,
		2563	0,
		2564	ATOM_DEVICE_CRT1_SUPPORT \|
		2565	ATOM_DEVICE_DFP1_SUPPORT,
		2566	DRM_MODE_CONNECTOR_DVII,
1268	serge	2567	&ddc_i2c,
1321	serge	2568	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2569	&hpd);
1123	serge	2570	} else {
1268	serge	2571	uint16_t crt_info =
		2572	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1963	serge	2573	DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
1268	serge	2574	if (crt_info) {
		2575	radeon_add_legacy_encoder(dev,
1963	serge	2576	radeon_get_encoder_enum(dev,
1268	serge	2577	ATOM_DEVICE_CRT1_SUPPORT,
		2578	1),
		2579	ATOM_DEVICE_CRT1_SUPPORT);
1963	serge	2580	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	2581	hpd.hpd = RADEON_HPD_NONE;
1268	serge	2582	radeon_add_legacy_connector(dev,
		2583	0,
		2584	ATOM_DEVICE_CRT1_SUPPORT,
		2585	DRM_MODE_CONNECTOR_VGA,
		2586	&ddc_i2c,
1321	serge	2587	CONNECTOR_OBJECT_ID_VGA,
		2588	&hpd);
1268	serge	2589	} else {
1963	serge	2590	DRM_DEBUG_KMS("No connector info found\n");
1123	serge	2591	return false;
		2592	}
		2593	}
1268	serge	2594	}
1123	serge	2595
		2596	if (rdev->flags & RADEON_IS_MOBILITY \|\| rdev->flags & RADEON_IS_IGP) {
		2597	uint16_t lcd_info =
		2598	combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		2599	if (lcd_info) {
		2600	uint16_t lcd_ddc_info =
		2601	combios_get_table_offset(dev,
		2602	COMBIOS_LCD_DDC_INFO_TABLE);
		2603
		2604	radeon_add_legacy_encoder(dev,
1963	serge	2605	radeon_get_encoder_enum(dev,
1123	serge	2606	ATOM_DEVICE_LCD1_SUPPORT,
		2607	0),
		2608	ATOM_DEVICE_LCD1_SUPPORT);
		2609
		2610	if (lcd_ddc_info) {
		2611	ddc_type = RBIOS8(lcd_ddc_info + 2);
		2612	switch (ddc_type) {
		2613	case DDC_LCD:
		2614	ddc_i2c =
1963	serge	2615	combios_setup_i2c_bus(rdev,
		2616	DDC_LCD,
		2617	RBIOS32(lcd_ddc_info + 3),
		2618	RBIOS32(lcd_ddc_info + 7));
		2619	radeon_i2c_add(rdev, &ddc_i2c, "LCD");
1123	serge	2620	break;
		2621	case DDC_GPIO:
		2622	ddc_i2c =
1963	serge	2623	combios_setup_i2c_bus(rdev,
		2624	DDC_GPIO,
		2625	RBIOS32(lcd_ddc_info + 3),
		2626	RBIOS32(lcd_ddc_info + 7));
		2627	radeon_i2c_add(rdev, &ddc_i2c, "LCD");
1123	serge	2628	break;
		2629	default:
1963	serge	2630	ddc_i2c =
		2631	combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
1123	serge	2632	break;
		2633	}
1963	serge	2634	DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
1123	serge	2635	} else
		2636	ddc_i2c.valid = false;
		2637
1321	serge	2638	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2639	radeon_add_legacy_connector(dev,
		2640	5,
		2641	ATOM_DEVICE_LCD1_SUPPORT,
		2642	DRM_MODE_CONNECTOR_LVDS,
1268	serge	2643	&ddc_i2c,
1321	serge	2644	CONNECTOR_OBJECT_ID_LVDS,
		2645	&hpd);
1123	serge	2646	}
		2647	}
		2648
		2649	/* check TV table */
		2650	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		2651	uint32_t tv_info =
		2652	combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		2653	if (tv_info) {
		2654	if (RBIOS8(tv_info + 6) == 'T') {
1268	serge	2655	if (radeon_apply_legacy_tv_quirks(dev)) {
1321	serge	2656	hpd.hpd = RADEON_HPD_NONE;
1963	serge	2657	ddc_i2c.valid = false;
1123	serge	2658	radeon_add_legacy_encoder(dev,
1963	serge	2659	radeon_get_encoder_enum
1123	serge	2660	(dev,
		2661	ATOM_DEVICE_TV1_SUPPORT,
		2662	2),
		2663	ATOM_DEVICE_TV1_SUPPORT);
		2664	radeon_add_legacy_connector(dev, 6,
		2665	ATOM_DEVICE_TV1_SUPPORT,
		2666	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2667	&ddc_i2c,
1321	serge	2668	CONNECTOR_OBJECT_ID_SVIDEO,
		2669	&hpd);
1268	serge	2670	}
1123	serge	2671	}
		2672	}
		2673	}
		2674
		2675	radeon_link_encoder_connector(dev);
		2676
		2677	return true;
		2678	}
		2679
1963	serge	2680	static const char *thermal_controller_names[] = {
		2681	"NONE",
		2682	"lm63",
		2683	"adm1032",
		2684	};
		2685
1430	serge	2686	void radeon_combios_get_power_modes(struct radeon_device *rdev)
		2687	{
		2688	struct drm_device *dev = rdev->ddev;
		2689	u16 offset, misc, misc2 = 0;
		2690	u8 rev, blocks, tmp;
		2691	int state_index = 0;
2160	serge	2692	struct radeon_i2c_bus_rec i2c_bus;
1430	serge	2693
1963	serge	2694	rdev->pm.default_power_state_index = -1;
1430	serge	2695
1963	serge	2696	/* allocate 2 power states */
		2697	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2997	Serge	2698	if (rdev->pm.power_state) {
		2699	/* allocate 1 clock mode per state */
		2700	rdev->pm.power_state[0].clock_info =
		2701	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2702	rdev->pm.power_state[1].clock_info =
		2703	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2704	if (!rdev->pm.power_state[0].clock_info \|\|
		2705	!rdev->pm.power_state[1].clock_info)
		2706	goto pm_failed;
		2707	} else
		2708	goto pm_failed;
1963	serge	2709
		2710	/* check for a thermal chip */
		2711	offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
		2712	if (offset) {
		2713	u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
		2714
		2715	rev = RBIOS8(offset);
		2716
		2717	if (rev == 0) {
		2718	thermal_controller = RBIOS8(offset + 3);
		2719	gpio = RBIOS8(offset + 4) & 0x3f;
		2720	i2c_addr = RBIOS8(offset + 5);
		2721	} else if (rev == 1) {
		2722	thermal_controller = RBIOS8(offset + 4);
		2723	gpio = RBIOS8(offset + 5) & 0x3f;
		2724	i2c_addr = RBIOS8(offset + 6);
		2725	} else if (rev == 2) {
		2726	thermal_controller = RBIOS8(offset + 4);
		2727	gpio = RBIOS8(offset + 5) & 0x3f;
		2728	i2c_addr = RBIOS8(offset + 6);
		2729	clk_bit = RBIOS8(offset + 0xa);
		2730	data_bit = RBIOS8(offset + 0xb);
		2731	}
		2732	if ((thermal_controller > 0) && (thermal_controller < 3)) {
		2733	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2734	thermal_controller_names[thermal_controller],
		2735	i2c_addr >> 1);
		2736	if (gpio == DDC_LCD) {
		2737	/* MM i2c */
		2738	i2c_bus.valid = true;
		2739	i2c_bus.hw_capable = true;
		2740	i2c_bus.mm_i2c = true;
		2741	i2c_bus.i2c_id = 0xa0;
		2742	} else if (gpio == DDC_GPIO)
		2743	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
		2744	else
		2745	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
		2746	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2747	if (rdev->pm.i2c_bus) {
		2748	struct i2c_board_info info = { };
		2749	const char *name = thermal_controller_names[thermal_controller];
		2750	info.addr = i2c_addr >> 1;
		2751	strlcpy(info.type, name, sizeof(info.type));
		2752	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2753	}
		2754	}
2997	Serge	2755	} else {
		2756	/* boards with a thermal chip, but no overdrive table */
		2757
		2758	/* Asus 9600xt has an f75375 on the monid bus */
		2759	if ((dev->pdev->device == 0x4152) &&
		2760	(dev->pdev->subsystem_vendor == 0x1043) &&
		2761	(dev->pdev->subsystem_device == 0xc002)) {
		2762	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		2763	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2764	if (rdev->pm.i2c_bus) {
		2765	struct i2c_board_info info = { };
		2766	const char *name = "f75375";
		2767	info.addr = 0x28;
		2768	strlcpy(info.type, name, sizeof(info.type));
		2769	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2770	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2771	name, info.addr);
		2772	}
		2773	}
1963	serge	2774	}
		2775
1430	serge	2776	if (rdev->flags & RADEON_IS_MOBILITY) {
		2777	offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
		2778	if (offset) {
		2779	rev = RBIOS8(offset);
		2780	blocks = RBIOS8(offset + 0x2);
		2781	/* power mode 0 tends to be the only valid one */
		2782	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2783	rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
		2784	rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
		2785	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2786	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2787	goto default_mode;
		2788	rdev->pm.power_state[state_index].type =
		2789	POWER_STATE_TYPE_BATTERY;
		2790	misc = RBIOS16(offset + 0x5 + 0x0);
		2791	if (rev > 4)
		2792	misc2 = RBIOS16(offset + 0x5 + 0xe);
1963	serge	2793	rdev->pm.power_state[state_index].misc = misc;
		2794	rdev->pm.power_state[state_index].misc2 = misc2;
1430	serge	2795	if (misc & 0x4) {
		2796	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
		2797	if (misc & 0x8)
		2798	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2799	true;
		2800	else
		2801	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2802	false;
		2803	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
		2804	if (rev < 6) {
		2805	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
		2806	RBIOS16(offset + 0x5 + 0xb) * 4;
		2807	tmp = RBIOS8(offset + 0x5 + 0xd);
		2808	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
		2809	} else {
		2810	u8 entries = RBIOS8(offset + 0x5 + 0xb);
		2811	u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
		2812	if (entries && voltage_table_offset) {
		2813	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
		2814	RBIOS16(voltage_table_offset) * 4;
		2815	tmp = RBIOS8(voltage_table_offset + 0x2);
		2816	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
		2817	} else
		2818	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
		2819	}
		2820	switch ((misc2 & 0x700) >> 8) {
		2821	case 0:
		2822	default:
		2823	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
		2824	break;
		2825	case 1:
		2826	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
		2827	break;
		2828	case 2:
		2829	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
		2830	break;
		2831	case 3:
		2832	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
		2833	break;
		2834	case 4:
		2835	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
		2836	break;
		2837	}
		2838	} else
		2839	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
		2840	if (rev > 6)
1963	serge	2841	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2842	RBIOS8(offset + 0x5 + 0x10);
1963	serge	2843	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1430	serge	2844	state_index++;
		2845	} else {
		2846	/* XXX figure out some good default low power mode for mobility cards w/out power tables */
		2847	}
		2848	} else {
		2849	/* XXX figure out some good default low power mode for desktop cards */
		2850	}
		2851
		2852	default_mode:
		2853	/* add the default mode */
		2854	rdev->pm.power_state[state_index].type =
		2855	POWER_STATE_TYPE_DEFAULT;
		2856	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2857	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
		2858	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
		2859	rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
1963	serge	2860	if ((state_index > 0) &&
		2861	(rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
		2862	rdev->pm.power_state[state_index].clock_info[0].voltage =
		2863	rdev->pm.power_state[0].clock_info[0].voltage;
		2864	else
1430	serge	2865	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1963	serge	2866	rdev->pm.power_state[state_index].pcie_lanes = 16;
		2867	rdev->pm.power_state[state_index].flags = 0;
		2868	rdev->pm.default_power_state_index = state_index;
1430	serge	2869	rdev->pm.num_power_states = state_index + 1;
		2870
1963	serge	2871	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2872	rdev->pm.current_clock_mode_index = 0;
2997	Serge	2873	return;
		2874
		2875	pm_failed:
		2876	rdev->pm.default_power_state_index = state_index;
		2877	rdev->pm.num_power_states = 0;
		2878
		2879	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2880	rdev->pm.current_clock_mode_index = 0;
1430	serge	2881	}
		2882
1321	serge	2883	void radeon_external_tmds_setup(struct drm_encoder *encoder)
		2884	{
		2885	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2886	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2887
		2888	if (!tmds)
		2889	return;
		2890
		2891	switch (tmds->dvo_chip) {
		2892	case DVO_SIL164:
		2893	/* sil 164 */
1430	serge	2894	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2895	tmds->slave_addr,
		2896	0x08, 0x30);
1430	serge	2897	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2898	tmds->slave_addr,
		2899	0x09, 0x00);
1430	serge	2900	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2901	tmds->slave_addr,
		2902	0x0a, 0x90);
1430	serge	2903	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2904	tmds->slave_addr,
		2905	0x0c, 0x89);
1430	serge	2906	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2907	tmds->slave_addr,
		2908	0x08, 0x3b);
		2909	break;
		2910	case DVO_SIL1178:
		2911	/* sil 1178 - untested */
		2912	/*
		2913	* 0x0f, 0x44
		2914	* 0x0f, 0x4c
		2915	* 0x0e, 0x01
		2916	* 0x0a, 0x80
		2917	* 0x09, 0x30
		2918	* 0x0c, 0xc9
		2919	* 0x0d, 0x70
		2920	* 0x08, 0x32
		2921	* 0x08, 0x33
		2922	*/
		2923	break;
		2924	default:
		2925	break;
		2926	}
		2927
		2928	}
		2929
		2930	bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
		2931	{
		2932	struct drm_device *dev = encoder->dev;
		2933	struct radeon_device *rdev = dev->dev_private;
		2934	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2935	uint16_t offset;
		2936	uint8_t blocks, slave_addr, rev;
		2937	uint32_t index, id;
		2938	uint32_t reg, val, and_mask, or_mask;
		2939	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2940
		2941	if (!tmds)
		2942	return false;
		2943
		2944	if (rdev->flags & RADEON_IS_IGP) {
		2945	offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
		2946	rev = RBIOS8(offset);
		2947	if (offset) {
		2948	rev = RBIOS8(offset);
		2949	if (rev > 1) {
		2950	blocks = RBIOS8(offset + 3);
		2951	index = offset + 4;
		2952	while (blocks > 0) {
		2953	id = RBIOS16(index);
		2954	index += 2;
		2955	switch (id >> 13) {
		2956	case 0:
		2957	reg = (id & 0x1fff) * 4;
		2958	val = RBIOS32(index);
		2959	index += 4;
		2960	WREG32(reg, val);
		2961	break;
		2962	case 2:
		2963	reg = (id & 0x1fff) * 4;
		2964	and_mask = RBIOS32(index);
		2965	index += 4;
		2966	or_mask = RBIOS32(index);
		2967	index += 4;
		2968	val = RREG32(reg);
		2969	val = (val & and_mask) \| or_mask;
		2970	WREG32(reg, val);
		2971	break;
		2972	case 3:
		2973	val = RBIOS16(index);
		2974	index += 2;
		2975	udelay(val);
		2976	break;
		2977	case 4:
		2978	val = RBIOS16(index);
		2979	index += 2;
2997	Serge	2980	mdelay(val);
1321	serge	2981	break;
		2982	case 6:
		2983	slave_addr = id & 0xff;
		2984	slave_addr >>= 1; /* 7 bit addressing */
		2985	index++;
		2986	reg = RBIOS8(index);
		2987	index++;
		2988	val = RBIOS8(index);
		2989	index++;
1430	serge	2990	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2991	slave_addr,
		2992	reg, val);
		2993	break;
		2994	default:
		2995	DRM_ERROR("Unknown id %d\n", id >> 13);
		2996	break;
		2997	}
		2998	blocks--;
		2999	}
		3000	return true;
		3001	}
		3002	}
		3003	} else {
		3004	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		3005	if (offset) {
		3006	index = offset + 10;
		3007	id = RBIOS16(index);
		3008	while (id != 0xffff) {
		3009	index += 2;
		3010	switch (id >> 13) {
		3011	case 0:
		3012	reg = (id & 0x1fff) * 4;
		3013	val = RBIOS32(index);
		3014	WREG32(reg, val);
		3015	break;
		3016	case 2:
		3017	reg = (id & 0x1fff) * 4;
		3018	and_mask = RBIOS32(index);
		3019	index += 4;
		3020	or_mask = RBIOS32(index);
		3021	index += 4;
		3022	val = RREG32(reg);
		3023	val = (val & and_mask) \| or_mask;
		3024	WREG32(reg, val);
		3025	break;
		3026	case 4:
		3027	val = RBIOS16(index);
		3028	index += 2;
		3029	udelay(val);
		3030	break;
		3031	case 5:
		3032	reg = id & 0x1fff;
		3033	and_mask = RBIOS32(index);
		3034	index += 4;
		3035	or_mask = RBIOS32(index);
		3036	index += 4;
		3037	val = RREG32_PLL(reg);
		3038	val = (val & and_mask) \| or_mask;
		3039	WREG32_PLL(reg, val);
		3040	break;
		3041	case 6:
		3042	reg = id & 0x1fff;
		3043	val = RBIOS8(index);
		3044	index += 1;
1430	serge	3045	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	3046	tmds->slave_addr,
		3047	reg, val);
		3048	break;
		3049	default:
		3050	DRM_ERROR("Unknown id %d\n", id >> 13);
		3051	break;
		3052	}
		3053	id = RBIOS16(index);
		3054	}
		3055	return true;
		3056	}
		3057	}
		3058	return false;
		3059	}
		3060
1123	serge	3061	static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
		3062	{
		3063	struct radeon_device *rdev = dev->dev_private;
		3064
		3065	if (offset) {
		3066	while (RBIOS16(offset)) {
		3067	uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
		3068	uint32_t addr = (RBIOS16(offset) & 0x1fff);
		3069	uint32_t val, and_mask, or_mask;
		3070	uint32_t tmp;
		3071
		3072	offset += 2;
		3073	switch (cmd) {
		3074	case 0:
		3075	val = RBIOS32(offset);
		3076	offset += 4;
		3077	WREG32(addr, val);
		3078	break;
		3079	case 1:
		3080	val = RBIOS32(offset);
		3081	offset += 4;
		3082	WREG32(addr, val);
		3083	break;
		3084	case 2:
		3085	and_mask = RBIOS32(offset);
		3086	offset += 4;
		3087	or_mask = RBIOS32(offset);
		3088	offset += 4;
		3089	tmp = RREG32(addr);
		3090	tmp &= and_mask;
		3091	tmp \|= or_mask;
		3092	WREG32(addr, tmp);
		3093	break;
		3094	case 3:
		3095	and_mask = RBIOS32(offset);
		3096	offset += 4;
		3097	or_mask = RBIOS32(offset);
		3098	offset += 4;
		3099	tmp = RREG32(addr);
		3100	tmp &= and_mask;
		3101	tmp \|= or_mask;
		3102	WREG32(addr, tmp);
		3103	break;
		3104	case 4:
		3105	val = RBIOS16(offset);
		3106	offset += 2;
		3107	udelay(val);
		3108	break;
		3109	case 5:
		3110	val = RBIOS16(offset);
		3111	offset += 2;
		3112	switch (addr) {
		3113	case 8:
		3114	while (val--) {
		3115	if (!
		3116	(RREG32_PLL
		3117	(RADEON_CLK_PWRMGT_CNTL) &
		3118	RADEON_MC_BUSY))
		3119	break;
		3120	}
		3121	break;
		3122	case 9:
		3123	while (val--) {
		3124	if ((RREG32(RADEON_MC_STATUS) &
		3125	RADEON_MC_IDLE))
		3126	break;
		3127	}
		3128	break;
		3129	default:
		3130	break;
		3131	}
		3132	break;
		3133	default:
		3134	break;
		3135	}
		3136	}
		3137	}
		3138	}
		3139
		3140	static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
		3141	{
		3142	struct radeon_device *rdev = dev->dev_private;
		3143
		3144	if (offset) {
		3145	while (RBIOS8(offset)) {
		3146	uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
		3147	uint8_t addr = (RBIOS8(offset) & 0x3f);
		3148	uint32_t val, shift, tmp;
		3149	uint32_t and_mask, or_mask;
		3150
		3151	offset++;
		3152	switch (cmd) {
		3153	case 0:
		3154	val = RBIOS32(offset);
		3155	offset += 4;
		3156	WREG32_PLL(addr, val);
		3157	break;
		3158	case 1:
		3159	shift = RBIOS8(offset) * 8;
		3160	offset++;
		3161	and_mask = RBIOS8(offset) << shift;
		3162	and_mask \|= ~(0xff << shift);
		3163	offset++;
		3164	or_mask = RBIOS8(offset) << shift;
		3165	offset++;
		3166	tmp = RREG32_PLL(addr);
		3167	tmp &= and_mask;
		3168	tmp \|= or_mask;
		3169	WREG32_PLL(addr, tmp);
		3170	break;
		3171	case 2:
		3172	case 3:
		3173	tmp = 1000;
		3174	switch (addr) {
		3175	case 1:
		3176	udelay(150);
		3177	break;
		3178	case 2:
2997	Serge	3179	mdelay(1);
1123	serge	3180	break;
		3181	case 3:
		3182	while (tmp--) {
		3183	if (!
		3184	(RREG32_PLL
		3185	(RADEON_CLK_PWRMGT_CNTL) &
		3186	RADEON_MC_BUSY))
		3187	break;
		3188	}
		3189	break;
		3190	case 4:
		3191	while (tmp--) {
		3192	if (RREG32_PLL
		3193	(RADEON_CLK_PWRMGT_CNTL) &
		3194	RADEON_DLL_READY)
		3195	break;
		3196	}
		3197	break;
		3198	case 5:
		3199	tmp =
		3200	RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
		3201	if (tmp & RADEON_CG_NO1_DEBUG_0) {
		3202	#if 0
		3203	uint32_t mclk_cntl =
		3204	RREG32_PLL
		3205	(RADEON_MCLK_CNTL);
		3206	mclk_cntl &= 0xffff0000;
		3207	/mclk_cntl \|= 0x00001111;//* ??? */
		3208	WREG32_PLL(RADEON_MCLK_CNTL,
		3209	mclk_cntl);
2997	Serge	3210	mdelay(10);
1123	serge	3211	#endif
		3212	WREG32_PLL
		3213	(RADEON_CLK_PWRMGT_CNTL,
		3214	tmp &
		3215	~RADEON_CG_NO1_DEBUG_0);
2997	Serge	3216	mdelay(10);
1123	serge	3217	}
		3218	break;
		3219	default:
		3220	break;
		3221	}
		3222	break;
		3223	default:
		3224	break;
		3225	}
		3226	}
		3227	}
		3228	}
		3229
		3230	static void combios_parse_ram_reset_table(struct drm_device *dev,
		3231	uint16_t offset)
		3232	{
		3233	struct radeon_device *rdev = dev->dev_private;
		3234	uint32_t tmp;
		3235
		3236	if (offset) {
		3237	uint8_t val = RBIOS8(offset);
		3238	while (val != 0xff) {
		3239	offset++;
		3240
		3241	if (val == 0x0f) {
		3242	uint32_t channel_complete_mask;
		3243
		3244	if (ASIC_IS_R300(rdev))
		3245	channel_complete_mask =
		3246	R300_MEM_PWRUP_COMPLETE;
		3247	else
		3248	channel_complete_mask =
		3249	RADEON_MEM_PWRUP_COMPLETE;
		3250	tmp = 20000;
		3251	while (tmp--) {
		3252	if ((RREG32(RADEON_MEM_STR_CNTL) &
		3253	channel_complete_mask) ==
		3254	channel_complete_mask)
		3255	break;
		3256	}
		3257	} else {
		3258	uint32_t or_mask = RBIOS16(offset);
		3259	offset += 2;
		3260
		3261	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3262	tmp &= RADEON_SDRAM_MODE_MASK;
		3263	tmp \|= or_mask;
		3264	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		3265
		3266	or_mask = val << 24;
		3267	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3268	tmp &= RADEON_B3MEM_RESET_MASK;
		3269	tmp \|= or_mask;
		3270	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		3271	}
		3272	val = RBIOS8(offset);
		3273	}
		3274	}
		3275	}
		3276
		3277	static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
		3278	int mem_addr_mapping)
		3279	{
		3280	struct radeon_device *rdev = dev->dev_private;
		3281	uint32_t mem_cntl;
		3282	uint32_t mem_size;
		3283	uint32_t addr = 0;
		3284
		3285	mem_cntl = RREG32(RADEON_MEM_CNTL);
		3286	if (mem_cntl & RV100_HALF_MODE)
		3287	ram /= 2;
		3288	mem_size = ram;
		3289	mem_cntl &= ~(0xff << 8);
		3290	mem_cntl \|= (mem_addr_mapping & 0xff) << 8;
		3291	WREG32(RADEON_MEM_CNTL, mem_cntl);
		3292	RREG32(RADEON_MEM_CNTL);
		3293
		3294	/* sdram reset ? */
		3295
		3296	/* something like this???? */
		3297	while (ram--) {
		3298	addr = ram * 1024 * 1024;
		3299	/* write to each page */
3192	Serge	3300	WREG32_IDX((addr) \| RADEON_MM_APER, 0xdeadbeef);
1123	serge	3301	/* read back and verify */
3192	Serge	3302	if (RREG32_IDX((addr) \| RADEON_MM_APER) != 0xdeadbeef)
1123	serge	3303	return 0;
		3304	}
		3305
		3306	return mem_size;
		3307	}
		3308
		3309	static void combios_write_ram_size(struct drm_device *dev)
		3310	{
		3311	struct radeon_device *rdev = dev->dev_private;
		3312	uint8_t rev;
		3313	uint16_t offset;
		3314	uint32_t mem_size = 0;
		3315	uint32_t mem_cntl = 0;
		3316
		3317	/* should do something smarter here I guess... */
		3318	if (rdev->flags & RADEON_IS_IGP)
		3319	return;
		3320
		3321	/* first check detected mem table */
		3322	offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
		3323	if (offset) {
		3324	rev = RBIOS8(offset);
		3325	if (rev < 3) {
		3326	mem_cntl = RBIOS32(offset + 1);
		3327	mem_size = RBIOS16(offset + 5);
1963	serge	3328	if ((rdev->family < CHIP_R200) &&
		3329	!ASIC_IS_RN50(rdev))
1123	serge	3330	WREG32(RADEON_MEM_CNTL, mem_cntl);
		3331	}
		3332	}
		3333
		3334	if (!mem_size) {
		3335	offset =
		3336	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		3337	if (offset) {
		3338	rev = RBIOS8(offset - 1);
		3339	if (rev < 1) {
1963	serge	3340	if ((rdev->family < CHIP_R200)
		3341	&& !ASIC_IS_RN50(rdev)) {
1123	serge	3342	int ram = 0;
		3343	int mem_addr_mapping = 0;
		3344
		3345	while (RBIOS8(offset)) {
		3346	ram = RBIOS8(offset);
		3347	mem_addr_mapping =
		3348	RBIOS8(offset + 1);
		3349	if (mem_addr_mapping != 0x25)
		3350	ram *= 2;
		3351	mem_size =
		3352	combios_detect_ram(dev, ram,
		3353	mem_addr_mapping);
		3354	if (mem_size)
		3355	break;
		3356	offset += 2;
		3357	}
		3358	} else
		3359	mem_size = RBIOS8(offset);
		3360	} else {
		3361	mem_size = RBIOS8(offset);
		3362	mem_size = 2; / convert to MB */
		3363	}
		3364	}
		3365	}
		3366
		3367	mem_size = (1024 1024); /* convert to bytes */
		3368	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
		3369	}
		3370
		3371	void radeon_combios_asic_init(struct drm_device *dev)
		3372	{
		3373	struct radeon_device *rdev = dev->dev_private;
		3374	uint16_t table;
		3375
		3376	/* port hardcoded mac stuff from radeonfb */
		3377	if (rdev->bios == NULL)
		3378	return;
		3379
		3380	/* ASIC INIT 1 */
		3381	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
		3382	if (table)
		3383	combios_parse_mmio_table(dev, table);
		3384
		3385	/* PLL INIT */
		3386	table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
		3387	if (table)
		3388	combios_parse_pll_table(dev, table);
		3389
		3390	/* ASIC INIT 2 */
		3391	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
		3392	if (table)
		3393	combios_parse_mmio_table(dev, table);
		3394
		3395	if (!(rdev->flags & RADEON_IS_IGP)) {
		3396	/* ASIC INIT 4 */
		3397	table =
		3398	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
		3399	if (table)
		3400	combios_parse_mmio_table(dev, table);
		3401
		3402	/* RAM RESET */
		3403	table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
		3404	if (table)
		3405	combios_parse_ram_reset_table(dev, table);
		3406
		3407	/* ASIC INIT 3 */
		3408	table =
		3409	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
		3410	if (table)
		3411	combios_parse_mmio_table(dev, table);
		3412
		3413	/* write CONFIG_MEMSIZE */
		3414	combios_write_ram_size(dev);
		3415	}
		3416
1963	serge	3417	/* quirk for rs4xx HP nx6125 laptop to make it resume
		3418	* - it hangs on resume inside the dynclk 1 table.
		3419	*/
		3420	if (rdev->family == CHIP_RS480 &&
		3421	rdev->pdev->subsystem_vendor == 0x103c &&
		3422	rdev->pdev->subsystem_device == 0x308b)
		3423	return;
		3424
		3425	/* quirk for rs4xx HP dv5000 laptop to make it resume
		3426	* - it hangs on resume inside the dynclk 1 table.
		3427	*/
		3428	if (rdev->family == CHIP_RS480 &&
		3429	rdev->pdev->subsystem_vendor == 0x103c &&
		3430	rdev->pdev->subsystem_device == 0x30a4)
		3431	return;
		3432
2997	Serge	3433	/* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
		3434	* - it hangs on resume inside the dynclk 1 table.
		3435	*/
		3436	if (rdev->family == CHIP_RS480 &&
		3437	rdev->pdev->subsystem_vendor == 0x103c &&
		3438	rdev->pdev->subsystem_device == 0x30ae)
		3439	return;
		3440
1123	serge	3441	/* DYN CLK 1 */
		3442	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		3443	if (table)
		3444	combios_parse_pll_table(dev, table);
		3445
		3446	}
		3447
		3448	void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
		3449	{
		3450	struct radeon_device *rdev = dev->dev_private;
		3451	uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
		3452
		3453	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		3454	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3455	bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
		3456
		3457	/* let the bios control the backlight */
		3458	bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
		3459
		3460	/* tell the bios not to handle mode switching */
		3461	bios_6_scratch \|= (RADEON_DISPLAY_SWITCHING_DIS \|
		3462	RADEON_ACC_MODE_CHANGE);
		3463
		3464	/* tell the bios a driver is loaded */
		3465	bios_7_scratch \|= RADEON_DRV_LOADED;
		3466
		3467	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		3468	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3469	WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
		3470	}
		3471
		3472	void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
		3473	{
		3474	struct drm_device *dev = encoder->dev;
		3475	struct radeon_device *rdev = dev->dev_private;
		3476	uint32_t bios_6_scratch;
		3477
		3478	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3479
		3480	if (lock)
		3481	bios_6_scratch \|= RADEON_DRIVER_CRITICAL;
		3482	else
		3483	bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
		3484
		3485	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3486	}
		3487
		3488	void
		3489	radeon_combios_connected_scratch_regs(struct drm_connector *connector,
		3490	struct drm_encoder *encoder,
		3491	bool connected)
		3492	{
		3493	struct drm_device *dev = connector->dev;
		3494	struct radeon_device *rdev = dev->dev_private;
		3495	struct radeon_connector *radeon_connector =
		3496	to_radeon_connector(connector);
		3497	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3498	uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
		3499	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		3500
		3501	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		3502	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		3503	if (connected) {
1963	serge	3504	DRM_DEBUG_KMS("TV1 connected\n");
1123	serge	3505	/* fix me */
		3506	bios_4_scratch \|= RADEON_TV1_ATTACHED_SVIDEO;
		3507	/save->bios_4_scratch \|= RADEON_TV1_ATTACHED_COMP; /
		3508	bios_5_scratch \|= RADEON_TV1_ON;
		3509	bios_5_scratch \|= RADEON_ACC_REQ_TV1;
		3510	} else {
1963	serge	3511	DRM_DEBUG_KMS("TV1 disconnected\n");
1123	serge	3512	bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
		3513	bios_5_scratch &= ~RADEON_TV1_ON;
		3514	bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
		3515	}
		3516	}
		3517	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		3518	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		3519	if (connected) {
1963	serge	3520	DRM_DEBUG_KMS("LCD1 connected\n");
1123	serge	3521	bios_4_scratch \|= RADEON_LCD1_ATTACHED;
		3522	bios_5_scratch \|= RADEON_LCD1_ON;
		3523	bios_5_scratch \|= RADEON_ACC_REQ_LCD1;
		3524	} else {
1963	serge	3525	DRM_DEBUG_KMS("LCD1 disconnected\n");
1123	serge	3526	bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
		3527	bios_5_scratch &= ~RADEON_LCD1_ON;
		3528	bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
		3529	}
		3530	}
		3531	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		3532	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		3533	if (connected) {
1963	serge	3534	DRM_DEBUG_KMS("CRT1 connected\n");
1123	serge	3535	bios_4_scratch \|= RADEON_CRT1_ATTACHED_COLOR;
		3536	bios_5_scratch \|= RADEON_CRT1_ON;
		3537	bios_5_scratch \|= RADEON_ACC_REQ_CRT1;
		3538	} else {
1963	serge	3539	DRM_DEBUG_KMS("CRT1 disconnected\n");
1123	serge	3540	bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
		3541	bios_5_scratch &= ~RADEON_CRT1_ON;
		3542	bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
		3543	}
		3544	}
		3545	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		3546	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		3547	if (connected) {
1963	serge	3548	DRM_DEBUG_KMS("CRT2 connected\n");
1123	serge	3549	bios_4_scratch \|= RADEON_CRT2_ATTACHED_COLOR;
		3550	bios_5_scratch \|= RADEON_CRT2_ON;
		3551	bios_5_scratch \|= RADEON_ACC_REQ_CRT2;
		3552	} else {
1963	serge	3553	DRM_DEBUG_KMS("CRT2 disconnected\n");
1123	serge	3554	bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
		3555	bios_5_scratch &= ~RADEON_CRT2_ON;
		3556	bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
		3557	}
		3558	}
		3559	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		3560	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		3561	if (connected) {
1963	serge	3562	DRM_DEBUG_KMS("DFP1 connected\n");
1123	serge	3563	bios_4_scratch \|= RADEON_DFP1_ATTACHED;
		3564	bios_5_scratch \|= RADEON_DFP1_ON;
		3565	bios_5_scratch \|= RADEON_ACC_REQ_DFP1;
		3566	} else {
1963	serge	3567	DRM_DEBUG_KMS("DFP1 disconnected\n");
1123	serge	3568	bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
		3569	bios_5_scratch &= ~RADEON_DFP1_ON;
		3570	bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
		3571	}
		3572	}
		3573	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		3574	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		3575	if (connected) {
1963	serge	3576	DRM_DEBUG_KMS("DFP2 connected\n");
1123	serge	3577	bios_4_scratch \|= RADEON_DFP2_ATTACHED;
		3578	bios_5_scratch \|= RADEON_DFP2_ON;
		3579	bios_5_scratch \|= RADEON_ACC_REQ_DFP2;
		3580	} else {
1963	serge	3581	DRM_DEBUG_KMS("DFP2 disconnected\n");
1123	serge	3582	bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
		3583	bios_5_scratch &= ~RADEON_DFP2_ON;
		3584	bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
		3585	}
		3586	}
		3587	WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
		3588	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3589	}
		3590
		3591	void
		3592	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		3593	{
		3594	struct drm_device *dev = encoder->dev;
		3595	struct radeon_device *rdev = dev->dev_private;
		3596	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3597	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		3598
		3599	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		3600	bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
		3601	bios_5_scratch \|= (crtc << RADEON_TV1_CRTC_SHIFT);
		3602	}
		3603	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		3604	bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
		3605	bios_5_scratch \|= (crtc << RADEON_CRT1_CRTC_SHIFT);
		3606	}
		3607	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		3608	bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
		3609	bios_5_scratch \|= (crtc << RADEON_CRT2_CRTC_SHIFT);
		3610	}
		3611	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		3612	bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
		3613	bios_5_scratch \|= (crtc << RADEON_LCD1_CRTC_SHIFT);
		3614	}
		3615	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		3616	bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
		3617	bios_5_scratch \|= (crtc << RADEON_DFP1_CRTC_SHIFT);
		3618	}
		3619	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		3620	bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
		3621	bios_5_scratch \|= (crtc << RADEON_DFP2_CRTC_SHIFT);
		3622	}
		3623	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3624	}
		3625
		3626	void
		3627	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		3628	{
		3629	struct drm_device *dev = encoder->dev;
		3630	struct radeon_device *rdev = dev->dev_private;
		3631	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3632	uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3633
		3634	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
		3635	if (on)
		3636	bios_6_scratch \|= RADEON_TV_DPMS_ON;
		3637	else
		3638	bios_6_scratch &= ~RADEON_TV_DPMS_ON;
		3639	}
		3640	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
		3641	if (on)
		3642	bios_6_scratch \|= RADEON_CRT_DPMS_ON;
		3643	else
		3644	bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
		3645	}
		3646	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		3647	if (on)
		3648	bios_6_scratch \|= RADEON_LCD_DPMS_ON;
		3649	else
		3650	bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
		3651	}
		3652	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		3653	if (on)
		3654	bios_6_scratch \|= RADEON_DFP_DPMS_ON;
		3655	else
		3656	bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
		3657	}
		3658	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3659	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_combios.c – Rev 3192