WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_combios.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2004 ATI Technologies Inc., Markham, Ontario
		3	* Copyright 2007-8 Advanced Micro Devices, Inc.
		4	* Copyright 2008 Red Hat Inc.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	*/
		27	#include "drmP.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	#ifdef CONFIG_PPC_PMAC
		33	/* not sure which of these are needed */
		34	#include
		35	#include
		36	#include
		37	#include
		38	#endif /* CONFIG_PPC_PMAC */
		39
		40	/* from radeon_encoder.c */
		41	extern uint32_t
		42	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		43	uint8_t dac);
		44	extern void radeon_link_encoder_connector(struct drm_device *dev);
		45
		46	/* from radeon_connector.c */
		47	extern void
		48	radeon_add_legacy_connector(struct drm_device *dev,
		49	uint32_t connector_id,
		50	uint32_t supported_device,
		51	int connector_type,
1268	serge	52	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	53	uint16_t connector_object_id,
		54	struct radeon_hpd *hpd);
1123	serge	55
		56	/* from radeon_legacy_encoder.c */
		57	extern void
		58	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		59	uint32_t supported_device);
		60
		61	/* old legacy ATI BIOS routines */
		62
		63	/* COMBIOS table offsets */
		64	enum radeon_combios_table_offset {
		65	/* absolute offset tables */
		66	COMBIOS_ASIC_INIT_1_TABLE,
		67	COMBIOS_BIOS_SUPPORT_TABLE,
		68	COMBIOS_DAC_PROGRAMMING_TABLE,
		69	COMBIOS_MAX_COLOR_DEPTH_TABLE,
		70	COMBIOS_CRTC_INFO_TABLE,
		71	COMBIOS_PLL_INFO_TABLE,
		72	COMBIOS_TV_INFO_TABLE,
		73	COMBIOS_DFP_INFO_TABLE,
		74	COMBIOS_HW_CONFIG_INFO_TABLE,
		75	COMBIOS_MULTIMEDIA_INFO_TABLE,
		76	COMBIOS_TV_STD_PATCH_TABLE,
		77	COMBIOS_LCD_INFO_TABLE,
		78	COMBIOS_MOBILE_INFO_TABLE,
		79	COMBIOS_PLL_INIT_TABLE,
		80	COMBIOS_MEM_CONFIG_TABLE,
		81	COMBIOS_SAVE_MASK_TABLE,
		82	COMBIOS_HARDCODED_EDID_TABLE,
		83	COMBIOS_ASIC_INIT_2_TABLE,
		84	COMBIOS_CONNECTOR_INFO_TABLE,
		85	COMBIOS_DYN_CLK_1_TABLE,
		86	COMBIOS_RESERVED_MEM_TABLE,
		87	COMBIOS_EXT_TMDS_INFO_TABLE,
		88	COMBIOS_MEM_CLK_INFO_TABLE,
		89	COMBIOS_EXT_DAC_INFO_TABLE,
		90	COMBIOS_MISC_INFO_TABLE,
		91	COMBIOS_CRT_INFO_TABLE,
		92	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
		93	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
		94	COMBIOS_FAN_SPEED_INFO_TABLE,
		95	COMBIOS_OVERDRIVE_INFO_TABLE,
		96	COMBIOS_OEM_INFO_TABLE,
		97	COMBIOS_DYN_CLK_2_TABLE,
		98	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
		99	COMBIOS_I2C_INFO_TABLE,
		100	/* relative offset tables */
		101	COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
		102	COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
		103	COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
		104	COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
		105	COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
		106	COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
		107	COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
		108	COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
		109	COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
		110	COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
		111	COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
		112	};
		113
		114	enum radeon_combios_ddc {
		115	DDC_NONE_DETECTED,
		116	DDC_MONID,
		117	DDC_DVI,
		118	DDC_VGA,
		119	DDC_CRT2,
		120	DDC_LCD,
		121	DDC_GPIO,
		122	};
		123
		124	enum radeon_combios_connector {
		125	CONNECTOR_NONE_LEGACY,
		126	CONNECTOR_PROPRIETARY_LEGACY,
		127	CONNECTOR_CRT_LEGACY,
		128	CONNECTOR_DVI_I_LEGACY,
		129	CONNECTOR_DVI_D_LEGACY,
		130	CONNECTOR_CTV_LEGACY,
		131	CONNECTOR_STV_LEGACY,
		132	CONNECTOR_UNSUPPORTED_LEGACY
		133	};
		134
		135	const int legacy_connector_convert[] = {
		136	DRM_MODE_CONNECTOR_Unknown,
		137	DRM_MODE_CONNECTOR_DVID,
		138	DRM_MODE_CONNECTOR_VGA,
		139	DRM_MODE_CONNECTOR_DVII,
		140	DRM_MODE_CONNECTOR_DVID,
		141	DRM_MODE_CONNECTOR_Composite,
		142	DRM_MODE_CONNECTOR_SVIDEO,
		143	DRM_MODE_CONNECTOR_Unknown,
		144	};
		145
		146	static uint16_t combios_get_table_offset(struct drm_device *dev,
		147	enum radeon_combios_table_offset table)
		148	{
		149	struct radeon_device *rdev = dev->dev_private;
		150	int rev;
		151	uint16_t offset = 0, check_offset;
		152
		153	switch (table) {
		154	/* absolute offset tables */
		155	case COMBIOS_ASIC_INIT_1_TABLE:
		156	check_offset = RBIOS16(rdev->bios_header_start + 0xc);
		157	if (check_offset)
		158	offset = check_offset;
		159	break;
		160	case COMBIOS_BIOS_SUPPORT_TABLE:
		161	check_offset = RBIOS16(rdev->bios_header_start + 0x14);
		162	if (check_offset)
		163	offset = check_offset;
		164	break;
		165	case COMBIOS_DAC_PROGRAMMING_TABLE:
		166	check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
		167	if (check_offset)
		168	offset = check_offset;
		169	break;
		170	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		171	check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
		172	if (check_offset)
		173	offset = check_offset;
		174	break;
		175	case COMBIOS_CRTC_INFO_TABLE:
		176	check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
		177	if (check_offset)
		178	offset = check_offset;
		179	break;
		180	case COMBIOS_PLL_INFO_TABLE:
		181	check_offset = RBIOS16(rdev->bios_header_start + 0x30);
		182	if (check_offset)
		183	offset = check_offset;
		184	break;
		185	case COMBIOS_TV_INFO_TABLE:
		186	check_offset = RBIOS16(rdev->bios_header_start + 0x32);
		187	if (check_offset)
		188	offset = check_offset;
		189	break;
		190	case COMBIOS_DFP_INFO_TABLE:
		191	check_offset = RBIOS16(rdev->bios_header_start + 0x34);
		192	if (check_offset)
		193	offset = check_offset;
		194	break;
		195	case COMBIOS_HW_CONFIG_INFO_TABLE:
		196	check_offset = RBIOS16(rdev->bios_header_start + 0x36);
		197	if (check_offset)
		198	offset = check_offset;
		199	break;
		200	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		201	check_offset = RBIOS16(rdev->bios_header_start + 0x38);
		202	if (check_offset)
		203	offset = check_offset;
		204	break;
		205	case COMBIOS_TV_STD_PATCH_TABLE:
		206	check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
		207	if (check_offset)
		208	offset = check_offset;
		209	break;
		210	case COMBIOS_LCD_INFO_TABLE:
		211	check_offset = RBIOS16(rdev->bios_header_start + 0x40);
		212	if (check_offset)
		213	offset = check_offset;
		214	break;
		215	case COMBIOS_MOBILE_INFO_TABLE:
		216	check_offset = RBIOS16(rdev->bios_header_start + 0x42);
		217	if (check_offset)
		218	offset = check_offset;
		219	break;
		220	case COMBIOS_PLL_INIT_TABLE:
		221	check_offset = RBIOS16(rdev->bios_header_start + 0x46);
		222	if (check_offset)
		223	offset = check_offset;
		224	break;
		225	case COMBIOS_MEM_CONFIG_TABLE:
		226	check_offset = RBIOS16(rdev->bios_header_start + 0x48);
		227	if (check_offset)
		228	offset = check_offset;
		229	break;
		230	case COMBIOS_SAVE_MASK_TABLE:
		231	check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
		232	if (check_offset)
		233	offset = check_offset;
		234	break;
		235	case COMBIOS_HARDCODED_EDID_TABLE:
		236	check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
		237	if (check_offset)
		238	offset = check_offset;
		239	break;
		240	case COMBIOS_ASIC_INIT_2_TABLE:
		241	check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
		242	if (check_offset)
		243	offset = check_offset;
		244	break;
		245	case COMBIOS_CONNECTOR_INFO_TABLE:
		246	check_offset = RBIOS16(rdev->bios_header_start + 0x50);
		247	if (check_offset)
		248	offset = check_offset;
		249	break;
		250	case COMBIOS_DYN_CLK_1_TABLE:
		251	check_offset = RBIOS16(rdev->bios_header_start + 0x52);
		252	if (check_offset)
		253	offset = check_offset;
		254	break;
		255	case COMBIOS_RESERVED_MEM_TABLE:
		256	check_offset = RBIOS16(rdev->bios_header_start + 0x54);
		257	if (check_offset)
		258	offset = check_offset;
		259	break;
		260	case COMBIOS_EXT_TMDS_INFO_TABLE:
		261	check_offset = RBIOS16(rdev->bios_header_start + 0x58);
		262	if (check_offset)
		263	offset = check_offset;
		264	break;
		265	case COMBIOS_MEM_CLK_INFO_TABLE:
		266	check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
		267	if (check_offset)
		268	offset = check_offset;
		269	break;
		270	case COMBIOS_EXT_DAC_INFO_TABLE:
		271	check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
		272	if (check_offset)
		273	offset = check_offset;
		274	break;
		275	case COMBIOS_MISC_INFO_TABLE:
		276	check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
		277	if (check_offset)
		278	offset = check_offset;
		279	break;
		280	case COMBIOS_CRT_INFO_TABLE:
		281	check_offset = RBIOS16(rdev->bios_header_start + 0x60);
		282	if (check_offset)
		283	offset = check_offset;
		284	break;
		285	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		286	check_offset = RBIOS16(rdev->bios_header_start + 0x62);
		287	if (check_offset)
		288	offset = check_offset;
		289	break;
		290	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		291	check_offset = RBIOS16(rdev->bios_header_start + 0x64);
		292	if (check_offset)
		293	offset = check_offset;
		294	break;
		295	case COMBIOS_FAN_SPEED_INFO_TABLE:
		296	check_offset = RBIOS16(rdev->bios_header_start + 0x66);
		297	if (check_offset)
		298	offset = check_offset;
		299	break;
		300	case COMBIOS_OVERDRIVE_INFO_TABLE:
		301	check_offset = RBIOS16(rdev->bios_header_start + 0x68);
		302	if (check_offset)
		303	offset = check_offset;
		304	break;
		305	case COMBIOS_OEM_INFO_TABLE:
		306	check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
		307	if (check_offset)
		308	offset = check_offset;
		309	break;
		310	case COMBIOS_DYN_CLK_2_TABLE:
		311	check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
		312	if (check_offset)
		313	offset = check_offset;
		314	break;
		315	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		316	check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
		317	if (check_offset)
		318	offset = check_offset;
		319	break;
		320	case COMBIOS_I2C_INFO_TABLE:
		321	check_offset = RBIOS16(rdev->bios_header_start + 0x70);
		322	if (check_offset)
		323	offset = check_offset;
		324	break;
		325	/* relative offset tables */
		326	case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
		327	check_offset =
		328	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		329	if (check_offset) {
		330	rev = RBIOS8(check_offset);
		331	if (rev > 0) {
		332	check_offset = RBIOS16(check_offset + 0x3);
		333	if (check_offset)
		334	offset = check_offset;
		335	}
		336	}
		337	break;
		338	case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
		339	check_offset =
		340	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		341	if (check_offset) {
		342	rev = RBIOS8(check_offset);
		343	if (rev > 0) {
		344	check_offset = RBIOS16(check_offset + 0x5);
		345	if (check_offset)
		346	offset = check_offset;
		347	}
		348	}
		349	break;
		350	case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
		351	check_offset =
		352	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		353	if (check_offset) {
		354	rev = RBIOS8(check_offset);
		355	if (rev > 0) {
		356	check_offset = RBIOS16(check_offset + 0x7);
		357	if (check_offset)
		358	offset = check_offset;
		359	}
		360	}
		361	break;
		362	case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
		363	check_offset =
		364	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		365	if (check_offset) {
		366	rev = RBIOS8(check_offset);
		367	if (rev == 2) {
		368	check_offset = RBIOS16(check_offset + 0x9);
		369	if (check_offset)
		370	offset = check_offset;
		371	}
		372	}
		373	break;
		374	case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
		375	check_offset =
		376	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		377	if (check_offset) {
		378	while (RBIOS8(check_offset++));
		379	check_offset += 2;
		380	if (check_offset)
		381	offset = check_offset;
		382	}
		383	break;
		384	case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
		385	check_offset =
		386	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		387	if (check_offset) {
		388	check_offset = RBIOS16(check_offset + 0x11);
		389	if (check_offset)
		390	offset = check_offset;
		391	}
		392	break;
		393	case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
		394	check_offset =
		395	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		396	if (check_offset) {
		397	check_offset = RBIOS16(check_offset + 0x13);
		398	if (check_offset)
		399	offset = check_offset;
		400	}
		401	break;
		402	case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
		403	check_offset =
		404	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		405	if (check_offset) {
		406	check_offset = RBIOS16(check_offset + 0x15);
		407	if (check_offset)
		408	offset = check_offset;
		409	}
		410	break;
		411	case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
		412	check_offset =
		413	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		414	if (check_offset) {
		415	check_offset = RBIOS16(check_offset + 0x17);
		416	if (check_offset)
		417	offset = check_offset;
		418	}
		419	break;
		420	case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
		421	check_offset =
		422	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		423	if (check_offset) {
		424	check_offset = RBIOS16(check_offset + 0x2);
		425	if (check_offset)
		426	offset = check_offset;
		427	}
		428	break;
		429	case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
		430	check_offset =
		431	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		432	if (check_offset) {
		433	check_offset = RBIOS16(check_offset + 0x4);
		434	if (check_offset)
		435	offset = check_offset;
		436	}
		437	break;
		438	default:
		439	break;
		440	}
		441
		442	return offset;
		443
		444	}
		445
1321	serge	446	static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
		447	int ddc_line)
1123	serge	448	{
		449	struct radeon_i2c_bus_rec i2c;
		450
1321	serge	451	if (ddc_line == RADEON_GPIOPAD_MASK) {
		452	i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
		453	i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
		454	i2c.a_clk_reg = RADEON_GPIOPAD_A;
		455	i2c.a_data_reg = RADEON_GPIOPAD_A;
		456	i2c.en_clk_reg = RADEON_GPIOPAD_EN;
		457	i2c.en_data_reg = RADEON_GPIOPAD_EN;
		458	i2c.y_clk_reg = RADEON_GPIOPAD_Y;
		459	i2c.y_data_reg = RADEON_GPIOPAD_Y;
		460	} else if (ddc_line == RADEON_MDGPIO_MASK) {
		461	i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
		462	i2c.mask_data_reg = RADEON_MDGPIO_MASK;
		463	i2c.a_clk_reg = RADEON_MDGPIO_A;
		464	i2c.a_data_reg = RADEON_MDGPIO_A;
		465	i2c.en_clk_reg = RADEON_MDGPIO_EN;
		466	i2c.en_data_reg = RADEON_MDGPIO_EN;
		467	i2c.y_clk_reg = RADEON_MDGPIO_Y;
		468	i2c.y_data_reg = RADEON_MDGPIO_Y;
		469	} else {
1123	serge	470	i2c.mask_clk_mask = RADEON_GPIO_EN_1;
		471	i2c.mask_data_mask = RADEON_GPIO_EN_0;
		472	i2c.a_clk_mask = RADEON_GPIO_A_1;
		473	i2c.a_data_mask = RADEON_GPIO_A_0;
1321	serge	474	i2c.en_clk_mask = RADEON_GPIO_EN_1;
		475	i2c.en_data_mask = RADEON_GPIO_EN_0;
		476	i2c.y_clk_mask = RADEON_GPIO_Y_1;
		477	i2c.y_data_mask = RADEON_GPIO_Y_0;
		478
1123	serge	479	i2c.mask_clk_reg = ddc_line;
		480	i2c.mask_data_reg = ddc_line;
		481	i2c.a_clk_reg = ddc_line;
		482	i2c.a_data_reg = ddc_line;
1321	serge	483	i2c.en_clk_reg = ddc_line;
		484	i2c.en_data_reg = ddc_line;
		485	i2c.y_clk_reg = ddc_line;
		486	i2c.y_data_reg = ddc_line;
1123	serge	487	}
		488
1321	serge	489	if (rdev->family < CHIP_R200)
		490	i2c.hw_capable = false;
		491	else {
		492	switch (ddc_line) {
		493	case RADEON_GPIO_VGA_DDC:
		494	case RADEON_GPIO_DVI_DDC:
		495	i2c.hw_capable = true;
		496	break;
		497	case RADEON_GPIO_MONID:
		498	/* hw i2c on RADEON_GPIO_MONID doesn't seem to work
		499	* reliably on some pre-r4xx hardware; not sure why.
		500	*/
		501	i2c.hw_capable = false;
		502	break;
		503	default:
		504	i2c.hw_capable = false;
		505	break;
		506	}
		507	}
		508	i2c.mm_i2c = false;
		509	i2c.i2c_id = 0;
		510
1123	serge	511	if (ddc_line)
		512	i2c.valid = true;
		513	else
		514	i2c.valid = false;
		515
		516	return i2c;
		517	}
		518
		519	bool radeon_combios_get_clock_info(struct drm_device *dev)
		520	{
		521	struct radeon_device *rdev = dev->dev_private;
		522	uint16_t pll_info;
		523	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		524	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		525	struct radeon_pll *spll = &rdev->clock.spll;
		526	struct radeon_pll *mpll = &rdev->clock.mpll;
		527	int8_t rev;
		528	uint16_t sclk, mclk;
		529
		530	if (rdev->bios == NULL)
1321	serge	531	return false;
1123	serge	532
		533	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
		534	if (pll_info) {
		535	rev = RBIOS8(pll_info);
		536
		537	/* pixel clocks */
		538	p1pll->reference_freq = RBIOS16(pll_info + 0xe);
		539	p1pll->reference_div = RBIOS16(pll_info + 0x10);
		540	p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
		541	p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
		542
		543	if (rev > 9) {
		544	p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
		545	p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
		546	} else {
		547	p1pll->pll_in_min = 40;
		548	p1pll->pll_in_max = 500;
		549	}
		550	p2pll = p1pll;
		551
		552	/* system clock */
		553	spll->reference_freq = RBIOS16(pll_info + 0x1a);
		554	spll->reference_div = RBIOS16(pll_info + 0x1c);
		555	spll->pll_out_min = RBIOS32(pll_info + 0x1e);
		556	spll->pll_out_max = RBIOS32(pll_info + 0x22);
		557
		558	if (rev > 10) {
		559	spll->pll_in_min = RBIOS32(pll_info + 0x48);
		560	spll->pll_in_max = RBIOS32(pll_info + 0x4c);
		561	} else {
		562	/* ??? */
		563	spll->pll_in_min = 40;
		564	spll->pll_in_max = 500;
		565	}
		566
		567	/* memory clock */
		568	mpll->reference_freq = RBIOS16(pll_info + 0x26);
		569	mpll->reference_div = RBIOS16(pll_info + 0x28);
		570	mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
		571	mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
		572
		573	if (rev > 10) {
		574	mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
		575	mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
		576	} else {
		577	/* ??? */
		578	mpll->pll_in_min = 40;
		579	mpll->pll_in_max = 500;
		580	}
		581
		582	/* default sclk/mclk */
		583	sclk = RBIOS16(pll_info + 0xa);
		584	mclk = RBIOS16(pll_info + 0x8);
		585	if (sclk == 0)
		586	sclk = 200 * 100;
		587	if (mclk == 0)
		588	mclk = 200 * 100;
		589
		590	rdev->clock.default_sclk = sclk;
		591	rdev->clock.default_mclk = mclk;
		592
		593	return true;
		594	}
		595	return false;
		596	}
		597
1404	serge	598	bool radeon_combios_sideport_present(struct radeon_device *rdev)
		599	{
		600	struct drm_device *dev = rdev->ddev;
		601	u16 igp_info;
		602
		603	igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
		604
		605	if (igp_info) {
		606	if (RBIOS16(igp_info + 0x4))
		607	return true;
		608	}
		609	return false;
		610	}
		611
		612	static const uint32_t default_primarydac_adj[CHIP_LAST] = {
		613	0x00000808, /* r100 */
		614	0x00000808, /* rv100 */
		615	0x00000808, /* rs100 */
		616	0x00000808, /* rv200 */
		617	0x00000808, /* rs200 */
		618	0x00000808, /* r200 */
		619	0x00000808, /* rv250 */
		620	0x00000000, /* rs300 */
		621	0x00000808, /* rv280 */
		622	0x00000808, /* r300 */
		623	0x00000808, /* r350 */
		624	0x00000808, /* rv350 */
		625	0x00000808, /* rv380 */
		626	0x00000808, /* r420 */
		627	0x00000808, /* r423 */
		628	0x00000808, /* rv410 */
		629	0x00000000, /* rs400 */
		630	0x00000000, /* rs480 */
		631	};
		632
		633	static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
		634	struct radeon_encoder_primary_dac *p_dac)
		635	{
		636	p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
		637	return;
		638	}
		639
1123	serge	640	struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
		641	radeon_encoder
		642	*encoder)
		643	{
		644	struct drm_device *dev = encoder->base.dev;
		645	struct radeon_device *rdev = dev->dev_private;
		646	uint16_t dac_info;
		647	uint8_t rev, bg, dac;
		648	struct radeon_encoder_primary_dac *p_dac = NULL;
1404	serge	649	int found = 0;
1123	serge	650
1404	serge	651	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
		652	GFP_KERNEL);
		653
		654	if (!p_dac)
1123	serge	655	return NULL;
		656
1404	serge	657	if (rdev->bios == NULL)
		658	goto out;
		659
1123	serge	660	/* check CRT table */
		661	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		662	if (dac_info) {
		663	rev = RBIOS8(dac_info) & 0x3;
		664	if (rev < 2) {
		665	bg = RBIOS8(dac_info + 0x2) & 0xf;
		666	dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
		667	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		668	} else {
		669	bg = RBIOS8(dac_info + 0x2) & 0xf;
		670	dac = RBIOS8(dac_info + 0x3) & 0xf;
		671	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		672	}
1404	serge	673	found = 1;
1123	serge	674	}
		675
1404	serge	676	out:
		677	if (!found) /* fallback to defaults */
		678	radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
		679
1123	serge	680	return p_dac;
		681	}
		682
1404	serge	683	enum radeon_tv_std
		684	radeon_combios_get_tv_info(struct radeon_device *rdev)
1123	serge	685	{
1404	serge	686	struct drm_device *dev = rdev->ddev;
1123	serge	687	uint16_t tv_info;
		688	enum radeon_tv_std tv_std = TV_STD_NTSC;
		689
1404	serge	690	if (rdev->bios == NULL)
		691	return tv_std;
		692
1123	serge	693	tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		694	if (tv_info) {
		695	if (RBIOS8(tv_info + 6) == 'T') {
		696	switch (RBIOS8(tv_info + 7) & 0xf) {
		697	case 1:
		698	tv_std = TV_STD_NTSC;
		699	DRM_INFO("Default TV standard: NTSC\n");
		700	break;
		701	case 2:
		702	tv_std = TV_STD_PAL;
		703	DRM_INFO("Default TV standard: PAL\n");
		704	break;
		705	case 3:
		706	tv_std = TV_STD_PAL_M;
		707	DRM_INFO("Default TV standard: PAL-M\n");
		708	break;
		709	case 4:
		710	tv_std = TV_STD_PAL_60;
		711	DRM_INFO("Default TV standard: PAL-60\n");
		712	break;
		713	case 5:
		714	tv_std = TV_STD_NTSC_J;
		715	DRM_INFO("Default TV standard: NTSC-J\n");
		716	break;
		717	case 6:
		718	tv_std = TV_STD_SCART_PAL;
		719	DRM_INFO("Default TV standard: SCART-PAL\n");
		720	break;
		721	default:
		722	tv_std = TV_STD_NTSC;
		723	DRM_INFO
		724	("Unknown TV standard; defaulting to NTSC\n");
		725	break;
		726	}
		727
		728	switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
		729	case 0:
		730	DRM_INFO("29.498928713 MHz TV ref clk\n");
		731	break;
		732	case 1:
		733	DRM_INFO("28.636360000 MHz TV ref clk\n");
		734	break;
		735	case 2:
		736	DRM_INFO("14.318180000 MHz TV ref clk\n");
		737	break;
		738	case 3:
		739	DRM_INFO("27.000000000 MHz TV ref clk\n");
		740	break;
		741	default:
		742	break;
		743	}
		744	}
		745	}
		746	return tv_std;
		747	}
		748
		749	static const uint32_t default_tvdac_adj[CHIP_LAST] = {
		750	0x00000000, /* r100 */
		751	0x00280000, /* rv100 */
		752	0x00000000, /* rs100 */
		753	0x00880000, /* rv200 */
		754	0x00000000, /* rs200 */
		755	0x00000000, /* r200 */
		756	0x00770000, /* rv250 */
		757	0x00290000, /* rs300 */
		758	0x00560000, /* rv280 */
		759	0x00780000, /* r300 */
		760	0x00770000, /* r350 */
		761	0x00780000, /* rv350 */
		762	0x00780000, /* rv380 */
		763	0x01080000, /* r420 */
		764	0x01080000, /* r423 */
		765	0x01080000, /* rv410 */
		766	0x00780000, /* rs400 */
		767	0x00780000, /* rs480 */
		768	};
		769
1179	serge	770	static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
		771	struct radeon_encoder_tv_dac *tv_dac)
1123	serge	772	{
		773	tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
		774	if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
		775	tv_dac->ps2_tvdac_adj = 0x00880000;
		776	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		777	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	778	return;
1123	serge	779	}
		780
		781	struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
		782	radeon_encoder
		783	*encoder)
		784	{
		785	struct drm_device *dev = encoder->base.dev;
		786	struct radeon_device *rdev = dev->dev_private;
		787	uint16_t dac_info;
		788	uint8_t rev, bg, dac;
		789	struct radeon_encoder_tv_dac *tv_dac = NULL;
1179	serge	790	int found = 0;
1123	serge	791
1179	serge	792	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		793	if (!tv_dac)
		794	return NULL;
		795
1123	serge	796	if (rdev->bios == NULL)
1179	serge	797	goto out;
1123	serge	798
		799	/* first check TV table */
		800	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		801	if (dac_info) {
		802	rev = RBIOS8(dac_info + 0x3);
		803	if (rev > 4) {
		804	bg = RBIOS8(dac_info + 0xc) & 0xf;
		805	dac = RBIOS8(dac_info + 0xd) & 0xf;
		806	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		807
		808	bg = RBIOS8(dac_info + 0xe) & 0xf;
		809	dac = RBIOS8(dac_info + 0xf) & 0xf;
		810	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		811
		812	bg = RBIOS8(dac_info + 0x10) & 0xf;
		813	dac = RBIOS8(dac_info + 0x11) & 0xf;
		814	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1179	serge	815	found = 1;
1123	serge	816	} else if (rev > 1) {
		817	bg = RBIOS8(dac_info + 0xc) & 0xf;
		818	dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
		819	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		820
		821	bg = RBIOS8(dac_info + 0xd) & 0xf;
		822	dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
		823	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		824
		825	bg = RBIOS8(dac_info + 0xe) & 0xf;
		826	dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
		827	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1179	serge	828	found = 1;
1123	serge	829	}
1404	serge	830	tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1179	serge	831	}
		832	if (!found) {
1123	serge	833	/* then check CRT table */
		834	dac_info =
		835	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		836	if (dac_info) {
		837	rev = RBIOS8(dac_info) & 0x3;
		838	if (rev < 2) {
		839	bg = RBIOS8(dac_info + 0x3) & 0xf;
		840	dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
		841	tv_dac->ps2_tvdac_adj =
		842	(bg << 16) \| (dac << 20);
		843	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		844	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	845	found = 1;
1123	serge	846	} else {
		847	bg = RBIOS8(dac_info + 0x4) & 0xf;
		848	dac = RBIOS8(dac_info + 0x5) & 0xf;
		849	tv_dac->ps2_tvdac_adj =
		850	(bg << 16) \| (dac << 20);
		851	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		852	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	853	found = 1;
1123	serge	854	}
		855	} else {
		856	DRM_INFO("No TV DAC info found in BIOS\n");
		857	}
		858	}
1221	serge	859
1179	serge	860	out:
		861	if (!found) /* fallback to defaults */
		862	radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1123	serge	863
		864	return tv_dac;
		865	}
		866
		867	static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
		868	radeon_device
		869	*rdev)
		870	{
		871	struct radeon_encoder_lvds *lvds = NULL;
		872	uint32_t fp_vert_stretch, fp_horz_stretch;
		873	uint32_t ppll_div_sel, ppll_val;
		874	uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		875
		876	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		877
		878	if (!lvds)
		879	return NULL;
		880
		881	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
		882	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
		883
		884	/* These should be fail-safe defaults, fingers crossed */
		885	lvds->panel_pwr_delay = 200;
		886	lvds->panel_vcc_delay = 2000;
		887
		888	lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		889	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
		890	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
		891
		892	if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1268	serge	893	lvds->native_mode.vdisplay =
1123	serge	894	((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
		895	RADEON_VERT_PANEL_SHIFT) + 1;
		896	else
1268	serge	897	lvds->native_mode.vdisplay =
1123	serge	898	(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
		899
		900	if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1268	serge	901	lvds->native_mode.hdisplay =
1123	serge	902	(((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
		903	RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
		904	else
1268	serge	905	lvds->native_mode.hdisplay =
1123	serge	906	((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
		907
1268	serge	908	if ((lvds->native_mode.hdisplay < 640) \|\|
		909	(lvds->native_mode.vdisplay < 480)) {
		910	lvds->native_mode.hdisplay = 640;
		911	lvds->native_mode.vdisplay = 480;
1123	serge	912	}
		913
		914	ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
		915	ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
		916	if ((ppll_val & 0x000707ff) == 0x1bb)
		917	lvds->use_bios_dividers = false;
		918	else {
		919	lvds->panel_ref_divider =
		920	RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
		921	lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
		922	lvds->panel_fb_divider = ppll_val & 0x7ff;
		923
		924	if ((lvds->panel_ref_divider != 0) &&
		925	(lvds->panel_fb_divider > 3))
		926	lvds->use_bios_dividers = true;
		927	}
		928	lvds->panel_vcc_delay = 200;
		929
		930	DRM_INFO("Panel info derived from registers\n");
1268	serge	931	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		932	lvds->native_mode.vdisplay);
1123	serge	933
		934	return lvds;
		935	}
		936
		937	struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
		938	*encoder)
		939	{
		940	struct drm_device *dev = encoder->base.dev;
		941	struct radeon_device *rdev = dev->dev_private;
		942	uint16_t lcd_info;
		943	uint32_t panel_setup;
		944	char stmp[30];
		945	int tmp, i;
		946	struct radeon_encoder_lvds *lvds = NULL;
		947
1179	serge	948	if (rdev->bios == NULL) {
		949	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
		950	goto out;
		951	}
1123	serge	952
		953	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		954
		955	if (lcd_info) {
		956	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		957
		958	if (!lvds)
		959	return NULL;
		960
		961	for (i = 0; i < 24; i++)
		962	stmp[i] = RBIOS8(lcd_info + i + 1);
		963	stmp[24] = 0;
		964
		965	DRM_INFO("Panel ID String: %s\n", stmp);
		966
1268	serge	967	lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
		968	lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1123	serge	969
1268	serge	970	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		971	lvds->native_mode.vdisplay);
1123	serge	972
		973	lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1404	serge	974	lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1123	serge	975
		976	lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
		977	lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
		978	lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
		979
		980	lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
		981	lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
		982	lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
		983	if ((lvds->panel_ref_divider != 0) &&
		984	(lvds->panel_fb_divider > 3))
		985	lvds->use_bios_dividers = true;
		986
		987	panel_setup = RBIOS32(lcd_info + 0x39);
		988	lvds->lvds_gen_cntl = 0xff00;
		989	if (panel_setup & 0x1)
		990	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_FORMAT;
		991
		992	if ((panel_setup >> 4) & 0x1)
		993	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_TYPE;
		994
		995	switch ((panel_setup >> 8) & 0x7) {
		996	case 0:
		997	lvds->lvds_gen_cntl \|= RADEON_LVDS_NO_FM;
		998	break;
		999	case 1:
		1000	lvds->lvds_gen_cntl \|= RADEON_LVDS_2_GREY;
		1001	break;
		1002	case 2:
		1003	lvds->lvds_gen_cntl \|= RADEON_LVDS_4_GREY;
		1004	break;
		1005	default:
		1006	break;
		1007	}
		1008
		1009	if ((panel_setup >> 16) & 0x1)
		1010	lvds->lvds_gen_cntl \|= RADEON_LVDS_FP_POL_LOW;
		1011
		1012	if ((panel_setup >> 17) & 0x1)
		1013	lvds->lvds_gen_cntl \|= RADEON_LVDS_LP_POL_LOW;
		1014
		1015	if ((panel_setup >> 18) & 0x1)
		1016	lvds->lvds_gen_cntl \|= RADEON_LVDS_DTM_POL_LOW;
		1017
		1018	if ((panel_setup >> 23) & 0x1)
		1019	lvds->lvds_gen_cntl \|= RADEON_LVDS_BL_CLK_SEL;
		1020
		1021	lvds->lvds_gen_cntl \|= (panel_setup & 0xf0000000);
		1022
		1023	for (i = 0; i < 32; i++) {
		1024	tmp = RBIOS16(lcd_info + 64 + i * 2);
		1025	if (tmp == 0)
		1026	break;
		1027
1268	serge	1028	if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1123	serge	1029	(RBIOS16(tmp + 2) ==
1268	serge	1030	lvds->native_mode.vdisplay)) {
		1031	lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
		1032	lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
		1033	lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
		1034	RBIOS16(tmp + 21)) * 8;
1123	serge	1035
1268	serge	1036	lvds->native_mode.vtotal = RBIOS16(tmp + 24);
		1037	lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
		1038	lvds->native_mode.vsync_end =
		1039	((RBIOS16(tmp + 28) & 0xf800) >> 11) +
		1040	(RBIOS16(tmp + 28) & 0x7ff);
		1041
		1042	lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1123	serge	1043	lvds->native_mode.flags = 0;
1268	serge	1044	/* set crtc values */
		1045	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
		1046
1123	serge	1047	}
		1048	}
		1049	} else {
		1050	DRM_INFO("No panel info found in BIOS\n");
1179	serge	1051	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1123	serge	1052	}
1179	serge	1053	out:
		1054	if (lvds)
		1055	encoder->native_mode = lvds->native_mode;
1123	serge	1056	return lvds;
		1057	}
		1058
		1059	static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
		1060	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
		1061	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
		1062	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
		1063	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
		1064	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
		1065	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
		1066	{{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
		1067	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
		1068	{{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
		1069	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
		1070	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
		1071	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
		1072	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
		1073	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
		1074	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
		1075	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1321	serge	1076	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
		1077	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1123	serge	1078	};
		1079
1179	serge	1080	bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
		1081	struct radeon_encoder_int_tmds *tmds)
1123	serge	1082	{
1179	serge	1083	struct drm_device *dev = encoder->base.dev;
		1084	struct radeon_device *rdev = dev->dev_private;
1123	serge	1085	int i;
		1086
		1087	for (i = 0; i < 4; i++) {
		1088	tmds->tmds_pll[i].value =
		1089	default_tmds_pll[rdev->family][i].value;
		1090	tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
		1091	}
		1092
1179	serge	1093	return true;
1123	serge	1094	}
		1095
1179	serge	1096	bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
		1097	struct radeon_encoder_int_tmds *tmds)
1123	serge	1098	{
		1099	struct drm_device *dev = encoder->base.dev;
		1100	struct radeon_device *rdev = dev->dev_private;
		1101	uint16_t tmds_info;
		1102	int i, n;
		1103	uint8_t ver;
		1104
		1105	if (rdev->bios == NULL)
1179	serge	1106	return false;
1123	serge	1107
		1108	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		1109
		1110	if (tmds_info) {
		1111	ver = RBIOS8(tmds_info);
		1112	DRM_INFO("DFP table revision: %d\n", ver);
		1113	if (ver == 3) {
		1114	n = RBIOS8(tmds_info + 5) + 1;
		1115	if (n > 4)
		1116	n = 4;
		1117	for (i = 0; i < n; i++) {
		1118	tmds->tmds_pll[i].value =
		1119	RBIOS32(tmds_info + i * 10 + 0x08);
		1120	tmds->tmds_pll[i].freq =
		1121	RBIOS16(tmds_info + i * 10 + 0x10);
		1122	DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
		1123	tmds->tmds_pll[i].freq,
		1124	tmds->tmds_pll[i].value);
		1125	}
		1126	} else if (ver == 4) {
		1127	int stride = 0;
		1128	n = RBIOS8(tmds_info + 5) + 1;
		1129	if (n > 4)
		1130	n = 4;
		1131	for (i = 0; i < n; i++) {
		1132	tmds->tmds_pll[i].value =
		1133	RBIOS32(tmds_info + stride + 0x08);
		1134	tmds->tmds_pll[i].freq =
		1135	RBIOS16(tmds_info + stride + 0x10);
		1136	if (i == 0)
		1137	stride += 10;
		1138	else
		1139	stride += 6;
		1140	DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
		1141	tmds->tmds_pll[i].freq,
		1142	tmds->tmds_pll[i].value);
		1143	}
		1144	}
1321	serge	1145	} else {
1123	serge	1146	DRM_INFO("No TMDS info found in BIOS\n");
1321	serge	1147	return false;
		1148	}
1179	serge	1149	return true;
		1150	}
		1151
1321	serge	1152	bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
		1153	struct radeon_encoder_ext_tmds *tmds)
1179	serge	1154	{
1321	serge	1155	struct drm_device *dev = encoder->base.dev;
		1156	struct radeon_device *rdev = dev->dev_private;
		1157	struct radeon_i2c_bus_rec i2c_bus;
1179	serge	1158
1321	serge	1159	/* default for macs */
		1160	i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
		1161	tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1179	serge	1162
1321	serge	1163	/* XXX some macs have duallink chips */
		1164	switch (rdev->mode_info.connector_table) {
		1165	case CT_POWERBOOK_EXTERNAL:
		1166	case CT_MINI_EXTERNAL:
		1167	default:
		1168	tmds->dvo_chip = DVO_SIL164;
		1169	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1170	break;
		1171	}
1179	serge	1172
1321	serge	1173	return true;
1123	serge	1174	}
		1175
1321	serge	1176	bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
		1177	struct radeon_encoder_ext_tmds *tmds)
1123	serge	1178	{
		1179	struct drm_device *dev = encoder->base.dev;
		1180	struct radeon_device *rdev = dev->dev_private;
1321	serge	1181	uint16_t offset;
		1182	uint8_t ver, id, blocks, clk, data;
		1183	int i;
		1184	enum radeon_combios_ddc gpio;
		1185	struct radeon_i2c_bus_rec i2c_bus;
1123	serge	1186
		1187	if (rdev->bios == NULL)
1321	serge	1188	return false;
1123	serge	1189
1321	serge	1190	tmds->i2c_bus = NULL;
		1191	if (rdev->flags & RADEON_IS_IGP) {
		1192	offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
		1193	if (offset) {
		1194	ver = RBIOS8(offset);
		1195	DRM_INFO("GPIO Table revision: %d\n", ver);
		1196	blocks = RBIOS8(offset + 2);
		1197	for (i = 0; i < blocks; i++) {
		1198	id = RBIOS8(offset + 3 + (i * 5) + 0);
		1199	if (id == 136) {
		1200	clk = RBIOS8(offset + 3 + (i * 5) + 3);
		1201	data = RBIOS8(offset + 3 + (i * 5) + 4);
		1202	i2c_bus.valid = true;
		1203	i2c_bus.mask_clk_mask = (1 << clk);
		1204	i2c_bus.mask_data_mask = (1 << data);
		1205	i2c_bus.a_clk_mask = (1 << clk);
		1206	i2c_bus.a_data_mask = (1 << data);
		1207	i2c_bus.en_clk_mask = (1 << clk);
		1208	i2c_bus.en_data_mask = (1 << data);
		1209	i2c_bus.y_clk_mask = (1 << clk);
		1210	i2c_bus.y_data_mask = (1 << data);
		1211	i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
		1212	i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
		1213	i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
		1214	i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
		1215	i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
		1216	i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
		1217	i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
		1218	i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
		1219	tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
		1220	tmds->dvo_chip = DVO_SIL164;
		1221	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1222	break;
		1223	}
		1224	}
		1225	}
		1226	} else {
		1227	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		1228	if (offset) {
		1229	ver = RBIOS8(offset);
1123	serge	1230	DRM_INFO("External TMDS Table revision: %d\n", ver);
1321	serge	1231	tmds->slave_addr = RBIOS8(offset + 4 + 2);
		1232	tmds->slave_addr >>= 1; /* 7 bit addressing */
		1233	gpio = RBIOS8(offset + 4 + 3);
		1234	switch (gpio) {
		1235	case DDC_MONID:
		1236	i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
		1237	tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
		1238	break;
		1239	case DDC_DVI:
		1240	i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1241	tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
		1242	break;
		1243	case DDC_VGA:
		1244	i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1245	tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
		1246	break;
		1247	case DDC_CRT2:
		1248	/* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
		1249	if (rdev->family >= CHIP_R300)
		1250	i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
		1251	else
		1252	i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
		1253	tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
		1254	break;
		1255	case DDC_LCD: /* MM i2c */
		1256	DRM_ERROR("MM i2c requires hw i2c engine\n");
		1257	break;
		1258	default:
		1259	DRM_ERROR("Unsupported gpio %d\n", gpio);
		1260	break;
1404	serge	1261	}
1321	serge	1262	}
		1263	}
		1264
		1265	if (!tmds->i2c_bus) {
		1266	DRM_INFO("No valid Ext TMDS info found in BIOS\n");
		1267	return false;
		1268	}
		1269
		1270	return true;
1123	serge	1271	}
		1272
		1273	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
		1274	{
		1275	struct radeon_device *rdev = dev->dev_private;
		1276	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	1277	struct radeon_hpd hpd;
1123	serge	1278
		1279	rdev->mode_info.connector_table = radeon_connector_table;
		1280	if (rdev->mode_info.connector_table == CT_NONE) {
		1281	#ifdef CONFIG_PPC_PMAC
		1282	if (machine_is_compatible("PowerBook3,3")) {
		1283	/* powerbook with VGA */
		1284	rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
		1285	} else if (machine_is_compatible("PowerBook3,4") \|\|
		1286	machine_is_compatible("PowerBook3,5")) {
		1287	/* powerbook with internal tmds */
		1288	rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
		1289	} else if (machine_is_compatible("PowerBook5,1") \|\|
		1290	machine_is_compatible("PowerBook5,2") \|\|
		1291	machine_is_compatible("PowerBook5,3") \|\|
		1292	machine_is_compatible("PowerBook5,4") \|\|
		1293	machine_is_compatible("PowerBook5,5")) {
		1294	/* powerbook with external single link tmds (sil164) */
		1295	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
		1296	} else if (machine_is_compatible("PowerBook5,6")) {
		1297	/* powerbook with external dual or single link tmds */
		1298	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
		1299	} else if (machine_is_compatible("PowerBook5,7") \|\|
		1300	machine_is_compatible("PowerBook5,8") \|\|
		1301	machine_is_compatible("PowerBook5,9")) {
		1302	/* PowerBook6,2 ? */
		1303	/* powerbook with external dual link tmds (sil1178?) */
		1304	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
		1305	} else if (machine_is_compatible("PowerBook4,1") \|\|
		1306	machine_is_compatible("PowerBook4,2") \|\|
		1307	machine_is_compatible("PowerBook4,3") \|\|
		1308	machine_is_compatible("PowerBook6,3") \|\|
		1309	machine_is_compatible("PowerBook6,5") \|\|
		1310	machine_is_compatible("PowerBook6,7")) {
		1311	/* ibook */
		1312	rdev->mode_info.connector_table = CT_IBOOK;
		1313	} else if (machine_is_compatible("PowerMac4,4")) {
		1314	/* emac */
		1315	rdev->mode_info.connector_table = CT_EMAC;
		1316	} else if (machine_is_compatible("PowerMac10,1")) {
		1317	/* mini with internal tmds */
		1318	rdev->mode_info.connector_table = CT_MINI_INTERNAL;
		1319	} else if (machine_is_compatible("PowerMac10,2")) {
		1320	/* mini with external tmds */
		1321	rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
		1322	} else if (machine_is_compatible("PowerMac12,1")) {
		1323	/* PowerMac8,1 ? */
		1324	/* imac g5 isight */
		1325	rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
		1326	} else
		1327	#endif /* CONFIG_PPC_PMAC */
		1328	rdev->mode_info.connector_table = CT_GENERIC;
		1329	}
		1330
		1331	switch (rdev->mode_info.connector_table) {
		1332	case CT_GENERIC:
		1333	DRM_INFO("Connector Table: %d (generic)\n",
		1334	rdev->mode_info.connector_table);
		1335	/* these are the most common settings */
		1336	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1337	/* VGA - primary dac */
1321	serge	1338	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1339	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1340	radeon_add_legacy_encoder(dev,
		1341	radeon_get_encoder_id(dev,
		1342	ATOM_DEVICE_CRT1_SUPPORT,
		1343	1),
		1344	ATOM_DEVICE_CRT1_SUPPORT);
		1345	radeon_add_legacy_connector(dev, 0,
		1346	ATOM_DEVICE_CRT1_SUPPORT,
		1347	DRM_MODE_CONNECTOR_VGA,
1268	serge	1348	&ddc_i2c,
1321	serge	1349	CONNECTOR_OBJECT_ID_VGA,
		1350	&hpd);
1123	serge	1351	} else if (rdev->flags & RADEON_IS_MOBILITY) {
		1352	/* LVDS */
1321	serge	1353	ddc_i2c = combios_setup_i2c_bus(rdev, 0);
		1354	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1355	radeon_add_legacy_encoder(dev,
		1356	radeon_get_encoder_id(dev,
		1357	ATOM_DEVICE_LCD1_SUPPORT,
		1358	0),
		1359	ATOM_DEVICE_LCD1_SUPPORT);
		1360	radeon_add_legacy_connector(dev, 0,
		1361	ATOM_DEVICE_LCD1_SUPPORT,
		1362	DRM_MODE_CONNECTOR_LVDS,
1268	serge	1363	&ddc_i2c,
1321	serge	1364	CONNECTOR_OBJECT_ID_LVDS,
		1365	&hpd);
1123	serge	1366
		1367	/* VGA - primary dac */
1321	serge	1368	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1369	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1370	radeon_add_legacy_encoder(dev,
		1371	radeon_get_encoder_id(dev,
		1372	ATOM_DEVICE_CRT1_SUPPORT,
		1373	1),
		1374	ATOM_DEVICE_CRT1_SUPPORT);
		1375	radeon_add_legacy_connector(dev, 1,
		1376	ATOM_DEVICE_CRT1_SUPPORT,
		1377	DRM_MODE_CONNECTOR_VGA,
1268	serge	1378	&ddc_i2c,
1321	serge	1379	CONNECTOR_OBJECT_ID_VGA,
		1380	&hpd);
1123	serge	1381	} else {
		1382	/* DVI-I - tv dac, int tmds */
1321	serge	1383	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1384	hpd.hpd = RADEON_HPD_1;
1123	serge	1385	radeon_add_legacy_encoder(dev,
		1386	radeon_get_encoder_id(dev,
		1387	ATOM_DEVICE_DFP1_SUPPORT,
		1388	0),
		1389	ATOM_DEVICE_DFP1_SUPPORT);
		1390	radeon_add_legacy_encoder(dev,
		1391	radeon_get_encoder_id(dev,
		1392	ATOM_DEVICE_CRT2_SUPPORT,
		1393	2),
		1394	ATOM_DEVICE_CRT2_SUPPORT);
		1395	radeon_add_legacy_connector(dev, 0,
		1396	ATOM_DEVICE_DFP1_SUPPORT \|
		1397	ATOM_DEVICE_CRT2_SUPPORT,
		1398	DRM_MODE_CONNECTOR_DVII,
1268	serge	1399	&ddc_i2c,
1321	serge	1400	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1401	&hpd);
1123	serge	1402
		1403	/* VGA - primary dac */
1321	serge	1404	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1405	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1406	radeon_add_legacy_encoder(dev,
		1407	radeon_get_encoder_id(dev,
		1408	ATOM_DEVICE_CRT1_SUPPORT,
		1409	1),
		1410	ATOM_DEVICE_CRT1_SUPPORT);
		1411	radeon_add_legacy_connector(dev, 1,
		1412	ATOM_DEVICE_CRT1_SUPPORT,
		1413	DRM_MODE_CONNECTOR_VGA,
1268	serge	1414	&ddc_i2c,
1321	serge	1415	CONNECTOR_OBJECT_ID_VGA,
		1416	&hpd);
1123	serge	1417	}
		1418
		1419	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		1420	/* TV - tv dac */
1321	serge	1421	ddc_i2c.valid = false;
		1422	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1423	radeon_add_legacy_encoder(dev,
		1424	radeon_get_encoder_id(dev,
		1425	ATOM_DEVICE_TV1_SUPPORT,
		1426	2),
		1427	ATOM_DEVICE_TV1_SUPPORT);
		1428	radeon_add_legacy_connector(dev, 2,
		1429	ATOM_DEVICE_TV1_SUPPORT,
		1430	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1431	&ddc_i2c,
1321	serge	1432	CONNECTOR_OBJECT_ID_SVIDEO,
		1433	&hpd);
1123	serge	1434	}
		1435	break;
		1436	case CT_IBOOK:
		1437	DRM_INFO("Connector Table: %d (ibook)\n",
		1438	rdev->mode_info.connector_table);
		1439	/* LVDS */
1321	serge	1440	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1441	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1442	radeon_add_legacy_encoder(dev,
		1443	radeon_get_encoder_id(dev,
		1444	ATOM_DEVICE_LCD1_SUPPORT,
		1445	0),
		1446	ATOM_DEVICE_LCD1_SUPPORT);
		1447	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1448	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1449	CONNECTOR_OBJECT_ID_LVDS,
		1450	&hpd);
1123	serge	1451	/* VGA - TV DAC */
1321	serge	1452	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1453	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1454	radeon_add_legacy_encoder(dev,
		1455	radeon_get_encoder_id(dev,
		1456	ATOM_DEVICE_CRT2_SUPPORT,
		1457	2),
		1458	ATOM_DEVICE_CRT2_SUPPORT);
		1459	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1460	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1461	CONNECTOR_OBJECT_ID_VGA,
		1462	&hpd);
1123	serge	1463	/* TV - TV DAC */
1321	serge	1464	ddc_i2c.valid = false;
		1465	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1466	radeon_add_legacy_encoder(dev,
		1467	radeon_get_encoder_id(dev,
		1468	ATOM_DEVICE_TV1_SUPPORT,
		1469	2),
		1470	ATOM_DEVICE_TV1_SUPPORT);
		1471	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1472	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1473	&ddc_i2c,
1321	serge	1474	CONNECTOR_OBJECT_ID_SVIDEO,
		1475	&hpd);
1123	serge	1476	break;
		1477	case CT_POWERBOOK_EXTERNAL:
		1478	DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
		1479	rdev->mode_info.connector_table);
		1480	/* LVDS */
1321	serge	1481	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1482	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1483	radeon_add_legacy_encoder(dev,
		1484	radeon_get_encoder_id(dev,
		1485	ATOM_DEVICE_LCD1_SUPPORT,
		1486	0),
		1487	ATOM_DEVICE_LCD1_SUPPORT);
		1488	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1489	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1490	CONNECTOR_OBJECT_ID_LVDS,
		1491	&hpd);
1123	serge	1492	/* DVI-I - primary dac, ext tmds */
1321	serge	1493	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1494	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1495	radeon_add_legacy_encoder(dev,
		1496	radeon_get_encoder_id(dev,
		1497	ATOM_DEVICE_DFP2_SUPPORT,
		1498	0),
		1499	ATOM_DEVICE_DFP2_SUPPORT);
		1500	radeon_add_legacy_encoder(dev,
		1501	radeon_get_encoder_id(dev,
		1502	ATOM_DEVICE_CRT1_SUPPORT,
		1503	1),
		1504	ATOM_DEVICE_CRT1_SUPPORT);
1268	serge	1505	/* XXX some are SL */
1123	serge	1506	radeon_add_legacy_connector(dev, 1,
		1507	ATOM_DEVICE_DFP2_SUPPORT \|
		1508	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1509	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1510	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		1511	&hpd);
1123	serge	1512	/* TV - TV DAC */
1321	serge	1513	ddc_i2c.valid = false;
		1514	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1515	radeon_add_legacy_encoder(dev,
		1516	radeon_get_encoder_id(dev,
		1517	ATOM_DEVICE_TV1_SUPPORT,
		1518	2),
		1519	ATOM_DEVICE_TV1_SUPPORT);
		1520	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1521	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1522	&ddc_i2c,
1321	serge	1523	CONNECTOR_OBJECT_ID_SVIDEO,
		1524	&hpd);
1123	serge	1525	break;
		1526	case CT_POWERBOOK_INTERNAL:
		1527	DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
		1528	rdev->mode_info.connector_table);
		1529	/* LVDS */
1321	serge	1530	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1531	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1532	radeon_add_legacy_encoder(dev,
		1533	radeon_get_encoder_id(dev,
		1534	ATOM_DEVICE_LCD1_SUPPORT,
		1535	0),
		1536	ATOM_DEVICE_LCD1_SUPPORT);
		1537	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1538	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1539	CONNECTOR_OBJECT_ID_LVDS,
		1540	&hpd);
1123	serge	1541	/* DVI-I - primary dac, int tmds */
1321	serge	1542	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1543	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1544	radeon_add_legacy_encoder(dev,
		1545	radeon_get_encoder_id(dev,
		1546	ATOM_DEVICE_DFP1_SUPPORT,
		1547	0),
		1548	ATOM_DEVICE_DFP1_SUPPORT);
		1549	radeon_add_legacy_encoder(dev,
		1550	radeon_get_encoder_id(dev,
		1551	ATOM_DEVICE_CRT1_SUPPORT,
		1552	1),
		1553	ATOM_DEVICE_CRT1_SUPPORT);
		1554	radeon_add_legacy_connector(dev, 1,
		1555	ATOM_DEVICE_DFP1_SUPPORT \|
		1556	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1557	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1558	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1559	&hpd);
1123	serge	1560	/* TV - TV DAC */
1321	serge	1561	ddc_i2c.valid = false;
		1562	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1563	radeon_add_legacy_encoder(dev,
		1564	radeon_get_encoder_id(dev,
		1565	ATOM_DEVICE_TV1_SUPPORT,
		1566	2),
		1567	ATOM_DEVICE_TV1_SUPPORT);
		1568	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1569	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1570	&ddc_i2c,
1321	serge	1571	CONNECTOR_OBJECT_ID_SVIDEO,
		1572	&hpd);
1123	serge	1573	break;
		1574	case CT_POWERBOOK_VGA:
		1575	DRM_INFO("Connector Table: %d (powerbook vga)\n",
		1576	rdev->mode_info.connector_table);
		1577	/* LVDS */
1321	serge	1578	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1579	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1580	radeon_add_legacy_encoder(dev,
		1581	radeon_get_encoder_id(dev,
		1582	ATOM_DEVICE_LCD1_SUPPORT,
		1583	0),
		1584	ATOM_DEVICE_LCD1_SUPPORT);
		1585	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1586	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1587	CONNECTOR_OBJECT_ID_LVDS,
		1588	&hpd);
1123	serge	1589	/* VGA - primary dac */
1321	serge	1590	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1591	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1592	radeon_add_legacy_encoder(dev,
		1593	radeon_get_encoder_id(dev,
		1594	ATOM_DEVICE_CRT1_SUPPORT,
		1595	1),
		1596	ATOM_DEVICE_CRT1_SUPPORT);
		1597	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1598	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1599	CONNECTOR_OBJECT_ID_VGA,
		1600	&hpd);
1123	serge	1601	/* TV - TV DAC */
1321	serge	1602	ddc_i2c.valid = false;
		1603	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1604	radeon_add_legacy_encoder(dev,
		1605	radeon_get_encoder_id(dev,
		1606	ATOM_DEVICE_TV1_SUPPORT,
		1607	2),
		1608	ATOM_DEVICE_TV1_SUPPORT);
		1609	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1610	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1611	&ddc_i2c,
1321	serge	1612	CONNECTOR_OBJECT_ID_SVIDEO,
		1613	&hpd);
1123	serge	1614	break;
		1615	case CT_MINI_EXTERNAL:
		1616	DRM_INFO("Connector Table: %d (mini external tmds)\n",
		1617	rdev->mode_info.connector_table);
		1618	/* DVI-I - tv dac, ext tmds */
1321	serge	1619	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
		1620	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1621	radeon_add_legacy_encoder(dev,
		1622	radeon_get_encoder_id(dev,
		1623	ATOM_DEVICE_DFP2_SUPPORT,
		1624	0),
		1625	ATOM_DEVICE_DFP2_SUPPORT);
		1626	radeon_add_legacy_encoder(dev,
		1627	radeon_get_encoder_id(dev,
		1628	ATOM_DEVICE_CRT2_SUPPORT,
		1629	2),
		1630	ATOM_DEVICE_CRT2_SUPPORT);
1268	serge	1631	/* XXX are any DL? */
1123	serge	1632	radeon_add_legacy_connector(dev, 0,
		1633	ATOM_DEVICE_DFP2_SUPPORT \|
		1634	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1635	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1636	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1637	&hpd);
1123	serge	1638	/* TV - TV DAC */
1321	serge	1639	ddc_i2c.valid = false;
		1640	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1641	radeon_add_legacy_encoder(dev,
		1642	radeon_get_encoder_id(dev,
		1643	ATOM_DEVICE_TV1_SUPPORT,
		1644	2),
		1645	ATOM_DEVICE_TV1_SUPPORT);
		1646	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1647	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1648	&ddc_i2c,
1321	serge	1649	CONNECTOR_OBJECT_ID_SVIDEO,
		1650	&hpd);
1123	serge	1651	break;
		1652	case CT_MINI_INTERNAL:
		1653	DRM_INFO("Connector Table: %d (mini internal tmds)\n",
		1654	rdev->mode_info.connector_table);
		1655	/* DVI-I - tv dac, int tmds */
1321	serge	1656	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
		1657	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1658	radeon_add_legacy_encoder(dev,
		1659	radeon_get_encoder_id(dev,
		1660	ATOM_DEVICE_DFP1_SUPPORT,
		1661	0),
		1662	ATOM_DEVICE_DFP1_SUPPORT);
		1663	radeon_add_legacy_encoder(dev,
		1664	radeon_get_encoder_id(dev,
		1665	ATOM_DEVICE_CRT2_SUPPORT,
		1666	2),
		1667	ATOM_DEVICE_CRT2_SUPPORT);
		1668	radeon_add_legacy_connector(dev, 0,
		1669	ATOM_DEVICE_DFP1_SUPPORT \|
		1670	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1671	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1672	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1673	&hpd);
1123	serge	1674	/* TV - TV DAC */
1321	serge	1675	ddc_i2c.valid = false;
		1676	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1677	radeon_add_legacy_encoder(dev,
		1678	radeon_get_encoder_id(dev,
		1679	ATOM_DEVICE_TV1_SUPPORT,
		1680	2),
		1681	ATOM_DEVICE_TV1_SUPPORT);
		1682	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1683	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1684	&ddc_i2c,
1321	serge	1685	CONNECTOR_OBJECT_ID_SVIDEO,
		1686	&hpd);
1123	serge	1687	break;
		1688	case CT_IMAC_G5_ISIGHT:
		1689	DRM_INFO("Connector Table: %d (imac g5 isight)\n",
		1690	rdev->mode_info.connector_table);
		1691	/* DVI-D - int tmds */
1321	serge	1692	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
		1693	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1694	radeon_add_legacy_encoder(dev,
		1695	radeon_get_encoder_id(dev,
		1696	ATOM_DEVICE_DFP1_SUPPORT,
		1697	0),
		1698	ATOM_DEVICE_DFP1_SUPPORT);
		1699	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1268	serge	1700	DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1321	serge	1701	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		1702	&hpd);
1123	serge	1703	/* VGA - tv dac */
1321	serge	1704	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1705	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1706	radeon_add_legacy_encoder(dev,
		1707	radeon_get_encoder_id(dev,
		1708	ATOM_DEVICE_CRT2_SUPPORT,
		1709	2),
		1710	ATOM_DEVICE_CRT2_SUPPORT);
		1711	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1712	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1713	CONNECTOR_OBJECT_ID_VGA,
		1714	&hpd);
1123	serge	1715	/* TV - TV DAC */
1321	serge	1716	ddc_i2c.valid = false;
		1717	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1718	radeon_add_legacy_encoder(dev,
		1719	radeon_get_encoder_id(dev,
		1720	ATOM_DEVICE_TV1_SUPPORT,
		1721	2),
		1722	ATOM_DEVICE_TV1_SUPPORT);
		1723	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1724	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1725	&ddc_i2c,
1321	serge	1726	CONNECTOR_OBJECT_ID_SVIDEO,
		1727	&hpd);
1123	serge	1728	break;
		1729	case CT_EMAC:
		1730	DRM_INFO("Connector Table: %d (emac)\n",
		1731	rdev->mode_info.connector_table);
		1732	/* VGA - primary dac */
1321	serge	1733	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		1734	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1735	radeon_add_legacy_encoder(dev,
		1736	radeon_get_encoder_id(dev,
		1737	ATOM_DEVICE_CRT1_SUPPORT,
		1738	1),
		1739	ATOM_DEVICE_CRT1_SUPPORT);
		1740	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1741	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1742	CONNECTOR_OBJECT_ID_VGA,
		1743	&hpd);
1123	serge	1744	/* VGA - tv dac */
1321	serge	1745	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
		1746	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1747	radeon_add_legacy_encoder(dev,
		1748	radeon_get_encoder_id(dev,
		1749	ATOM_DEVICE_CRT2_SUPPORT,
		1750	2),
		1751	ATOM_DEVICE_CRT2_SUPPORT);
		1752	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1753	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1754	CONNECTOR_OBJECT_ID_VGA,
		1755	&hpd);
1123	serge	1756	/* TV - TV DAC */
1321	serge	1757	ddc_i2c.valid = false;
		1758	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1759	radeon_add_legacy_encoder(dev,
		1760	radeon_get_encoder_id(dev,
		1761	ATOM_DEVICE_TV1_SUPPORT,
		1762	2),
		1763	ATOM_DEVICE_TV1_SUPPORT);
		1764	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1765	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1766	&ddc_i2c,
1321	serge	1767	CONNECTOR_OBJECT_ID_SVIDEO,
		1768	&hpd);
1123	serge	1769	break;
		1770	default:
		1771	DRM_INFO("Connector table: %d (invalid)\n",
		1772	rdev->mode_info.connector_table);
		1773	return false;
		1774	}
		1775
		1776	radeon_link_encoder_connector(dev);
		1777
		1778	return true;
		1779	}
		1780
		1781	static bool radeon_apply_legacy_quirks(struct drm_device *dev,
		1782	int bios_index,
		1783	enum radeon_combios_connector
		1784	*legacy_connector,
1321	serge	1785	struct radeon_i2c_bus_rec *ddc_i2c,
		1786	struct radeon_hpd *hpd)
1123	serge	1787	{
		1788	struct radeon_device *rdev = dev->dev_private;
		1789
		1790	/* XPRESS DDC quirks */
		1791	if ((rdev->family == CHIP_RS400 \|\|
		1792	rdev->family == CHIP_RS480) &&
		1793	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1321	serge	1794	*ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1123	serge	1795	else if ((rdev->family == CHIP_RS400 \|\|
		1796	rdev->family == CHIP_RS480) &&
		1797	ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1321	serge	1798	*ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1123	serge	1799	ddc_i2c->mask_clk_mask = (0x20 << 8);
		1800	ddc_i2c->mask_data_mask = 0x80;
		1801	ddc_i2c->a_clk_mask = (0x20 << 8);
		1802	ddc_i2c->a_data_mask = 0x80;
1321	serge	1803	ddc_i2c->en_clk_mask = (0x20 << 8);
		1804	ddc_i2c->en_data_mask = 0x80;
		1805	ddc_i2c->y_clk_mask = (0x20 << 8);
		1806	ddc_i2c->y_data_mask = 0x80;
1123	serge	1807	}
		1808
1321	serge	1809	/* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
		1810	if ((rdev->family >= CHIP_R300) &&
		1811	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		1812	*ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		1813
1123	serge	1814	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
		1815	one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
		1816	if (dev->pdev->device == 0x515e &&
		1817	dev->pdev->subsystem_vendor == 0x1014) {
		1818	if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
		1819	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		1820	return false;
		1821	}
		1822
		1823	/* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
		1824	if (dev->pdev->device == 0x5159 &&
		1825	dev->pdev->subsystem_vendor == 0x1002 &&
		1826	dev->pdev->subsystem_device == 0x013a) {
		1827	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		1828	*legacy_connector = CONNECTOR_CRT_LEGACY;
		1829
		1830	}
		1831
		1832	/* X300 card with extra non-existent DVI port */
		1833	if (dev->pdev->device == 0x5B60 &&
		1834	dev->pdev->subsystem_vendor == 0x17af &&
		1835	dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
		1836	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		1837	return false;
		1838	}
		1839
		1840	return true;
		1841	}
		1842
1268	serge	1843	static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
		1844	{
		1845	/* Acer 5102 has non-existent TV port */
		1846	if (dev->pdev->device == 0x5975 &&
		1847	dev->pdev->subsystem_vendor == 0x1025 &&
		1848	dev->pdev->subsystem_device == 0x009f)
		1849	return false;
		1850
		1851	/* HP dc5750 has non-existent TV port */
		1852	if (dev->pdev->device == 0x5974 &&
		1853	dev->pdev->subsystem_vendor == 0x103c &&
		1854	dev->pdev->subsystem_device == 0x280a)
		1855	return false;
		1856
1321	serge	1857	/* MSI S270 has non-existent TV port */
		1858	if (dev->pdev->device == 0x5955 &&
		1859	dev->pdev->subsystem_vendor == 0x1462 &&
		1860	dev->pdev->subsystem_device == 0x0131)
		1861	return false;
		1862
1268	serge	1863	return true;
		1864	}
		1865
		1866	static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
		1867	{
		1868	struct radeon_device *rdev = dev->dev_private;
		1869	uint32_t ext_tmds_info;
		1870
		1871	if (rdev->flags & RADEON_IS_IGP) {
		1872	if (is_dvi_d)
		1873	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		1874	else
		1875	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		1876	}
		1877	ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		1878	if (ext_tmds_info) {
		1879	uint8_t rev = RBIOS8(ext_tmds_info);
		1880	uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
		1881	if (rev >= 3) {
		1882	if (is_dvi_d)
		1883	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		1884	else
		1885	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		1886	} else {
		1887	if (flags & 1) {
		1888	if (is_dvi_d)
		1889	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		1890	else
		1891	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		1892	}
		1893	}
		1894	}
		1895	if (is_dvi_d)
		1896	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		1897	else
		1898	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		1899	}
		1900
1123	serge	1901	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
		1902	{
		1903	struct radeon_device *rdev = dev->dev_private;
		1904	uint32_t conn_info, entry, devices;
1268	serge	1905	uint16_t tmp, connector_object_id;
1123	serge	1906	enum radeon_combios_ddc ddc_type;
		1907	enum radeon_combios_connector connector;
		1908	int i = 0;
		1909	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	1910	struct radeon_hpd hpd;
1123	serge	1911
		1912	if (rdev->bios == NULL)
		1913	return false;
		1914
		1915	conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
		1916	if (conn_info) {
		1917	for (i = 0; i < 4; i++) {
		1918	entry = conn_info + 2 + i * 2;
		1919
		1920	if (!RBIOS16(entry))
		1921	break;
		1922
		1923	tmp = RBIOS16(entry);
		1924
		1925	connector = (tmp >> 12) & 0xf;
		1926
		1927	ddc_type = (tmp >> 8) & 0xf;
		1928	switch (ddc_type) {
		1929	case DDC_MONID:
		1930	ddc_i2c =
1321	serge	1931	combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1123	serge	1932	break;
		1933	case DDC_DVI:
		1934	ddc_i2c =
1321	serge	1935	combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1123	serge	1936	break;
		1937	case DDC_VGA:
		1938	ddc_i2c =
1321	serge	1939	combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1123	serge	1940	break;
		1941	case DDC_CRT2:
		1942	ddc_i2c =
1321	serge	1943	combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1123	serge	1944	break;
		1945	default:
		1946	break;
		1947	}
		1948
1321	serge	1949	switch (connector) {
		1950	case CONNECTOR_PROPRIETARY_LEGACY:
		1951	case CONNECTOR_DVI_I_LEGACY:
		1952	case CONNECTOR_DVI_D_LEGACY:
		1953	if ((tmp >> 4) & 0x1)
		1954	hpd.hpd = RADEON_HPD_2;
		1955	else
		1956	hpd.hpd = RADEON_HPD_1;
		1957	break;
		1958	default:
		1959	hpd.hpd = RADEON_HPD_NONE;
		1960	break;
		1961	}
		1962
1268	serge	1963	if (!radeon_apply_legacy_quirks(dev, i, &connector,
1321	serge	1964	&ddc_i2c, &hpd))
1268	serge	1965	continue;
1123	serge	1966
		1967	switch (connector) {
		1968	case CONNECTOR_PROPRIETARY_LEGACY:
		1969	if ((tmp >> 4) & 0x1)
		1970	devices = ATOM_DEVICE_DFP2_SUPPORT;
		1971	else
		1972	devices = ATOM_DEVICE_DFP1_SUPPORT;
		1973	radeon_add_legacy_encoder(dev,
		1974	radeon_get_encoder_id
		1975	(dev, devices, 0),
		1976	devices);
		1977	radeon_add_legacy_connector(dev, i, devices,
		1978	legacy_connector_convert
		1979	[connector],
1268	serge	1980	&ddc_i2c,
1321	serge	1981	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		1982	&hpd);
1123	serge	1983	break;
		1984	case CONNECTOR_CRT_LEGACY:
		1985	if (tmp & 0x1) {
		1986	devices = ATOM_DEVICE_CRT2_SUPPORT;
		1987	radeon_add_legacy_encoder(dev,
		1988	radeon_get_encoder_id
		1989	(dev,
		1990	ATOM_DEVICE_CRT2_SUPPORT,
		1991	2),
		1992	ATOM_DEVICE_CRT2_SUPPORT);
		1993	} else {
		1994	devices = ATOM_DEVICE_CRT1_SUPPORT;
		1995	radeon_add_legacy_encoder(dev,
		1996	radeon_get_encoder_id
		1997	(dev,
		1998	ATOM_DEVICE_CRT1_SUPPORT,
		1999	1),
		2000	ATOM_DEVICE_CRT1_SUPPORT);
		2001	}
		2002	radeon_add_legacy_connector(dev,
		2003	i,
		2004	devices,
		2005	legacy_connector_convert
		2006	[connector],
1268	serge	2007	&ddc_i2c,
1321	serge	2008	CONNECTOR_OBJECT_ID_VGA,
		2009	&hpd);
1123	serge	2010	break;
		2011	case CONNECTOR_DVI_I_LEGACY:
		2012	devices = 0;
		2013	if (tmp & 0x1) {
		2014	devices \|= ATOM_DEVICE_CRT2_SUPPORT;
		2015	radeon_add_legacy_encoder(dev,
		2016	radeon_get_encoder_id
		2017	(dev,
		2018	ATOM_DEVICE_CRT2_SUPPORT,
		2019	2),
		2020	ATOM_DEVICE_CRT2_SUPPORT);
		2021	} else {
		2022	devices \|= ATOM_DEVICE_CRT1_SUPPORT;
		2023	radeon_add_legacy_encoder(dev,
		2024	radeon_get_encoder_id
		2025	(dev,
		2026	ATOM_DEVICE_CRT1_SUPPORT,
		2027	1),
		2028	ATOM_DEVICE_CRT1_SUPPORT);
		2029	}
		2030	if ((tmp >> 4) & 0x1) {
		2031	devices \|= ATOM_DEVICE_DFP2_SUPPORT;
		2032	radeon_add_legacy_encoder(dev,
		2033	radeon_get_encoder_id
		2034	(dev,
		2035	ATOM_DEVICE_DFP2_SUPPORT,
		2036	0),
		2037	ATOM_DEVICE_DFP2_SUPPORT);
1268	serge	2038	connector_object_id = combios_check_dl_dvi(dev, 0);
1123	serge	2039	} else {
		2040	devices \|= ATOM_DEVICE_DFP1_SUPPORT;
		2041	radeon_add_legacy_encoder(dev,
		2042	radeon_get_encoder_id
		2043	(dev,
		2044	ATOM_DEVICE_DFP1_SUPPORT,
		2045	0),
		2046	ATOM_DEVICE_DFP1_SUPPORT);
1268	serge	2047	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1123	serge	2048	}
		2049	radeon_add_legacy_connector(dev,
		2050	i,
		2051	devices,
		2052	legacy_connector_convert
		2053	[connector],
1268	serge	2054	&ddc_i2c,
1321	serge	2055	connector_object_id,
		2056	&hpd);
1123	serge	2057	break;
		2058	case CONNECTOR_DVI_D_LEGACY:
1268	serge	2059	if ((tmp >> 4) & 0x1) {
1123	serge	2060	devices = ATOM_DEVICE_DFP2_SUPPORT;
1268	serge	2061	connector_object_id = combios_check_dl_dvi(dev, 1);
		2062	} else {
1123	serge	2063	devices = ATOM_DEVICE_DFP1_SUPPORT;
1268	serge	2064	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2065	}
1123	serge	2066	radeon_add_legacy_encoder(dev,
		2067	radeon_get_encoder_id
		2068	(dev, devices, 0),
		2069	devices);
		2070	radeon_add_legacy_connector(dev, i, devices,
		2071	legacy_connector_convert
		2072	[connector],
1268	serge	2073	&ddc_i2c,
1321	serge	2074	connector_object_id,
		2075	&hpd);
1123	serge	2076	break;
		2077	case CONNECTOR_CTV_LEGACY:
		2078	case CONNECTOR_STV_LEGACY:
		2079	radeon_add_legacy_encoder(dev,
		2080	radeon_get_encoder_id
		2081	(dev,
		2082	ATOM_DEVICE_TV1_SUPPORT,
		2083	2),
		2084	ATOM_DEVICE_TV1_SUPPORT);
		2085	radeon_add_legacy_connector(dev, i,
		2086	ATOM_DEVICE_TV1_SUPPORT,
		2087	legacy_connector_convert
		2088	[connector],
1268	serge	2089	&ddc_i2c,
1321	serge	2090	CONNECTOR_OBJECT_ID_SVIDEO,
		2091	&hpd);
1123	serge	2092	break;
		2093	default:
		2094	DRM_ERROR("Unknown connector type: %d\n",
		2095	connector);
		2096	continue;
		2097	}
		2098
		2099	}
		2100	} else {
		2101	uint16_t tmds_info =
		2102	combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		2103	if (tmds_info) {
		2104	DRM_DEBUG("Found DFP table, assuming DVI connector\n");
		2105
		2106	radeon_add_legacy_encoder(dev,
		2107	radeon_get_encoder_id(dev,
		2108	ATOM_DEVICE_CRT1_SUPPORT,
		2109	1),
		2110	ATOM_DEVICE_CRT1_SUPPORT);
		2111	radeon_add_legacy_encoder(dev,
		2112	radeon_get_encoder_id(dev,
		2113	ATOM_DEVICE_DFP1_SUPPORT,
		2114	0),
		2115	ATOM_DEVICE_DFP1_SUPPORT);
		2116
1321	serge	2117	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
		2118	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2119	radeon_add_legacy_connector(dev,
		2120	0,
		2121	ATOM_DEVICE_CRT1_SUPPORT \|
		2122	ATOM_DEVICE_DFP1_SUPPORT,
		2123	DRM_MODE_CONNECTOR_DVII,
1268	serge	2124	&ddc_i2c,
1321	serge	2125	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2126	&hpd);
1123	serge	2127	} else {
1268	serge	2128	uint16_t crt_info =
		2129	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		2130	DRM_DEBUG("Found CRT table, assuming VGA connector\n");
		2131	if (crt_info) {
		2132	radeon_add_legacy_encoder(dev,
		2133	radeon_get_encoder_id(dev,
		2134	ATOM_DEVICE_CRT1_SUPPORT,
		2135	1),
		2136	ATOM_DEVICE_CRT1_SUPPORT);
1321	serge	2137	ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
		2138	hpd.hpd = RADEON_HPD_NONE;
1268	serge	2139	radeon_add_legacy_connector(dev,
		2140	0,
		2141	ATOM_DEVICE_CRT1_SUPPORT,
		2142	DRM_MODE_CONNECTOR_VGA,
		2143	&ddc_i2c,
1321	serge	2144	CONNECTOR_OBJECT_ID_VGA,
		2145	&hpd);
1268	serge	2146	} else {
1123	serge	2147	DRM_DEBUG("No connector info found\n");
		2148	return false;
		2149	}
		2150	}
1268	serge	2151	}
1123	serge	2152
		2153	if (rdev->flags & RADEON_IS_MOBILITY \|\| rdev->flags & RADEON_IS_IGP) {
		2154	uint16_t lcd_info =
		2155	combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		2156	if (lcd_info) {
		2157	uint16_t lcd_ddc_info =
		2158	combios_get_table_offset(dev,
		2159	COMBIOS_LCD_DDC_INFO_TABLE);
		2160
		2161	radeon_add_legacy_encoder(dev,
		2162	radeon_get_encoder_id(dev,
		2163	ATOM_DEVICE_LCD1_SUPPORT,
		2164	0),
		2165	ATOM_DEVICE_LCD1_SUPPORT);
		2166
		2167	if (lcd_ddc_info) {
		2168	ddc_type = RBIOS8(lcd_ddc_info + 2);
		2169	switch (ddc_type) {
		2170	case DDC_MONID:
		2171	ddc_i2c =
		2172	combios_setup_i2c_bus
1321	serge	2173	(rdev, RADEON_GPIO_MONID);
1123	serge	2174	break;
		2175	case DDC_DVI:
		2176	ddc_i2c =
		2177	combios_setup_i2c_bus
1321	serge	2178	(rdev, RADEON_GPIO_DVI_DDC);
1123	serge	2179	break;
		2180	case DDC_VGA:
		2181	ddc_i2c =
		2182	combios_setup_i2c_bus
1321	serge	2183	(rdev, RADEON_GPIO_VGA_DDC);
1123	serge	2184	break;
		2185	case DDC_CRT2:
		2186	ddc_i2c =
		2187	combios_setup_i2c_bus
1321	serge	2188	(rdev, RADEON_GPIO_CRT2_DDC);
1123	serge	2189	break;
		2190	case DDC_LCD:
		2191	ddc_i2c =
		2192	combios_setup_i2c_bus
1321	serge	2193	(rdev, RADEON_GPIOPAD_MASK);
1123	serge	2194	ddc_i2c.mask_clk_mask =
		2195	RBIOS32(lcd_ddc_info + 3);
		2196	ddc_i2c.mask_data_mask =
		2197	RBIOS32(lcd_ddc_info + 7);
		2198	ddc_i2c.a_clk_mask =
		2199	RBIOS32(lcd_ddc_info + 3);
		2200	ddc_i2c.a_data_mask =
		2201	RBIOS32(lcd_ddc_info + 7);
1321	serge	2202	ddc_i2c.en_clk_mask =
1123	serge	2203	RBIOS32(lcd_ddc_info + 3);
1321	serge	2204	ddc_i2c.en_data_mask =
1123	serge	2205	RBIOS32(lcd_ddc_info + 7);
1321	serge	2206	ddc_i2c.y_clk_mask =
1123	serge	2207	RBIOS32(lcd_ddc_info + 3);
1321	serge	2208	ddc_i2c.y_data_mask =
1123	serge	2209	RBIOS32(lcd_ddc_info + 7);
		2210	break;
		2211	case DDC_GPIO:
		2212	ddc_i2c =
		2213	combios_setup_i2c_bus
1321	serge	2214	(rdev, RADEON_MDGPIO_MASK);
1123	serge	2215	ddc_i2c.mask_clk_mask =
		2216	RBIOS32(lcd_ddc_info + 3);
		2217	ddc_i2c.mask_data_mask =
		2218	RBIOS32(lcd_ddc_info + 7);
		2219	ddc_i2c.a_clk_mask =
		2220	RBIOS32(lcd_ddc_info + 3);
		2221	ddc_i2c.a_data_mask =
		2222	RBIOS32(lcd_ddc_info + 7);
1321	serge	2223	ddc_i2c.en_clk_mask =
1123	serge	2224	RBIOS32(lcd_ddc_info + 3);
1321	serge	2225	ddc_i2c.en_data_mask =
1123	serge	2226	RBIOS32(lcd_ddc_info + 7);
1321	serge	2227	ddc_i2c.y_clk_mask =
1123	serge	2228	RBIOS32(lcd_ddc_info + 3);
1321	serge	2229	ddc_i2c.y_data_mask =
1123	serge	2230	RBIOS32(lcd_ddc_info + 7);
		2231	break;
		2232	default:
		2233	ddc_i2c.valid = false;
		2234	break;
		2235	}
		2236	DRM_DEBUG("LCD DDC Info Table found!\n");
		2237	} else
		2238	ddc_i2c.valid = false;
		2239
1321	serge	2240	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2241	radeon_add_legacy_connector(dev,
		2242	5,
		2243	ATOM_DEVICE_LCD1_SUPPORT,
		2244	DRM_MODE_CONNECTOR_LVDS,
1268	serge	2245	&ddc_i2c,
1321	serge	2246	CONNECTOR_OBJECT_ID_LVDS,
		2247	&hpd);
1123	serge	2248	}
		2249	}
		2250
		2251	/* check TV table */
		2252	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		2253	uint32_t tv_info =
		2254	combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		2255	if (tv_info) {
		2256	if (RBIOS8(tv_info + 6) == 'T') {
1268	serge	2257	if (radeon_apply_legacy_tv_quirks(dev)) {
1321	serge	2258	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2259	radeon_add_legacy_encoder(dev,
		2260	radeon_get_encoder_id
		2261	(dev,
		2262	ATOM_DEVICE_TV1_SUPPORT,
		2263	2),
		2264	ATOM_DEVICE_TV1_SUPPORT);
		2265	radeon_add_legacy_connector(dev, 6,
		2266	ATOM_DEVICE_TV1_SUPPORT,
		2267	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2268	&ddc_i2c,
1321	serge	2269	CONNECTOR_OBJECT_ID_SVIDEO,
		2270	&hpd);
1268	serge	2271	}
1123	serge	2272	}
		2273	}
		2274	}
		2275
		2276	radeon_link_encoder_connector(dev);
		2277
		2278	return true;
		2279	}
		2280
1321	serge	2281	void radeon_external_tmds_setup(struct drm_encoder *encoder)
		2282	{
		2283	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2284	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2285
		2286	if (!tmds)
		2287	return;
		2288
		2289	switch (tmds->dvo_chip) {
		2290	case DVO_SIL164:
		2291	/* sil 164 */
		2292	radeon_i2c_do_lock(tmds->i2c_bus, 1);
		2293	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2294	tmds->slave_addr,
		2295	0x08, 0x30);
		2296	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2297	tmds->slave_addr,
		2298	0x09, 0x00);
		2299	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2300	tmds->slave_addr,
		2301	0x0a, 0x90);
		2302	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2303	tmds->slave_addr,
		2304	0x0c, 0x89);
		2305	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2306	tmds->slave_addr,
		2307	0x08, 0x3b);
		2308	radeon_i2c_do_lock(tmds->i2c_bus, 0);
		2309	break;
		2310	case DVO_SIL1178:
		2311	/* sil 1178 - untested */
		2312	/*
		2313	* 0x0f, 0x44
		2314	* 0x0f, 0x4c
		2315	* 0x0e, 0x01
		2316	* 0x0a, 0x80
		2317	* 0x09, 0x30
		2318	* 0x0c, 0xc9
		2319	* 0x0d, 0x70
		2320	* 0x08, 0x32
		2321	* 0x08, 0x33
		2322	*/
		2323	break;
		2324	default:
		2325	break;
		2326	}
		2327
		2328	}
		2329
		2330	bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
		2331	{
		2332	struct drm_device *dev = encoder->dev;
		2333	struct radeon_device *rdev = dev->dev_private;
		2334	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2335	uint16_t offset;
		2336	uint8_t blocks, slave_addr, rev;
		2337	uint32_t index, id;
		2338	uint32_t reg, val, and_mask, or_mask;
		2339	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2340
		2341	if (rdev->bios == NULL)
		2342	return false;
		2343
		2344	if (!tmds)
		2345	return false;
		2346
		2347	if (rdev->flags & RADEON_IS_IGP) {
		2348	offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
		2349	rev = RBIOS8(offset);
		2350	if (offset) {
		2351	rev = RBIOS8(offset);
		2352	if (rev > 1) {
		2353	blocks = RBIOS8(offset + 3);
		2354	index = offset + 4;
		2355	while (blocks > 0) {
		2356	id = RBIOS16(index);
		2357	index += 2;
		2358	switch (id >> 13) {
		2359	case 0:
		2360	reg = (id & 0x1fff) * 4;
		2361	val = RBIOS32(index);
		2362	index += 4;
		2363	WREG32(reg, val);
		2364	break;
		2365	case 2:
		2366	reg = (id & 0x1fff) * 4;
		2367	and_mask = RBIOS32(index);
		2368	index += 4;
		2369	or_mask = RBIOS32(index);
		2370	index += 4;
		2371	val = RREG32(reg);
		2372	val = (val & and_mask) \| or_mask;
		2373	WREG32(reg, val);
		2374	break;
		2375	case 3:
		2376	val = RBIOS16(index);
		2377	index += 2;
		2378	udelay(val);
		2379	break;
		2380	case 4:
		2381	val = RBIOS16(index);
		2382	index += 2;
		2383	udelay(val * 1000);
		2384	break;
		2385	case 6:
		2386	slave_addr = id & 0xff;
		2387	slave_addr >>= 1; /* 7 bit addressing */
		2388	index++;
		2389	reg = RBIOS8(index);
		2390	index++;
		2391	val = RBIOS8(index);
		2392	index++;
		2393	radeon_i2c_do_lock(tmds->i2c_bus, 1);
		2394	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2395	slave_addr,
		2396	reg, val);
		2397	radeon_i2c_do_lock(tmds->i2c_bus, 0);
		2398	break;
		2399	default:
		2400	DRM_ERROR("Unknown id %d\n", id >> 13);
		2401	break;
		2402	}
		2403	blocks--;
		2404	}
		2405	return true;
		2406	}
		2407	}
		2408	} else {
		2409	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		2410	if (offset) {
		2411	index = offset + 10;
		2412	id = RBIOS16(index);
		2413	while (id != 0xffff) {
		2414	index += 2;
		2415	switch (id >> 13) {
		2416	case 0:
		2417	reg = (id & 0x1fff) * 4;
		2418	val = RBIOS32(index);
		2419	WREG32(reg, val);
		2420	break;
		2421	case 2:
		2422	reg = (id & 0x1fff) * 4;
		2423	and_mask = RBIOS32(index);
		2424	index += 4;
		2425	or_mask = RBIOS32(index);
		2426	index += 4;
		2427	val = RREG32(reg);
		2428	val = (val & and_mask) \| or_mask;
		2429	WREG32(reg, val);
		2430	break;
		2431	case 4:
		2432	val = RBIOS16(index);
		2433	index += 2;
		2434	udelay(val);
		2435	break;
		2436	case 5:
		2437	reg = id & 0x1fff;
		2438	and_mask = RBIOS32(index);
		2439	index += 4;
		2440	or_mask = RBIOS32(index);
		2441	index += 4;
		2442	val = RREG32_PLL(reg);
		2443	val = (val & and_mask) \| or_mask;
		2444	WREG32_PLL(reg, val);
		2445	break;
		2446	case 6:
		2447	reg = id & 0x1fff;
		2448	val = RBIOS8(index);
		2449	index += 1;
		2450	radeon_i2c_do_lock(tmds->i2c_bus, 1);
		2451	radeon_i2c_sw_put_byte(tmds->i2c_bus,
		2452	tmds->slave_addr,
		2453	reg, val);
		2454	radeon_i2c_do_lock(tmds->i2c_bus, 0);
		2455	break;
		2456	default:
		2457	DRM_ERROR("Unknown id %d\n", id >> 13);
		2458	break;
		2459	}
		2460	id = RBIOS16(index);
		2461	}
		2462	return true;
		2463	}
		2464	}
		2465	return false;
		2466	}
		2467
1123	serge	2468	static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
		2469	{
		2470	struct radeon_device *rdev = dev->dev_private;
		2471
		2472	if (offset) {
		2473	while (RBIOS16(offset)) {
		2474	uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
		2475	uint32_t addr = (RBIOS16(offset) & 0x1fff);
		2476	uint32_t val, and_mask, or_mask;
		2477	uint32_t tmp;
		2478
		2479	offset += 2;
		2480	switch (cmd) {
		2481	case 0:
		2482	val = RBIOS32(offset);
		2483	offset += 4;
		2484	WREG32(addr, val);
		2485	break;
		2486	case 1:
		2487	val = RBIOS32(offset);
		2488	offset += 4;
		2489	WREG32(addr, val);
		2490	break;
		2491	case 2:
		2492	and_mask = RBIOS32(offset);
		2493	offset += 4;
		2494	or_mask = RBIOS32(offset);
		2495	offset += 4;
		2496	tmp = RREG32(addr);
		2497	tmp &= and_mask;
		2498	tmp \|= or_mask;
		2499	WREG32(addr, tmp);
		2500	break;
		2501	case 3:
		2502	and_mask = RBIOS32(offset);
		2503	offset += 4;
		2504	or_mask = RBIOS32(offset);
		2505	offset += 4;
		2506	tmp = RREG32(addr);
		2507	tmp &= and_mask;
		2508	tmp \|= or_mask;
		2509	WREG32(addr, tmp);
		2510	break;
		2511	case 4:
		2512	val = RBIOS16(offset);
		2513	offset += 2;
		2514	udelay(val);
		2515	break;
		2516	case 5:
		2517	val = RBIOS16(offset);
		2518	offset += 2;
		2519	switch (addr) {
		2520	case 8:
		2521	while (val--) {
		2522	if (!
		2523	(RREG32_PLL
		2524	(RADEON_CLK_PWRMGT_CNTL) &
		2525	RADEON_MC_BUSY))
		2526	break;
		2527	}
		2528	break;
		2529	case 9:
		2530	while (val--) {
		2531	if ((RREG32(RADEON_MC_STATUS) &
		2532	RADEON_MC_IDLE))
		2533	break;
		2534	}
		2535	break;
		2536	default:
		2537	break;
		2538	}
		2539	break;
		2540	default:
		2541	break;
		2542	}
		2543	}
		2544	}
		2545	}
		2546
		2547	static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
		2548	{
		2549	struct radeon_device *rdev = dev->dev_private;
		2550
		2551	if (offset) {
		2552	while (RBIOS8(offset)) {
		2553	uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
		2554	uint8_t addr = (RBIOS8(offset) & 0x3f);
		2555	uint32_t val, shift, tmp;
		2556	uint32_t and_mask, or_mask;
		2557
		2558	offset++;
		2559	switch (cmd) {
		2560	case 0:
		2561	val = RBIOS32(offset);
		2562	offset += 4;
		2563	WREG32_PLL(addr, val);
		2564	break;
		2565	case 1:
		2566	shift = RBIOS8(offset) * 8;
		2567	offset++;
		2568	and_mask = RBIOS8(offset) << shift;
		2569	and_mask \|= ~(0xff << shift);
		2570	offset++;
		2571	or_mask = RBIOS8(offset) << shift;
		2572	offset++;
		2573	tmp = RREG32_PLL(addr);
		2574	tmp &= and_mask;
		2575	tmp \|= or_mask;
		2576	WREG32_PLL(addr, tmp);
		2577	break;
		2578	case 2:
		2579	case 3:
		2580	tmp = 1000;
		2581	switch (addr) {
		2582	case 1:
		2583	udelay(150);
		2584	break;
		2585	case 2:
		2586	udelay(1000);
		2587	break;
		2588	case 3:
		2589	while (tmp--) {
		2590	if (!
		2591	(RREG32_PLL
		2592	(RADEON_CLK_PWRMGT_CNTL) &
		2593	RADEON_MC_BUSY))
		2594	break;
		2595	}
		2596	break;
		2597	case 4:
		2598	while (tmp--) {
		2599	if (RREG32_PLL
		2600	(RADEON_CLK_PWRMGT_CNTL) &
		2601	RADEON_DLL_READY)
		2602	break;
		2603	}
		2604	break;
		2605	case 5:
		2606	tmp =
		2607	RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
		2608	if (tmp & RADEON_CG_NO1_DEBUG_0) {
		2609	#if 0
		2610	uint32_t mclk_cntl =
		2611	RREG32_PLL
		2612	(RADEON_MCLK_CNTL);
		2613	mclk_cntl &= 0xffff0000;
		2614	/mclk_cntl \|= 0x00001111;//* ??? */
		2615	WREG32_PLL(RADEON_MCLK_CNTL,
		2616	mclk_cntl);
		2617	udelay(10000);
		2618	#endif
		2619	WREG32_PLL
		2620	(RADEON_CLK_PWRMGT_CNTL,
		2621	tmp &
		2622	~RADEON_CG_NO1_DEBUG_0);
		2623	udelay(10000);
		2624	}
		2625	break;
		2626	default:
		2627	break;
		2628	}
		2629	break;
		2630	default:
		2631	break;
		2632	}
		2633	}
		2634	}
		2635	}
		2636
		2637	static void combios_parse_ram_reset_table(struct drm_device *dev,
		2638	uint16_t offset)
		2639	{
		2640	struct radeon_device *rdev = dev->dev_private;
		2641	uint32_t tmp;
		2642
		2643	if (offset) {
		2644	uint8_t val = RBIOS8(offset);
		2645	while (val != 0xff) {
		2646	offset++;
		2647
		2648	if (val == 0x0f) {
		2649	uint32_t channel_complete_mask;
		2650
		2651	if (ASIC_IS_R300(rdev))
		2652	channel_complete_mask =
		2653	R300_MEM_PWRUP_COMPLETE;
		2654	else
		2655	channel_complete_mask =
		2656	RADEON_MEM_PWRUP_COMPLETE;
		2657	tmp = 20000;
		2658	while (tmp--) {
		2659	if ((RREG32(RADEON_MEM_STR_CNTL) &
		2660	channel_complete_mask) ==
		2661	channel_complete_mask)
		2662	break;
		2663	}
		2664	} else {
		2665	uint32_t or_mask = RBIOS16(offset);
		2666	offset += 2;
		2667
		2668	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2669	tmp &= RADEON_SDRAM_MODE_MASK;
		2670	tmp \|= or_mask;
		2671	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		2672
		2673	or_mask = val << 24;
		2674	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2675	tmp &= RADEON_B3MEM_RESET_MASK;
		2676	tmp \|= or_mask;
		2677	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		2678	}
		2679	val = RBIOS8(offset);
		2680	}
		2681	}
		2682	}
		2683
		2684	static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
		2685	int mem_addr_mapping)
		2686	{
		2687	struct radeon_device *rdev = dev->dev_private;
		2688	uint32_t mem_cntl;
		2689	uint32_t mem_size;
		2690	uint32_t addr = 0;
		2691
		2692	mem_cntl = RREG32(RADEON_MEM_CNTL);
		2693	if (mem_cntl & RV100_HALF_MODE)
		2694	ram /= 2;
		2695	mem_size = ram;
		2696	mem_cntl &= ~(0xff << 8);
		2697	mem_cntl \|= (mem_addr_mapping & 0xff) << 8;
		2698	WREG32(RADEON_MEM_CNTL, mem_cntl);
		2699	RREG32(RADEON_MEM_CNTL);
		2700
		2701	/* sdram reset ? */
		2702
		2703	/* something like this???? */
		2704	while (ram--) {
		2705	addr = ram * 1024 * 1024;
		2706	/* write to each page */
		2707	WREG32(RADEON_MM_INDEX, (addr) \| RADEON_MM_APER);
		2708	WREG32(RADEON_MM_DATA, 0xdeadbeef);
		2709	/* read back and verify */
		2710	WREG32(RADEON_MM_INDEX, (addr) \| RADEON_MM_APER);
		2711	if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
		2712	return 0;
		2713	}
		2714
		2715	return mem_size;
		2716	}
		2717
		2718	static void combios_write_ram_size(struct drm_device *dev)
		2719	{
		2720	struct radeon_device *rdev = dev->dev_private;
		2721	uint8_t rev;
		2722	uint16_t offset;
		2723	uint32_t mem_size = 0;
		2724	uint32_t mem_cntl = 0;
		2725
		2726	/* should do something smarter here I guess... */
		2727	if (rdev->flags & RADEON_IS_IGP)
		2728	return;
		2729
		2730	/* first check detected mem table */
		2731	offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
		2732	if (offset) {
		2733	rev = RBIOS8(offset);
		2734	if (rev < 3) {
		2735	mem_cntl = RBIOS32(offset + 1);
		2736	mem_size = RBIOS16(offset + 5);
		2737	if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
		2738	((dev->pdev->device != 0x515e)
		2739	&& (dev->pdev->device != 0x5969)))
		2740	WREG32(RADEON_MEM_CNTL, mem_cntl);
		2741	}
		2742	}
		2743
		2744	if (!mem_size) {
		2745	offset =
		2746	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		2747	if (offset) {
		2748	rev = RBIOS8(offset - 1);
		2749	if (rev < 1) {
		2750	if (((rdev->flags & RADEON_FAMILY_MASK) <
		2751	CHIP_R200)
		2752	&& ((dev->pdev->device != 0x515e)
		2753	&& (dev->pdev->device != 0x5969))) {
		2754	int ram = 0;
		2755	int mem_addr_mapping = 0;
		2756
		2757	while (RBIOS8(offset)) {
		2758	ram = RBIOS8(offset);
		2759	mem_addr_mapping =
		2760	RBIOS8(offset + 1);
		2761	if (mem_addr_mapping != 0x25)
		2762	ram *= 2;
		2763	mem_size =
		2764	combios_detect_ram(dev, ram,
		2765	mem_addr_mapping);
		2766	if (mem_size)
		2767	break;
		2768	offset += 2;
		2769	}
		2770	} else
		2771	mem_size = RBIOS8(offset);
		2772	} else {
		2773	mem_size = RBIOS8(offset);
		2774	mem_size = 2; / convert to MB */
		2775	}
		2776	}
		2777	}
		2778
		2779	mem_size = (1024 1024); /* convert to bytes */
		2780	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
		2781	}
		2782
		2783	void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
		2784	{
		2785	uint16_t dyn_clk_info =
		2786	combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		2787
		2788	if (dyn_clk_info)
		2789	combios_parse_pll_table(dev, dyn_clk_info);
		2790	}
		2791
		2792	void radeon_combios_asic_init(struct drm_device *dev)
		2793	{
		2794	struct radeon_device *rdev = dev->dev_private;
		2795	uint16_t table;
		2796
		2797	/* port hardcoded mac stuff from radeonfb */
		2798	if (rdev->bios == NULL)
		2799	return;
		2800
		2801	/* ASIC INIT 1 */
		2802	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
		2803	if (table)
		2804	combios_parse_mmio_table(dev, table);
		2805
		2806	/* PLL INIT */
		2807	table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
		2808	if (table)
		2809	combios_parse_pll_table(dev, table);
		2810
		2811	/* ASIC INIT 2 */
		2812	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
		2813	if (table)
		2814	combios_parse_mmio_table(dev, table);
		2815
		2816	if (!(rdev->flags & RADEON_IS_IGP)) {
		2817	/* ASIC INIT 4 */
		2818	table =
		2819	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
		2820	if (table)
		2821	combios_parse_mmio_table(dev, table);
		2822
		2823	/* RAM RESET */
		2824	table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
		2825	if (table)
		2826	combios_parse_ram_reset_table(dev, table);
		2827
		2828	/* ASIC INIT 3 */
		2829	table =
		2830	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
		2831	if (table)
		2832	combios_parse_mmio_table(dev, table);
		2833
		2834	/* write CONFIG_MEMSIZE */
		2835	combios_write_ram_size(dev);
		2836	}
		2837
		2838	/* DYN CLK 1 */
		2839	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		2840	if (table)
		2841	combios_parse_pll_table(dev, table);
		2842
		2843	}
		2844
		2845	void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
		2846	{
		2847	struct radeon_device *rdev = dev->dev_private;
		2848	uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
		2849
		2850	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		2851	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2852	bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
		2853
		2854	/* let the bios control the backlight */
		2855	bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
		2856
		2857	/* tell the bios not to handle mode switching */
		2858	bios_6_scratch \|= (RADEON_DISPLAY_SWITCHING_DIS \|
		2859	RADEON_ACC_MODE_CHANGE);
		2860
		2861	/* tell the bios a driver is loaded */
		2862	bios_7_scratch \|= RADEON_DRV_LOADED;
		2863
		2864	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		2865	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2866	WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
		2867	}
		2868
		2869	void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
		2870	{
		2871	struct drm_device *dev = encoder->dev;
		2872	struct radeon_device *rdev = dev->dev_private;
		2873	uint32_t bios_6_scratch;
		2874
		2875	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2876
		2877	if (lock)
		2878	bios_6_scratch \|= RADEON_DRIVER_CRITICAL;
		2879	else
		2880	bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
		2881
		2882	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2883	}
		2884
		2885	void
		2886	radeon_combios_connected_scratch_regs(struct drm_connector *connector,
		2887	struct drm_encoder *encoder,
		2888	bool connected)
		2889	{
		2890	struct drm_device *dev = connector->dev;
		2891	struct radeon_device *rdev = dev->dev_private;
		2892	struct radeon_connector *radeon_connector =
		2893	to_radeon_connector(connector);
		2894	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2895	uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
		2896	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		2897
		2898	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		2899	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		2900	if (connected) {
		2901	DRM_DEBUG("TV1 connected\n");
		2902	/* fix me */
		2903	bios_4_scratch \|= RADEON_TV1_ATTACHED_SVIDEO;
		2904	/save->bios_4_scratch \|= RADEON_TV1_ATTACHED_COMP; /
		2905	bios_5_scratch \|= RADEON_TV1_ON;
		2906	bios_5_scratch \|= RADEON_ACC_REQ_TV1;
		2907	} else {
		2908	DRM_DEBUG("TV1 disconnected\n");
		2909	bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
		2910	bios_5_scratch &= ~RADEON_TV1_ON;
		2911	bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
		2912	}
		2913	}
		2914	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		2915	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		2916	if (connected) {
		2917	DRM_DEBUG("LCD1 connected\n");
		2918	bios_4_scratch \|= RADEON_LCD1_ATTACHED;
		2919	bios_5_scratch \|= RADEON_LCD1_ON;
		2920	bios_5_scratch \|= RADEON_ACC_REQ_LCD1;
		2921	} else {
		2922	DRM_DEBUG("LCD1 disconnected\n");
		2923	bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
		2924	bios_5_scratch &= ~RADEON_LCD1_ON;
		2925	bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
		2926	}
		2927	}
		2928	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		2929	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		2930	if (connected) {
		2931	DRM_DEBUG("CRT1 connected\n");
		2932	bios_4_scratch \|= RADEON_CRT1_ATTACHED_COLOR;
		2933	bios_5_scratch \|= RADEON_CRT1_ON;
		2934	bios_5_scratch \|= RADEON_ACC_REQ_CRT1;
		2935	} else {
		2936	DRM_DEBUG("CRT1 disconnected\n");
		2937	bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
		2938	bios_5_scratch &= ~RADEON_CRT1_ON;
		2939	bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
		2940	}
		2941	}
		2942	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		2943	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		2944	if (connected) {
		2945	DRM_DEBUG("CRT2 connected\n");
		2946	bios_4_scratch \|= RADEON_CRT2_ATTACHED_COLOR;
		2947	bios_5_scratch \|= RADEON_CRT2_ON;
		2948	bios_5_scratch \|= RADEON_ACC_REQ_CRT2;
		2949	} else {
		2950	DRM_DEBUG("CRT2 disconnected\n");
		2951	bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
		2952	bios_5_scratch &= ~RADEON_CRT2_ON;
		2953	bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
		2954	}
		2955	}
		2956	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		2957	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		2958	if (connected) {
		2959	DRM_DEBUG("DFP1 connected\n");
		2960	bios_4_scratch \|= RADEON_DFP1_ATTACHED;
		2961	bios_5_scratch \|= RADEON_DFP1_ON;
		2962	bios_5_scratch \|= RADEON_ACC_REQ_DFP1;
		2963	} else {
		2964	DRM_DEBUG("DFP1 disconnected\n");
		2965	bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
		2966	bios_5_scratch &= ~RADEON_DFP1_ON;
		2967	bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
		2968	}
		2969	}
		2970	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		2971	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		2972	if (connected) {
		2973	DRM_DEBUG("DFP2 connected\n");
		2974	bios_4_scratch \|= RADEON_DFP2_ATTACHED;
		2975	bios_5_scratch \|= RADEON_DFP2_ON;
		2976	bios_5_scratch \|= RADEON_ACC_REQ_DFP2;
		2977	} else {
		2978	DRM_DEBUG("DFP2 disconnected\n");
		2979	bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
		2980	bios_5_scratch &= ~RADEON_DFP2_ON;
		2981	bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
		2982	}
		2983	}
		2984	WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
		2985	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		2986	}
		2987
		2988	void
		2989	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		2990	{
		2991	struct drm_device *dev = encoder->dev;
		2992	struct radeon_device *rdev = dev->dev_private;
		2993	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2994	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		2995
		2996	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2997	bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
		2998	bios_5_scratch \|= (crtc << RADEON_TV1_CRTC_SHIFT);
		2999	}
		3000	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		3001	bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
		3002	bios_5_scratch \|= (crtc << RADEON_CRT1_CRTC_SHIFT);
		3003	}
		3004	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		3005	bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
		3006	bios_5_scratch \|= (crtc << RADEON_CRT2_CRTC_SHIFT);
		3007	}
		3008	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		3009	bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
		3010	bios_5_scratch \|= (crtc << RADEON_LCD1_CRTC_SHIFT);
		3011	}
		3012	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		3013	bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
		3014	bios_5_scratch \|= (crtc << RADEON_DFP1_CRTC_SHIFT);
		3015	}
		3016	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		3017	bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
		3018	bios_5_scratch \|= (crtc << RADEON_DFP2_CRTC_SHIFT);
		3019	}
		3020	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3021	}
		3022
		3023	void
		3024	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		3025	{
		3026	struct drm_device *dev = encoder->dev;
		3027	struct radeon_device *rdev = dev->dev_private;
		3028	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3029	uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3030
		3031	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
		3032	if (on)
		3033	bios_6_scratch \|= RADEON_TV_DPMS_ON;
		3034	else
		3035	bios_6_scratch &= ~RADEON_TV_DPMS_ON;
		3036	}
		3037	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
		3038	if (on)
		3039	bios_6_scratch \|= RADEON_CRT_DPMS_ON;
		3040	else
		3041	bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
		3042	}
		3043	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		3044	if (on)
		3045	bios_6_scratch \|= RADEON_LCD_DPMS_ON;
		3046	else
		3047	bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
		3048	}
		3049	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		3050	if (on)
		3051	bios_6_scratch \|= RADEON_DFP_DPMS_ON;
		3052	else
		3053	bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
		3054	}
		3055	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3056	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_combios.c – Rev 1404