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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1123 | serge | 28 | #include "drmP.h" |
| 1117 | serge | 29 | #include "radeon_drm.h" |
| 30 | #include "radeon_reg.h" |
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| 31 | #include "radeon.h" |
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| 32 | #include "atom.h" |
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| 33 | |||
| 34 | /* 10 khz */ |
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| 1268 | serge | 35 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) |
| 1117 | serge | 36 | { |
| 37 | struct radeon_pll *spll = &rdev->clock.spll; |
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| 38 | uint32_t fb_div, ref_div, post_div, sclk; |
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| 39 | |||
| 40 | fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
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| 41 | fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; |
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| 42 | fb_div <<= 1; |
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| 43 | fb_div *= spll->reference_freq; |
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| 44 | |||
| 45 | ref_div = |
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| 46 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
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| 1321 | serge | 47 | |
| 48 | if (ref_div == 0) |
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| 49 | return 0; |
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| 50 | |||
| 1117 | serge | 51 | sclk = fb_div / ref_div; |
| 52 | |||
| 53 | post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; |
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| 54 | if (post_div == 2) |
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| 55 | sclk >>= 1; |
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| 56 | else if (post_div == 3) |
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| 57 | sclk >>= 2; |
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| 58 | else if (post_div == 4) |
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| 1403 | serge | 59 | sclk >>= 3; |
| 1117 | serge | 60 | |
| 61 | return sclk; |
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| 62 | } |
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| 63 | |||
| 64 | /* 10 khz */ |
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| 1403 | serge | 65 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) |
| 1117 | serge | 66 | { |
| 67 | struct radeon_pll *mpll = &rdev->clock.mpll; |
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| 68 | uint32_t fb_div, ref_div, post_div, mclk; |
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| 69 | |||
| 70 | fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
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| 71 | fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; |
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| 72 | fb_div <<= 1; |
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| 73 | fb_div *= mpll->reference_freq; |
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| 74 | |||
| 75 | ref_div = |
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| 76 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
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| 1321 | serge | 77 | |
| 78 | if (ref_div == 0) |
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| 79 | return 0; |
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| 80 | |||
| 1117 | serge | 81 | mclk = fb_div / ref_div; |
| 82 | |||
| 83 | post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; |
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| 84 | if (post_div == 2) |
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| 85 | mclk >>= 1; |
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| 86 | else if (post_div == 3) |
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| 87 | mclk >>= 2; |
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| 88 | else if (post_div == 4) |
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| 1403 | serge | 89 | mclk >>= 3; |
| 1117 | serge | 90 | |
| 91 | return mclk; |
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| 92 | } |
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| 93 | |||
| 94 | void radeon_get_clock_info(struct drm_device *dev) |
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| 95 | { |
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| 96 | struct radeon_device *rdev = dev->dev_private; |
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| 97 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
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| 98 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
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| 99 | struct radeon_pll *spll = &rdev->clock.spll; |
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| 100 | struct radeon_pll *mpll = &rdev->clock.mpll; |
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| 101 | int ret; |
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| 102 | |||
| 103 | if (rdev->is_atom_bios) |
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| 104 | ret = radeon_atom_get_clock_info(dev); |
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| 1128 | serge | 105 | else |
| 106 | ret = radeon_combios_get_clock_info(dev); |
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| 1117 | serge | 107 | |
| 108 | if (ret) { |
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| 1321 | serge | 109 | if (p1pll->reference_div < 2) { |
| 110 | if (!ASIC_IS_AVIVO(rdev)) { |
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| 111 | u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); |
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| 112 | if (ASIC_IS_R300(rdev)) |
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| 113 | p1pll->reference_div = |
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| 114 | (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; |
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| 115 | else |
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| 116 | p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; |
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| 1117 | serge | 117 | if (p1pll->reference_div < 2) |
| 118 | p1pll->reference_div = 12; |
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| 1321 | serge | 119 | } else |
| 120 | p1pll->reference_div = 12; |
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| 121 | } |
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| 1117 | serge | 122 | if (p2pll->reference_div < 2) |
| 123 | p2pll->reference_div = 12; |
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| 1179 | serge | 124 | if (rdev->family < CHIP_RS600) { |
| 1117 | serge | 125 | if (spll->reference_div < 2) |
| 126 | spll->reference_div = |
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| 127 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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| 128 | RADEON_M_SPLL_REF_DIV_MASK; |
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| 1179 | serge | 129 | } |
| 1117 | serge | 130 | if (mpll->reference_div < 2) |
| 131 | mpll->reference_div = spll->reference_div; |
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| 132 | } else { |
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| 133 | if (ASIC_IS_AVIVO(rdev)) { |
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| 134 | /* TODO FALLBACK */ |
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| 135 | } else { |
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| 136 | DRM_INFO("Using generic clock info\n"); |
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| 137 | |||
| 138 | if (rdev->flags & RADEON_IS_IGP) { |
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| 139 | p1pll->reference_freq = 1432; |
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| 140 | p2pll->reference_freq = 1432; |
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| 141 | spll->reference_freq = 1432; |
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| 142 | mpll->reference_freq = 1432; |
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| 143 | } else { |
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| 144 | p1pll->reference_freq = 2700; |
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| 145 | p2pll->reference_freq = 2700; |
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| 146 | spll->reference_freq = 2700; |
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| 147 | mpll->reference_freq = 2700; |
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| 148 | } |
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| 149 | p1pll->reference_div = |
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| 150 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
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| 151 | if (p1pll->reference_div < 2) |
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| 152 | p1pll->reference_div = 12; |
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| 153 | p2pll->reference_div = p1pll->reference_div; |
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| 154 | |||
| 155 | if (rdev->family >= CHIP_R420) { |
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| 156 | p1pll->pll_in_min = 100; |
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| 157 | p1pll->pll_in_max = 1350; |
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| 158 | p1pll->pll_out_min = 20000; |
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| 159 | p1pll->pll_out_max = 50000; |
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| 160 | p2pll->pll_in_min = 100; |
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| 161 | p2pll->pll_in_max = 1350; |
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| 162 | p2pll->pll_out_min = 20000; |
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| 163 | p2pll->pll_out_max = 50000; |
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| 164 | } else { |
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| 165 | p1pll->pll_in_min = 40; |
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| 166 | p1pll->pll_in_max = 500; |
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| 167 | p1pll->pll_out_min = 12500; |
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| 168 | p1pll->pll_out_max = 35000; |
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| 169 | p2pll->pll_in_min = 40; |
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| 170 | p2pll->pll_in_max = 500; |
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| 171 | p2pll->pll_out_min = 12500; |
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| 172 | p2pll->pll_out_max = 35000; |
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| 173 | } |
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| 174 | |||
| 175 | spll->reference_div = |
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| 176 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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| 177 | RADEON_M_SPLL_REF_DIV_MASK; |
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| 178 | mpll->reference_div = spll->reference_div; |
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| 179 | rdev->clock.default_sclk = |
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| 180 | radeon_legacy_get_engine_clock(rdev); |
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| 181 | rdev->clock.default_mclk = |
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| 182 | radeon_legacy_get_memory_clock(rdev); |
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| 183 | } |
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| 184 | } |
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| 185 | |||
| 186 | /* pixel clocks */ |
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| 187 | if (ASIC_IS_AVIVO(rdev)) { |
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| 188 | p1pll->min_post_div = 2; |
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| 189 | p1pll->max_post_div = 0x7f; |
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| 190 | p1pll->min_frac_feedback_div = 0; |
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| 191 | p1pll->max_frac_feedback_div = 9; |
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| 192 | p2pll->min_post_div = 2; |
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| 193 | p2pll->max_post_div = 0x7f; |
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| 194 | p2pll->min_frac_feedback_div = 0; |
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| 195 | p2pll->max_frac_feedback_div = 9; |
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| 196 | } else { |
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| 197 | p1pll->min_post_div = 1; |
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| 198 | p1pll->max_post_div = 16; |
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| 199 | p1pll->min_frac_feedback_div = 0; |
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| 200 | p1pll->max_frac_feedback_div = 0; |
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| 201 | p2pll->min_post_div = 1; |
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| 202 | p2pll->max_post_div = 12; |
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| 203 | p2pll->min_frac_feedback_div = 0; |
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| 204 | p2pll->max_frac_feedback_div = 0; |
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| 205 | } |
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| 206 | |||
| 207 | p1pll->min_ref_div = 2; |
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| 208 | p1pll->max_ref_div = 0x3ff; |
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| 209 | p1pll->min_feedback_div = 4; |
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| 210 | p1pll->max_feedback_div = 0x7ff; |
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| 211 | p1pll->best_vco = 0; |
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| 212 | |||
| 213 | p2pll->min_ref_div = 2; |
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| 214 | p2pll->max_ref_div = 0x3ff; |
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| 215 | p2pll->min_feedback_div = 4; |
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| 216 | p2pll->max_feedback_div = 0x7ff; |
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| 217 | p2pll->best_vco = 0; |
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| 218 | |||
| 219 | /* system clock */ |
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| 220 | spll->min_post_div = 1; |
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| 221 | spll->max_post_div = 1; |
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| 222 | spll->min_ref_div = 2; |
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| 223 | spll->max_ref_div = 0xff; |
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| 224 | spll->min_feedback_div = 4; |
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| 225 | spll->max_feedback_div = 0xff; |
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| 226 | spll->best_vco = 0; |
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| 227 | |||
| 228 | /* memory clock */ |
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| 229 | mpll->min_post_div = 1; |
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| 230 | mpll->max_post_div = 1; |
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| 231 | mpll->min_ref_div = 2; |
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| 232 | mpll->max_ref_div = 0xff; |
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| 233 | mpll->min_feedback_div = 4; |
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| 234 | mpll->max_feedback_div = 0xff; |
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| 235 | mpll->best_vco = 0; |
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| 236 | |||
| 237 | } |
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| 238 | |||
| 239 | /* 10 khz */ |
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| 240 | static uint32_t calc_eng_mem_clock(struct radeon_device *rdev, |
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| 241 | uint32_t req_clock, |
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| 242 | int *fb_div, int *post_div) |
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| 243 | { |
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| 244 | struct radeon_pll *spll = &rdev->clock.spll; |
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| 245 | int ref_div = spll->reference_div; |
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| 246 | |||
| 247 | if (!ref_div) |
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| 248 | ref_div = |
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| 249 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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| 250 | RADEON_M_SPLL_REF_DIV_MASK; |
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| 251 | |||
| 252 | if (req_clock < 15000) { |
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| 253 | *post_div = 8; |
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| 254 | req_clock *= 8; |
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| 255 | } else if (req_clock < 30000) { |
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| 256 | *post_div = 4; |
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| 257 | req_clock *= 4; |
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| 258 | } else if (req_clock < 60000) { |
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| 259 | *post_div = 2; |
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| 260 | req_clock *= 2; |
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| 261 | } else |
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| 262 | *post_div = 1; |
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| 263 | |||
| 264 | req_clock *= ref_div; |
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| 265 | req_clock += spll->reference_freq; |
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| 266 | req_clock /= (2 * spll->reference_freq); |
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| 267 | |||
| 268 | *fb_div = req_clock & 0xff; |
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| 269 | |||
| 270 | req_clock = (req_clock & 0xffff) << 1; |
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| 271 | req_clock *= spll->reference_freq; |
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| 272 | req_clock /= ref_div; |
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| 273 | req_clock /= *post_div; |
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| 274 | |||
| 275 | return req_clock; |
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| 276 | } |
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| 277 | |||
| 278 | /* 10 khz */ |
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| 279 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, |
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| 280 | uint32_t eng_clock) |
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| 281 | { |
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| 282 | uint32_t tmp; |
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| 283 | int fb_div, post_div; |
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| 284 | |||
| 285 | /* XXX: wait for idle */ |
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| 286 | |||
| 287 | eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); |
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| 288 | |||
| 289 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
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| 290 | tmp &= ~RADEON_DONT_USE_XTALIN; |
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| 291 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
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| 292 | |||
| 293 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
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| 294 | tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
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| 295 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
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| 296 | |||
| 297 | udelay(10); |
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| 298 | |||
| 299 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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| 300 | tmp |= RADEON_SPLL_SLEEP; |
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| 301 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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| 302 | |||
| 303 | udelay(2); |
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| 304 | |||
| 305 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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| 306 | tmp |= RADEON_SPLL_RESET; |
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| 307 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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| 308 | |||
| 309 | udelay(200); |
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| 310 | |||
| 311 | tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
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| 312 | tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); |
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| 313 | tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; |
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| 314 | WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); |
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| 315 | |||
| 316 | /* XXX: verify on different asics */ |
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| 317 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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| 318 | tmp &= ~RADEON_SPLL_PVG_MASK; |
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| 319 | if ((eng_clock * post_div) >= 90000) |
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| 320 | tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); |
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| 321 | else |
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| 322 | tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); |
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| 323 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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| 324 | |||
| 325 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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| 326 | tmp &= ~RADEON_SPLL_SLEEP; |
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| 327 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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| 328 | |||
| 329 | udelay(2); |
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| 330 | |||
| 331 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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| 332 | tmp &= ~RADEON_SPLL_RESET; |
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| 333 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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| 334 | |||
| 335 | udelay(200); |
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| 336 | |||
| 337 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
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| 338 | tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
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| 339 | switch (post_div) { |
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| 340 | case 1: |
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| 341 | default: |
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| 342 | tmp |= 1; |
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| 343 | break; |
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| 344 | case 2: |
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| 345 | tmp |= 2; |
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| 346 | break; |
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| 347 | case 4: |
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| 348 | tmp |= 3; |
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| 349 | break; |
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| 350 | case 8: |
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| 351 | tmp |= 4; |
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| 352 | break; |
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| 353 | } |
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| 354 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
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| 355 | |||
| 356 | udelay(20); |
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| 357 | |||
| 358 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
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| 359 | tmp |= RADEON_DONT_USE_XTALIN; |
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| 360 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
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| 361 | |||
| 362 | udelay(10); |
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| 363 | } |
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| 364 | |||
| 365 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) |
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| 366 | { |
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| 367 | uint32_t tmp; |
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| 368 | |||
| 369 | if (enable) { |
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| 370 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
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| 371 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
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| 372 | if ((RREG32(RADEON_CONFIG_CNTL) & |
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| 373 | RADEON_CFG_ATI_REV_ID_MASK) > |
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| 374 | RADEON_CFG_ATI_REV_A13) { |
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| 375 | tmp &= |
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| 376 | ~(RADEON_SCLK_FORCE_CP | |
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| 377 | RADEON_SCLK_FORCE_RB); |
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| 378 | } |
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| 379 | tmp &= |
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| 380 | ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | |
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| 381 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | |
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| 382 | RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | |
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| 383 | RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | |
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| 384 | RADEON_SCLK_FORCE_TDM); |
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| 385 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
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| 386 | } else if (ASIC_IS_R300(rdev)) { |
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| 387 | if ((rdev->family == CHIP_RS400) || |
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| 388 | (rdev->family == CHIP_RS480)) { |
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| 389 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
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| 390 | tmp &= |
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| 391 | ~(RADEON_SCLK_FORCE_DISP2 | |
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| 392 | RADEON_SCLK_FORCE_CP | |
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| 393 | RADEON_SCLK_FORCE_HDP | |
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| 394 | RADEON_SCLK_FORCE_DISP1 | |
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| 395 | RADEON_SCLK_FORCE_TOP | |
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| 396 | RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
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| 397 | | RADEON_SCLK_FORCE_IDCT | |
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| 398 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
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| 399 | | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
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| 400 | | R300_SCLK_FORCE_US | |
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| 401 | RADEON_SCLK_FORCE_TV_SCLK | |
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| 402 | R300_SCLK_FORCE_SU | |
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| 403 | RADEON_SCLK_FORCE_OV0); |
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| 404 | tmp |= RADEON_DYN_STOP_LAT_MASK; |
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| 405 | tmp |= |
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| 406 | RADEON_SCLK_FORCE_TOP | |
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| 407 | RADEON_SCLK_FORCE_VIP; |
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| 408 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
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| 409 | |||
| 410 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
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| 411 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
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| 412 | tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
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| 413 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
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| 414 | |||
| 415 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
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| 416 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
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| 417 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
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| 418 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
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| 419 | |||
| 420 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
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| 421 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
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| 422 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
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| 423 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
| 424 | R300_DVOCLK_ALWAYS_ONb | |
||
| 425 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
| 426 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
| 427 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
| 428 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
| 429 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
| 430 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
| 431 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
| 432 | R300_P2G2CLK_ALWAYS_ONb | |
||
| 1221 | serge | 433 | R300_P2G2CLK_DAC_ALWAYS_ONb); |
| 1117 | serge | 434 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 435 | } else if (rdev->family >= CHIP_RV350) { |
||
| 436 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
| 437 | tmp &= ~(R300_SCLK_FORCE_TCL | |
||
| 438 | R300_SCLK_FORCE_GA | |
||
| 439 | R300_SCLK_FORCE_CBA); |
||
| 440 | tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | |
||
| 441 | R300_SCLK_GA_MAX_DYN_STOP_LAT | |
||
| 442 | R300_SCLK_CBA_MAX_DYN_STOP_LAT); |
||
| 443 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
| 444 | |||
| 445 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 446 | tmp &= |
||
| 447 | ~(RADEON_SCLK_FORCE_DISP2 | |
||
| 448 | RADEON_SCLK_FORCE_CP | |
||
| 449 | RADEON_SCLK_FORCE_HDP | |
||
| 450 | RADEON_SCLK_FORCE_DISP1 | |
||
| 451 | RADEON_SCLK_FORCE_TOP | |
||
| 452 | RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
||
| 453 | | RADEON_SCLK_FORCE_IDCT | |
||
| 454 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
||
| 455 | | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
||
| 456 | | R300_SCLK_FORCE_US | |
||
| 457 | RADEON_SCLK_FORCE_TV_SCLK | |
||
| 458 | R300_SCLK_FORCE_SU | |
||
| 459 | RADEON_SCLK_FORCE_OV0); |
||
| 460 | tmp |= RADEON_DYN_STOP_LAT_MASK; |
||
| 461 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 462 | |||
| 463 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
| 464 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
||
| 465 | tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
||
| 466 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
| 467 | |||
| 468 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
| 469 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
||
| 470 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
| 471 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
| 472 | |||
| 473 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
| 474 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
||
| 475 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
| 476 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
| 477 | R300_DVOCLK_ALWAYS_ONb | |
||
| 478 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
| 479 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
| 480 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
| 481 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
| 482 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
| 483 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
| 484 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
| 485 | R300_P2G2CLK_ALWAYS_ONb | |
||
| 1221 | serge | 486 | R300_P2G2CLK_DAC_ALWAYS_ONb); |
| 1117 | serge | 487 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 488 | |||
| 489 | tmp = RREG32_PLL(RADEON_MCLK_MISC); |
||
| 490 | tmp |= (RADEON_MC_MCLK_DYN_ENABLE | |
||
| 491 | RADEON_IO_MCLK_DYN_ENABLE); |
||
| 492 | WREG32_PLL(RADEON_MCLK_MISC, tmp); |
||
| 493 | |||
| 494 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
| 495 | tmp |= (RADEON_FORCEON_MCLKA | |
||
| 496 | RADEON_FORCEON_MCLKB); |
||
| 497 | |||
| 498 | tmp &= ~(RADEON_FORCEON_YCLKA | |
||
| 499 | RADEON_FORCEON_YCLKB | |
||
| 500 | RADEON_FORCEON_MC); |
||
| 501 | |||
| 502 | /* Some releases of vbios have set DISABLE_MC_MCLKA |
||
| 503 | and DISABLE_MC_MCLKB bits in the vbios table. Setting these |
||
| 504 | bits will cause H/W hang when reading video memory with dynamic clocking |
||
| 505 | enabled. */ |
||
| 506 | if ((tmp & R300_DISABLE_MC_MCLKA) && |
||
| 507 | (tmp & R300_DISABLE_MC_MCLKB)) { |
||
| 508 | /* If both bits are set, then check the active channels */ |
||
| 509 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
| 510 | if (rdev->mc.vram_width == 64) { |
||
| 511 | if (RREG32(RADEON_MEM_CNTL) & |
||
| 512 | R300_MEM_USE_CD_CH_ONLY) |
||
| 513 | tmp &= |
||
| 514 | ~R300_DISABLE_MC_MCLKB; |
||
| 515 | else |
||
| 516 | tmp &= |
||
| 517 | ~R300_DISABLE_MC_MCLKA; |
||
| 518 | } else { |
||
| 519 | tmp &= ~(R300_DISABLE_MC_MCLKA | |
||
| 520 | R300_DISABLE_MC_MCLKB); |
||
| 521 | } |
||
| 522 | } |
||
| 523 | |||
| 524 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
||
| 525 | } else { |
||
| 526 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 527 | tmp &= ~(R300_SCLK_FORCE_VAP); |
||
| 528 | tmp |= RADEON_SCLK_FORCE_CP; |
||
| 529 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 530 | udelay(15000); |
||
| 531 | |||
| 532 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
| 533 | tmp &= ~(R300_SCLK_FORCE_TCL | |
||
| 534 | R300_SCLK_FORCE_GA | |
||
| 535 | R300_SCLK_FORCE_CBA); |
||
| 536 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
| 537 | } |
||
| 538 | } else { |
||
| 539 | tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
||
| 540 | |||
| 541 | tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | |
||
| 542 | RADEON_DISP_DYN_STOP_LAT_MASK | |
||
| 543 | RADEON_DYN_STOP_MODE_MASK); |
||
| 544 | |||
| 545 | tmp |= (RADEON_ENGIN_DYNCLK_MODE | |
||
| 546 | (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); |
||
| 547 | WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); |
||
| 548 | udelay(15000); |
||
| 549 | |||
| 550 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
||
| 551 | tmp |= RADEON_SCLK_DYN_START_CNTL; |
||
| 552 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
||
| 553 | udelay(15000); |
||
| 554 | |||
| 555 | /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 |
||
| 556 | to lockup randomly, leave them as set by BIOS. |
||
| 557 | */ |
||
| 558 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 559 | /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */ |
||
| 560 | tmp &= ~RADEON_SCLK_FORCEON_MASK; |
||
| 561 | |||
| 562 | /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */ |
||
| 563 | if (((rdev->family == CHIP_RV250) && |
||
| 564 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
| 565 | RADEON_CFG_ATI_REV_ID_MASK) < |
||
| 566 | RADEON_CFG_ATI_REV_A13)) |
||
| 567 | || ((rdev->family == CHIP_RV100) |
||
| 568 | && |
||
| 569 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
| 570 | RADEON_CFG_ATI_REV_ID_MASK) <= |
||
| 571 | RADEON_CFG_ATI_REV_A13))) { |
||
| 572 | tmp |= RADEON_SCLK_FORCE_CP; |
||
| 573 | tmp |= RADEON_SCLK_FORCE_VIP; |
||
| 574 | } |
||
| 575 | |||
| 576 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 577 | |||
| 578 | if ((rdev->family == CHIP_RV200) || |
||
| 579 | (rdev->family == CHIP_RV250) || |
||
| 580 | (rdev->family == CHIP_RV280)) { |
||
| 581 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
| 582 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
||
| 583 | |||
| 584 | /* RV200::A11 A12 RV250::A11 A12 */ |
||
| 585 | if (((rdev->family == CHIP_RV200) || |
||
| 586 | (rdev->family == CHIP_RV250)) && |
||
| 587 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
| 588 | RADEON_CFG_ATI_REV_ID_MASK) < |
||
| 589 | RADEON_CFG_ATI_REV_A13)) { |
||
| 590 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
| 591 | } |
||
| 592 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
| 593 | udelay(15000); |
||
| 594 | } |
||
| 595 | |||
| 596 | /* RV200::A11 A12, RV250::A11 A12 */ |
||
| 597 | if (((rdev->family == CHIP_RV200) || |
||
| 598 | (rdev->family == CHIP_RV250)) && |
||
| 599 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
| 600 | RADEON_CFG_ATI_REV_ID_MASK) < |
||
| 601 | RADEON_CFG_ATI_REV_A13)) { |
||
| 602 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
||
| 603 | tmp |= RADEON_TCL_BYPASS_DISABLE; |
||
| 604 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
||
| 605 | } |
||
| 606 | udelay(15000); |
||
| 607 | |||
| 608 | /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ |
||
| 609 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
| 610 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
||
| 611 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
| 612 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
| 613 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
| 614 | RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
||
| 615 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
| 616 | RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
||
| 617 | |||
| 618 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
| 619 | udelay(15000); |
||
| 620 | |||
| 621 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
| 622 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
||
| 623 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
| 624 | |||
| 625 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
| 626 | udelay(15000); |
||
| 627 | } |
||
| 628 | } else { |
||
| 629 | /* Turn everything OFF (ForceON to everything) */ |
||
| 630 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
| 631 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 632 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | |
||
| 633 | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
||
| 634 | | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | |
||
| 635 | RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | |
||
| 636 | RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | |
||
| 637 | RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | |
||
| 638 | RADEON_SCLK_FORCE_RB); |
||
| 639 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 640 | } else if ((rdev->family == CHIP_RS400) || |
||
| 641 | (rdev->family == CHIP_RS480)) { |
||
| 642 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 643 | tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
||
| 644 | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
||
| 645 | | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
||
| 646 | R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
||
| 647 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
||
| 648 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
||
| 649 | R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
||
| 650 | R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
||
| 651 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 652 | |||
| 653 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
| 654 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
| 655 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
| 656 | |||
| 657 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
| 658 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
||
| 659 | RADEON_PIXCLK_DAC_ALWAYS_ONb | |
||
| 660 | R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
||
| 661 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
| 662 | |||
| 663 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
| 664 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
||
| 665 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
| 666 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
| 667 | R300_DVOCLK_ALWAYS_ONb | |
||
| 668 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
| 669 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
| 670 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
| 671 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
| 672 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
| 673 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
| 674 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
| 675 | R300_P2G2CLK_ALWAYS_ONb | |
||
| 1221 | serge | 676 | R300_P2G2CLK_DAC_ALWAYS_ONb | |
| 1117 | serge | 677 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| 678 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
| 679 | } else if (rdev->family >= CHIP_RV350) { |
||
| 680 | /* for RV350/M10, no delays are required. */ |
||
| 681 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
| 682 | tmp |= (R300_SCLK_FORCE_TCL | |
||
| 683 | R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); |
||
| 684 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
| 685 | |||
| 686 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 687 | tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
||
| 688 | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
||
| 689 | | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
||
| 690 | R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
||
| 691 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
||
| 692 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
||
| 693 | R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
||
| 694 | R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
||
| 695 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 696 | |||
| 697 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
| 698 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
| 699 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
| 700 | |||
| 701 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
| 702 | tmp |= (RADEON_FORCEON_MCLKA | |
||
| 703 | RADEON_FORCEON_MCLKB | |
||
| 704 | RADEON_FORCEON_YCLKA | |
||
| 705 | RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC); |
||
| 706 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
||
| 707 | |||
| 708 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
| 709 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
||
| 710 | RADEON_PIXCLK_DAC_ALWAYS_ONb | |
||
| 711 | R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
||
| 712 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
| 713 | |||
| 714 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
| 715 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
||
| 716 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
| 717 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
| 718 | R300_DVOCLK_ALWAYS_ONb | |
||
| 719 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
| 720 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
| 721 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
| 722 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
| 723 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
| 724 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
| 725 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
| 726 | R300_P2G2CLK_ALWAYS_ONb | |
||
| 1221 | serge | 727 | R300_P2G2CLK_DAC_ALWAYS_ONb | |
| 1117 | serge | 728 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| 729 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
| 730 | } else { |
||
| 731 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 732 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); |
||
| 733 | tmp |= RADEON_SCLK_FORCE_SE; |
||
| 734 | |||
| 735 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
| 736 | tmp |= (RADEON_SCLK_FORCE_RB | |
||
| 737 | RADEON_SCLK_FORCE_TDM | |
||
| 738 | RADEON_SCLK_FORCE_TAM | |
||
| 739 | RADEON_SCLK_FORCE_PB | |
||
| 740 | RADEON_SCLK_FORCE_RE | |
||
| 741 | RADEON_SCLK_FORCE_VIP | |
||
| 742 | RADEON_SCLK_FORCE_IDCT | |
||
| 743 | RADEON_SCLK_FORCE_TOP | |
||
| 744 | RADEON_SCLK_FORCE_DISP1 | |
||
| 745 | RADEON_SCLK_FORCE_DISP2 | |
||
| 746 | RADEON_SCLK_FORCE_HDP); |
||
| 747 | } else if ((rdev->family == CHIP_R300) || |
||
| 748 | (rdev->family == CHIP_R350)) { |
||
| 749 | tmp |= (RADEON_SCLK_FORCE_HDP | |
||
| 750 | RADEON_SCLK_FORCE_DISP1 | |
||
| 751 | RADEON_SCLK_FORCE_DISP2 | |
||
| 752 | RADEON_SCLK_FORCE_TOP | |
||
| 753 | RADEON_SCLK_FORCE_IDCT | |
||
| 754 | RADEON_SCLK_FORCE_VIP); |
||
| 755 | } |
||
| 756 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 757 | |||
| 758 | udelay(16000); |
||
| 759 | |||
| 760 | if ((rdev->family == CHIP_R300) || |
||
| 761 | (rdev->family == CHIP_R350)) { |
||
| 762 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
| 763 | tmp |= (R300_SCLK_FORCE_TCL | |
||
| 764 | R300_SCLK_FORCE_GA | |
||
| 765 | R300_SCLK_FORCE_CBA); |
||
| 766 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
| 767 | udelay(16000); |
||
| 768 | } |
||
| 769 | |||
| 770 | if (rdev->flags & RADEON_IS_IGP) { |
||
| 771 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
| 772 | tmp &= ~(RADEON_FORCEON_MCLKA | |
||
| 773 | RADEON_FORCEON_YCLKA); |
||
| 774 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
||
| 775 | udelay(16000); |
||
| 776 | } |
||
| 777 | |||
| 778 | if ((rdev->family == CHIP_RV200) || |
||
| 779 | (rdev->family == CHIP_RV250) || |
||
| 780 | (rdev->family == CHIP_RV280)) { |
||
| 781 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
| 782 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
| 783 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
| 784 | udelay(16000); |
||
| 785 | } |
||
| 786 | |||
| 787 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
| 788 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
||
| 789 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
| 790 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
| 791 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
| 792 | RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
||
| 793 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
| 794 | RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
||
| 795 | |||
| 796 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
| 797 | udelay(16000); |
||
| 798 | |||
| 799 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
| 800 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
||
| 801 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
| 802 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
| 803 | } |
||
| 804 | } |
||
| 805 | } |
||
| 806 | |||
| 807 | static void radeon_apply_clock_quirks(struct radeon_device *rdev) |
||
| 808 | { |
||
| 809 | uint32_t tmp; |
||
| 810 | |||
| 811 | /* XXX make sure engine is idle */ |
||
| 812 | |||
| 813 | if (rdev->family < CHIP_RS600) { |
||
| 814 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
| 815 | if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev)) |
||
| 816 | tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; |
||
| 817 | if ((rdev->family == CHIP_RV250) |
||
| 818 | || (rdev->family == CHIP_RV280)) |
||
| 819 | tmp |= |
||
| 820 | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2; |
||
| 821 | if ((rdev->family == CHIP_RV350) |
||
| 822 | || (rdev->family == CHIP_RV380)) |
||
| 823 | tmp |= R300_SCLK_FORCE_VAP; |
||
| 824 | if (rdev->family == CHIP_R420) |
||
| 825 | tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX; |
||
| 826 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
| 827 | } else if (rdev->family < CHIP_R600) { |
||
| 828 | tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL); |
||
| 829 | tmp |= AVIVO_CP_FORCEON; |
||
| 830 | WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp); |
||
| 831 | |||
| 832 | tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL); |
||
| 833 | tmp |= AVIVO_E2_FORCEON; |
||
| 834 | WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp); |
||
| 835 | |||
| 836 | tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL); |
||
| 837 | tmp |= AVIVO_IDCT_FORCEON; |
||
| 838 | WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp); |
||
| 839 | } |
||
| 840 | } |
||
| 841 | |||
| 842 | int radeon_static_clocks_init(struct drm_device *dev) |
||
| 843 | { |
||
| 844 | struct radeon_device *rdev = dev->dev_private; |
||
| 845 | |||
| 846 | /* XXX make sure engine is idle */ |
||
| 847 | |||
| 848 | if (radeon_dynclks != -1) { |
||
| 849 | if (radeon_dynclks) |
||
| 850 | radeon_set_clock_gating(rdev, 1); |
||
| 851 | } |
||
| 852 | radeon_apply_clock_quirks(rdev); |
||
| 853 | return 0; |
||
| 854 | } |