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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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2997 | Serge | 28 | #include |
1117 | serge | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" |
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31 | #include "atom.h" |
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32 | |||
1963 | serge | 33 | //#include |
34 | #include |
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1117 | serge | 35 | /* |
36 | * BIOS. |
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37 | */ |
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1233 | serge | 38 | |
39 | /* If you boot an IGP board with a discrete card as the primary, |
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40 | * the IGP rom is not accessible via the rom bar as the IGP rom is |
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41 | * part of the system bios. On boot, the system bios puts a |
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42 | * copy of the igp rom at the start of vram if a discrete card is |
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43 | * present. |
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44 | */ |
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45 | static bool igp_read_bios_from_vram(struct radeon_device *rdev) |
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46 | { |
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47 | uint8_t __iomem *bios; |
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48 | resource_size_t vram_base; |
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49 | resource_size_t size = 256 * 1024; /* ??? */ |
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50 | |||
1963 | serge | 51 | if (!(rdev->flags & RADEON_IS_IGP)) |
52 | if (!radeon_card_posted(rdev)) |
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53 | return false; |
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54 | |||
1233 | serge | 55 | rdev->bios = NULL; |
1963 | serge | 56 | vram_base = pci_resource_start(rdev->pdev, 0); |
1233 | serge | 57 | bios = ioremap(vram_base, size); |
58 | if (!bios) { |
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59 | return false; |
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60 | } |
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61 | |||
62 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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63 | iounmap(bios); |
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64 | return false; |
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65 | } |
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66 | rdev->bios = kmalloc(size, GFP_KERNEL); |
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67 | if (rdev->bios == NULL) { |
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68 | iounmap(bios); |
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69 | return false; |
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70 | } |
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71 | memcpy(rdev->bios, bios, size); |
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72 | iounmap(bios); |
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73 | return true; |
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74 | } |
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75 | |||
1117 | serge | 76 | static bool radeon_read_bios(struct radeon_device *rdev) |
77 | { |
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1179 | serge | 78 | uint8_t __iomem *bios; |
1117 | serge | 79 | size_t size; |
80 | |||
81 | rdev->bios = NULL; |
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1221 | serge | 82 | /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
83 | bios = pci_map_rom(rdev->pdev, &size); |
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1117 | serge | 84 | if (!bios) { |
85 | return false; |
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86 | } |
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87 | |||
88 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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89 | // pci_unmap_rom(rdev->pdev, bios); |
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90 | return false; |
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91 | } |
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1179 | serge | 92 | rdev->bios = kmalloc(size, GFP_KERNEL); |
1117 | serge | 93 | if (rdev->bios == NULL) { |
94 | return false; |
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95 | } |
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96 | memcpy(rdev->bios, bios, size); |
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97 | return true; |
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98 | } |
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99 | |||
2997 | Serge | 100 | #ifdef CONFIG_ACPI |
1430 | serge | 101 | /* ATRM is used to get the BIOS on the discrete cards in |
102 | * dual-gpu systems. |
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103 | */ |
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2997 | Serge | 104 | /* retrieve the ROM in 4k blocks */ |
105 | #define ATRM_BIOS_PAGE 4096 |
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106 | /** |
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107 | * radeon_atrm_call - fetch a chunk of the vbios |
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108 | * |
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109 | * @atrm_handle: acpi ATRM handle |
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110 | * @bios: vbios image pointer |
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111 | * @offset: offset of vbios image data to fetch |
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112 | * @len: length of vbios image data to fetch |
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113 | * |
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114 | * Executes ATRM to fetch a chunk of the discrete |
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115 | * vbios image on PX systems (all asics). |
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116 | * Returns the length of the buffer fetched. |
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117 | */ |
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118 | static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, |
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119 | int offset, int len) |
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120 | { |
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121 | acpi_status status; |
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122 | union acpi_object atrm_arg_elements[2], *obj; |
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123 | struct acpi_object_list atrm_arg; |
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124 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; |
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125 | |||
126 | atrm_arg.count = 2; |
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127 | atrm_arg.pointer = &atrm_arg_elements[0]; |
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128 | |||
129 | atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; |
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130 | atrm_arg_elements[0].integer.value = offset; |
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131 | |||
132 | atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; |
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133 | atrm_arg_elements[1].integer.value = len; |
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134 | |||
135 | status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); |
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136 | if (ACPI_FAILURE(status)) { |
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137 | printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); |
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138 | return -ENODEV; |
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139 | } |
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140 | |||
141 | obj = (union acpi_object *)buffer.pointer; |
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142 | memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); |
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143 | len = obj->buffer.length; |
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144 | kfree(buffer.pointer); |
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145 | return len; |
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146 | } |
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147 | |||
1430 | serge | 148 | static bool radeon_atrm_get_bios(struct radeon_device *rdev) |
149 | { |
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150 | int ret; |
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2004 | serge | 151 | int size = 256 * 1024; |
1430 | serge | 152 | int i; |
2997 | Serge | 153 | struct pci_dev *pdev = NULL; |
154 | acpi_handle dhandle, atrm_handle; |
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155 | acpi_status status; |
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156 | bool found = false; |
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1430 | serge | 157 | |
2997 | Serge | 158 | /* ATRM is for the discrete card only */ |
159 | if (rdev->flags & RADEON_IS_IGP) |
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1430 | serge | 160 | return false; |
161 | |||
2997 | Serge | 162 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { |
5078 | serge | 163 | dhandle = ACPI_HANDLE(&pdev->dev); |
2997 | Serge | 164 | if (!dhandle) |
165 | continue; |
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166 | |||
167 | status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); |
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168 | if (!ACPI_FAILURE(status)) { |
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169 | found = true; |
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170 | break; |
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171 | } |
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172 | } |
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173 | |||
174 | if (!found) |
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175 | return false; |
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176 | |||
1430 | serge | 177 | rdev->bios = kmalloc(size, GFP_KERNEL); |
178 | if (!rdev->bios) { |
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179 | DRM_ERROR("Unable to allocate bios\n"); |
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180 | return false; |
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181 | } |
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182 | |||
183 | for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { |
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2997 | Serge | 184 | ret = radeon_atrm_call(atrm_handle, |
185 | rdev->bios, |
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1430 | serge | 186 | (i * ATRM_BIOS_PAGE), |
187 | ATRM_BIOS_PAGE); |
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2997 | Serge | 188 | if (ret < ATRM_BIOS_PAGE) |
1430 | serge | 189 | break; |
190 | } |
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191 | |||
192 | if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
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193 | kfree(rdev->bios); |
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194 | return false; |
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195 | } |
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196 | return true; |
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197 | } |
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2997 | Serge | 198 | #else |
3120 | serge | 199 | static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) |
2997 | Serge | 200 | { |
201 | return false; |
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202 | } |
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203 | #endif |
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1963 | serge | 204 | |
205 | static bool ni_read_disabled_bios(struct radeon_device *rdev) |
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206 | { |
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207 | u32 bus_cntl; |
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208 | u32 d1vga_control; |
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209 | u32 d2vga_control; |
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210 | u32 vga_render_control; |
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211 | u32 rom_cntl; |
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212 | bool r; |
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213 | |||
214 | bus_cntl = RREG32(R600_BUS_CNTL); |
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215 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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216 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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217 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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218 | rom_cntl = RREG32(R600_ROM_CNTL); |
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219 | |||
220 | /* enable the rom */ |
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221 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
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3764 | Serge | 222 | if (!ASIC_IS_NODCE(rdev)) { |
1963 | serge | 223 | /* Disable VGA mode */ |
224 | WREG32(AVIVO_D1VGA_CONTROL, |
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225 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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226 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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227 | WREG32(AVIVO_D2VGA_CONTROL, |
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228 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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229 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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230 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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231 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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3764 | Serge | 232 | } |
1963 | serge | 233 | WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); |
234 | |||
235 | r = radeon_read_bios(rdev); |
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236 | |||
237 | /* restore regs */ |
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238 | WREG32(R600_BUS_CNTL, bus_cntl); |
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3764 | Serge | 239 | if (!ASIC_IS_NODCE(rdev)) { |
1963 | serge | 240 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
241 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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242 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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3764 | Serge | 243 | } |
1963 | serge | 244 | WREG32(R600_ROM_CNTL, rom_cntl); |
245 | return r; |
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246 | } |
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247 | |||
1117 | serge | 248 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
249 | { |
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250 | uint32_t viph_control; |
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251 | uint32_t bus_cntl; |
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252 | uint32_t d1vga_control; |
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253 | uint32_t d2vga_control; |
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254 | uint32_t vga_render_control; |
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255 | uint32_t rom_cntl; |
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256 | uint32_t cg_spll_func_cntl = 0; |
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257 | uint32_t cg_spll_status; |
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258 | bool r; |
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259 | |||
260 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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1963 | serge | 261 | bus_cntl = RREG32(R600_BUS_CNTL); |
1117 | serge | 262 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
263 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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264 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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265 | rom_cntl = RREG32(R600_ROM_CNTL); |
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266 | |||
267 | /* disable VIP */ |
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268 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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269 | /* enable the rom */ |
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1963 | serge | 270 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
1117 | serge | 271 | /* Disable VGA mode */ |
272 | WREG32(AVIVO_D1VGA_CONTROL, |
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273 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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274 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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275 | WREG32(AVIVO_D2VGA_CONTROL, |
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276 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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277 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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278 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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279 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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280 | |||
281 | if (rdev->family == CHIP_RV730) { |
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282 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); |
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283 | |||
284 | /* enable bypass mode */ |
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285 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | |
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286 | R600_SPLL_BYPASS_EN)); |
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287 | |||
288 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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289 | cg_spll_status = 0; |
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290 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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291 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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292 | |||
293 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); |
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294 | } else |
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295 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); |
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296 | |||
297 | r = radeon_read_bios(rdev); |
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298 | |||
299 | /* restore regs */ |
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300 | if (rdev->family == CHIP_RV730) { |
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301 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); |
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302 | |||
303 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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304 | cg_spll_status = 0; |
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305 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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306 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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307 | } |
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308 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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1963 | serge | 309 | WREG32(R600_BUS_CNTL, bus_cntl); |
1117 | serge | 310 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
311 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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312 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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313 | WREG32(R600_ROM_CNTL, rom_cntl); |
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314 | return r; |
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315 | } |
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316 | |||
317 | static bool r600_read_disabled_bios(struct radeon_device *rdev) |
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318 | { |
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319 | uint32_t viph_control; |
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320 | uint32_t bus_cntl; |
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321 | uint32_t d1vga_control; |
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322 | uint32_t d2vga_control; |
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323 | uint32_t vga_render_control; |
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324 | uint32_t rom_cntl; |
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325 | uint32_t general_pwrmgt; |
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326 | uint32_t low_vid_lower_gpio_cntl; |
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327 | uint32_t medium_vid_lower_gpio_cntl; |
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328 | uint32_t high_vid_lower_gpio_cntl; |
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329 | uint32_t ctxsw_vid_lower_gpio_cntl; |
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330 | uint32_t lower_gpio_enable; |
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331 | bool r; |
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332 | |||
333 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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1963 | serge | 334 | bus_cntl = RREG32(R600_BUS_CNTL); |
1117 | serge | 335 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
336 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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337 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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338 | rom_cntl = RREG32(R600_ROM_CNTL); |
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339 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); |
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340 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); |
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341 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); |
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342 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); |
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343 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); |
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344 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); |
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345 | |||
346 | /* disable VIP */ |
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347 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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348 | /* enable the rom */ |
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1963 | serge | 349 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
1117 | serge | 350 | /* Disable VGA mode */ |
351 | WREG32(AVIVO_D1VGA_CONTROL, |
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352 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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353 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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354 | WREG32(AVIVO_D2VGA_CONTROL, |
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355 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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356 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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357 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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358 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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359 | |||
360 | WREG32(R600_ROM_CNTL, |
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361 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | |
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362 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | |
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363 | R600_SCK_OVERWRITE)); |
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364 | |||
365 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); |
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366 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, |
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367 | (low_vid_lower_gpio_cntl & ~0x400)); |
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368 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, |
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369 | (medium_vid_lower_gpio_cntl & ~0x400)); |
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370 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, |
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371 | (high_vid_lower_gpio_cntl & ~0x400)); |
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372 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, |
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373 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); |
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374 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); |
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375 | |||
376 | r = radeon_read_bios(rdev); |
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377 | |||
378 | /* restore regs */ |
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379 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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1963 | serge | 380 | WREG32(R600_BUS_CNTL, bus_cntl); |
1117 | serge | 381 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
382 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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383 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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384 | WREG32(R600_ROM_CNTL, rom_cntl); |
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385 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); |
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386 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); |
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387 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); |
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388 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); |
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389 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); |
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390 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); |
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391 | return r; |
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392 | } |
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393 | |||
394 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) |
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395 | { |
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396 | uint32_t seprom_cntl1; |
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397 | uint32_t viph_control; |
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398 | uint32_t bus_cntl; |
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399 | uint32_t d1vga_control; |
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400 | uint32_t d2vga_control; |
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401 | uint32_t vga_render_control; |
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402 | uint32_t gpiopad_a; |
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403 | uint32_t gpiopad_en; |
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404 | uint32_t gpiopad_mask; |
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405 | bool r; |
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406 | |||
407 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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408 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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2005 | serge | 409 | bus_cntl = RREG32(RV370_BUS_CNTL); |
1117 | serge | 410 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
411 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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412 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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413 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
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414 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); |
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415 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); |
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416 | |||
417 | WREG32(RADEON_SEPROM_CNTL1, |
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418 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
||
419 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
||
420 | WREG32(RADEON_GPIOPAD_A, 0); |
||
421 | WREG32(RADEON_GPIOPAD_EN, 0); |
||
422 | WREG32(RADEON_GPIOPAD_MASK, 0); |
||
423 | |||
424 | /* disable VIP */ |
||
425 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
||
426 | |||
427 | /* enable the rom */ |
||
2005 | serge | 428 | WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); |
1117 | serge | 429 | |
430 | /* Disable VGA mode */ |
||
431 | WREG32(AVIVO_D1VGA_CONTROL, |
||
432 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
||
433 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
||
434 | WREG32(AVIVO_D2VGA_CONTROL, |
||
435 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
||
436 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
||
437 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
||
438 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
||
439 | |||
440 | r = radeon_read_bios(rdev); |
||
441 | |||
442 | /* restore regs */ |
||
443 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
||
444 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
||
2005 | serge | 445 | WREG32(RV370_BUS_CNTL, bus_cntl); |
1117 | serge | 446 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
447 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
||
448 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
||
449 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); |
||
450 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); |
||
451 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); |
||
452 | return r; |
||
453 | } |
||
454 | |||
455 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) |
||
456 | { |
||
457 | uint32_t seprom_cntl1; |
||
458 | uint32_t viph_control; |
||
459 | uint32_t bus_cntl; |
||
460 | uint32_t crtc_gen_cntl; |
||
461 | uint32_t crtc2_gen_cntl; |
||
462 | uint32_t crtc_ext_cntl; |
||
463 | uint32_t fp2_gen_cntl; |
||
464 | bool r; |
||
465 | |||
466 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
||
467 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
||
2005 | serge | 468 | if (rdev->flags & RADEON_IS_PCIE) |
469 | bus_cntl = RREG32(RV370_BUS_CNTL); |
||
470 | else |
||
1117 | serge | 471 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
472 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
||
473 | crtc2_gen_cntl = 0; |
||
474 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
475 | fp2_gen_cntl = 0; |
||
476 | |||
5078 | serge | 477 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
1117 | serge | 478 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
479 | } |
||
480 | |||
481 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
482 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
483 | } |
||
484 | |||
485 | WREG32(RADEON_SEPROM_CNTL1, |
||
486 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
||
487 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
||
488 | |||
489 | /* disable VIP */ |
||
490 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
||
491 | |||
492 | /* enable the rom */ |
||
2005 | serge | 493 | if (rdev->flags & RADEON_IS_PCIE) |
494 | WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); |
||
495 | else |
||
1117 | serge | 496 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
497 | |||
498 | /* Turn off mem requests and CRTC for both controllers */ |
||
499 | WREG32(RADEON_CRTC_GEN_CNTL, |
||
500 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | |
||
501 | (RADEON_CRTC_DISP_REQ_EN_B | |
||
502 | RADEON_CRTC_EXT_DISP_EN))); |
||
503 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
504 | WREG32(RADEON_CRTC2_GEN_CNTL, |
||
505 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | |
||
506 | RADEON_CRTC2_DISP_REQ_EN_B)); |
||
507 | } |
||
508 | /* Turn off CRTC */ |
||
509 | WREG32(RADEON_CRTC_EXT_CNTL, |
||
510 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | |
||
511 | (RADEON_CRTC_SYNC_TRISTAT | |
||
512 | RADEON_CRTC_DISPLAY_DIS))); |
||
513 | |||
5078 | serge | 514 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
1117 | serge | 515 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
516 | } |
||
517 | |||
518 | r = radeon_read_bios(rdev); |
||
519 | |||
520 | /* restore regs */ |
||
521 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
||
522 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
||
2005 | serge | 523 | if (rdev->flags & RADEON_IS_PCIE) |
524 | WREG32(RV370_BUS_CNTL, bus_cntl); |
||
525 | else |
||
1117 | serge | 526 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
527 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
||
528 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
529 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
530 | } |
||
531 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
5078 | serge | 532 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
1117 | serge | 533 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
534 | } |
||
535 | return r; |
||
536 | } |
||
537 | |||
538 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) |
||
539 | { |
||
1233 | serge | 540 | if (rdev->flags & RADEON_IS_IGP) |
541 | return igp_read_bios_from_vram(rdev); |
||
1963 | serge | 542 | else if (rdev->family >= CHIP_BARTS) |
543 | return ni_read_disabled_bios(rdev); |
||
1233 | serge | 544 | else if (rdev->family >= CHIP_RV770) |
1117 | serge | 545 | return r700_read_disabled_bios(rdev); |
546 | else if (rdev->family >= CHIP_R600) |
||
547 | return r600_read_disabled_bios(rdev); |
||
548 | else if (rdev->family >= CHIP_RS600) |
||
549 | return avivo_read_disabled_bios(rdev); |
||
550 | else |
||
551 | return legacy_read_disabled_bios(rdev); |
||
552 | } |
||
553 | |||
2997 | Serge | 554 | #ifdef CONFIG_ACPI |
555 | static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) |
||
556 | { |
||
557 | bool ret = false; |
||
558 | struct acpi_table_header *hdr; |
||
559 | acpi_size tbl_size; |
||
560 | UEFI_ACPI_VFCT *vfct; |
||
561 | GOP_VBIOS_CONTENT *vbios; |
||
562 | VFCT_IMAGE_HEADER *vhdr; |
||
1430 | serge | 563 | |
2997 | Serge | 564 | if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) |
565 | return false; |
||
566 | if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { |
||
567 | DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); |
||
568 | goto out_unmap; |
||
569 | } |
||
570 | |||
571 | vfct = (UEFI_ACPI_VFCT *)hdr; |
||
572 | if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { |
||
573 | DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); |
||
574 | goto out_unmap; |
||
575 | } |
||
576 | |||
577 | vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); |
||
578 | vhdr = &vbios->VbiosHeader; |
||
579 | DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", |
||
580 | vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, |
||
581 | vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); |
||
582 | |||
583 | if (vhdr->PCIBus != rdev->pdev->bus->number || |
||
584 | vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || |
||
585 | vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || |
||
586 | vhdr->VendorID != rdev->pdev->vendor || |
||
587 | vhdr->DeviceID != rdev->pdev->device) { |
||
588 | DRM_INFO("ACPI VFCT table is not for this card\n"); |
||
589 | goto out_unmap; |
||
5078 | serge | 590 | } |
2997 | Serge | 591 | |
592 | if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { |
||
593 | DRM_ERROR("ACPI VFCT image truncated\n"); |
||
594 | goto out_unmap; |
||
595 | } |
||
596 | |||
597 | rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); |
||
598 | ret = !!rdev->bios; |
||
599 | |||
600 | out_unmap: |
||
601 | return ret; |
||
602 | } |
||
603 | #else |
||
604 | static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) |
||
605 | { |
||
606 | return false; |
||
607 | } |
||
608 | #endif |
||
609 | |||
1117 | serge | 610 | bool radeon_get_bios(struct radeon_device *rdev) |
611 | { |
||
612 | bool r; |
||
613 | uint16_t tmp; |
||
614 | |||
1430 | serge | 615 | r = radeon_atrm_get_bios(rdev); |
616 | if (r == false) |
||
2997 | Serge | 617 | r = radeon_acpi_vfct_bios(rdev); |
618 | if (r == false) |
||
1233 | serge | 619 | r = igp_read_bios_from_vram(rdev); |
2997 | Serge | 620 | if (r == false) |
621 | r = radeon_read_bios(rdev); |
||
1129 | serge | 622 | if (r == false) { |
623 | r = radeon_read_disabled_bios(rdev); |
||
624 | } |
||
1117 | serge | 625 | if (r == false || rdev->bios == NULL) { |
626 | DRM_ERROR("Unable to locate a BIOS ROM\n"); |
||
627 | rdev->bios = NULL; |
||
628 | return false; |
||
629 | } |
||
630 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
||
1430 | serge | 631 | printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); |
1117 | serge | 632 | goto free_bios; |
633 | } |
||
634 | |||
1430 | serge | 635 | tmp = RBIOS16(0x18); |
636 | if (RBIOS8(tmp + 0x14) != 0x0) { |
||
637 | DRM_INFO("Not an x86 BIOS ROM, not using.\n"); |
||
638 | goto free_bios; |
||
639 | } |
||
640 | |||
1117 | serge | 641 | rdev->bios_header_start = RBIOS16(0x48); |
642 | if (!rdev->bios_header_start) { |
||
643 | goto free_bios; |
||
644 | } |
||
645 | tmp = rdev->bios_header_start + 4; |
||
646 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || |
||
647 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { |
||
648 | rdev->is_atom_bios = true; |
||
649 | } else { |
||
650 | rdev->is_atom_bios = false; |
||
651 | } |
||
652 | |||
1179 | serge | 653 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); |
1117 | serge | 654 | return true; |
655 | free_bios: |
||
656 | kfree(rdev->bios); |
||
657 | rdev->bios = NULL; |
||
658 | return false; |
||
659 | }>><>><>><>>>><> |