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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1123 | serge | 28 | #include "drmP.h" |
1117 | serge | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" |
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31 | #include "atom.h" |
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32 | |||
33 | /* |
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34 | * BIOS. |
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35 | */ |
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1233 | serge | 36 | |
37 | /* If you boot an IGP board with a discrete card as the primary, |
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38 | * the IGP rom is not accessible via the rom bar as the IGP rom is |
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39 | * part of the system bios. On boot, the system bios puts a |
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40 | * copy of the igp rom at the start of vram if a discrete card is |
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41 | * present. |
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42 | */ |
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43 | static bool igp_read_bios_from_vram(struct radeon_device *rdev) |
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44 | { |
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45 | uint8_t __iomem *bios; |
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46 | resource_size_t vram_base; |
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47 | resource_size_t size = 256 * 1024; /* ??? */ |
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48 | |||
49 | rdev->bios = NULL; |
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50 | vram_base = drm_get_resource_start(rdev->ddev, 0); |
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51 | bios = ioremap(vram_base, size); |
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52 | if (!bios) { |
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53 | return false; |
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54 | } |
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55 | |||
56 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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57 | iounmap(bios); |
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58 | return false; |
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59 | } |
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60 | rdev->bios = kmalloc(size, GFP_KERNEL); |
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61 | if (rdev->bios == NULL) { |
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62 | iounmap(bios); |
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63 | return false; |
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64 | } |
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65 | memcpy(rdev->bios, bios, size); |
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66 | iounmap(bios); |
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67 | return true; |
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68 | } |
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69 | |||
1117 | serge | 70 | static bool radeon_read_bios(struct radeon_device *rdev) |
71 | { |
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1179 | serge | 72 | uint8_t __iomem *bios; |
1117 | serge | 73 | size_t size; |
74 | |||
75 | rdev->bios = NULL; |
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1221 | serge | 76 | /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
77 | bios = pci_map_rom(rdev->pdev, &size); |
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1117 | serge | 78 | if (!bios) { |
79 | return false; |
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80 | } |
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81 | |||
82 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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83 | // pci_unmap_rom(rdev->pdev, bios); |
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84 | return false; |
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85 | } |
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1179 | serge | 86 | rdev->bios = kmalloc(size, GFP_KERNEL); |
1117 | serge | 87 | if (rdev->bios == NULL) { |
1268 | serge | 88 | // pci_unmap_rom(rdev->pdev, bios); |
1117 | serge | 89 | return false; |
90 | } |
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91 | memcpy(rdev->bios, bios, size); |
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1268 | serge | 92 | // pci_unmap_rom(rdev->pdev, bios); |
1117 | serge | 93 | return true; |
94 | } |
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95 | |||
1430 | serge | 96 | /* ATRM is used to get the BIOS on the discrete cards in |
97 | * dual-gpu systems. |
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98 | */ |
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99 | static bool radeon_atrm_get_bios(struct radeon_device *rdev) |
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100 | { |
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101 | int ret; |
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102 | int size = 64 * 1024; |
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103 | int i; |
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104 | |||
105 | if (!radeon_atrm_supported(rdev->pdev)) |
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106 | return false; |
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107 | |||
108 | rdev->bios = kmalloc(size, GFP_KERNEL); |
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109 | if (!rdev->bios) { |
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110 | DRM_ERROR("Unable to allocate bios\n"); |
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111 | return false; |
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112 | } |
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113 | |||
114 | for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { |
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115 | ret = radeon_atrm_get_bios_chunk(rdev->bios, |
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116 | (i * ATRM_BIOS_PAGE), |
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117 | ATRM_BIOS_PAGE); |
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118 | if (ret <= 0) |
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119 | break; |
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120 | } |
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121 | |||
122 | if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
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123 | kfree(rdev->bios); |
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124 | return false; |
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125 | } |
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126 | return true; |
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127 | } |
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1117 | serge | 128 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
129 | { |
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130 | uint32_t viph_control; |
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131 | uint32_t bus_cntl; |
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132 | uint32_t d1vga_control; |
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133 | uint32_t d2vga_control; |
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134 | uint32_t vga_render_control; |
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135 | uint32_t rom_cntl; |
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136 | uint32_t cg_spll_func_cntl = 0; |
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137 | uint32_t cg_spll_status; |
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138 | bool r; |
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139 | |||
140 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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141 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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142 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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143 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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144 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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145 | rom_cntl = RREG32(R600_ROM_CNTL); |
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146 | |||
147 | /* disable VIP */ |
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148 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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149 | /* enable the rom */ |
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150 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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151 | /* Disable VGA mode */ |
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152 | WREG32(AVIVO_D1VGA_CONTROL, |
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153 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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154 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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155 | WREG32(AVIVO_D2VGA_CONTROL, |
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156 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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157 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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158 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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159 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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160 | |||
161 | if (rdev->family == CHIP_RV730) { |
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162 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); |
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163 | |||
164 | /* enable bypass mode */ |
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165 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | |
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166 | R600_SPLL_BYPASS_EN)); |
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167 | |||
168 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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169 | cg_spll_status = 0; |
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170 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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171 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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172 | |||
173 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); |
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174 | } else |
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175 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); |
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176 | |||
177 | r = radeon_read_bios(rdev); |
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178 | |||
179 | /* restore regs */ |
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180 | if (rdev->family == CHIP_RV730) { |
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181 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); |
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182 | |||
183 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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184 | cg_spll_status = 0; |
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185 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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186 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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187 | } |
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188 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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189 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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190 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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191 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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192 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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193 | WREG32(R600_ROM_CNTL, rom_cntl); |
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194 | return r; |
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195 | } |
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196 | |||
197 | static bool r600_read_disabled_bios(struct radeon_device *rdev) |
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198 | { |
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199 | uint32_t viph_control; |
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200 | uint32_t bus_cntl; |
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201 | uint32_t d1vga_control; |
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202 | uint32_t d2vga_control; |
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203 | uint32_t vga_render_control; |
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204 | uint32_t rom_cntl; |
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205 | uint32_t general_pwrmgt; |
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206 | uint32_t low_vid_lower_gpio_cntl; |
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207 | uint32_t medium_vid_lower_gpio_cntl; |
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208 | uint32_t high_vid_lower_gpio_cntl; |
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209 | uint32_t ctxsw_vid_lower_gpio_cntl; |
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210 | uint32_t lower_gpio_enable; |
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211 | bool r; |
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212 | |||
213 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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214 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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215 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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216 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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217 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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218 | rom_cntl = RREG32(R600_ROM_CNTL); |
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219 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); |
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220 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); |
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221 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); |
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222 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); |
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223 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); |
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224 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); |
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225 | |||
226 | /* disable VIP */ |
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227 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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228 | /* enable the rom */ |
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229 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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230 | /* Disable VGA mode */ |
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231 | WREG32(AVIVO_D1VGA_CONTROL, |
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232 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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233 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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234 | WREG32(AVIVO_D2VGA_CONTROL, |
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235 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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236 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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237 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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238 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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239 | |||
240 | WREG32(R600_ROM_CNTL, |
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241 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | |
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242 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | |
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243 | R600_SCK_OVERWRITE)); |
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244 | |||
245 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); |
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246 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, |
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247 | (low_vid_lower_gpio_cntl & ~0x400)); |
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248 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, |
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249 | (medium_vid_lower_gpio_cntl & ~0x400)); |
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250 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, |
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251 | (high_vid_lower_gpio_cntl & ~0x400)); |
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252 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, |
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253 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); |
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254 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); |
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255 | |||
256 | r = radeon_read_bios(rdev); |
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257 | |||
258 | /* restore regs */ |
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259 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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260 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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261 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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262 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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263 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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264 | WREG32(R600_ROM_CNTL, rom_cntl); |
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265 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); |
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266 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); |
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267 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); |
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268 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); |
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269 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); |
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270 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); |
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271 | return r; |
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272 | } |
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273 | |||
274 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) |
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275 | { |
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276 | uint32_t seprom_cntl1; |
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277 | uint32_t viph_control; |
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278 | uint32_t bus_cntl; |
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279 | uint32_t d1vga_control; |
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280 | uint32_t d2vga_control; |
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281 | uint32_t vga_render_control; |
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282 | uint32_t gpiopad_a; |
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283 | uint32_t gpiopad_en; |
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284 | uint32_t gpiopad_mask; |
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285 | bool r; |
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286 | |||
287 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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288 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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289 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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290 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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291 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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292 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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293 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
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294 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); |
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295 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); |
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296 | |||
297 | WREG32(RADEON_SEPROM_CNTL1, |
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298 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
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299 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
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300 | WREG32(RADEON_GPIOPAD_A, 0); |
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301 | WREG32(RADEON_GPIOPAD_EN, 0); |
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302 | WREG32(RADEON_GPIOPAD_MASK, 0); |
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303 | |||
304 | /* disable VIP */ |
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305 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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306 | |||
307 | /* enable the rom */ |
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308 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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309 | |||
310 | /* Disable VGA mode */ |
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311 | WREG32(AVIVO_D1VGA_CONTROL, |
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312 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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313 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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314 | WREG32(AVIVO_D2VGA_CONTROL, |
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315 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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316 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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317 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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318 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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319 | |||
320 | r = radeon_read_bios(rdev); |
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321 | |||
322 | /* restore regs */ |
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323 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
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324 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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325 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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326 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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327 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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328 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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329 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); |
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330 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); |
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331 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); |
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332 | return r; |
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333 | } |
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334 | |||
335 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) |
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336 | { |
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337 | uint32_t seprom_cntl1; |
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338 | uint32_t viph_control; |
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339 | uint32_t bus_cntl; |
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340 | uint32_t crtc_gen_cntl; |
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341 | uint32_t crtc2_gen_cntl; |
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342 | uint32_t crtc_ext_cntl; |
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343 | uint32_t fp2_gen_cntl; |
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344 | bool r; |
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345 | |||
346 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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347 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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348 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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349 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
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350 | crtc2_gen_cntl = 0; |
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351 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
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352 | fp2_gen_cntl = 0; |
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353 | |||
354 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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355 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
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356 | } |
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357 | |||
358 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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359 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
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360 | } |
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361 | |||
362 | WREG32(RADEON_SEPROM_CNTL1, |
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363 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
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364 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
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365 | |||
366 | /* disable VIP */ |
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367 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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368 | |||
369 | /* enable the rom */ |
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370 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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371 | |||
372 | /* Turn off mem requests and CRTC for both controllers */ |
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373 | WREG32(RADEON_CRTC_GEN_CNTL, |
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374 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | |
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375 | (RADEON_CRTC_DISP_REQ_EN_B | |
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376 | RADEON_CRTC_EXT_DISP_EN))); |
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377 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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378 | WREG32(RADEON_CRTC2_GEN_CNTL, |
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379 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | |
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380 | RADEON_CRTC2_DISP_REQ_EN_B)); |
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381 | } |
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382 | /* Turn off CRTC */ |
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383 | WREG32(RADEON_CRTC_EXT_CNTL, |
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384 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | |
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385 | (RADEON_CRTC_SYNC_TRISTAT | |
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386 | RADEON_CRTC_DISPLAY_DIS))); |
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387 | |||
388 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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389 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
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390 | } |
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391 | |||
392 | r = radeon_read_bios(rdev); |
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393 | |||
394 | /* restore regs */ |
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395 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
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396 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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397 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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398 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
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399 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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400 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
401 | } |
||
402 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
403 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
||
404 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
||
405 | } |
||
406 | return r; |
||
407 | } |
||
408 | |||
409 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) |
||
410 | { |
||
1233 | serge | 411 | if (rdev->flags & RADEON_IS_IGP) |
412 | return igp_read_bios_from_vram(rdev); |
||
413 | else if (rdev->family >= CHIP_RV770) |
||
1117 | serge | 414 | return r700_read_disabled_bios(rdev); |
415 | else if (rdev->family >= CHIP_R600) |
||
416 | return r600_read_disabled_bios(rdev); |
||
417 | else if (rdev->family >= CHIP_RS600) |
||
418 | return avivo_read_disabled_bios(rdev); |
||
419 | else |
||
420 | return legacy_read_disabled_bios(rdev); |
||
421 | } |
||
422 | |||
1430 | serge | 423 | |
1117 | serge | 424 | bool radeon_get_bios(struct radeon_device *rdev) |
425 | { |
||
426 | bool r; |
||
427 | uint16_t tmp; |
||
428 | |||
1430 | serge | 429 | r = radeon_atrm_get_bios(rdev); |
430 | if (r == false) |
||
1233 | serge | 431 | r = igp_read_bios_from_vram(rdev); |
432 | if (r == false) |
||
433 | r = radeon_read_bios(rdev); |
||
1129 | serge | 434 | if (r == false) { |
435 | r = radeon_read_disabled_bios(rdev); |
||
436 | } |
||
1117 | serge | 437 | if (r == false || rdev->bios == NULL) { |
438 | DRM_ERROR("Unable to locate a BIOS ROM\n"); |
||
439 | rdev->bios = NULL; |
||
440 | return false; |
||
441 | } |
||
442 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
||
1430 | serge | 443 | printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); |
1117 | serge | 444 | goto free_bios; |
445 | } |
||
446 | |||
1430 | serge | 447 | tmp = RBIOS16(0x18); |
448 | if (RBIOS8(tmp + 0x14) != 0x0) { |
||
449 | DRM_INFO("Not an x86 BIOS ROM, not using.\n"); |
||
450 | goto free_bios; |
||
451 | } |
||
452 | |||
1117 | serge | 453 | rdev->bios_header_start = RBIOS16(0x48); |
454 | if (!rdev->bios_header_start) { |
||
455 | goto free_bios; |
||
456 | } |
||
457 | tmp = rdev->bios_header_start + 4; |
||
458 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || |
||
459 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { |
||
460 | rdev->is_atom_bios = true; |
||
461 | } else { |
||
462 | rdev->is_atom_bios = false; |
||
463 | } |
||
464 | |||
1179 | serge | 465 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); |
1117 | serge | 466 | return true; |
467 | free_bios: |
||
468 | kfree(rdev->bios); |
||
469 | rdev->bios = NULL; |
||
470 | return false; |
||
471 | }><>><>><>=>> |