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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1123 | serge | 28 | #include "drmP.h" |
| 1117 | serge | 29 | #include "radeon_reg.h" |
| 30 | #include "radeon.h" |
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| 31 | #include "atom.h" |
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| 32 | |||
| 33 | /* |
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| 34 | * BIOS. |
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| 35 | */ |
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| 36 | static bool radeon_read_bios(struct radeon_device *rdev) |
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| 37 | { |
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| 38 | uint8_t *bios; |
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| 39 | size_t size; |
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| 40 | |||
| 41 | rdev->bios = NULL; |
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| 1120 | serge | 42 | bios = (uint8_t*)pci_map_rom(rdev->pdev, &size); |
| 1117 | serge | 43 | if (!bios) { |
| 44 | return false; |
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| 45 | } |
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| 46 | |||
| 47 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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| 48 | // pci_unmap_rom(rdev->pdev, bios); |
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| 49 | return false; |
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| 50 | } |
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| 51 | rdev->bios = malloc(size); |
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| 52 | if (rdev->bios == NULL) { |
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| 53 | // pci_unmap_rom(rdev->pdev, bios); |
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| 54 | return false; |
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| 55 | } |
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| 56 | memcpy(rdev->bios, bios, size); |
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| 57 | // pci_unmap_rom(rdev->pdev, bios); |
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| 58 | return true; |
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| 59 | } |
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| 60 | |||
| 61 | |||
| 62 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
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| 63 | { |
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| 64 | uint32_t viph_control; |
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| 65 | uint32_t bus_cntl; |
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| 66 | uint32_t d1vga_control; |
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| 67 | uint32_t d2vga_control; |
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| 68 | uint32_t vga_render_control; |
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| 69 | uint32_t rom_cntl; |
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| 70 | uint32_t cg_spll_func_cntl = 0; |
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| 71 | uint32_t cg_spll_status; |
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| 72 | bool r; |
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| 73 | |||
| 74 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 75 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 76 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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| 77 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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| 78 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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| 79 | rom_cntl = RREG32(R600_ROM_CNTL); |
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| 80 | |||
| 81 | /* disable VIP */ |
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| 82 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 83 | /* enable the rom */ |
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| 84 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 85 | /* Disable VGA mode */ |
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| 86 | WREG32(AVIVO_D1VGA_CONTROL, |
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| 87 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 88 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 89 | WREG32(AVIVO_D2VGA_CONTROL, |
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| 90 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 91 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 92 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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| 93 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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| 94 | |||
| 95 | if (rdev->family == CHIP_RV730) { |
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| 96 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); |
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| 97 | |||
| 98 | /* enable bypass mode */ |
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| 99 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | |
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| 100 | R600_SPLL_BYPASS_EN)); |
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| 101 | |||
| 102 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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| 103 | cg_spll_status = 0; |
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| 104 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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| 105 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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| 106 | |||
| 107 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); |
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| 108 | } else |
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| 109 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); |
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| 110 | |||
| 111 | r = radeon_read_bios(rdev); |
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| 112 | |||
| 113 | /* restore regs */ |
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| 114 | if (rdev->family == CHIP_RV730) { |
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| 115 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); |
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| 116 | |||
| 117 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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| 118 | cg_spll_status = 0; |
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| 119 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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| 120 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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| 121 | } |
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| 122 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 123 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 124 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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| 125 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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| 126 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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| 127 | WREG32(R600_ROM_CNTL, rom_cntl); |
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| 128 | return r; |
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| 129 | } |
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| 130 | |||
| 131 | static bool r600_read_disabled_bios(struct radeon_device *rdev) |
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| 132 | { |
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| 133 | uint32_t viph_control; |
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| 134 | uint32_t bus_cntl; |
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| 135 | uint32_t d1vga_control; |
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| 136 | uint32_t d2vga_control; |
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| 137 | uint32_t vga_render_control; |
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| 138 | uint32_t rom_cntl; |
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| 139 | uint32_t general_pwrmgt; |
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| 140 | uint32_t low_vid_lower_gpio_cntl; |
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| 141 | uint32_t medium_vid_lower_gpio_cntl; |
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| 142 | uint32_t high_vid_lower_gpio_cntl; |
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| 143 | uint32_t ctxsw_vid_lower_gpio_cntl; |
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| 144 | uint32_t lower_gpio_enable; |
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| 145 | bool r; |
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| 146 | |||
| 147 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 148 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 149 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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| 150 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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| 151 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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| 152 | rom_cntl = RREG32(R600_ROM_CNTL); |
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| 153 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); |
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| 154 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); |
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| 155 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); |
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| 156 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); |
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| 157 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); |
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| 158 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); |
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| 159 | |||
| 160 | /* disable VIP */ |
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| 161 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 162 | /* enable the rom */ |
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| 163 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 164 | /* Disable VGA mode */ |
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| 165 | WREG32(AVIVO_D1VGA_CONTROL, |
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| 166 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 167 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 168 | WREG32(AVIVO_D2VGA_CONTROL, |
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| 169 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 170 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 171 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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| 172 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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| 173 | |||
| 174 | WREG32(R600_ROM_CNTL, |
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| 175 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | |
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| 176 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | |
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| 177 | R600_SCK_OVERWRITE)); |
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| 178 | |||
| 179 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); |
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| 180 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, |
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| 181 | (low_vid_lower_gpio_cntl & ~0x400)); |
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| 182 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, |
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| 183 | (medium_vid_lower_gpio_cntl & ~0x400)); |
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| 184 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, |
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| 185 | (high_vid_lower_gpio_cntl & ~0x400)); |
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| 186 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, |
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| 187 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); |
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| 188 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); |
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| 189 | |||
| 190 | r = radeon_read_bios(rdev); |
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| 191 | |||
| 192 | /* restore regs */ |
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| 193 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 194 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 195 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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| 196 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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| 197 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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| 198 | WREG32(R600_ROM_CNTL, rom_cntl); |
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| 199 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); |
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| 200 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); |
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| 201 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); |
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| 202 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); |
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| 203 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); |
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| 204 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); |
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| 205 | return r; |
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| 206 | } |
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| 207 | |||
| 208 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) |
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| 209 | { |
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| 210 | uint32_t seprom_cntl1; |
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| 211 | uint32_t viph_control; |
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| 212 | uint32_t bus_cntl; |
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| 213 | uint32_t d1vga_control; |
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| 214 | uint32_t d2vga_control; |
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| 215 | uint32_t vga_render_control; |
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| 216 | uint32_t gpiopad_a; |
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| 217 | uint32_t gpiopad_en; |
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| 218 | uint32_t gpiopad_mask; |
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| 219 | bool r; |
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| 220 | |||
| 221 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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| 222 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 223 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 224 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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| 225 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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| 226 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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| 227 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
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| 228 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); |
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| 229 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); |
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| 230 | |||
| 231 | WREG32(RADEON_SEPROM_CNTL1, |
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| 232 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
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| 233 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
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| 234 | WREG32(RADEON_GPIOPAD_A, 0); |
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| 235 | WREG32(RADEON_GPIOPAD_EN, 0); |
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| 236 | WREG32(RADEON_GPIOPAD_MASK, 0); |
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| 237 | |||
| 238 | /* disable VIP */ |
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| 239 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 240 | |||
| 241 | /* enable the rom */ |
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| 242 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 243 | |||
| 244 | /* Disable VGA mode */ |
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| 245 | WREG32(AVIVO_D1VGA_CONTROL, |
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| 246 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 247 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 248 | WREG32(AVIVO_D2VGA_CONTROL, |
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| 249 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 250 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 251 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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| 252 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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| 253 | |||
| 254 | r = radeon_read_bios(rdev); |
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| 255 | |||
| 256 | /* restore regs */ |
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| 257 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
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| 258 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 259 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 260 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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| 261 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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| 262 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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| 263 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); |
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| 264 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); |
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| 265 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); |
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| 266 | return r; |
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| 267 | } |
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| 268 | |||
| 269 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) |
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| 270 | { |
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| 271 | uint32_t seprom_cntl1; |
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| 272 | uint32_t viph_control; |
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| 273 | uint32_t bus_cntl; |
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| 274 | uint32_t crtc_gen_cntl; |
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| 275 | uint32_t crtc2_gen_cntl; |
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| 276 | uint32_t crtc_ext_cntl; |
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| 277 | uint32_t fp2_gen_cntl; |
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| 278 | bool r; |
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| 279 | |||
| 280 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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| 281 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 282 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 283 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
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| 284 | crtc2_gen_cntl = 0; |
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| 285 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
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| 286 | fp2_gen_cntl = 0; |
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| 287 | |||
| 288 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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| 289 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
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| 290 | } |
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| 291 | |||
| 292 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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| 293 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
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| 294 | } |
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| 295 | |||
| 296 | WREG32(RADEON_SEPROM_CNTL1, |
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| 297 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
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| 298 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
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| 299 | |||
| 300 | /* disable VIP */ |
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| 301 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 302 | |||
| 303 | /* enable the rom */ |
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| 304 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 305 | |||
| 306 | /* Turn off mem requests and CRTC for both controllers */ |
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| 307 | WREG32(RADEON_CRTC_GEN_CNTL, |
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| 308 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | |
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| 309 | (RADEON_CRTC_DISP_REQ_EN_B | |
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| 310 | RADEON_CRTC_EXT_DISP_EN))); |
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| 311 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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| 312 | WREG32(RADEON_CRTC2_GEN_CNTL, |
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| 313 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | |
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| 314 | RADEON_CRTC2_DISP_REQ_EN_B)); |
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| 315 | } |
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| 316 | /* Turn off CRTC */ |
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| 317 | WREG32(RADEON_CRTC_EXT_CNTL, |
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| 318 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | |
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| 319 | (RADEON_CRTC_SYNC_TRISTAT | |
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| 320 | RADEON_CRTC_DISPLAY_DIS))); |
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| 321 | |||
| 322 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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| 323 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
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| 324 | } |
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| 325 | |||
| 326 | r = radeon_read_bios(rdev); |
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| 327 | |||
| 328 | /* restore regs */ |
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| 329 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
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| 330 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 331 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 332 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
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| 333 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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| 334 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
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| 335 | } |
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| 336 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
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| 337 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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| 338 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
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| 339 | } |
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| 340 | return r; |
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| 341 | } |
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| 342 | |||
| 343 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) |
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| 344 | { |
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| 345 | if (rdev->family >= CHIP_RV770) |
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| 346 | return r700_read_disabled_bios(rdev); |
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| 347 | else if (rdev->family >= CHIP_R600) |
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| 348 | return r600_read_disabled_bios(rdev); |
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| 349 | else if (rdev->family >= CHIP_RS600) |
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| 350 | return avivo_read_disabled_bios(rdev); |
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| 351 | else |
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| 352 | return legacy_read_disabled_bios(rdev); |
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| 353 | } |
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| 354 | |||
| 355 | |||
| 356 | bool radeon_get_bios(struct radeon_device *rdev) |
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| 357 | { |
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| 358 | bool r; |
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| 359 | uint16_t tmp; |
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| 360 | |||
| 361 | dbgprintf("%s\n\r",__FUNCTION__); |
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| 362 | |||
| 363 | r = radeon_read_bios(rdev); |
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| 1129 | serge | 364 | if (r == false) { |
| 365 | r = radeon_read_disabled_bios(rdev); |
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| 366 | } |
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| 1117 | serge | 367 | if (r == false || rdev->bios == NULL) { |
| 368 | DRM_ERROR("Unable to locate a BIOS ROM\n"); |
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| 369 | rdev->bios = NULL; |
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| 370 | return false; |
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| 371 | } |
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| 372 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
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| 373 | goto free_bios; |
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| 374 | } |
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| 375 | |||
| 376 | rdev->bios_header_start = RBIOS16(0x48); |
||
| 377 | if (!rdev->bios_header_start) { |
||
| 378 | goto free_bios; |
||
| 379 | } |
||
| 380 | tmp = rdev->bios_header_start + 4; |
||
| 381 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || |
||
| 382 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { |
||
| 383 | rdev->is_atom_bios = true; |
||
| 384 | } else { |
||
| 385 | rdev->is_atom_bios = false; |
||
| 386 | } |
||
| 387 | |||
| 388 | dbgprintf("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); |
||
| 389 | return true; |
||
| 390 | free_bios: |
||
| 391 | kfree(rdev->bios); |
||
| 392 | rdev->bios = NULL; |
||
| 393 | return false; |
||
| 394 | } |