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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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2997 | Serge | 26 | #include |
27 | #include |
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1117 | serge | 28 | #include "radeon.h" |
29 | |||
30 | #include "atom.h" |
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31 | #include "atom-bits.h" |
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32 | |||
33 | extern void |
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1963 | serge | 34 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, |
35 | uint32_t supported_device, u16 caps); |
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1117 | serge | 36 | |
37 | /* from radeon_legacy_encoder.c */ |
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38 | extern void |
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1963 | serge | 39 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
1117 | serge | 40 | uint32_t supported_device); |
41 | |||
42 | union atom_supported_devices { |
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43 | struct _ATOM_SUPPORTED_DEVICES_INFO info; |
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44 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; |
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45 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; |
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46 | }; |
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47 | |||
2997 | Serge | 48 | static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, |
49 | ATOM_GPIO_I2C_ASSIGMENT *gpio, |
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50 | u8 index) |
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1117 | serge | 51 | { |
2997 | Serge | 52 | /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ |
53 | if ((rdev->family == CHIP_R420) || |
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54 | (rdev->family == CHIP_R423) || |
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55 | (rdev->family == CHIP_RV410)) { |
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56 | if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || |
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57 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || |
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58 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { |
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59 | gpio->ucClkMaskShift = 0x19; |
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60 | gpio->ucDataMaskShift = 0x18; |
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61 | } |
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62 | } |
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1117 | serge | 63 | |
1963 | serge | 64 | /* some evergreen boards have bad data for this entry */ |
65 | if (ASIC_IS_DCE4(rdev)) { |
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2997 | Serge | 66 | if ((index == 7) && |
1963 | serge | 67 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && |
68 | (gpio->sucI2cId.ucAccess == 0)) { |
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69 | gpio->sucI2cId.ucAccess = 0x97; |
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70 | gpio->ucDataMaskShift = 8; |
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71 | gpio->ucDataEnShift = 8; |
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72 | gpio->ucDataY_Shift = 8; |
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73 | gpio->ucDataA_Shift = 8; |
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74 | } |
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75 | } |
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76 | |||
77 | /* some DCE3 boards have bad data for this entry */ |
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78 | if (ASIC_IS_DCE3(rdev)) { |
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2997 | Serge | 79 | if ((index == 4) && |
1963 | serge | 80 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && |
81 | (gpio->sucI2cId.ucAccess == 0x94)) |
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82 | gpio->sucI2cId.ucAccess = 0x14; |
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83 | } |
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2997 | Serge | 84 | } |
1963 | serge | 85 | |
2997 | Serge | 86 | static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) |
87 | { |
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88 | struct radeon_i2c_bus_rec i2c; |
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89 | |||
90 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
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91 | |||
1321 | serge | 92 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; |
93 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; |
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94 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; |
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95 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; |
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96 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; |
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97 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; |
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98 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; |
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99 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; |
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100 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); |
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101 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); |
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102 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); |
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103 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); |
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104 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); |
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105 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); |
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106 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); |
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107 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); |
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108 | |||
109 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) |
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110 | i2c.hw_capable = true; |
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111 | else |
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112 | i2c.hw_capable = false; |
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113 | |||
114 | if (gpio->sucI2cId.ucAccess == 0xa0) |
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115 | i2c.mm_i2c = true; |
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116 | else |
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117 | i2c.mm_i2c = false; |
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118 | |||
119 | i2c.i2c_id = gpio->sucI2cId.ucAccess; |
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120 | |||
1963 | serge | 121 | if (i2c.mask_clk_reg) |
1117 | serge | 122 | i2c.valid = true; |
2997 | Serge | 123 | else |
124 | i2c.valid = false; |
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1117 | serge | 125 | |
126 | return i2c; |
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127 | } |
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128 | |||
2997 | Serge | 129 | static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, |
130 | uint8_t id) |
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1963 | serge | 131 | { |
132 | struct atom_context *ctx = rdev->mode_info.atom_context; |
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133 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
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134 | struct radeon_i2c_bus_rec i2c; |
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135 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
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136 | struct _ATOM_GPIO_I2C_INFO *i2c_info; |
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137 | uint16_t data_offset, size; |
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138 | int i, num_indices; |
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139 | |||
140 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
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2997 | Serge | 141 | i2c.valid = false; |
1963 | serge | 142 | |
143 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
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144 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
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145 | |||
146 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
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147 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); |
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148 | |||
5078 | serge | 149 | gpio = &i2c_info->asGPIO_Info[0]; |
1963 | serge | 150 | for (i = 0; i < num_indices; i++) { |
151 | |||
2997 | Serge | 152 | radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); |
153 | |||
154 | if (gpio->sucI2cId.ucAccess == id) { |
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155 | i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); |
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156 | break; |
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157 | } |
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5078 | serge | 158 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) |
159 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); |
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1963 | serge | 160 | } |
161 | } |
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162 | |||
2997 | Serge | 163 | return i2c; |
164 | } |
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1963 | serge | 165 | |
2997 | Serge | 166 | void radeon_atombios_i2c_init(struct radeon_device *rdev) |
167 | { |
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168 | struct atom_context *ctx = rdev->mode_info.atom_context; |
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169 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
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170 | struct radeon_i2c_bus_rec i2c; |
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171 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
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172 | struct _ATOM_GPIO_I2C_INFO *i2c_info; |
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173 | uint16_t data_offset, size; |
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174 | int i, num_indices; |
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175 | char stmp[32]; |
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1963 | serge | 176 | |
2997 | Serge | 177 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
178 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
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1963 | serge | 179 | |
2997 | Serge | 180 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
181 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); |
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1963 | serge | 182 | |
5078 | serge | 183 | gpio = &i2c_info->asGPIO_Info[0]; |
2997 | Serge | 184 | for (i = 0; i < num_indices; i++) { |
185 | radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); |
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186 | |||
187 | i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); |
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188 | |||
189 | if (i2c.valid) { |
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1963 | serge | 190 | sprintf(stmp, "0x%x", i2c.i2c_id); |
191 | rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); |
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192 | } |
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5078 | serge | 193 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) |
194 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); |
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1963 | serge | 195 | } |
196 | } |
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197 | } |
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198 | |||
2997 | Serge | 199 | static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, |
1321 | serge | 200 | u8 id) |
201 | { |
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202 | struct atom_context *ctx = rdev->mode_info.atom_context; |
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203 | struct radeon_gpio_rec gpio; |
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204 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); |
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205 | struct _ATOM_GPIO_PIN_LUT *gpio_info; |
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206 | ATOM_GPIO_PIN_ASSIGNMENT *pin; |
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207 | u16 data_offset, size; |
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208 | int i, num_indices; |
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209 | |||
210 | memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); |
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211 | gpio.valid = false; |
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212 | |||
1963 | serge | 213 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
1321 | serge | 214 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); |
215 | |||
1963 | serge | 216 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
217 | sizeof(ATOM_GPIO_PIN_ASSIGNMENT); |
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1321 | serge | 218 | |
5078 | serge | 219 | pin = gpio_info->asGPIO_Pin; |
1321 | serge | 220 | for (i = 0; i < num_indices; i++) { |
221 | if (id == pin->ucGPIO_ID) { |
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222 | gpio.id = pin->ucGPIO_ID; |
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1963 | serge | 223 | gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; |
1321 | serge | 224 | gpio.mask = (1 << pin->ucGpioPinBitShift); |
225 | gpio.valid = true; |
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226 | break; |
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227 | } |
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5078 | serge | 228 | pin = (ATOM_GPIO_PIN_ASSIGNMENT *) |
229 | ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); |
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1321 | serge | 230 | } |
1963 | serge | 231 | } |
1321 | serge | 232 | |
233 | return gpio; |
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234 | } |
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235 | |||
236 | static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, |
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237 | struct radeon_gpio_rec *gpio) |
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238 | { |
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239 | struct radeon_hpd hpd; |
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1430 | serge | 240 | u32 reg; |
241 | |||
1963 | serge | 242 | memset(&hpd, 0, sizeof(struct radeon_hpd)); |
243 | |||
2997 | Serge | 244 | if (ASIC_IS_DCE6(rdev)) |
245 | reg = SI_DC_GPIO_HPD_A; |
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246 | else if (ASIC_IS_DCE4(rdev)) |
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1430 | serge | 247 | reg = EVERGREEN_DC_GPIO_HPD_A; |
248 | else |
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249 | reg = AVIVO_DC_GPIO_HPD_A; |
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250 | |||
1321 | serge | 251 | hpd.gpio = *gpio; |
1430 | serge | 252 | if (gpio->reg == reg) { |
1321 | serge | 253 | switch(gpio->mask) { |
254 | case (1 << 0): |
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255 | hpd.hpd = RADEON_HPD_1; |
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256 | break; |
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257 | case (1 << 8): |
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258 | hpd.hpd = RADEON_HPD_2; |
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259 | break; |
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260 | case (1 << 16): |
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261 | hpd.hpd = RADEON_HPD_3; |
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262 | break; |
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263 | case (1 << 24): |
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264 | hpd.hpd = RADEON_HPD_4; |
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265 | break; |
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266 | case (1 << 26): |
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267 | hpd.hpd = RADEON_HPD_5; |
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268 | break; |
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269 | case (1 << 28): |
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270 | hpd.hpd = RADEON_HPD_6; |
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271 | break; |
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272 | default: |
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273 | hpd.hpd = RADEON_HPD_NONE; |
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274 | break; |
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275 | } |
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276 | } else |
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277 | hpd.hpd = RADEON_HPD_NONE; |
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278 | return hpd; |
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279 | } |
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280 | |||
1117 | serge | 281 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
282 | uint32_t supported_device, |
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283 | int *connector_type, |
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1179 | serge | 284 | struct radeon_i2c_bus_rec *i2c_bus, |
1321 | serge | 285 | uint16_t *line_mux, |
286 | struct radeon_hpd *hpd) |
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1117 | serge | 287 | { |
288 | |||
289 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
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290 | if ((dev->pdev->device == 0x791e) && |
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291 | (dev->pdev->subsystem_vendor == 0x1043) && |
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292 | (dev->pdev->subsystem_device == 0x826d)) { |
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293 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
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294 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
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295 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
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296 | } |
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297 | |||
1428 | serge | 298 | /* Asrock RS600 board lists the DVI port as HDMI */ |
299 | if ((dev->pdev->device == 0x7941) && |
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300 | (dev->pdev->subsystem_vendor == 0x1849) && |
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301 | (dev->pdev->subsystem_device == 0x7941)) { |
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302 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
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303 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
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304 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
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305 | } |
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306 | |||
1963 | serge | 307 | /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ |
308 | if ((dev->pdev->device == 0x796e) && |
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309 | (dev->pdev->subsystem_vendor == 0x1462) && |
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310 | (dev->pdev->subsystem_device == 0x7302)) { |
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311 | if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || |
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312 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
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313 | return false; |
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314 | } |
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315 | |||
1117 | serge | 316 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
317 | if ((dev->pdev->device == 0x7941) && |
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318 | (dev->pdev->subsystem_vendor == 0x147b) && |
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319 | (dev->pdev->subsystem_device == 0x2412)) { |
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320 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) |
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321 | return false; |
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322 | } |
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323 | |||
324 | /* Falcon NW laptop lists vga ddc line for LVDS */ |
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325 | if ((dev->pdev->device == 0x5653) && |
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326 | (dev->pdev->subsystem_vendor == 0x1462) && |
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327 | (dev->pdev->subsystem_device == 0x0291)) { |
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1179 | serge | 328 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
1117 | serge | 329 | i2c_bus->valid = false; |
1179 | serge | 330 | *line_mux = 53; |
331 | } |
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1117 | serge | 332 | } |
333 | |||
1321 | serge | 334 | /* HIS X1300 is DVI+VGA, not DVI+DVI */ |
335 | if ((dev->pdev->device == 0x7146) && |
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336 | (dev->pdev->subsystem_vendor == 0x17af) && |
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337 | (dev->pdev->subsystem_device == 0x2058)) { |
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338 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) |
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339 | return false; |
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340 | } |
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341 | |||
342 | /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ |
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343 | if ((dev->pdev->device == 0x7142) && |
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344 | (dev->pdev->subsystem_vendor == 0x1458) && |
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345 | (dev->pdev->subsystem_device == 0x2134)) { |
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346 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) |
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347 | return false; |
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348 | } |
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349 | |||
350 | |||
1117 | serge | 351 | /* Funky macbooks */ |
352 | if ((dev->pdev->device == 0x71C5) && |
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353 | (dev->pdev->subsystem_vendor == 0x106b) && |
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354 | (dev->pdev->subsystem_device == 0x0080)) { |
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355 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
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356 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
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357 | return false; |
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1963 | serge | 358 | if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) |
359 | *line_mux = 0x90; |
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1117 | serge | 360 | } |
361 | |||
1963 | serge | 362 | /* mac rv630, rv730, others */ |
363 | if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && |
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364 | (*connector_type == DRM_MODE_CONNECTOR_DVII)) { |
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365 | *connector_type = DRM_MODE_CONNECTOR_9PinDIN; |
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366 | *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; |
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367 | } |
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368 | |||
1117 | serge | 369 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
370 | if ((dev->pdev->device == 0x9598) && |
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371 | (dev->pdev->subsystem_vendor == 0x1043) && |
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372 | (dev->pdev->subsystem_device == 0x01da)) { |
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1179 | serge | 373 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
374 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
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1117 | serge | 375 | } |
376 | } |
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377 | |||
1963 | serge | 378 | /* ASUS HD 3600 board lists the DVI port as HDMI */ |
379 | if ((dev->pdev->device == 0x9598) && |
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380 | (dev->pdev->subsystem_vendor == 0x1043) && |
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381 | (dev->pdev->subsystem_device == 0x01e4)) { |
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382 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
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383 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
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384 | } |
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385 | } |
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386 | |||
1179 | serge | 387 | /* ASUS HD 3450 board lists the DVI port as HDMI */ |
388 | if ((dev->pdev->device == 0x95C5) && |
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389 | (dev->pdev->subsystem_vendor == 0x1043) && |
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390 | (dev->pdev->subsystem_device == 0x01e2)) { |
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391 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
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392 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
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393 | } |
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394 | } |
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395 | |||
396 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
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397 | * HDMI + VGA reporting as HDMI |
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398 | */ |
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399 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
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400 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
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401 | *connector_type = DRM_MODE_CONNECTOR_VGA; |
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402 | *line_mux = 0; |
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403 | } |
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404 | } |
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405 | |||
1963 | serge | 406 | /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port |
407 | * on the laptop and a DVI port on the docking station and |
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408 | * both share the same encoder, hpd pin, and ddc line. |
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409 | * So while the bios table is technically correct, |
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410 | * we drop the DVI port here since xrandr has no concept of |
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411 | * encoders and will try and drive both connectors |
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412 | * with different crtcs which isn't possible on the hardware |
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413 | * side and leaves no crtcs for LVDS or VGA. |
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414 | */ |
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415 | if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && |
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1321 | serge | 416 | (dev->pdev->subsystem_vendor == 0x1025) && |
417 | (dev->pdev->subsystem_device == 0x013c)) { |
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418 | if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && |
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1963 | serge | 419 | (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { |
420 | /* actually it's a DVI-D port not DVI-I */ |
||
1321 | serge | 421 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
1963 | serge | 422 | return false; |
423 | } |
||
1321 | serge | 424 | } |
425 | |||
1412 | serge | 426 | /* XFX Pine Group device rv730 reports no VGA DDC lines |
427 | * even though they are wired up to record 0x93 |
||
428 | */ |
||
429 | if ((dev->pdev->device == 0x9498) && |
||
430 | (dev->pdev->subsystem_vendor == 0x1682) && |
||
2997 | Serge | 431 | (dev->pdev->subsystem_device == 0x2452) && |
432 | (i2c_bus->valid == false) && |
||
433 | !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { |
||
1412 | serge | 434 | struct radeon_device *rdev = dev->dev_private; |
435 | *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); |
||
436 | } |
||
2997 | Serge | 437 | |
438 | /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ |
||
439 | if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) && |
||
440 | (dev->pdev->subsystem_vendor == 0x1734) && |
||
441 | (dev->pdev->subsystem_device == 0x11bd)) { |
||
442 | if (*connector_type == DRM_MODE_CONNECTOR_VGA) { |
||
443 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
||
444 | *line_mux = 0x3103; |
||
445 | } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { |
||
446 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
||
447 | } |
||
448 | } |
||
449 | |||
450 | |||
1117 | serge | 451 | return true; |
452 | } |
||
453 | |||
454 | const int supported_devices_connector_convert[] = { |
||
455 | DRM_MODE_CONNECTOR_Unknown, |
||
456 | DRM_MODE_CONNECTOR_VGA, |
||
457 | DRM_MODE_CONNECTOR_DVII, |
||
458 | DRM_MODE_CONNECTOR_DVID, |
||
459 | DRM_MODE_CONNECTOR_DVIA, |
||
460 | DRM_MODE_CONNECTOR_SVIDEO, |
||
461 | DRM_MODE_CONNECTOR_Composite, |
||
462 | DRM_MODE_CONNECTOR_LVDS, |
||
463 | DRM_MODE_CONNECTOR_Unknown, |
||
464 | DRM_MODE_CONNECTOR_Unknown, |
||
465 | DRM_MODE_CONNECTOR_HDMIA, |
||
466 | DRM_MODE_CONNECTOR_HDMIB, |
||
467 | DRM_MODE_CONNECTOR_Unknown, |
||
468 | DRM_MODE_CONNECTOR_Unknown, |
||
469 | DRM_MODE_CONNECTOR_9PinDIN, |
||
470 | DRM_MODE_CONNECTOR_DisplayPort |
||
471 | }; |
||
472 | |||
1268 | serge | 473 | const uint16_t supported_devices_connector_object_id_convert[] = { |
474 | CONNECTOR_OBJECT_ID_NONE, |
||
475 | CONNECTOR_OBJECT_ID_VGA, |
||
476 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ |
||
477 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ |
||
478 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ |
||
479 | CONNECTOR_OBJECT_ID_COMPOSITE, |
||
480 | CONNECTOR_OBJECT_ID_SVIDEO, |
||
481 | CONNECTOR_OBJECT_ID_LVDS, |
||
482 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
||
483 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
||
484 | CONNECTOR_OBJECT_ID_DISPLAYPORT, |
||
485 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, |
||
486 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, |
||
487 | CONNECTOR_OBJECT_ID_SVIDEO |
||
488 | }; |
||
489 | |||
1117 | serge | 490 | const int object_connector_convert[] = { |
491 | DRM_MODE_CONNECTOR_Unknown, |
||
492 | DRM_MODE_CONNECTOR_DVII, |
||
493 | DRM_MODE_CONNECTOR_DVII, |
||
494 | DRM_MODE_CONNECTOR_DVID, |
||
495 | DRM_MODE_CONNECTOR_DVID, |
||
496 | DRM_MODE_CONNECTOR_VGA, |
||
497 | DRM_MODE_CONNECTOR_Composite, |
||
498 | DRM_MODE_CONNECTOR_SVIDEO, |
||
499 | DRM_MODE_CONNECTOR_Unknown, |
||
1179 | serge | 500 | DRM_MODE_CONNECTOR_Unknown, |
1117 | serge | 501 | DRM_MODE_CONNECTOR_9PinDIN, |
502 | DRM_MODE_CONNECTOR_Unknown, |
||
503 | DRM_MODE_CONNECTOR_HDMIA, |
||
504 | DRM_MODE_CONNECTOR_HDMIB, |
||
505 | DRM_MODE_CONNECTOR_LVDS, |
||
506 | DRM_MODE_CONNECTOR_9PinDIN, |
||
507 | DRM_MODE_CONNECTOR_Unknown, |
||
508 | DRM_MODE_CONNECTOR_Unknown, |
||
509 | DRM_MODE_CONNECTOR_Unknown, |
||
1404 | serge | 510 | DRM_MODE_CONNECTOR_DisplayPort, |
511 | DRM_MODE_CONNECTOR_eDP, |
||
512 | DRM_MODE_CONNECTOR_Unknown |
||
1117 | serge | 513 | }; |
514 | |||
515 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) |
||
516 | { |
||
517 | struct radeon_device *rdev = dev->dev_private; |
||
518 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
519 | struct atom_context *ctx = mode_info->atom_context; |
||
520 | int index = GetIndexIntoMasterTable(DATA, Object_Header); |
||
1321 | serge | 521 | u16 size, data_offset; |
522 | u8 frev, crev; |
||
1117 | serge | 523 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
1963 | serge | 524 | ATOM_ENCODER_OBJECT_TABLE *enc_obj; |
525 | ATOM_OBJECT_TABLE *router_obj; |
||
1117 | serge | 526 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
527 | ATOM_OBJECT_HEADER *obj_header; |
||
1963 | serge | 528 | int i, j, k, path_size, device_support; |
1117 | serge | 529 | int connector_type; |
1321 | serge | 530 | u16 igp_lane_info, conn_id, connector_object_id; |
1117 | serge | 531 | struct radeon_i2c_bus_rec ddc_bus; |
1963 | serge | 532 | struct radeon_router router; |
1321 | serge | 533 | struct radeon_gpio_rec gpio; |
534 | struct radeon_hpd hpd; |
||
1117 | serge | 535 | |
1963 | serge | 536 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) |
1117 | serge | 537 | return false; |
538 | |||
539 | if (crev < 2) |
||
540 | return false; |
||
541 | |||
542 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); |
||
543 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) |
||
544 | (ctx->bios + data_offset + |
||
545 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); |
||
546 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) |
||
547 | (ctx->bios + data_offset + |
||
548 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); |
||
1963 | serge | 549 | enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) |
550 | (ctx->bios + data_offset + |
||
551 | le16_to_cpu(obj_header->usEncoderObjectTableOffset)); |
||
552 | router_obj = (ATOM_OBJECT_TABLE *) |
||
553 | (ctx->bios + data_offset + |
||
554 | le16_to_cpu(obj_header->usRouterObjectTableOffset)); |
||
1117 | serge | 555 | device_support = le16_to_cpu(obj_header->usDeviceSupport); |
556 | |||
557 | path_size = 0; |
||
558 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { |
||
559 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; |
||
560 | ATOM_DISPLAY_OBJECT_PATH *path; |
||
561 | addr += path_size; |
||
562 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; |
||
563 | path_size += le16_to_cpu(path->usSize); |
||
1963 | serge | 564 | |
1117 | serge | 565 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
566 | uint8_t con_obj_id, con_obj_num, con_obj_type; |
||
567 | |||
568 | con_obj_id = |
||
569 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) |
||
570 | >> OBJECT_ID_SHIFT; |
||
571 | con_obj_num = |
||
572 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) |
||
573 | >> ENUM_ID_SHIFT; |
||
574 | con_obj_type = |
||
575 | (le16_to_cpu(path->usConnObjectId) & |
||
576 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
||
577 | |||
1221 | serge | 578 | /* TODO CV support */ |
579 | if (le16_to_cpu(path->usDeviceTag) == |
||
580 | ATOM_DEVICE_CV_SUPPORT) |
||
1117 | serge | 581 | continue; |
582 | |||
1268 | serge | 583 | /* IGP chips */ |
584 | if ((rdev->flags & RADEON_IS_IGP) && |
||
1117 | serge | 585 | (con_obj_id == |
586 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
||
587 | uint16_t igp_offset = 0; |
||
588 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; |
||
589 | |||
590 | index = |
||
591 | GetIndexIntoMasterTable(DATA, |
||
592 | IntegratedSystemInfo); |
||
593 | |||
1963 | serge | 594 | if (atom_parse_data_header(ctx, index, &size, &frev, |
595 | &crev, &igp_offset)) { |
||
1117 | serge | 596 | |
597 | if (crev >= 2) { |
||
598 | igp_obj = |
||
599 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 |
||
600 | *) (ctx->bios + igp_offset); |
||
601 | |||
602 | if (igp_obj) { |
||
603 | uint32_t slot_config, ct; |
||
604 | |||
605 | if (con_obj_num == 1) |
||
606 | slot_config = |
||
607 | igp_obj-> |
||
608 | ulDDISlot1Config; |
||
609 | else |
||
610 | slot_config = |
||
611 | igp_obj-> |
||
612 | ulDDISlot2Config; |
||
613 | |||
614 | ct = (slot_config >> 16) & 0xff; |
||
615 | connector_type = |
||
616 | object_connector_convert |
||
617 | [ct]; |
||
1268 | serge | 618 | connector_object_id = ct; |
1117 | serge | 619 | igp_lane_info = |
620 | slot_config & 0xffff; |
||
621 | } else |
||
622 | continue; |
||
623 | } else |
||
624 | continue; |
||
625 | } else { |
||
626 | igp_lane_info = 0; |
||
627 | connector_type = |
||
628 | object_connector_convert[con_obj_id]; |
||
1268 | serge | 629 | connector_object_id = con_obj_id; |
1117 | serge | 630 | } |
1963 | serge | 631 | } else { |
632 | igp_lane_info = 0; |
||
633 | connector_type = |
||
634 | object_connector_convert[con_obj_id]; |
||
635 | connector_object_id = con_obj_id; |
||
636 | } |
||
1117 | serge | 637 | |
638 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
||
639 | continue; |
||
640 | |||
1963 | serge | 641 | router.ddc_valid = false; |
642 | router.cd_valid = false; |
||
643 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { |
||
644 | uint8_t grph_obj_id, grph_obj_num, grph_obj_type; |
||
1117 | serge | 645 | |
1963 | serge | 646 | grph_obj_id = |
1117 | serge | 647 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
648 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
||
1963 | serge | 649 | grph_obj_num = |
1117 | serge | 650 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
651 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
||
1963 | serge | 652 | grph_obj_type = |
1117 | serge | 653 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
654 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
||
655 | |||
1963 | serge | 656 | if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { |
657 | for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { |
||
658 | u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); |
||
659 | if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { |
||
660 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) |
||
661 | (ctx->bios + data_offset + |
||
662 | le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); |
||
663 | ATOM_ENCODER_CAP_RECORD *cap_record; |
||
664 | u16 caps = 0; |
||
1117 | serge | 665 | |
1963 | serge | 666 | while (record->ucRecordSize > 0 && |
667 | record->ucRecordType > 0 && |
||
668 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
||
669 | switch (record->ucRecordType) { |
||
670 | case ATOM_ENCODER_CAP_RECORD_TYPE: |
||
671 | cap_record =(ATOM_ENCODER_CAP_RECORD *) |
||
672 | record; |
||
673 | caps = le16_to_cpu(cap_record->usEncoderCap); |
||
674 | break; |
||
675 | } |
||
676 | record = (ATOM_COMMON_RECORD_HEADER *) |
||
677 | ((char *)record + record->ucRecordSize); |
||
678 | } |
||
1123 | serge | 679 | radeon_add_atom_encoder(dev, |
1963 | serge | 680 | encoder_obj, |
1123 | serge | 681 | le16_to_cpu |
682 | (path-> |
||
1963 | serge | 683 | usDeviceTag), |
684 | caps); |
||
685 | } |
||
686 | } |
||
687 | } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { |
||
688 | for (k = 0; k < router_obj->ucNumberOfObjects; k++) { |
||
689 | u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); |
||
690 | if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { |
||
691 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) |
||
692 | (ctx->bios + data_offset + |
||
693 | le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); |
||
694 | ATOM_I2C_RECORD *i2c_record; |
||
695 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
||
696 | ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; |
||
697 | ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; |
||
698 | ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = |
||
699 | (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) |
||
700 | (ctx->bios + data_offset + |
||
701 | le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); |
||
5078 | serge | 702 | u8 *num_dst_objs = (u8 *) |
703 | ((u8 *)router_src_dst_table + 1 + |
||
704 | (router_src_dst_table->ucNumberOfSrc * 2)); |
||
705 | u16 *dst_objs = (u16 *)(num_dst_objs + 1); |
||
1963 | serge | 706 | int enum_id; |
1117 | serge | 707 | |
1963 | serge | 708 | router.router_id = router_obj_id; |
5078 | serge | 709 | for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { |
1963 | serge | 710 | if (le16_to_cpu(path->usConnObjectId) == |
5078 | serge | 711 | le16_to_cpu(dst_objs[enum_id])) |
1963 | serge | 712 | break; |
713 | } |
||
714 | |||
715 | while (record->ucRecordSize > 0 && |
||
716 | record->ucRecordType > 0 && |
||
717 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
||
718 | switch (record->ucRecordType) { |
||
719 | case ATOM_I2C_RECORD_TYPE: |
||
720 | i2c_record = |
||
721 | (ATOM_I2C_RECORD *) |
||
722 | record; |
||
723 | i2c_config = |
||
724 | (ATOM_I2C_ID_CONFIG_ACCESS *) |
||
725 | &i2c_record->sucI2cId; |
||
726 | router.i2c_info = |
||
727 | radeon_lookup_i2c_gpio(rdev, |
||
728 | i2c_config-> |
||
729 | ucAccess); |
||
730 | router.i2c_addr = i2c_record->ucI2CAddr >> 1; |
||
731 | break; |
||
732 | case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: |
||
733 | ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) |
||
734 | record; |
||
735 | router.ddc_valid = true; |
||
736 | router.ddc_mux_type = ddc_path->ucMuxType; |
||
737 | router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; |
||
738 | router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; |
||
739 | break; |
||
740 | case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: |
||
741 | cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) |
||
742 | record; |
||
743 | router.cd_valid = true; |
||
744 | router.cd_mux_type = cd_path->ucMuxType; |
||
745 | router.cd_mux_control_pin = cd_path->ucMuxControlPin; |
||
746 | router.cd_mux_state = cd_path->ucMuxState[enum_id]; |
||
747 | break; |
||
748 | } |
||
749 | record = (ATOM_COMMON_RECORD_HEADER *) |
||
750 | ((char *)record + record->ucRecordSize); |
||
751 | } |
||
752 | } |
||
753 | } |
||
1117 | serge | 754 | } |
755 | } |
||
756 | |||
1321 | serge | 757 | /* look up gpio for ddc, hpd */ |
1963 | serge | 758 | ddc_bus.valid = false; |
759 | hpd.hpd = RADEON_HPD_NONE; |
||
1117 | serge | 760 | if ((le16_to_cpu(path->usDeviceTag) & |
1321 | serge | 761 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { |
1117 | serge | 762 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
763 | if (le16_to_cpu(path->usConnObjectId) == |
||
764 | le16_to_cpu(con_obj->asObjects[j]. |
||
765 | usObjectID)) { |
||
766 | ATOM_COMMON_RECORD_HEADER |
||
767 | *record = |
||
768 | (ATOM_COMMON_RECORD_HEADER |
||
769 | *) |
||
770 | (ctx->bios + data_offset + |
||
771 | le16_to_cpu(con_obj-> |
||
772 | asObjects[j]. |
||
773 | usRecordOffset)); |
||
774 | ATOM_I2C_RECORD *i2c_record; |
||
1321 | serge | 775 | ATOM_HPD_INT_RECORD *hpd_record; |
776 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
||
1117 | serge | 777 | |
1963 | serge | 778 | while (record->ucRecordSize > 0 && |
779 | record->ucRecordType > 0 && |
||
780 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
||
1321 | serge | 781 | switch (record->ucRecordType) { |
1117 | serge | 782 | case ATOM_I2C_RECORD_TYPE: |
783 | i2c_record = |
||
1321 | serge | 784 | (ATOM_I2C_RECORD *) |
785 | record; |
||
786 | i2c_config = |
||
787 | (ATOM_I2C_ID_CONFIG_ACCESS *) |
||
788 | &i2c_record->sucI2cId; |
||
789 | ddc_bus = radeon_lookup_i2c_gpio(rdev, |
||
790 | i2c_config-> |
||
791 | ucAccess); |
||
1117 | serge | 792 | break; |
1321 | serge | 793 | case ATOM_HPD_INT_RECORD_TYPE: |
794 | hpd_record = |
||
795 | (ATOM_HPD_INT_RECORD *) |
||
796 | record; |
||
797 | gpio = radeon_lookup_gpio(rdev, |
||
798 | hpd_record->ucHPDIntGPIOID); |
||
799 | hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); |
||
800 | hpd.plugged_state = hpd_record->ucPlugged_PinState; |
||
801 | break; |
||
1117 | serge | 802 | } |
803 | record = |
||
804 | (ATOM_COMMON_RECORD_HEADER |
||
805 | *) ((char *)record |
||
806 | + |
||
807 | record-> |
||
808 | ucRecordSize); |
||
809 | } |
||
810 | break; |
||
811 | } |
||
812 | } |
||
1321 | serge | 813 | } |
1117 | serge | 814 | |
1430 | serge | 815 | /* needed for aux chan transactions */ |
1963 | serge | 816 | ddc_bus.hpd = hpd.hpd; |
1430 | serge | 817 | |
1179 | serge | 818 | conn_id = le16_to_cpu(path->usConnObjectId); |
819 | |||
820 | if (!radeon_atom_apply_quirks |
||
821 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, |
||
1321 | serge | 822 | &ddc_bus, &conn_id, &hpd)) |
1179 | serge | 823 | continue; |
824 | |||
1123 | serge | 825 | radeon_add_atom_connector(dev, |
1179 | serge | 826 | conn_id, |
1123 | serge | 827 | le16_to_cpu(path-> |
828 | usDeviceTag), |
||
829 | connector_type, &ddc_bus, |
||
1963 | serge | 830 | igp_lane_info, |
1321 | serge | 831 | connector_object_id, |
1963 | serge | 832 | &hpd, |
833 | &router); |
||
1117 | serge | 834 | |
835 | } |
||
836 | } |
||
837 | |||
1123 | serge | 838 | radeon_link_encoder_connector(dev); |
1117 | serge | 839 | |
840 | return true; |
||
841 | } |
||
842 | |||
1268 | serge | 843 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
844 | int connector_type, |
||
845 | uint16_t devices) |
||
846 | { |
||
847 | struct radeon_device *rdev = dev->dev_private; |
||
848 | |||
849 | if (rdev->flags & RADEON_IS_IGP) { |
||
850 | return supported_devices_connector_object_id_convert |
||
851 | [connector_type]; |
||
852 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || |
||
853 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && |
||
854 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
||
855 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
856 | struct atom_context *ctx = mode_info->atom_context; |
||
857 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); |
||
858 | uint16_t size, data_offset; |
||
859 | uint8_t frev, crev; |
||
860 | ATOM_XTMDS_INFO *xtmds; |
||
861 | |||
1963 | serge | 862 | if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { |
1268 | serge | 863 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); |
864 | |||
865 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { |
||
866 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
||
867 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
||
868 | else |
||
869 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
||
870 | } else { |
||
871 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
||
872 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
||
873 | else |
||
874 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
||
875 | } |
||
1963 | serge | 876 | } else |
877 | return supported_devices_connector_object_id_convert |
||
878 | [connector_type]; |
||
1268 | serge | 879 | } else { |
880 | return supported_devices_connector_object_id_convert |
||
881 | [connector_type]; |
||
882 | } |
||
883 | } |
||
884 | |||
1117 | serge | 885 | struct bios_connector { |
886 | bool valid; |
||
1179 | serge | 887 | uint16_t line_mux; |
1117 | serge | 888 | uint16_t devices; |
889 | int connector_type; |
||
890 | struct radeon_i2c_bus_rec ddc_bus; |
||
1321 | serge | 891 | struct radeon_hpd hpd; |
1117 | serge | 892 | }; |
893 | |||
894 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct |
||
895 | drm_device |
||
896 | *dev) |
||
897 | { |
||
898 | struct radeon_device *rdev = dev->dev_private; |
||
899 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
900 | struct atom_context *ctx = mode_info->atom_context; |
||
901 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); |
||
902 | uint16_t size, data_offset; |
||
903 | uint8_t frev, crev; |
||
904 | uint16_t device_support; |
||
905 | uint8_t dac; |
||
906 | union atom_supported_devices *supported_devices; |
||
1321 | serge | 907 | int i, j, max_device; |
1963 | serge | 908 | struct bios_connector *bios_connectors; |
909 | size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; |
||
910 | struct radeon_router router; |
||
1117 | serge | 911 | |
1963 | serge | 912 | router.ddc_valid = false; |
913 | router.cd_valid = false; |
||
1128 | serge | 914 | |
1963 | serge | 915 | bios_connectors = kzalloc(bc_size, GFP_KERNEL); |
916 | if (!bios_connectors) |
||
917 | return false; |
||
918 | |||
919 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, |
||
920 | &data_offset)) { |
||
921 | kfree(bios_connectors); |
||
922 | return false; |
||
923 | } |
||
924 | |||
1117 | serge | 925 | supported_devices = |
926 | (union atom_supported_devices *)(ctx->bios + data_offset); |
||
927 | |||
928 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); |
||
929 | |||
1321 | serge | 930 | if (frev > 1) |
931 | max_device = ATOM_MAX_SUPPORTED_DEVICE; |
||
932 | else |
||
933 | max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; |
||
934 | |||
935 | for (i = 0; i < max_device; i++) { |
||
1117 | serge | 936 | ATOM_CONNECTOR_INFO_I2C ci = |
937 | supported_devices->info.asConnInfo[i]; |
||
938 | |||
939 | bios_connectors[i].valid = false; |
||
940 | |||
941 | if (!(device_support & (1 << i))) { |
||
942 | continue; |
||
943 | } |
||
944 | |||
945 | if (i == ATOM_DEVICE_CV_INDEX) { |
||
1963 | serge | 946 | DRM_DEBUG_KMS("Skipping Component Video\n"); |
1117 | serge | 947 | continue; |
948 | } |
||
949 | |||
950 | bios_connectors[i].connector_type = |
||
951 | supported_devices_connector_convert[ci.sucConnectorInfo. |
||
952 | sbfAccess. |
||
953 | bfConnectorType]; |
||
954 | |||
955 | if (bios_connectors[i].connector_type == |
||
956 | DRM_MODE_CONNECTOR_Unknown) |
||
957 | continue; |
||
958 | |||
959 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; |
||
960 | |||
961 | bios_connectors[i].line_mux = |
||
1321 | serge | 962 | ci.sucI2cId.ucAccess; |
1117 | serge | 963 | |
964 | /* give tv unique connector ids */ |
||
965 | if (i == ATOM_DEVICE_TV1_INDEX) { |
||
966 | bios_connectors[i].ddc_bus.valid = false; |
||
967 | bios_connectors[i].line_mux = 50; |
||
968 | } else if (i == ATOM_DEVICE_TV2_INDEX) { |
||
969 | bios_connectors[i].ddc_bus.valid = false; |
||
970 | bios_connectors[i].line_mux = 51; |
||
971 | } else if (i == ATOM_DEVICE_CV_INDEX) { |
||
972 | bios_connectors[i].ddc_bus.valid = false; |
||
973 | bios_connectors[i].line_mux = 52; |
||
974 | } else |
||
975 | bios_connectors[i].ddc_bus = |
||
1321 | serge | 976 | radeon_lookup_i2c_gpio(rdev, |
1117 | serge | 977 | bios_connectors[i].line_mux); |
978 | |||
1321 | serge | 979 | if ((crev > 1) && (frev > 1)) { |
980 | u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; |
||
981 | switch (isb) { |
||
982 | case 0x4: |
||
983 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; |
||
984 | break; |
||
985 | case 0xa: |
||
986 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; |
||
987 | break; |
||
988 | default: |
||
989 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; |
||
990 | break; |
||
991 | } |
||
992 | } else { |
||
993 | if (i == ATOM_DEVICE_DFP1_INDEX) |
||
994 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; |
||
995 | else if (i == ATOM_DEVICE_DFP2_INDEX) |
||
996 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; |
||
997 | else |
||
998 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; |
||
999 | } |
||
1000 | |||
1117 | serge | 1001 | /* Always set the connector type to VGA for CRT1/CRT2. if they are |
1002 | * shared with a DVI port, we'll pick up the DVI connector when we |
||
1003 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. |
||
1004 | */ |
||
1005 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) |
||
1006 | bios_connectors[i].connector_type = |
||
1007 | DRM_MODE_CONNECTOR_VGA; |
||
1008 | |||
1009 | if (!radeon_atom_apply_quirks |
||
1010 | (dev, (1 << i), &bios_connectors[i].connector_type, |
||
1321 | serge | 1011 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, |
1012 | &bios_connectors[i].hpd)) |
||
1117 | serge | 1013 | continue; |
1014 | |||
1015 | bios_connectors[i].valid = true; |
||
1016 | bios_connectors[i].devices = (1 << i); |
||
1017 | |||
1123 | serge | 1018 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) |
1019 | radeon_add_atom_encoder(dev, |
||
1963 | serge | 1020 | radeon_get_encoder_enum(dev, |
1123 | serge | 1021 | (1 << i), |
1022 | dac), |
||
1963 | serge | 1023 | (1 << i), |
1024 | 0); |
||
1123 | serge | 1025 | else |
1026 | radeon_add_legacy_encoder(dev, |
||
1963 | serge | 1027 | radeon_get_encoder_enum(dev, |
1404 | serge | 1028 | (1 << i), |
1123 | serge | 1029 | dac), |
1030 | (1 << i)); |
||
1117 | serge | 1031 | } |
1032 | |||
1033 | /* combine shared connectors */ |
||
1321 | serge | 1034 | for (i = 0; i < max_device; i++) { |
1117 | serge | 1035 | if (bios_connectors[i].valid) { |
1321 | serge | 1036 | for (j = 0; j < max_device; j++) { |
1117 | serge | 1037 | if (bios_connectors[j].valid && (i != j)) { |
1038 | if (bios_connectors[i].line_mux == |
||
1039 | bios_connectors[j].line_mux) { |
||
1404 | serge | 1040 | /* make sure not to combine LVDS */ |
1041 | if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
||
1042 | bios_connectors[i].line_mux = 53; |
||
1043 | bios_connectors[i].ddc_bus.valid = false; |
||
1044 | continue; |
||
1045 | } |
||
1046 | if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
||
1047 | bios_connectors[j].line_mux = 53; |
||
1048 | bios_connectors[j].ddc_bus.valid = false; |
||
1049 | continue; |
||
1050 | } |
||
1051 | /* combine analog and digital for DVI-I */ |
||
1052 | if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && |
||
1053 | (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || |
||
1054 | ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && |
||
1055 | (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { |
||
1056 | bios_connectors[i].devices |= |
||
1057 | bios_connectors[j].devices; |
||
1058 | bios_connectors[i].connector_type = |
||
1117 | serge | 1059 | DRM_MODE_CONNECTOR_DVII; |
1404 | serge | 1060 | if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) |
1321 | serge | 1061 | bios_connectors[i].hpd = |
1062 | bios_connectors[j].hpd; |
||
1404 | serge | 1063 | bios_connectors[j].valid = false; |
1117 | serge | 1064 | } |
1065 | } |
||
1066 | } |
||
1067 | } |
||
1068 | } |
||
1069 | } |
||
1070 | |||
1071 | /* add the connectors */ |
||
1321 | serge | 1072 | for (i = 0; i < max_device; i++) { |
1268 | serge | 1073 | if (bios_connectors[i].valid) { |
1074 | uint16_t connector_object_id = |
||
1075 | atombios_get_connector_object_id(dev, |
||
1076 | bios_connectors[i].connector_type, |
||
1077 | bios_connectors[i].devices); |
||
1123 | serge | 1078 | radeon_add_atom_connector(dev, |
1079 | bios_connectors[i].line_mux, |
||
1080 | bios_connectors[i].devices, |
||
1081 | bios_connectors[i]. |
||
1082 | connector_type, |
||
1083 | &bios_connectors[i].ddc_bus, |
||
1963 | serge | 1084 | 0, |
1321 | serge | 1085 | connector_object_id, |
1963 | serge | 1086 | &bios_connectors[i].hpd, |
1087 | &router); |
||
1268 | serge | 1088 | } |
1123 | serge | 1089 | } |
1117 | serge | 1090 | |
1123 | serge | 1091 | radeon_link_encoder_connector(dev); |
1128 | serge | 1092 | |
1963 | serge | 1093 | kfree(bios_connectors); |
1117 | serge | 1094 | return true; |
1095 | } |
||
1096 | |||
1097 | union firmware_info { |
||
1098 | ATOM_FIRMWARE_INFO info; |
||
1099 | ATOM_FIRMWARE_INFO_V1_2 info_12; |
||
1100 | ATOM_FIRMWARE_INFO_V1_3 info_13; |
||
1101 | ATOM_FIRMWARE_INFO_V1_4 info_14; |
||
1430 | serge | 1102 | ATOM_FIRMWARE_INFO_V2_1 info_21; |
1963 | serge | 1103 | ATOM_FIRMWARE_INFO_V2_2 info_22; |
1117 | serge | 1104 | }; |
1105 | |||
1106 | bool radeon_atom_get_clock_info(struct drm_device *dev) |
||
1107 | { |
||
1108 | struct radeon_device *rdev = dev->dev_private; |
||
1109 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1110 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
||
1111 | union firmware_info *firmware_info; |
||
1112 | uint8_t frev, crev; |
||
1113 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
||
1114 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
||
1430 | serge | 1115 | struct radeon_pll *dcpll = &rdev->clock.dcpll; |
1117 | serge | 1116 | struct radeon_pll *spll = &rdev->clock.spll; |
1117 | struct radeon_pll *mpll = &rdev->clock.mpll; |
||
1118 | uint16_t data_offset; |
||
1119 | |||
1963 | serge | 1120 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1121 | &frev, &crev, &data_offset)) { |
||
1117 | serge | 1122 | firmware_info = |
1123 | (union firmware_info *)(mode_info->atom_context->bios + |
||
1124 | data_offset); |
||
1125 | /* pixel clocks */ |
||
1126 | p1pll->reference_freq = |
||
1127 | le16_to_cpu(firmware_info->info.usReferenceClock); |
||
1128 | p1pll->reference_div = 0; |
||
1129 | |||
1268 | serge | 1130 | if (crev < 2) |
1117 | serge | 1131 | p1pll->pll_out_min = |
1132 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
||
1268 | serge | 1133 | else |
1134 | p1pll->pll_out_min = |
||
1135 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); |
||
1117 | serge | 1136 | p1pll->pll_out_max = |
1137 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
||
1138 | |||
1963 | serge | 1139 | if (crev >= 4) { |
1140 | p1pll->lcd_pll_out_min = |
||
1141 | le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; |
||
1142 | if (p1pll->lcd_pll_out_min == 0) |
||
1143 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
||
1144 | p1pll->lcd_pll_out_max = |
||
1145 | le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; |
||
1146 | if (p1pll->lcd_pll_out_max == 0) |
||
1147 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
||
1148 | } else { |
||
1149 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
||
1150 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
||
1151 | } |
||
1152 | |||
1117 | serge | 1153 | if (p1pll->pll_out_min == 0) { |
1154 | if (ASIC_IS_AVIVO(rdev)) |
||
1155 | p1pll->pll_out_min = 64800; |
||
1156 | else |
||
1157 | p1pll->pll_out_min = 20000; |
||
1158 | } |
||
1159 | |||
1160 | p1pll->pll_in_min = |
||
1161 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); |
||
1162 | p1pll->pll_in_max = |
||
1163 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); |
||
1164 | |||
1165 | *p2pll = *p1pll; |
||
1166 | |||
1167 | /* system clock */ |
||
1963 | serge | 1168 | if (ASIC_IS_DCE4(rdev)) |
1169 | spll->reference_freq = |
||
1170 | le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); |
||
1171 | else |
||
1117 | serge | 1172 | spll->reference_freq = |
1173 | le16_to_cpu(firmware_info->info.usReferenceClock); |
||
1174 | spll->reference_div = 0; |
||
1175 | |||
1176 | spll->pll_out_min = |
||
1177 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); |
||
1178 | spll->pll_out_max = |
||
1179 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); |
||
1180 | |||
1181 | /* ??? */ |
||
1182 | if (spll->pll_out_min == 0) { |
||
1183 | if (ASIC_IS_AVIVO(rdev)) |
||
1184 | spll->pll_out_min = 64800; |
||
1185 | else |
||
1186 | spll->pll_out_min = 20000; |
||
1187 | } |
||
1188 | |||
1189 | spll->pll_in_min = |
||
1190 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); |
||
1191 | spll->pll_in_max = |
||
1192 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); |
||
1193 | |||
1194 | /* memory clock */ |
||
1963 | serge | 1195 | if (ASIC_IS_DCE4(rdev)) |
1196 | mpll->reference_freq = |
||
1197 | le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); |
||
1198 | else |
||
1117 | serge | 1199 | mpll->reference_freq = |
1200 | le16_to_cpu(firmware_info->info.usReferenceClock); |
||
1201 | mpll->reference_div = 0; |
||
1202 | |||
1203 | mpll->pll_out_min = |
||
1204 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); |
||
1205 | mpll->pll_out_max = |
||
1206 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); |
||
1207 | |||
1208 | /* ??? */ |
||
1209 | if (mpll->pll_out_min == 0) { |
||
1210 | if (ASIC_IS_AVIVO(rdev)) |
||
1211 | mpll->pll_out_min = 64800; |
||
1212 | else |
||
1213 | mpll->pll_out_min = 20000; |
||
1214 | } |
||
1215 | |||
1216 | mpll->pll_in_min = |
||
1217 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); |
||
1218 | mpll->pll_in_max = |
||
1219 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); |
||
1220 | |||
1221 | rdev->clock.default_sclk = |
||
1222 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); |
||
1223 | rdev->clock.default_mclk = |
||
1224 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); |
||
1225 | |||
1430 | serge | 1226 | if (ASIC_IS_DCE4(rdev)) { |
1227 | rdev->clock.default_dispclk = |
||
1228 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); |
||
1963 | serge | 1229 | if (rdev->clock.default_dispclk == 0) { |
5078 | serge | 1230 | if (ASIC_IS_DCE6(rdev)) |
1231 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ |
||
1232 | else if (ASIC_IS_DCE5(rdev)) |
||
1963 | serge | 1233 | rdev->clock.default_dispclk = 54000; /* 540 Mhz */ |
1234 | else |
||
1430 | serge | 1235 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ |
1963 | serge | 1236 | } |
5078 | serge | 1237 | /* set a reasonable default for DP */ |
1238 | if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { |
||
1239 | DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", |
||
1240 | rdev->clock.default_dispclk / 100); |
||
1241 | rdev->clock.default_dispclk = 60000; |
||
1242 | } |
||
1430 | serge | 1243 | rdev->clock.dp_extclk = |
1244 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); |
||
5078 | serge | 1245 | rdev->clock.current_dispclk = rdev->clock.default_dispclk; |
1430 | serge | 1246 | } |
1247 | *dcpll = *p1pll; |
||
1248 | |||
1963 | serge | 1249 | rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); |
1250 | if (rdev->clock.max_pixel_clock == 0) |
||
1251 | rdev->clock.max_pixel_clock = 40000; |
||
1252 | |||
2997 | Serge | 1253 | /* not technically a clock, but... */ |
1254 | rdev->mode_info.firmware_flags = |
||
1255 | le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); |
||
1256 | |||
1117 | serge | 1257 | return true; |
1258 | } |
||
1430 | serge | 1259 | |
1117 | serge | 1260 | return false; |
1261 | } |
||
1262 | |||
1404 | serge | 1263 | union igp_info { |
1264 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; |
||
1265 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; |
||
2997 | Serge | 1266 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; |
1267 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; |
||
5078 | serge | 1268 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; |
1404 | serge | 1269 | }; |
1270 | |||
1271 | bool radeon_atombios_sideport_present(struct radeon_device *rdev) |
||
1272 | { |
||
1273 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1274 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
||
1275 | union igp_info *igp_info; |
||
1276 | u8 frev, crev; |
||
1277 | u16 data_offset; |
||
1278 | |||
1963 | serge | 1279 | /* sideport is AMD only */ |
1280 | if (rdev->family == CHIP_RS600) |
||
1281 | return false; |
||
1404 | serge | 1282 | |
1963 | serge | 1283 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1284 | &frev, &crev, &data_offset)) { |
||
1404 | serge | 1285 | igp_info = (union igp_info *)(mode_info->atom_context->bios + |
1286 | data_offset); |
||
1287 | switch (crev) { |
||
1288 | case 1: |
||
1963 | serge | 1289 | if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) |
1404 | serge | 1290 | return true; |
1291 | break; |
||
1292 | case 2: |
||
1963 | serge | 1293 | if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) |
1404 | serge | 1294 | return true; |
1295 | break; |
||
1296 | default: |
||
1297 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); |
||
1298 | break; |
||
1299 | } |
||
1300 | } |
||
1301 | return false; |
||
1302 | } |
||
1303 | |||
1179 | serge | 1304 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1305 | struct radeon_encoder_int_tmds *tmds) |
||
1117 | serge | 1306 | { |
1307 | struct drm_device *dev = encoder->base.dev; |
||
1308 | struct radeon_device *rdev = dev->dev_private; |
||
1309 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1310 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
||
1311 | uint16_t data_offset; |
||
1312 | struct _ATOM_TMDS_INFO *tmds_info; |
||
1313 | uint8_t frev, crev; |
||
1314 | uint16_t maxfreq; |
||
1315 | int i; |
||
1316 | |||
1963 | serge | 1317 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1318 | &frev, &crev, &data_offset)) { |
||
1117 | serge | 1319 | tmds_info = |
1320 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
||
1321 | data_offset); |
||
1322 | |||
1323 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
||
1324 | for (i = 0; i < 4; i++) { |
||
1325 | tmds->tmds_pll[i].freq = |
||
1326 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); |
||
1327 | tmds->tmds_pll[i].value = |
||
1328 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; |
||
1329 | tmds->tmds_pll[i].value |= |
||
1330 | (tmds_info->asMiscInfo[i]. |
||
1331 | ucPLL_VCO_Gain & 0x3f) << 6; |
||
1332 | tmds->tmds_pll[i].value |= |
||
1333 | (tmds_info->asMiscInfo[i]. |
||
1334 | ucPLL_DutyCycle & 0xf) << 12; |
||
1335 | tmds->tmds_pll[i].value |= |
||
1336 | (tmds_info->asMiscInfo[i]. |
||
1337 | ucPLL_VoltageSwing & 0xf) << 16; |
||
1338 | |||
1963 | serge | 1339 | DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", |
1117 | serge | 1340 | tmds->tmds_pll[i].freq, |
1341 | tmds->tmds_pll[i].value); |
||
1342 | |||
1343 | if (maxfreq == tmds->tmds_pll[i].freq) { |
||
1344 | tmds->tmds_pll[i].freq = 0xffffffff; |
||
1345 | break; |
||
1346 | } |
||
1347 | } |
||
1179 | serge | 1348 | return true; |
1117 | serge | 1349 | } |
1179 | serge | 1350 | return false; |
1117 | serge | 1351 | } |
1352 | |||
1963 | serge | 1353 | bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
1354 | struct radeon_atom_ss *ss, |
||
1268 | serge | 1355 | int id) |
1356 | { |
||
1357 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1358 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); |
||
1963 | serge | 1359 | uint16_t data_offset, size; |
1268 | serge | 1360 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; |
5078 | serge | 1361 | struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; |
1268 | serge | 1362 | uint8_t frev, crev; |
1963 | serge | 1363 | int i, num_indices; |
1268 | serge | 1364 | |
1963 | serge | 1365 | memset(ss, 0, sizeof(struct radeon_atom_ss)); |
1366 | if (atom_parse_data_header(mode_info->atom_context, index, &size, |
||
1367 | &frev, &crev, &data_offset)) { |
||
1268 | serge | 1368 | ss_info = |
1369 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); |
||
1370 | |||
1963 | serge | 1371 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
1372 | sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); |
||
5078 | serge | 1373 | ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) |
1374 | ((u8 *)&ss_info->asSS_Info[0]); |
||
1963 | serge | 1375 | for (i = 0; i < num_indices; i++) { |
5078 | serge | 1376 | if (ss_assign->ucSS_Id == id) { |
1321 | serge | 1377 | ss->percentage = |
5078 | serge | 1378 | le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); |
1379 | ss->type = ss_assign->ucSpreadSpectrumType; |
||
1380 | ss->step = ss_assign->ucSS_Step; |
||
1381 | ss->delay = ss_assign->ucSS_Delay; |
||
1382 | ss->range = ss_assign->ucSS_Range; |
||
1383 | ss->refdiv = ss_assign->ucRecommendedRef_Div; |
||
1963 | serge | 1384 | return true; |
1385 | } |
||
5078 | serge | 1386 | ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) |
1387 | ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); |
||
1963 | serge | 1388 | } |
1268 | serge | 1389 | } |
1963 | serge | 1390 | return false; |
1391 | } |
||
1392 | |||
1393 | static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, |
||
1394 | struct radeon_atom_ss *ss, |
||
1395 | int id) |
||
1396 | { |
||
1397 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1398 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
||
1399 | u16 data_offset, size; |
||
2997 | Serge | 1400 | union igp_info *igp_info; |
1963 | serge | 1401 | u8 frev, crev; |
1402 | u16 percentage = 0, rate = 0; |
||
1403 | |||
1404 | /* get any igp specific overrides */ |
||
1405 | if (atom_parse_data_header(mode_info->atom_context, index, &size, |
||
1406 | &frev, &crev, &data_offset)) { |
||
2997 | Serge | 1407 | igp_info = (union igp_info *) |
1963 | serge | 1408 | (mode_info->atom_context->bios + data_offset); |
2997 | Serge | 1409 | switch (crev) { |
1410 | case 6: |
||
1411 | switch (id) { |
||
1412 | case ASIC_INTERNAL_SS_ON_TMDS: |
||
1413 | percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); |
||
1414 | rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); |
||
1415 | break; |
||
1416 | case ASIC_INTERNAL_SS_ON_HDMI: |
||
1417 | percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); |
||
1418 | rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); |
||
1419 | break; |
||
1420 | case ASIC_INTERNAL_SS_ON_LVDS: |
||
1421 | percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); |
||
1422 | rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); |
||
1423 | break; |
||
1424 | } |
||
1425 | break; |
||
1426 | case 7: |
||
1963 | serge | 1427 | switch (id) { |
1428 | case ASIC_INTERNAL_SS_ON_TMDS: |
||
2997 | Serge | 1429 | percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); |
1430 | rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); |
||
1963 | serge | 1431 | break; |
1432 | case ASIC_INTERNAL_SS_ON_HDMI: |
||
2997 | Serge | 1433 | percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); |
1434 | rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); |
||
1963 | serge | 1435 | break; |
1436 | case ASIC_INTERNAL_SS_ON_LVDS: |
||
2997 | Serge | 1437 | percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); |
1438 | rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); |
||
1439 | break; |
||
1440 | } |
||
1963 | serge | 1441 | break; |
5078 | serge | 1442 | case 8: |
1443 | switch (id) { |
||
1444 | case ASIC_INTERNAL_SS_ON_TMDS: |
||
1445 | percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); |
||
1446 | rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); |
||
1447 | break; |
||
1448 | case ASIC_INTERNAL_SS_ON_HDMI: |
||
1449 | percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); |
||
1450 | rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); |
||
1451 | break; |
||
1452 | case ASIC_INTERNAL_SS_ON_LVDS: |
||
1453 | percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); |
||
1454 | rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); |
||
1455 | break; |
||
1456 | } |
||
1457 | break; |
||
2997 | Serge | 1458 | default: |
1459 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); |
||
1460 | break; |
||
1321 | serge | 1461 | } |
1963 | serge | 1462 | if (percentage) |
1463 | ss->percentage = percentage; |
||
1464 | if (rate) |
||
1465 | ss->rate = rate; |
||
1321 | serge | 1466 | } |
1268 | serge | 1467 | } |
1468 | |||
1963 | serge | 1469 | union asic_ss_info { |
1470 | struct _ATOM_ASIC_INTERNAL_SS_INFO info; |
||
1471 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; |
||
1472 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; |
||
1473 | }; |
||
1474 | |||
5078 | serge | 1475 | union asic_ss_assignment { |
1476 | struct _ATOM_ASIC_SS_ASSIGNMENT v1; |
||
1477 | struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; |
||
1478 | struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; |
||
1479 | }; |
||
1480 | |||
1963 | serge | 1481 | bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
1482 | struct radeon_atom_ss *ss, |
||
1483 | int id, u32 clock) |
||
1430 | serge | 1484 | { |
1963 | serge | 1485 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
1486 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); |
||
1487 | uint16_t data_offset, size; |
||
1488 | union asic_ss_info *ss_info; |
||
5078 | serge | 1489 | union asic_ss_assignment *ss_assign; |
1963 | serge | 1490 | uint8_t frev, crev; |
1491 | int i, num_indices; |
||
1430 | serge | 1492 | |
5078 | serge | 1493 | if (id == ASIC_INTERNAL_MEMORY_SS) { |
1494 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) |
||
1495 | return false; |
||
1496 | } |
||
1497 | if (id == ASIC_INTERNAL_ENGINE_SS) { |
||
1498 | if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) |
||
1499 | return false; |
||
1500 | } |
||
1501 | |||
1963 | serge | 1502 | memset(ss, 0, sizeof(struct radeon_atom_ss)); |
1503 | if (atom_parse_data_header(mode_info->atom_context, index, &size, |
||
1504 | &frev, &crev, &data_offset)) { |
||
1505 | |||
1506 | ss_info = |
||
1507 | (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); |
||
1508 | |||
1509 | switch (frev) { |
||
1510 | case 1: |
||
1511 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
||
1512 | sizeof(ATOM_ASIC_SS_ASSIGNMENT); |
||
1513 | |||
5078 | serge | 1514 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); |
1963 | serge | 1515 | for (i = 0; i < num_indices; i++) { |
5078 | serge | 1516 | if ((ss_assign->v1.ucClockIndication == id) && |
1517 | (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { |
||
1963 | serge | 1518 | ss->percentage = |
5078 | serge | 1519 | le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); |
1520 | ss->type = ss_assign->v1.ucSpreadSpectrumMode; |
||
1521 | ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); |
||
1522 | ss->percentage_divider = 100; |
||
1963 | serge | 1523 | return true; |
1524 | } |
||
5078 | serge | 1525 | ss_assign = (union asic_ss_assignment *) |
1526 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); |
||
1963 | serge | 1527 | } |
1528 | break; |
||
1529 | case 2: |
||
1530 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
||
1531 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); |
||
5078 | serge | 1532 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); |
1963 | serge | 1533 | for (i = 0; i < num_indices; i++) { |
5078 | serge | 1534 | if ((ss_assign->v2.ucClockIndication == id) && |
1535 | (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { |
||
1963 | serge | 1536 | ss->percentage = |
5078 | serge | 1537 | le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); |
1538 | ss->type = ss_assign->v2.ucSpreadSpectrumMode; |
||
1539 | ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); |
||
1540 | ss->percentage_divider = 100; |
||
1541 | if ((crev == 2) && |
||
1542 | ((id == ASIC_INTERNAL_ENGINE_SS) || |
||
1543 | (id == ASIC_INTERNAL_MEMORY_SS))) |
||
1544 | ss->rate /= 100; |
||
1963 | serge | 1545 | return true; |
1546 | } |
||
5078 | serge | 1547 | ss_assign = (union asic_ss_assignment *) |
1548 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); |
||
1430 | serge | 1549 | } |
1963 | serge | 1550 | break; |
1551 | case 3: |
||
1552 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
||
1553 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); |
||
5078 | serge | 1554 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); |
1963 | serge | 1555 | for (i = 0; i < num_indices; i++) { |
5078 | serge | 1556 | if ((ss_assign->v3.ucClockIndication == id) && |
1557 | (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { |
||
1963 | serge | 1558 | ss->percentage = |
5078 | serge | 1559 | le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); |
1560 | ss->type = ss_assign->v3.ucSpreadSpectrumMode; |
||
1561 | ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); |
||
1562 | if (ss_assign->v3.ucSpreadSpectrumMode & |
||
1563 | SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) |
||
1564 | ss->percentage_divider = 1000; |
||
1565 | else |
||
1566 | ss->percentage_divider = 100; |
||
1567 | if ((id == ASIC_INTERNAL_ENGINE_SS) || |
||
1568 | (id == ASIC_INTERNAL_MEMORY_SS)) |
||
1569 | ss->rate /= 100; |
||
1963 | serge | 1570 | if (rdev->flags & RADEON_IS_IGP) |
1571 | radeon_atombios_get_igp_ss_overrides(rdev, ss, id); |
||
1572 | return true; |
||
1573 | } |
||
5078 | serge | 1574 | ss_assign = (union asic_ss_assignment *) |
1575 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); |
||
1963 | serge | 1576 | } |
1577 | break; |
||
1578 | default: |
||
1579 | DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); |
||
1580 | break; |
||
1581 | } |
||
1430 | serge | 1582 | |
1583 | } |
||
1963 | serge | 1584 | return false; |
1430 | serge | 1585 | } |
1586 | |||
1117 | serge | 1587 | union lvds_info { |
1588 | struct _ATOM_LVDS_INFO info; |
||
1589 | struct _ATOM_LVDS_INFO_V12 info_12; |
||
1590 | }; |
||
1591 | |||
1592 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct |
||
1593 | radeon_encoder |
||
1594 | *encoder) |
||
1595 | { |
||
1596 | struct drm_device *dev = encoder->base.dev; |
||
1597 | struct radeon_device *rdev = dev->dev_private; |
||
1598 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1599 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); |
||
1321 | serge | 1600 | uint16_t data_offset, misc; |
1117 | serge | 1601 | union lvds_info *lvds_info; |
1602 | uint8_t frev, crev; |
||
1603 | struct radeon_encoder_atom_dig *lvds = NULL; |
||
1963 | serge | 1604 | int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
1117 | serge | 1605 | |
1963 | serge | 1606 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1607 | &frev, &crev, &data_offset)) { |
||
1117 | serge | 1608 | lvds_info = |
1609 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); |
||
1610 | lvds = |
||
1611 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
||
1612 | |||
1613 | if (!lvds) |
||
1614 | return NULL; |
||
1615 | |||
1268 | serge | 1616 | lvds->native_mode.clock = |
1117 | serge | 1617 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
1268 | serge | 1618 | lvds->native_mode.hdisplay = |
1117 | serge | 1619 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
1268 | serge | 1620 | lvds->native_mode.vdisplay = |
1117 | serge | 1621 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
1268 | serge | 1622 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1117 | serge | 1623 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
1268 | serge | 1624 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
1117 | serge | 1625 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
1268 | serge | 1626 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
1117 | serge | 1627 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
1268 | serge | 1628 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
1117 | serge | 1629 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
1268 | serge | 1630 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
1963 | serge | 1631 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
1268 | serge | 1632 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
1117 | serge | 1633 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
1634 | lvds->panel_pwr_delay = |
||
1635 | le16_to_cpu(lvds_info->info.usOffDelayInMs); |
||
1963 | serge | 1636 | lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; |
1321 | serge | 1637 | |
1638 | misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); |
||
1639 | if (misc & ATOM_VSYNC_POLARITY) |
||
1640 | lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
||
1641 | if (misc & ATOM_HSYNC_POLARITY) |
||
1642 | lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
||
1643 | if (misc & ATOM_COMPOSITESYNC) |
||
1644 | lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; |
||
1645 | if (misc & ATOM_INTERLACE) |
||
1646 | lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
||
1647 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
||
1648 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; |
||
1649 | |||
1963 | serge | 1650 | lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); |
1651 | lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); |
||
1652 | |||
1268 | serge | 1653 | /* set crtc values */ |
1654 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
||
1117 | serge | 1655 | |
1963 | serge | 1656 | lvds->lcd_ss_id = lvds_info->info.ucSS_Id; |
1268 | serge | 1657 | |
1963 | serge | 1658 | encoder->native_mode = lvds->native_mode; |
1659 | |||
1660 | if (encoder_enum == 2) |
||
1661 | lvds->linkb = true; |
||
1662 | else |
||
1663 | lvds->linkb = false; |
||
1664 | |||
1665 | /* parse the lcd record table */ |
||
1666 | if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { |
||
1667 | ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; |
||
1668 | ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; |
||
1669 | bool bad_record = false; |
||
1670 | u8 *record; |
||
1671 | |||
1672 | if ((frev == 1) && (crev < 2)) |
||
1673 | /* absolute */ |
||
1674 | record = (u8 *)(mode_info->atom_context->bios + |
||
1675 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); |
||
1430 | serge | 1676 | else |
1963 | serge | 1677 | /* relative */ |
1678 | record = (u8 *)(mode_info->atom_context->bios + |
||
1679 | data_offset + |
||
1680 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); |
||
1681 | while (*record != ATOM_RECORD_END_TYPE) { |
||
1682 | switch (*record) { |
||
1683 | case LCD_MODE_PATCH_RECORD_MODE_TYPE: |
||
1684 | record += sizeof(ATOM_PATCH_RECORD_MODE); |
||
1685 | break; |
||
1686 | case LCD_RTS_RECORD_TYPE: |
||
1687 | record += sizeof(ATOM_LCD_RTS_RECORD); |
||
1688 | break; |
||
1689 | case LCD_CAP_RECORD_TYPE: |
||
1690 | record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); |
||
1691 | break; |
||
1692 | case LCD_FAKE_EDID_PATCH_RECORD_TYPE: |
||
1693 | fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; |
||
1694 | if (fake_edid_record->ucFakeEDIDLength) { |
||
1695 | struct edid *edid; |
||
1696 | int edid_size = |
||
1697 | max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); |
||
1698 | edid = kmalloc(edid_size, GFP_KERNEL); |
||
1699 | if (edid) { |
||
1700 | memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], |
||
1701 | fake_edid_record->ucFakeEDIDLength); |
||
1702 | |||
1703 | if (drm_edid_is_valid(edid)) { |
||
1704 | rdev->mode_info.bios_hardcoded_edid = edid; |
||
1705 | rdev->mode_info.bios_hardcoded_edid_size = edid_size; |
||
1706 | } else |
||
1707 | kfree(edid); |
||
1708 | } |
||
1709 | } |
||
5078 | serge | 1710 | record += fake_edid_record->ucFakeEDIDLength ? |
1711 | fake_edid_record->ucFakeEDIDLength + 2 : |
||
1712 | sizeof(ATOM_FAKE_EDID_PATCH_RECORD); |
||
1963 | serge | 1713 | break; |
1714 | case LCD_PANEL_RESOLUTION_RECORD_TYPE: |
||
1715 | panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; |
||
1716 | lvds->native_mode.width_mm = panel_res_record->usHSize; |
||
1717 | lvds->native_mode.height_mm = panel_res_record->usVSize; |
||
1718 | record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); |
||
1719 | break; |
||
1720 | default: |
||
1721 | DRM_ERROR("Bad LCD record %d\n", *record); |
||
1722 | bad_record = true; |
||
1723 | break; |
||
1724 | } |
||
1725 | if (bad_record) |
||
1726 | break; |
||
1727 | } |
||
1430 | serge | 1728 | } |
1117 | serge | 1729 | } |
1730 | return lvds; |
||
1731 | } |
||
1732 | |||
1733 | struct radeon_encoder_primary_dac * |
||
1734 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) |
||
1735 | { |
||
1736 | struct drm_device *dev = encoder->base.dev; |
||
1737 | struct radeon_device *rdev = dev->dev_private; |
||
1738 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1739 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
||
1740 | uint16_t data_offset; |
||
1741 | struct _COMPASSIONATE_DATA *dac_info; |
||
1742 | uint8_t frev, crev; |
||
1743 | uint8_t bg, dac; |
||
1744 | struct radeon_encoder_primary_dac *p_dac = NULL; |
||
1745 | |||
1963 | serge | 1746 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1747 | &frev, &crev, &data_offset)) { |
||
1748 | dac_info = (struct _COMPASSIONATE_DATA *) |
||
1749 | (mode_info->atom_context->bios + data_offset); |
||
1117 | serge | 1750 | |
1751 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
||
1752 | |||
1753 | if (!p_dac) |
||
1754 | return NULL; |
||
1755 | |||
1756 | bg = dac_info->ucDAC1_BG_Adjustment; |
||
1757 | dac = dac_info->ucDAC1_DAC_Adjustment; |
||
1758 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
||
1759 | |||
1760 | } |
||
1761 | return p_dac; |
||
1762 | } |
||
1763 | |||
1179 | serge | 1764 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
1268 | serge | 1765 | struct drm_display_mode *mode) |
1179 | serge | 1766 | { |
1767 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1768 | ATOM_ANALOG_TV_INFO *tv_info; |
||
1769 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; |
||
1770 | ATOM_DTD_FORMAT *dtd_timings; |
||
1771 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
||
1772 | u8 frev, crev; |
||
1268 | serge | 1773 | u16 data_offset, misc; |
1179 | serge | 1774 | |
1963 | serge | 1775 | if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, |
1776 | &frev, &crev, &data_offset)) |
||
1777 | return false; |
||
1179 | serge | 1778 | |
1779 | switch (crev) { |
||
1780 | case 1: |
||
1781 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); |
||
1963 | serge | 1782 | if (index >= MAX_SUPPORTED_TV_TIMING) |
1179 | serge | 1783 | return false; |
1784 | |||
1268 | serge | 1785 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
1786 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); |
||
1787 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); |
||
1788 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + |
||
1789 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); |
||
1179 | serge | 1790 | |
1268 | serge | 1791 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); |
1792 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); |
||
1793 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); |
||
1794 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + |
||
1795 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); |
||
1179 | serge | 1796 | |
1268 | serge | 1797 | mode->flags = 0; |
1798 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); |
||
1799 | if (misc & ATOM_VSYNC_POLARITY) |
||
1800 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
||
1801 | if (misc & ATOM_HSYNC_POLARITY) |
||
1802 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
||
1803 | if (misc & ATOM_COMPOSITESYNC) |
||
1804 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
||
1805 | if (misc & ATOM_INTERLACE) |
||
1806 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
||
1807 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
||
1808 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
||
1179 | serge | 1809 | |
5078 | serge | 1810 | mode->crtc_clock = mode->clock = |
1811 | le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; |
||
1179 | serge | 1812 | |
1813 | if (index == 1) { |
||
1814 | /* PAL timings appear to have wrong values for totals */ |
||
1268 | serge | 1815 | mode->crtc_htotal -= 1; |
1816 | mode->crtc_vtotal -= 1; |
||
1179 | serge | 1817 | } |
1818 | break; |
||
1819 | case 2: |
||
1820 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); |
||
1963 | serge | 1821 | if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) |
1179 | serge | 1822 | return false; |
1823 | |||
1824 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; |
||
1268 | serge | 1825 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
1826 | le16_to_cpu(dtd_timings->usHBlanking_Time); |
||
1827 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); |
||
1828 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + |
||
1829 | le16_to_cpu(dtd_timings->usHSyncOffset); |
||
1830 | mode->crtc_hsync_end = mode->crtc_hsync_start + |
||
1831 | le16_to_cpu(dtd_timings->usHSyncWidth); |
||
1179 | serge | 1832 | |
1268 | serge | 1833 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + |
1834 | le16_to_cpu(dtd_timings->usVBlanking_Time); |
||
1835 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); |
||
1836 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + |
||
1837 | le16_to_cpu(dtd_timings->usVSyncOffset); |
||
1838 | mode->crtc_vsync_end = mode->crtc_vsync_start + |
||
1839 | le16_to_cpu(dtd_timings->usVSyncWidth); |
||
1840 | |||
1841 | mode->flags = 0; |
||
1842 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); |
||
1843 | if (misc & ATOM_VSYNC_POLARITY) |
||
1844 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
||
1845 | if (misc & ATOM_HSYNC_POLARITY) |
||
1846 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
||
1847 | if (misc & ATOM_COMPOSITESYNC) |
||
1848 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
||
1849 | if (misc & ATOM_INTERLACE) |
||
1850 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
||
1851 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
||
1852 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
||
1853 | |||
5078 | serge | 1854 | mode->crtc_clock = mode->clock = |
1855 | le16_to_cpu(dtd_timings->usPixClk) * 10; |
||
1179 | serge | 1856 | break; |
1857 | } |
||
1858 | return true; |
||
1859 | } |
||
1860 | |||
1404 | serge | 1861 | enum radeon_tv_std |
1862 | radeon_atombios_get_tv_info(struct radeon_device *rdev) |
||
1863 | { |
||
1864 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1865 | int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
||
1866 | uint16_t data_offset; |
||
1867 | uint8_t frev, crev; |
||
1868 | struct _ATOM_ANALOG_TV_INFO *tv_info; |
||
1869 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
||
1870 | |||
1963 | serge | 1871 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1872 | &frev, &crev, &data_offset)) { |
||
1404 | serge | 1873 | |
1963 | serge | 1874 | tv_info = (struct _ATOM_ANALOG_TV_INFO *) |
1875 | (mode_info->atom_context->bios + data_offset); |
||
1404 | serge | 1876 | |
1877 | switch (tv_info->ucTV_BootUpDefaultStandard) { |
||
1878 | case ATOM_TV_NTSC: |
||
1879 | tv_std = TV_STD_NTSC; |
||
1963 | serge | 1880 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
1404 | serge | 1881 | break; |
1882 | case ATOM_TV_NTSCJ: |
||
1883 | tv_std = TV_STD_NTSC_J; |
||
1963 | serge | 1884 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
1404 | serge | 1885 | break; |
1886 | case ATOM_TV_PAL: |
||
1887 | tv_std = TV_STD_PAL; |
||
1963 | serge | 1888 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
1404 | serge | 1889 | break; |
1890 | case ATOM_TV_PALM: |
||
1891 | tv_std = TV_STD_PAL_M; |
||
1963 | serge | 1892 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
1404 | serge | 1893 | break; |
1894 | case ATOM_TV_PALN: |
||
1895 | tv_std = TV_STD_PAL_N; |
||
1963 | serge | 1896 | DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); |
1404 | serge | 1897 | break; |
1898 | case ATOM_TV_PALCN: |
||
1899 | tv_std = TV_STD_PAL_CN; |
||
1963 | serge | 1900 | DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); |
1404 | serge | 1901 | break; |
1902 | case ATOM_TV_PAL60: |
||
1903 | tv_std = TV_STD_PAL_60; |
||
1963 | serge | 1904 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
1404 | serge | 1905 | break; |
1906 | case ATOM_TV_SECAM: |
||
1907 | tv_std = TV_STD_SECAM; |
||
1963 | serge | 1908 | DRM_DEBUG_KMS("Default TV standard: SECAM\n"); |
1404 | serge | 1909 | break; |
1910 | default: |
||
1911 | tv_std = TV_STD_NTSC; |
||
1963 | serge | 1912 | DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); |
1404 | serge | 1913 | break; |
1914 | } |
||
1963 | serge | 1915 | } |
1404 | serge | 1916 | return tv_std; |
1917 | } |
||
1918 | |||
1117 | serge | 1919 | struct radeon_encoder_tv_dac * |
1920 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
||
1921 | { |
||
1922 | struct drm_device *dev = encoder->base.dev; |
||
1923 | struct radeon_device *rdev = dev->dev_private; |
||
1924 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
1925 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
||
1926 | uint16_t data_offset; |
||
1927 | struct _COMPASSIONATE_DATA *dac_info; |
||
1928 | uint8_t frev, crev; |
||
1929 | uint8_t bg, dac; |
||
1930 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
||
1931 | |||
1963 | serge | 1932 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1933 | &frev, &crev, &data_offset)) { |
||
1117 | serge | 1934 | |
1963 | serge | 1935 | dac_info = (struct _COMPASSIONATE_DATA *) |
1936 | (mode_info->atom_context->bios + data_offset); |
||
1117 | serge | 1937 | |
1938 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
||
1939 | |||
1940 | if (!tv_dac) |
||
1941 | return NULL; |
||
1942 | |||
1943 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; |
||
1944 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; |
||
1945 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
||
1946 | |||
1947 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; |
||
1948 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; |
||
1949 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
||
1950 | |||
1951 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; |
||
1952 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; |
||
1953 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
||
1954 | |||
1404 | serge | 1955 | tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); |
1117 | serge | 1956 | } |
1957 | return tv_dac; |
||
1958 | } |
||
1959 | |||
1963 | serge | 1960 | static const char *thermal_controller_names[] = { |
1961 | "NONE", |
||
1962 | "lm63", |
||
1963 | "adm1032", |
||
1964 | "adm1030", |
||
1965 | "max6649", |
||
5078 | serge | 1966 | "lm63", /* lm64 */ |
1963 | serge | 1967 | "f75375", |
1968 | "asc7xxx", |
||
1969 | }; |
||
1970 | |||
1971 | static const char *pp_lib_thermal_controller_names[] = { |
||
1972 | "NONE", |
||
1973 | "lm63", |
||
1974 | "adm1032", |
||
1975 | "adm1030", |
||
1976 | "max6649", |
||
5078 | serge | 1977 | "lm63", /* lm64 */ |
1963 | serge | 1978 | "f75375", |
1979 | "RV6xx", |
||
1980 | "RV770", |
||
1981 | "adt7473", |
||
1982 | "NONE", |
||
1983 | "External GPIO", |
||
1984 | "Evergreen", |
||
1985 | "emc2103", |
||
1986 | "Sumo", |
||
1987 | "Northern Islands", |
||
2997 | Serge | 1988 | "Southern Islands", |
1989 | "lm96163", |
||
5078 | serge | 1990 | "Sea Islands", |
1963 | serge | 1991 | }; |
1992 | |||
1430 | serge | 1993 | union power_info { |
1994 | struct _ATOM_POWERPLAY_INFO info; |
||
1995 | struct _ATOM_POWERPLAY_INFO_V2 info_2; |
||
1996 | struct _ATOM_POWERPLAY_INFO_V3 info_3; |
||
1963 | serge | 1997 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
1998 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
||
1999 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; |
||
1430 | serge | 2000 | }; |
2001 | |||
1963 | serge | 2002 | union pplib_clock_info { |
2003 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
||
2004 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; |
||
2005 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; |
||
2006 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
||
2997 | Serge | 2007 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; |
5078 | serge | 2008 | struct _ATOM_PPLIB_CI_CLOCK_INFO ci; |
1963 | serge | 2009 | }; |
2010 | |||
2011 | union pplib_power_state { |
||
2012 | struct _ATOM_PPLIB_STATE v1; |
||
2013 | struct _ATOM_PPLIB_STATE_V2 v2; |
||
2014 | }; |
||
2015 | |||
2016 | static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, |
||
2017 | int state_index, |
||
2018 | u32 misc, u32 misc2) |
||
1117 | serge | 2019 | { |
1963 | serge | 2020 | rdev->pm.power_state[state_index].misc = misc; |
2021 | rdev->pm.power_state[state_index].misc2 = misc2; |
||
2022 | /* order matters! */ |
||
2023 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) |
||
2024 | rdev->pm.power_state[state_index].type = |
||
2025 | POWER_STATE_TYPE_POWERSAVE; |
||
2026 | if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) |
||
2027 | rdev->pm.power_state[state_index].type = |
||
2028 | POWER_STATE_TYPE_BATTERY; |
||
2029 | if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) |
||
2030 | rdev->pm.power_state[state_index].type = |
||
2031 | POWER_STATE_TYPE_BATTERY; |
||
2032 | if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) |
||
2033 | rdev->pm.power_state[state_index].type = |
||
2034 | POWER_STATE_TYPE_BALANCED; |
||
2035 | if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { |
||
2036 | rdev->pm.power_state[state_index].type = |
||
2037 | POWER_STATE_TYPE_PERFORMANCE; |
||
2038 | rdev->pm.power_state[state_index].flags &= |
||
2039 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
||
2040 | } |
||
2041 | if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) |
||
2042 | rdev->pm.power_state[state_index].type = |
||
2043 | POWER_STATE_TYPE_BALANCED; |
||
2044 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { |
||
2045 | rdev->pm.power_state[state_index].type = |
||
2046 | POWER_STATE_TYPE_DEFAULT; |
||
2047 | rdev->pm.default_power_state_index = state_index; |
||
2048 | rdev->pm.power_state[state_index].default_clock_mode = |
||
2049 | &rdev->pm.power_state[state_index].clock_info[0]; |
||
2050 | } else if (state_index == 0) { |
||
2051 | rdev->pm.power_state[state_index].clock_info[0].flags |= |
||
2052 | RADEON_PM_MODE_NO_DISPLAY; |
||
2053 | } |
||
2054 | } |
||
2055 | |||
2056 | static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) |
||
2057 | { |
||
1430 | serge | 2058 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
1963 | serge | 2059 | u32 misc, misc2 = 0; |
2060 | int num_modes = 0, i; |
||
2061 | int state_index = 0; |
||
2062 | struct radeon_i2c_bus_rec i2c_bus; |
||
2063 | union power_info *power_info; |
||
1430 | serge | 2064 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
2065 | u16 data_offset; |
||
2066 | u8 frev, crev; |
||
1117 | serge | 2067 | |
1963 | serge | 2068 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
2069 | &frev, &crev, &data_offset)) |
||
2070 | return state_index; |
||
1430 | serge | 2071 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
2072 | |||
1963 | serge | 2073 | /* add the i2c bus for thermal/fan chip */ |
2997 | Serge | 2074 | if ((power_info->info.ucOverdriveThermalController > 0) && |
2075 | (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { |
||
1963 | serge | 2076 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
2077 | thermal_controller_names[power_info->info.ucOverdriveThermalController], |
||
2078 | power_info->info.ucOverdriveControllerAddress >> 1); |
||
2079 | i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); |
||
2080 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
||
2081 | if (rdev->pm.i2c_bus) { |
||
2082 | struct i2c_board_info info = { }; |
||
2083 | const char *name = thermal_controller_names[power_info->info. |
||
2084 | ucOverdriveThermalController]; |
||
2085 | info.addr = power_info->info.ucOverdriveControllerAddress >> 1; |
||
2086 | strlcpy(info.type, name, sizeof(info.type)); |
||
2087 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
||
2088 | } |
||
2089 | } |
||
1430 | serge | 2090 | num_modes = power_info->info.ucNumOfPowerModeEntries; |
2091 | if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) |
||
2092 | num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; |
||
3764 | Serge | 2093 | if (num_modes == 0) |
2094 | return state_index; |
||
1963 | serge | 2095 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); |
2096 | if (!rdev->pm.power_state) |
||
2097 | return state_index; |
||
2098 | /* last mode is usually default, array is low to high */ |
||
1430 | serge | 2099 | for (i = 0; i < num_modes; i++) { |
2997 | Serge | 2100 | rdev->pm.power_state[state_index].clock_info = |
2101 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
||
2102 | if (!rdev->pm.power_state[state_index].clock_info) |
||
2103 | return state_index; |
||
2104 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
||
1430 | serge | 2105 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2106 | switch (frev) { |
||
2107 | case 1: |
||
2108 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
||
2109 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); |
||
2110 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
||
2111 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); |
||
2112 | /* skip invalid modes */ |
||
2113 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
||
2114 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
||
2115 | continue; |
||
1963 | serge | 2116 | rdev->pm.power_state[state_index].pcie_lanes = |
1430 | serge | 2117 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; |
2118 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); |
||
1963 | serge | 2119 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
2120 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { |
||
1430 | serge | 2121 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
2122 | VOLTAGE_GPIO; |
||
2123 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = |
||
2124 | radeon_lookup_gpio(rdev, |
||
2125 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); |
||
2126 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) |
||
2127 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
||
2128 | true; |
||
2129 | else |
||
2130 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
||
2131 | false; |
||
2132 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { |
||
2133 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
||
2134 | VOLTAGE_VDDC; |
||
2135 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = |
||
2136 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; |
||
2137 | } |
||
1963 | serge | 2138 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2139 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); |
||
1430 | serge | 2140 | state_index++; |
2141 | break; |
||
2142 | case 2: |
||
2143 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
||
2144 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); |
||
2145 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
||
2146 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); |
||
2147 | /* skip invalid modes */ |
||
2148 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
||
2149 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
||
2150 | continue; |
||
1963 | serge | 2151 | rdev->pm.power_state[state_index].pcie_lanes = |
1430 | serge | 2152 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; |
2153 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); |
||
2154 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); |
||
1963 | serge | 2155 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
2156 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { |
||
1430 | serge | 2157 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
2158 | VOLTAGE_GPIO; |
||
2159 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = |
||
2160 | radeon_lookup_gpio(rdev, |
||
2161 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); |
||
2162 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) |
||
2163 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
||
2164 | true; |
||
2165 | else |
||
2166 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
||
2167 | false; |
||
2168 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { |
||
2169 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
||
2170 | VOLTAGE_VDDC; |
||
2171 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = |
||
2172 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; |
||
2173 | } |
||
1963 | serge | 2174 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2175 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); |
||
1430 | serge | 2176 | state_index++; |
2177 | break; |
||
2178 | case 3: |
||
2179 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
||
2180 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); |
||
2181 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
||
2182 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); |
||
2183 | /* skip invalid modes */ |
||
2184 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
||
2185 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
||
2186 | continue; |
||
1963 | serge | 2187 | rdev->pm.power_state[state_index].pcie_lanes = |
1430 | serge | 2188 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; |
2189 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); |
||
2190 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); |
||
1963 | serge | 2191 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
2192 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { |
||
1430 | serge | 2193 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
2194 | VOLTAGE_GPIO; |
||
2195 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = |
||
2196 | radeon_lookup_gpio(rdev, |
||
2197 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); |
||
2198 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) |
||
2199 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
||
2200 | true; |
||
2201 | else |
||
2202 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
||
2203 | false; |
||
2204 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { |
||
2205 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
||
2206 | VOLTAGE_VDDC; |
||
2207 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = |
||
2208 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; |
||
2209 | if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { |
||
2210 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = |
||
2211 | true; |
||
2212 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = |
||
2213 | power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; |
||
2214 | } |
||
2215 | } |
||
1963 | serge | 2216 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2217 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); |
||
1430 | serge | 2218 | state_index++; |
2219 | break; |
||
2220 | } |
||
2221 | } |
||
1963 | serge | 2222 | /* last mode is usually default */ |
2223 | if (rdev->pm.default_power_state_index == -1) { |
||
2224 | rdev->pm.power_state[state_index - 1].type = |
||
2225 | POWER_STATE_TYPE_DEFAULT; |
||
2226 | rdev->pm.default_power_state_index = state_index - 1; |
||
2227 | rdev->pm.power_state[state_index - 1].default_clock_mode = |
||
2228 | &rdev->pm.power_state[state_index - 1].clock_info[0]; |
||
2229 | rdev->pm.power_state[state_index].flags &= |
||
2230 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
||
2231 | rdev->pm.power_state[state_index].misc = 0; |
||
2232 | rdev->pm.power_state[state_index].misc2 = 0; |
||
2233 | } |
||
2234 | return state_index; |
||
2235 | } |
||
2236 | |||
2237 | static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, |
||
2238 | ATOM_PPLIB_THERMALCONTROLLER *controller) |
||
2239 | { |
||
2240 | struct radeon_i2c_bus_rec i2c_bus; |
||
2241 | |||
2242 | /* add the i2c bus for thermal/fan chip */ |
||
2243 | if (controller->ucType > 0) { |
||
2244 | if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { |
||
2245 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2246 | (controller->ucFanParameters & |
||
2247 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2248 | rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; |
||
2249 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { |
||
2250 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2251 | (controller->ucFanParameters & |
||
2252 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2253 | rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; |
||
2254 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { |
||
2255 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2256 | (controller->ucFanParameters & |
||
2257 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2258 | rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; |
||
2259 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { |
||
2260 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2261 | (controller->ucFanParameters & |
||
2262 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2263 | rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; |
||
2264 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { |
||
2265 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2266 | (controller->ucFanParameters & |
||
2267 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2268 | rdev->pm.int_thermal_type = THERMAL_TYPE_NI; |
||
2997 | Serge | 2269 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { |
2270 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2271 | (controller->ucFanParameters & |
||
2272 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2273 | rdev->pm.int_thermal_type = THERMAL_TYPE_SI; |
||
5078 | serge | 2274 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { |
2275 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2276 | (controller->ucFanParameters & |
||
2277 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2278 | rdev->pm.int_thermal_type = THERMAL_TYPE_CI; |
||
2279 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { |
||
2280 | DRM_INFO("Internal thermal controller %s fan control\n", |
||
2281 | (controller->ucFanParameters & |
||
2282 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2283 | rdev->pm.int_thermal_type = THERMAL_TYPE_KV; |
||
1963 | serge | 2284 | } else if ((controller->ucType == |
2285 | ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || |
||
2286 | (controller->ucType == |
||
2287 | ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || |
||
2288 | (controller->ucType == |
||
2289 | ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { |
||
2290 | DRM_INFO("Special thermal controller config\n"); |
||
2997 | Serge | 2291 | } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { |
1963 | serge | 2292 | DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", |
2293 | pp_lib_thermal_controller_names[controller->ucType], |
||
2294 | controller->ucI2cAddress >> 1, |
||
2295 | (controller->ucFanParameters & |
||
2296 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
2297 | i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); |
||
2298 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
||
2299 | if (rdev->pm.i2c_bus) { |
||
2300 | struct i2c_board_info info = { }; |
||
2301 | const char *name = pp_lib_thermal_controller_names[controller->ucType]; |
||
2302 | info.addr = controller->ucI2cAddress >> 1; |
||
2303 | strlcpy(info.type, name, sizeof(info.type)); |
||
2304 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
||
1430 | serge | 2305 | } |
2997 | Serge | 2306 | } else { |
2307 | DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", |
||
2308 | controller->ucType, |
||
2309 | controller->ucI2cAddress >> 1, |
||
2310 | (controller->ucFanParameters & |
||
2311 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
||
1430 | serge | 2312 | } |
1963 | serge | 2313 | } |
2314 | } |
||
2315 | |||
5078 | serge | 2316 | void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
2317 | u16 *vddc, u16 *vddci, u16 *mvdd) |
||
1963 | serge | 2318 | { |
2319 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
2320 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
||
2321 | u8 frev, crev; |
||
2322 | u16 data_offset; |
||
2323 | union firmware_info *firmware_info; |
||
2324 | |||
2325 | *vddc = 0; |
||
2326 | *vddci = 0; |
||
5078 | serge | 2327 | *mvdd = 0; |
1963 | serge | 2328 | |
2329 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
||
2330 | &frev, &crev, &data_offset)) { |
||
2331 | firmware_info = |
||
2332 | (union firmware_info *)(mode_info->atom_context->bios + |
||
2333 | data_offset); |
||
2334 | *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); |
||
5078 | serge | 2335 | if ((frev == 2) && (crev >= 2)) { |
1963 | serge | 2336 | *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); |
5078 | serge | 2337 | *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); |
2338 | } |
||
1963 | serge | 2339 | } |
2340 | } |
||
2341 | |||
2342 | static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, |
||
2343 | int state_index, int mode_index, |
||
2344 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) |
||
2345 | { |
||
2346 | int j; |
||
2347 | u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
||
2348 | u32 misc2 = le16_to_cpu(non_clock_info->usClassification); |
||
5078 | serge | 2349 | u16 vddc, vddci, mvdd; |
1963 | serge | 2350 | |
5078 | serge | 2351 | radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); |
1963 | serge | 2352 | |
2353 | rdev->pm.power_state[state_index].misc = misc; |
||
2354 | rdev->pm.power_state[state_index].misc2 = misc2; |
||
2355 | rdev->pm.power_state[state_index].pcie_lanes = |
||
1430 | serge | 2356 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> |
2357 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
||
2358 | switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
||
2359 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: |
||
2360 | rdev->pm.power_state[state_index].type = |
||
2361 | POWER_STATE_TYPE_BATTERY; |
||
2362 | break; |
||
2363 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: |
||
2364 | rdev->pm.power_state[state_index].type = |
||
2365 | POWER_STATE_TYPE_BALANCED; |
||
2366 | break; |
||
2367 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: |
||
2368 | rdev->pm.power_state[state_index].type = |
||
2369 | POWER_STATE_TYPE_PERFORMANCE; |
||
2370 | break; |
||
1963 | serge | 2371 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: |
2372 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) |
||
2373 | rdev->pm.power_state[state_index].type = |
||
2374 | POWER_STATE_TYPE_PERFORMANCE; |
||
2375 | break; |
||
1430 | serge | 2376 | } |
1963 | serge | 2377 | rdev->pm.power_state[state_index].flags = 0; |
2378 | if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) |
||
2379 | rdev->pm.power_state[state_index].flags |= |
||
2380 | RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
||
1430 | serge | 2381 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
2382 | rdev->pm.power_state[state_index].type = |
||
2383 | POWER_STATE_TYPE_DEFAULT; |
||
1963 | serge | 2384 | rdev->pm.default_power_state_index = state_index; |
1430 | serge | 2385 | rdev->pm.power_state[state_index].default_clock_mode = |
2386 | &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; |
||
3764 | Serge | 2387 | if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { |
1963 | serge | 2388 | /* NI chips post without MC ucode, so default clocks are strobe mode only */ |
2389 | rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; |
||
2390 | rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; |
||
2391 | rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; |
||
2392 | rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; |
||
2393 | } else { |
||
5078 | serge | 2394 | u16 max_vddci = 0; |
2395 | |||
2396 | if (ASIC_IS_DCE4(rdev)) |
||
2397 | radeon_atom_get_max_voltage(rdev, |
||
2398 | SET_VOLTAGE_TYPE_ASIC_VDDCI, |
||
2399 | &max_vddci); |
||
2400 | /* patch the table values with the default sclk/mclk from firmware info */ |
||
1963 | serge | 2401 | for (j = 0; j < mode_index; j++) { |
2402 | rdev->pm.power_state[state_index].clock_info[j].mclk = |
||
2403 | rdev->clock.default_mclk; |
||
2404 | rdev->pm.power_state[state_index].clock_info[j].sclk = |
||
2405 | rdev->clock.default_sclk; |
||
2406 | if (vddc) |
||
2407 | rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = |
||
2408 | vddc; |
||
5078 | serge | 2409 | if (max_vddci) |
2410 | rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = |
||
2411 | max_vddci; |
||
1963 | serge | 2412 | } |
1430 | serge | 2413 | } |
1963 | serge | 2414 | } |
2415 | } |
||
2416 | |||
2417 | static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, |
||
2418 | int state_index, int mode_index, |
||
2419 | union pplib_clock_info *clock_info) |
||
2420 | { |
||
2421 | u32 sclk, mclk; |
||
2997 | Serge | 2422 | u16 vddc; |
1963 | serge | 2423 | |
2424 | if (rdev->flags & RADEON_IS_IGP) { |
||
2425 | if (rdev->family >= CHIP_PALM) { |
||
2426 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); |
||
2427 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; |
||
2428 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
||
2429 | } else { |
||
2430 | sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); |
||
2431 | sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; |
||
2432 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
||
2433 | } |
||
5078 | serge | 2434 | } else if (rdev->family >= CHIP_BONAIRE) { |
2435 | sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); |
||
2436 | sclk |= clock_info->ci.ucEngineClockHigh << 16; |
||
2437 | mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); |
||
2438 | mclk |= clock_info->ci.ucMemoryClockHigh << 16; |
||
2439 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
||
2440 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
||
2441 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
||
2442 | VOLTAGE_NONE; |
||
3764 | Serge | 2443 | } else if (rdev->family >= CHIP_TAHITI) { |
2997 | Serge | 2444 | sclk = le16_to_cpu(clock_info->si.usEngineClockLow); |
2445 | sclk |= clock_info->si.ucEngineClockHigh << 16; |
||
2446 | mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); |
||
2447 | mclk |= clock_info->si.ucMemoryClockHigh << 16; |
||
2448 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
||
2449 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
||
2450 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
||
2451 | VOLTAGE_SW; |
||
2452 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
||
2453 | le16_to_cpu(clock_info->si.usVDDC); |
||
2454 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = |
||
2455 | le16_to_cpu(clock_info->si.usVDDCI); |
||
3764 | Serge | 2456 | } else if (rdev->family >= CHIP_CEDAR) { |
1963 | serge | 2457 | sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); |
2458 | sclk |= clock_info->evergreen.ucEngineClockHigh << 16; |
||
2459 | mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); |
||
2460 | mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; |
||
2461 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
||
2462 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
||
2463 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
||
2464 | VOLTAGE_SW; |
||
2465 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
||
2466 | le16_to_cpu(clock_info->evergreen.usVDDC); |
||
2467 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = |
||
2468 | le16_to_cpu(clock_info->evergreen.usVDDCI); |
||
2469 | } else { |
||
2470 | sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); |
||
2471 | sclk |= clock_info->r600.ucEngineClockHigh << 16; |
||
2472 | mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); |
||
2473 | mclk |= clock_info->r600.ucMemoryClockHigh << 16; |
||
2474 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
||
2475 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
||
2476 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
||
2477 | VOLTAGE_SW; |
||
2478 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
||
2479 | le16_to_cpu(clock_info->r600.usVDDC); |
||
2480 | } |
||
2481 | |||
1986 | serge | 2482 | /* patch up vddc if necessary */ |
2997 | Serge | 2483 | switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { |
2484 | case ATOM_VIRTUAL_VOLTAGE_ID0: |
||
2485 | case ATOM_VIRTUAL_VOLTAGE_ID1: |
||
2486 | case ATOM_VIRTUAL_VOLTAGE_ID2: |
||
2487 | case ATOM_VIRTUAL_VOLTAGE_ID3: |
||
5078 | serge | 2488 | case ATOM_VIRTUAL_VOLTAGE_ID4: |
2489 | case ATOM_VIRTUAL_VOLTAGE_ID5: |
||
2490 | case ATOM_VIRTUAL_VOLTAGE_ID6: |
||
2491 | case ATOM_VIRTUAL_VOLTAGE_ID7: |
||
2997 | Serge | 2492 | if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, |
2493 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, |
||
2494 | &vddc) == 0) |
||
1986 | serge | 2495 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; |
2997 | Serge | 2496 | break; |
2497 | default: |
||
2498 | break; |
||
1986 | serge | 2499 | } |
2500 | |||
1963 | serge | 2501 | if (rdev->flags & RADEON_IS_IGP) { |
2502 | /* skip invalid modes */ |
||
2503 | if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) |
||
2504 | return false; |
||
2505 | } else { |
||
2506 | /* skip invalid modes */ |
||
2507 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || |
||
2508 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) |
||
2509 | return false; |
||
2510 | } |
||
2511 | return true; |
||
2512 | } |
||
2513 | |||
2514 | static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) |
||
2515 | { |
||
2516 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
2517 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
||
2518 | union pplib_power_state *power_state; |
||
2519 | int i, j; |
||
2520 | int state_index = 0, mode_index = 0; |
||
2521 | union pplib_clock_info *clock_info; |
||
2522 | bool valid; |
||
2523 | union power_info *power_info; |
||
2524 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
||
2525 | u16 data_offset; |
||
2526 | u8 frev, crev; |
||
2527 | |||
2528 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
||
2529 | &frev, &crev, &data_offset)) |
||
2530 | return state_index; |
||
2531 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
||
2532 | |||
2533 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); |
||
3764 | Serge | 2534 | if (power_info->pplib.ucNumStates == 0) |
2535 | return state_index; |
||
1963 | serge | 2536 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * |
2537 | power_info->pplib.ucNumStates, GFP_KERNEL); |
||
2538 | if (!rdev->pm.power_state) |
||
2539 | return state_index; |
||
2540 | /* first mode is usually default, followed by low to high */ |
||
2541 | for (i = 0; i < power_info->pplib.ucNumStates; i++) { |
||
2542 | mode_index = 0; |
||
2543 | power_state = (union pplib_power_state *) |
||
2544 | (mode_info->atom_context->bios + data_offset + |
||
2545 | le16_to_cpu(power_info->pplib.usStateArrayOffset) + |
||
2546 | i * power_info->pplib.ucStateEntrySize); |
||
2547 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
||
2548 | (mode_info->atom_context->bios + data_offset + |
||
2549 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + |
||
2550 | (power_state->v1.ucNonClockStateIndex * |
||
2551 | power_info->pplib.ucNonClockSize)); |
||
2997 | Serge | 2552 | rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * |
2553 | ((power_info->pplib.ucStateEntrySize - 1) ? |
||
2554 | (power_info->pplib.ucStateEntrySize - 1) : 1), |
||
2555 | GFP_KERNEL); |
||
2556 | if (!rdev->pm.power_state[i].clock_info) |
||
2557 | return state_index; |
||
2558 | if (power_info->pplib.ucStateEntrySize - 1) { |
||
1963 | serge | 2559 | for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { |
2560 | clock_info = (union pplib_clock_info *) |
||
2561 | (mode_info->atom_context->bios + data_offset + |
||
2562 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + |
||
2563 | (power_state->v1.ucClockStateIndices[j] * |
||
2564 | power_info->pplib.ucClockInfoSize)); |
||
2565 | valid = radeon_atombios_parse_pplib_clock_info(rdev, |
||
2566 | state_index, mode_index, |
||
2567 | clock_info); |
||
2568 | if (valid) |
||
2569 | mode_index++; |
||
2570 | } |
||
2997 | Serge | 2571 | } else { |
2572 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
||
2573 | rdev->clock.default_mclk; |
||
2574 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
||
2575 | rdev->clock.default_sclk; |
||
2576 | mode_index++; |
||
2577 | } |
||
1963 | serge | 2578 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; |
2579 | if (mode_index) { |
||
2580 | radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, |
||
2581 | non_clock_info); |
||
2582 | state_index++; |
||
2583 | } |
||
2584 | } |
||
2585 | /* if multiple clock modes, mark the lowest as no display */ |
||
2586 | for (i = 0; i < state_index; i++) { |
||
2587 | if (rdev->pm.power_state[i].num_clock_modes > 1) |
||
2588 | rdev->pm.power_state[i].clock_info[0].flags |= |
||
2589 | RADEON_PM_MODE_NO_DISPLAY; |
||
2590 | } |
||
2591 | /* first mode is usually default */ |
||
2592 | if (rdev->pm.default_power_state_index == -1) { |
||
2593 | rdev->pm.power_state[0].type = |
||
2594 | POWER_STATE_TYPE_DEFAULT; |
||
2595 | rdev->pm.default_power_state_index = 0; |
||
2596 | rdev->pm.power_state[0].default_clock_mode = |
||
2597 | &rdev->pm.power_state[0].clock_info[0]; |
||
2598 | } |
||
2599 | return state_index; |
||
2600 | } |
||
2601 | |||
2602 | static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) |
||
2603 | { |
||
2604 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
2605 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
||
2606 | union pplib_power_state *power_state; |
||
2607 | int i, j, non_clock_array_index, clock_array_index; |
||
2608 | int state_index = 0, mode_index = 0; |
||
2609 | union pplib_clock_info *clock_info; |
||
2997 | Serge | 2610 | struct _StateArray *state_array; |
2611 | struct _ClockInfoArray *clock_info_array; |
||
2612 | struct _NonClockInfoArray *non_clock_info_array; |
||
1963 | serge | 2613 | bool valid; |
2614 | union power_info *power_info; |
||
2615 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
||
2616 | u16 data_offset; |
||
2617 | u8 frev, crev; |
||
3764 | Serge | 2618 | u8 *power_state_offset; |
1963 | serge | 2619 | |
2620 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
||
2621 | &frev, &crev, &data_offset)) |
||
2622 | return state_index; |
||
2623 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
||
2624 | |||
2625 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); |
||
2997 | Serge | 2626 | state_array = (struct _StateArray *) |
1963 | serge | 2627 | (mode_info->atom_context->bios + data_offset + |
2628 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
||
2997 | Serge | 2629 | clock_info_array = (struct _ClockInfoArray *) |
1963 | serge | 2630 | (mode_info->atom_context->bios + data_offset + |
2631 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
||
2997 | Serge | 2632 | non_clock_info_array = (struct _NonClockInfoArray *) |
1963 | serge | 2633 | (mode_info->atom_context->bios + data_offset + |
2634 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
||
3764 | Serge | 2635 | if (state_array->ucNumEntries == 0) |
2636 | return state_index; |
||
1963 | serge | 2637 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * |
2638 | state_array->ucNumEntries, GFP_KERNEL); |
||
2639 | if (!rdev->pm.power_state) |
||
2640 | return state_index; |
||
3764 | Serge | 2641 | power_state_offset = (u8 *)state_array->states; |
1963 | serge | 2642 | for (i = 0; i < state_array->ucNumEntries; i++) { |
2643 | mode_index = 0; |
||
3764 | Serge | 2644 | power_state = (union pplib_power_state *)power_state_offset; |
2645 | non_clock_array_index = power_state->v2.nonClockInfoIndex; |
||
1963 | serge | 2646 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
2647 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; |
||
2997 | Serge | 2648 | rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * |
2649 | (power_state->v2.ucNumDPMLevels ? |
||
2650 | power_state->v2.ucNumDPMLevels : 1), |
||
2651 | GFP_KERNEL); |
||
2652 | if (!rdev->pm.power_state[i].clock_info) |
||
2653 | return state_index; |
||
2654 | if (power_state->v2.ucNumDPMLevels) { |
||
1963 | serge | 2655 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
2656 | clock_array_index = power_state->v2.clockInfoIndex[j]; |
||
2657 | clock_info = (union pplib_clock_info *) |
||
2997 | Serge | 2658 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
1963 | serge | 2659 | valid = radeon_atombios_parse_pplib_clock_info(rdev, |
2660 | state_index, mode_index, |
||
2661 | clock_info); |
||
2662 | if (valid) |
||
2663 | mode_index++; |
||
2664 | } |
||
2997 | Serge | 2665 | } else { |
2666 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
||
2667 | rdev->clock.default_mclk; |
||
2668 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
||
2669 | rdev->clock.default_sclk; |
||
2670 | mode_index++; |
||
2671 | } |
||
1963 | serge | 2672 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; |
2673 | if (mode_index) { |
||
2674 | radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, |
||
2675 | non_clock_info); |
||
1430 | serge | 2676 | state_index++; |
2677 | } |
||
3764 | Serge | 2678 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; |
1430 | serge | 2679 | } |
1963 | serge | 2680 | /* if multiple clock modes, mark the lowest as no display */ |
2681 | for (i = 0; i < state_index; i++) { |
||
2682 | if (rdev->pm.power_state[i].num_clock_modes > 1) |
||
2683 | rdev->pm.power_state[i].clock_info[0].flags |= |
||
2684 | RADEON_PM_MODE_NO_DISPLAY; |
||
2685 | } |
||
2686 | /* first mode is usually default */ |
||
2687 | if (rdev->pm.default_power_state_index == -1) { |
||
2688 | rdev->pm.power_state[0].type = |
||
2689 | POWER_STATE_TYPE_DEFAULT; |
||
2690 | rdev->pm.default_power_state_index = 0; |
||
2691 | rdev->pm.power_state[0].default_clock_mode = |
||
2692 | &rdev->pm.power_state[0].clock_info[0]; |
||
2693 | } |
||
2694 | return state_index; |
||
2695 | } |
||
2696 | |||
2697 | void radeon_atombios_get_power_modes(struct radeon_device *rdev) |
||
2698 | { |
||
2699 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
||
2700 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
||
2701 | u16 data_offset; |
||
2702 | u8 frev, crev; |
||
2703 | int state_index = 0; |
||
2704 | |||
2705 | rdev->pm.default_power_state_index = -1; |
||
2706 | |||
2707 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
||
2708 | &frev, &crev, &data_offset)) { |
||
2709 | switch (frev) { |
||
2710 | case 1: |
||
2711 | case 2: |
||
2712 | case 3: |
||
2713 | state_index = radeon_atombios_parse_power_table_1_3(rdev); |
||
2714 | break; |
||
2715 | case 4: |
||
2716 | case 5: |
||
2717 | state_index = radeon_atombios_parse_power_table_4_5(rdev); |
||
2718 | break; |
||
2719 | case 6: |
||
2720 | state_index = radeon_atombios_parse_power_table_6(rdev); |
||
2721 | break; |
||
2722 | default: |
||
2723 | break; |
||
1430 | serge | 2724 | } |
3764 | Serge | 2725 | } |
2726 | |||
2727 | if (state_index == 0) { |
||
1963 | serge | 2728 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); |
2729 | if (rdev->pm.power_state) { |
||
2997 | Serge | 2730 | rdev->pm.power_state[0].clock_info = |
2731 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
||
2732 | if (rdev->pm.power_state[0].clock_info) { |
||
1430 | serge | 2733 | /* add the default mode */ |
2734 | rdev->pm.power_state[state_index].type = |
||
2735 | POWER_STATE_TYPE_DEFAULT; |
||
2736 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
||
2737 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
||
2738 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
||
2739 | rdev->pm.power_state[state_index].default_clock_mode = |
||
2740 | &rdev->pm.power_state[state_index].clock_info[0]; |
||
2741 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
||
1963 | serge | 2742 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
2743 | rdev->pm.default_power_state_index = state_index; |
||
2744 | rdev->pm.power_state[state_index].flags = 0; |
||
1430 | serge | 2745 | state_index++; |
2746 | } |
||
1963 | serge | 2747 | } |
2997 | Serge | 2748 | } |
1963 | serge | 2749 | |
1430 | serge | 2750 | rdev->pm.num_power_states = state_index; |
2751 | |||
1963 | serge | 2752 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2753 | rdev->pm.current_clock_mode_index = 0; |
||
2997 | Serge | 2754 | if (rdev->pm.default_power_state_index >= 0) |
2755 | rdev->pm.current_vddc = |
||
2756 | rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
||
2757 | else |
||
2758 | rdev->pm.current_vddc = 0; |
||
1117 | serge | 2759 | } |
2760 | |||
3764 | Serge | 2761 | union get_clock_dividers { |
2762 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; |
||
2763 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; |
||
2764 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; |
||
2765 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; |
||
2766 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; |
||
5078 | serge | 2767 | struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; |
2768 | struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; |
||
3764 | Serge | 2769 | }; |
2770 | |||
2771 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
||
2772 | u8 clock_type, |
||
2773 | u32 clock, |
||
2774 | bool strobe_mode, |
||
2775 | struct atom_clock_dividers *dividers) |
||
2776 | { |
||
2777 | union get_clock_dividers args; |
||
2778 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); |
||
2779 | u8 frev, crev; |
||
2780 | |||
2781 | memset(&args, 0, sizeof(args)); |
||
2782 | memset(dividers, 0, sizeof(struct atom_clock_dividers)); |
||
2783 | |||
2784 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
||
2785 | return -EINVAL; |
||
2786 | |||
2787 | switch (crev) { |
||
2788 | case 1: |
||
2789 | /* r4xx, r5xx */ |
||
2790 | args.v1.ucAction = clock_type; |
||
2791 | args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ |
||
2792 | |||
2793 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2794 | |||
2795 | dividers->post_div = args.v1.ucPostDiv; |
||
2796 | dividers->fb_div = args.v1.ucFbDiv; |
||
2797 | dividers->enable_post_div = true; |
||
2798 | break; |
||
2799 | case 2: |
||
2800 | case 3: |
||
5078 | serge | 2801 | case 5: |
2802 | /* r6xx, r7xx, evergreen, ni, si */ |
||
3764 | Serge | 2803 | if (rdev->family <= CHIP_RV770) { |
2804 | args.v2.ucAction = clock_type; |
||
2805 | args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ |
||
2806 | |||
2807 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2808 | |||
2809 | dividers->post_div = args.v2.ucPostDiv; |
||
2810 | dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); |
||
2811 | dividers->ref_div = args.v2.ucAction; |
||
2812 | if (rdev->family == CHIP_RV770) { |
||
2813 | dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? |
||
2814 | true : false; |
||
2815 | dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; |
||
2816 | } else |
||
2817 | dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; |
||
2818 | } else { |
||
2819 | if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { |
||
2820 | args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); |
||
2821 | |||
2822 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2823 | |||
2824 | dividers->post_div = args.v3.ucPostDiv; |
||
2825 | dividers->enable_post_div = (args.v3.ucCntlFlag & |
||
2826 | ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; |
||
2827 | dividers->enable_dithen = (args.v3.ucCntlFlag & |
||
2828 | ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; |
||
5078 | serge | 2829 | dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); |
3764 | Serge | 2830 | dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); |
2831 | dividers->ref_div = args.v3.ucRefDiv; |
||
2832 | dividers->vco_mode = (args.v3.ucCntlFlag & |
||
2833 | ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; |
||
2834 | } else { |
||
5078 | serge | 2835 | /* for SI we use ComputeMemoryClockParam for memory plls */ |
2836 | if (rdev->family >= CHIP_TAHITI) |
||
2837 | return -EINVAL; |
||
3764 | Serge | 2838 | args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); |
2839 | if (strobe_mode) |
||
2840 | args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; |
||
2841 | |||
2842 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2843 | |||
2844 | dividers->post_div = args.v5.ucPostDiv; |
||
2845 | dividers->enable_post_div = (args.v5.ucCntlFlag & |
||
2846 | ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; |
||
2847 | dividers->enable_dithen = (args.v5.ucCntlFlag & |
||
2848 | ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; |
||
2849 | dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); |
||
2850 | dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); |
||
2851 | dividers->ref_div = args.v5.ucRefDiv; |
||
2852 | dividers->vco_mode = (args.v5.ucCntlFlag & |
||
2853 | ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; |
||
2854 | } |
||
2855 | } |
||
2856 | break; |
||
2857 | case 4: |
||
2858 | /* fusion */ |
||
2859 | args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ |
||
2860 | |||
2861 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2862 | |||
5078 | serge | 2863 | dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; |
3764 | Serge | 2864 | dividers->real_clock = le32_to_cpu(args.v4.ulClock); |
2865 | break; |
||
5078 | serge | 2866 | case 6: |
2867 | /* CI */ |
||
2868 | /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ |
||
2869 | args.v6_in.ulClock.ulComputeClockFlag = clock_type; |
||
2870 | args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ |
||
2871 | |||
2872 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2873 | |||
2874 | dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); |
||
2875 | dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); |
||
2876 | dividers->ref_div = args.v6_out.ucPllRefDiv; |
||
2877 | dividers->post_div = args.v6_out.ucPllPostDiv; |
||
2878 | dividers->flags = args.v6_out.ucPllCntlFlag; |
||
2879 | dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); |
||
2880 | dividers->post_divider = args.v6_out.ulClock.ucPostDiv; |
||
2881 | break; |
||
3764 | Serge | 2882 | default: |
2883 | return -EINVAL; |
||
2884 | } |
||
2885 | return 0; |
||
2886 | } |
||
2887 | |||
5078 | serge | 2888 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
2889 | u32 clock, |
||
2890 | bool strobe_mode, |
||
2891 | struct atom_mpll_param *mpll_param) |
||
2892 | { |
||
2893 | COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; |
||
2894 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); |
||
2895 | u8 frev, crev; |
||
2896 | |||
2897 | memset(&args, 0, sizeof(args)); |
||
2898 | memset(mpll_param, 0, sizeof(struct atom_mpll_param)); |
||
2899 | |||
2900 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
||
2901 | return -EINVAL; |
||
2902 | |||
2903 | switch (frev) { |
||
2904 | case 2: |
||
2905 | switch (crev) { |
||
2906 | case 1: |
||
2907 | /* SI */ |
||
2908 | args.ulClock = cpu_to_le32(clock); /* 10 khz */ |
||
2909 | args.ucInputFlag = 0; |
||
2910 | if (strobe_mode) |
||
2911 | args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; |
||
2912 | |||
2913 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2914 | |||
2915 | mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); |
||
2916 | mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); |
||
2917 | mpll_param->post_div = args.ucPostDiv; |
||
2918 | mpll_param->dll_speed = args.ucDllSpeed; |
||
2919 | mpll_param->bwcntl = args.ucBWCntl; |
||
2920 | mpll_param->vco_mode = |
||
2921 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); |
||
2922 | mpll_param->yclk_sel = |
||
2923 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; |
||
2924 | mpll_param->qdr = |
||
2925 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; |
||
2926 | mpll_param->half_rate = |
||
2927 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; |
||
2928 | break; |
||
2929 | default: |
||
2930 | return -EINVAL; |
||
2931 | } |
||
2932 | break; |
||
2933 | default: |
||
2934 | return -EINVAL; |
||
2935 | } |
||
2936 | return 0; |
||
2937 | } |
||
2938 | |||
1430 | serge | 2939 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
1117 | serge | 2940 | { |
1430 | serge | 2941 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
2942 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); |
||
1117 | serge | 2943 | |
2944 | args.ucEnable = enable; |
||
2945 | |||
2946 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2947 | } |
||
2948 | |||
1268 | serge | 2949 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
2950 | { |
||
2951 | GET_ENGINE_CLOCK_PS_ALLOCATION args; |
||
2952 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); |
||
2953 | |||
2954 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
1963 | serge | 2955 | return le32_to_cpu(args.ulReturnEngineClock); |
1268 | serge | 2956 | } |
2957 | |||
2958 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) |
||
2959 | { |
||
2960 | GET_MEMORY_CLOCK_PS_ALLOCATION args; |
||
2961 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); |
||
2962 | |||
2963 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
1963 | serge | 2964 | return le32_to_cpu(args.ulReturnMemoryClock); |
1268 | serge | 2965 | } |
2966 | |||
1117 | serge | 2967 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
2968 | uint32_t eng_clock) |
||
2969 | { |
||
2970 | SET_ENGINE_CLOCK_PS_ALLOCATION args; |
||
2971 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); |
||
2972 | |||
1963 | serge | 2973 | args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ |
1117 | serge | 2974 | |
2975 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2976 | } |
||
2977 | |||
2978 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, |
||
2979 | uint32_t mem_clock) |
||
2980 | { |
||
2981 | SET_MEMORY_CLOCK_PS_ALLOCATION args; |
||
2982 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); |
||
2983 | |||
2984 | if (rdev->flags & RADEON_IS_IGP) |
||
2985 | return; |
||
2986 | |||
1963 | serge | 2987 | args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ |
1117 | serge | 2988 | |
2989 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
2990 | } |
||
2991 | |||
5078 | serge | 2992 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
2993 | u32 eng_clock, u32 mem_clock) |
||
2994 | { |
||
2995 | SET_ENGINE_CLOCK_PS_ALLOCATION args; |
||
2996 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); |
||
2997 | u32 tmp; |
||
2998 | |||
2999 | memset(&args, 0, sizeof(args)); |
||
3000 | |||
3001 | tmp = eng_clock & SET_CLOCK_FREQ_MASK; |
||
3002 | tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); |
||
3003 | |||
3004 | args.ulTargetEngineClock = cpu_to_le32(tmp); |
||
3005 | if (mem_clock) |
||
3006 | args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); |
||
3007 | |||
3008 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3009 | } |
||
3010 | |||
3011 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
||
3012 | u32 mem_clock) |
||
3013 | { |
||
3014 | u32 args; |
||
3015 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); |
||
3016 | |||
3017 | args = cpu_to_le32(mem_clock); /* 10 khz */ |
||
3018 | |||
3019 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3020 | } |
||
3021 | |||
3022 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
||
3023 | u32 mem_clock) |
||
3024 | { |
||
3025 | SET_MEMORY_CLOCK_PS_ALLOCATION args; |
||
3026 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); |
||
3027 | u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); |
||
3028 | |||
3029 | args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ |
||
3030 | |||
3031 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3032 | } |
||
3033 | |||
1963 | serge | 3034 | union set_voltage { |
3035 | struct _SET_VOLTAGE_PS_ALLOCATION alloc; |
||
3036 | struct _SET_VOLTAGE_PARAMETERS v1; |
||
3037 | struct _SET_VOLTAGE_PARAMETERS_V2 v2; |
||
2997 | Serge | 3038 | struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; |
1963 | serge | 3039 | }; |
3040 | |||
3041 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) |
||
3042 | { |
||
3043 | union set_voltage args; |
||
3044 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); |
||
3045 | u8 frev, crev, volt_index = voltage_level; |
||
3046 | |||
3047 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
||
3048 | return; |
||
3049 | |||
1986 | serge | 3050 | /* 0xff01 is a flag rather then an actual voltage */ |
3051 | if (voltage_level == 0xff01) |
||
3052 | return; |
||
3053 | |||
1963 | serge | 3054 | switch (crev) { |
3055 | case 1: |
||
3056 | args.v1.ucVoltageType = voltage_type; |
||
3057 | args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; |
||
3058 | args.v1.ucVoltageIndex = volt_index; |
||
3059 | break; |
||
3060 | case 2: |
||
3061 | args.v2.ucVoltageType = voltage_type; |
||
3062 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; |
||
3063 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); |
||
3064 | break; |
||
2997 | Serge | 3065 | case 3: |
3066 | args.v3.ucVoltageType = voltage_type; |
||
3067 | args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; |
||
3068 | args.v3.usVoltageLevel = cpu_to_le16(voltage_level); |
||
3069 | break; |
||
1963 | serge | 3070 | default: |
3071 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3072 | return; |
||
3073 | } |
||
3074 | |||
3075 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3076 | } |
||
3077 | |||
5078 | serge | 3078 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
2997 | Serge | 3079 | u16 voltage_id, u16 *voltage) |
1986 | serge | 3080 | { |
3081 | union set_voltage args; |
||
3082 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); |
||
3083 | u8 frev, crev; |
||
1963 | serge | 3084 | |
1986 | serge | 3085 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
3086 | return -EINVAL; |
||
1963 | serge | 3087 | |
1986 | serge | 3088 | switch (crev) { |
3089 | case 1: |
||
3090 | return -EINVAL; |
||
3091 | case 2: |
||
3092 | args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; |
||
3093 | args.v2.ucVoltageMode = 0; |
||
3094 | args.v2.usVoltageLevel = 0; |
||
3095 | |||
3096 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3097 | |||
3098 | *voltage = le16_to_cpu(args.v2.usVoltageLevel); |
||
3099 | break; |
||
2997 | Serge | 3100 | case 3: |
3101 | args.v3.ucVoltageType = voltage_type; |
||
3102 | args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; |
||
3103 | args.v3.usVoltageLevel = cpu_to_le16(voltage_id); |
||
3104 | |||
3105 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3106 | |||
3107 | *voltage = le16_to_cpu(args.v3.usVoltageLevel); |
||
3108 | break; |
||
1986 | serge | 3109 | default: |
3110 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3111 | return -EINVAL; |
||
3112 | } |
||
3113 | |||
3114 | return 0; |
||
3115 | } |
||
3116 | |||
5078 | serge | 3117 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
3118 | u16 *voltage, |
||
3119 | u16 leakage_idx) |
||
3120 | { |
||
3121 | return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); |
||
3122 | } |
||
3123 | |||
3124 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
||
3125 | u16 *leakage_id) |
||
3126 | { |
||
3127 | union set_voltage args; |
||
3128 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); |
||
3129 | u8 frev, crev; |
||
3130 | |||
3131 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
||
3132 | return -EINVAL; |
||
3133 | |||
3134 | switch (crev) { |
||
3135 | case 3: |
||
3136 | case 4: |
||
3137 | args.v3.ucVoltageType = 0; |
||
3138 | args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; |
||
3139 | args.v3.usVoltageLevel = 0; |
||
3140 | |||
3141 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3142 | |||
3143 | *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); |
||
3144 | break; |
||
3145 | default: |
||
3146 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3147 | return -EINVAL; |
||
3148 | } |
||
3149 | |||
3150 | return 0; |
||
3151 | } |
||
3152 | |||
3153 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
||
3154 | u16 *vddc, u16 *vddci, |
||
3155 | u16 virtual_voltage_id, |
||
3156 | u16 vbios_voltage_id) |
||
3157 | { |
||
3158 | int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); |
||
3159 | u8 frev, crev; |
||
3160 | u16 data_offset, size; |
||
3161 | int i, j; |
||
3162 | ATOM_ASIC_PROFILING_INFO_V2_1 *profile; |
||
3163 | u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; |
||
3164 | |||
3165 | *vddc = 0; |
||
3166 | *vddci = 0; |
||
3167 | |||
3168 | if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3169 | &frev, &crev, &data_offset)) |
||
3170 | return -EINVAL; |
||
3171 | |||
3172 | profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) |
||
3173 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3174 | |||
3175 | switch (frev) { |
||
3176 | case 1: |
||
3177 | return -EINVAL; |
||
3178 | case 2: |
||
3179 | switch (crev) { |
||
3180 | case 1: |
||
3181 | if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) |
||
3182 | return -EINVAL; |
||
3183 | leakage_bin = (u16 *) |
||
3184 | (rdev->mode_info.atom_context->bios + data_offset + |
||
3185 | le16_to_cpu(profile->usLeakageBinArrayOffset)); |
||
3186 | vddc_id_buf = (u16 *) |
||
3187 | (rdev->mode_info.atom_context->bios + data_offset + |
||
3188 | le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); |
||
3189 | vddc_buf = (u16 *) |
||
3190 | (rdev->mode_info.atom_context->bios + data_offset + |
||
3191 | le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); |
||
3192 | vddci_id_buf = (u16 *) |
||
3193 | (rdev->mode_info.atom_context->bios + data_offset + |
||
3194 | le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); |
||
3195 | vddci_buf = (u16 *) |
||
3196 | (rdev->mode_info.atom_context->bios + data_offset + |
||
3197 | le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); |
||
3198 | |||
3199 | if (profile->ucElbVDDC_Num > 0) { |
||
3200 | for (i = 0; i < profile->ucElbVDDC_Num; i++) { |
||
3201 | if (vddc_id_buf[i] == virtual_voltage_id) { |
||
3202 | for (j = 0; j < profile->ucLeakageBinNum; j++) { |
||
3203 | if (vbios_voltage_id <= leakage_bin[j]) { |
||
3204 | *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; |
||
3205 | break; |
||
3206 | } |
||
3207 | } |
||
3208 | break; |
||
3209 | } |
||
3210 | } |
||
3211 | } |
||
3212 | if (profile->ucElbVDDCI_Num > 0) { |
||
3213 | for (i = 0; i < profile->ucElbVDDCI_Num; i++) { |
||
3214 | if (vddci_id_buf[i] == virtual_voltage_id) { |
||
3215 | for (j = 0; j < profile->ucLeakageBinNum; j++) { |
||
3216 | if (vbios_voltage_id <= leakage_bin[j]) { |
||
3217 | *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; |
||
3218 | break; |
||
3219 | } |
||
3220 | } |
||
3221 | break; |
||
3222 | } |
||
3223 | } |
||
3224 | } |
||
3225 | break; |
||
3226 | default: |
||
3227 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3228 | return -EINVAL; |
||
3229 | } |
||
3230 | break; |
||
3231 | default: |
||
3232 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3233 | return -EINVAL; |
||
3234 | } |
||
3235 | |||
3236 | return 0; |
||
3237 | } |
||
3238 | |||
3239 | union get_voltage_info { |
||
3240 | struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; |
||
3241 | struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; |
||
3242 | }; |
||
3243 | |||
3244 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
||
3245 | u16 virtual_voltage_id, |
||
3246 | u16 *voltage) |
||
3247 | { |
||
3248 | int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); |
||
3249 | u32 entry_id; |
||
3250 | u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; |
||
3251 | union get_voltage_info args; |
||
3252 | |||
3253 | for (entry_id = 0; entry_id < count; entry_id++) { |
||
3254 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == |
||
3255 | virtual_voltage_id) |
||
3256 | break; |
||
3257 | } |
||
3258 | |||
3259 | if (entry_id >= count) |
||
3260 | return -EINVAL; |
||
3261 | |||
3262 | args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; |
||
3263 | args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; |
||
3264 | args.in.ulSCLKFreq = |
||
3265 | cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); |
||
3266 | |||
3267 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3268 | |||
3269 | *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); |
||
3270 | |||
3271 | return 0; |
||
3272 | } |
||
3273 | |||
3274 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
||
3275 | u16 voltage_level, u8 voltage_type, |
||
3276 | u32 *gpio_value, u32 *gpio_mask) |
||
3277 | { |
||
3278 | union set_voltage args; |
||
3279 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); |
||
3280 | u8 frev, crev; |
||
3281 | |||
3282 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
||
3283 | return -EINVAL; |
||
3284 | |||
3285 | switch (crev) { |
||
3286 | case 1: |
||
3287 | return -EINVAL; |
||
3288 | case 2: |
||
3289 | args.v2.ucVoltageType = voltage_type; |
||
3290 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; |
||
3291 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); |
||
3292 | |||
3293 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3294 | |||
3295 | *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); |
||
3296 | |||
3297 | args.v2.ucVoltageType = voltage_type; |
||
3298 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; |
||
3299 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); |
||
3300 | |||
3301 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
3302 | |||
3303 | *gpio_value = le32_to_cpu(*(u32 *)&args.v2); |
||
3304 | break; |
||
3305 | default: |
||
3306 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3307 | return -EINVAL; |
||
3308 | } |
||
3309 | |||
3310 | return 0; |
||
3311 | } |
||
3312 | |||
3313 | union voltage_object_info { |
||
3314 | struct _ATOM_VOLTAGE_OBJECT_INFO v1; |
||
3315 | struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; |
||
3316 | struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; |
||
3317 | }; |
||
3318 | |||
3319 | union voltage_object { |
||
3320 | struct _ATOM_VOLTAGE_OBJECT v1; |
||
3321 | struct _ATOM_VOLTAGE_OBJECT_V2 v2; |
||
3322 | union _ATOM_VOLTAGE_OBJECT_V3 v3; |
||
3323 | }; |
||
3324 | |||
3325 | static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, |
||
3326 | u8 voltage_type) |
||
3327 | { |
||
3328 | u32 size = le16_to_cpu(v1->sHeader.usStructureSize); |
||
3329 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); |
||
3330 | u8 *start = (u8 *)v1; |
||
3331 | |||
3332 | while (offset < size) { |
||
3333 | ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); |
||
3334 | if (vo->ucVoltageType == voltage_type) |
||
3335 | return vo; |
||
3336 | offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + |
||
3337 | vo->asFormula.ucNumOfVoltageEntries; |
||
3338 | } |
||
3339 | return NULL; |
||
3340 | } |
||
3341 | |||
3342 | static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, |
||
3343 | u8 voltage_type) |
||
3344 | { |
||
3345 | u32 size = le16_to_cpu(v2->sHeader.usStructureSize); |
||
3346 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); |
||
3347 | u8 *start = (u8*)v2; |
||
3348 | |||
3349 | while (offset < size) { |
||
3350 | ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); |
||
3351 | if (vo->ucVoltageType == voltage_type) |
||
3352 | return vo; |
||
3353 | offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + |
||
3354 | (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); |
||
3355 | } |
||
3356 | return NULL; |
||
3357 | } |
||
3358 | |||
3359 | static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, |
||
3360 | u8 voltage_type, u8 voltage_mode) |
||
3361 | { |
||
3362 | u32 size = le16_to_cpu(v3->sHeader.usStructureSize); |
||
3363 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); |
||
3364 | u8 *start = (u8*)v3; |
||
3365 | |||
3366 | while (offset < size) { |
||
3367 | ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); |
||
3368 | if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && |
||
3369 | (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) |
||
3370 | return vo; |
||
3371 | offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); |
||
3372 | } |
||
3373 | return NULL; |
||
3374 | } |
||
3375 | |||
3376 | bool |
||
3377 | radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
||
3378 | u8 voltage_type, u8 voltage_mode) |
||
3379 | { |
||
3380 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); |
||
3381 | u8 frev, crev; |
||
3382 | u16 data_offset, size; |
||
3383 | union voltage_object_info *voltage_info; |
||
3384 | union voltage_object *voltage_object = NULL; |
||
3385 | |||
3386 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3387 | &frev, &crev, &data_offset)) { |
||
3388 | voltage_info = (union voltage_object_info *) |
||
3389 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3390 | |||
3391 | switch (frev) { |
||
3392 | case 1: |
||
3393 | case 2: |
||
3394 | switch (crev) { |
||
3395 | case 1: |
||
3396 | voltage_object = (union voltage_object *) |
||
3397 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); |
||
3398 | if (voltage_object && |
||
3399 | (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) |
||
3400 | return true; |
||
3401 | break; |
||
3402 | case 2: |
||
3403 | voltage_object = (union voltage_object *) |
||
3404 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); |
||
3405 | if (voltage_object && |
||
3406 | (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) |
||
3407 | return true; |
||
3408 | break; |
||
3409 | default: |
||
3410 | DRM_ERROR("unknown voltage object table\n"); |
||
3411 | return false; |
||
3412 | } |
||
3413 | break; |
||
3414 | case 3: |
||
3415 | switch (crev) { |
||
3416 | case 1: |
||
3417 | if (atom_lookup_voltage_object_v3(&voltage_info->v3, |
||
3418 | voltage_type, voltage_mode)) |
||
3419 | return true; |
||
3420 | break; |
||
3421 | default: |
||
3422 | DRM_ERROR("unknown voltage object table\n"); |
||
3423 | return false; |
||
3424 | } |
||
3425 | break; |
||
3426 | default: |
||
3427 | DRM_ERROR("unknown voltage object table\n"); |
||
3428 | return false; |
||
3429 | } |
||
3430 | |||
3431 | } |
||
3432 | return false; |
||
3433 | } |
||
3434 | |||
3435 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
||
3436 | u8 voltage_type, |
||
3437 | u8 *svd_gpio_id, u8 *svc_gpio_id) |
||
3438 | { |
||
3439 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); |
||
3440 | u8 frev, crev; |
||
3441 | u16 data_offset, size; |
||
3442 | union voltage_object_info *voltage_info; |
||
3443 | union voltage_object *voltage_object = NULL; |
||
3444 | |||
3445 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3446 | &frev, &crev, &data_offset)) { |
||
3447 | voltage_info = (union voltage_object_info *) |
||
3448 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3449 | |||
3450 | switch (frev) { |
||
3451 | case 3: |
||
3452 | switch (crev) { |
||
3453 | case 1: |
||
3454 | voltage_object = (union voltage_object *) |
||
3455 | atom_lookup_voltage_object_v3(&voltage_info->v3, |
||
3456 | voltage_type, |
||
3457 | VOLTAGE_OBJ_SVID2); |
||
3458 | if (voltage_object) { |
||
3459 | *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; |
||
3460 | *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; |
||
3461 | } else { |
||
3462 | return -EINVAL; |
||
3463 | } |
||
3464 | break; |
||
3465 | default: |
||
3466 | DRM_ERROR("unknown voltage object table\n"); |
||
3467 | return -EINVAL; |
||
3468 | } |
||
3469 | break; |
||
3470 | default: |
||
3471 | DRM_ERROR("unknown voltage object table\n"); |
||
3472 | return -EINVAL; |
||
3473 | } |
||
3474 | |||
3475 | } |
||
3476 | return 0; |
||
3477 | } |
||
3478 | |||
3479 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
||
3480 | u8 voltage_type, u16 *max_voltage) |
||
3481 | { |
||
3482 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); |
||
3483 | u8 frev, crev; |
||
3484 | u16 data_offset, size; |
||
3485 | union voltage_object_info *voltage_info; |
||
3486 | union voltage_object *voltage_object = NULL; |
||
3487 | |||
3488 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3489 | &frev, &crev, &data_offset)) { |
||
3490 | voltage_info = (union voltage_object_info *) |
||
3491 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3492 | |||
3493 | switch (crev) { |
||
3494 | case 1: |
||
3495 | voltage_object = (union voltage_object *) |
||
3496 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); |
||
3497 | if (voltage_object) { |
||
3498 | ATOM_VOLTAGE_FORMULA *formula = |
||
3499 | &voltage_object->v1.asFormula; |
||
3500 | if (formula->ucFlag & 1) |
||
3501 | *max_voltage = |
||
3502 | le16_to_cpu(formula->usVoltageBaseLevel) + |
||
3503 | formula->ucNumOfVoltageEntries / 2 * |
||
3504 | le16_to_cpu(formula->usVoltageStep); |
||
3505 | else |
||
3506 | *max_voltage = |
||
3507 | le16_to_cpu(formula->usVoltageBaseLevel) + |
||
3508 | (formula->ucNumOfVoltageEntries - 1) * |
||
3509 | le16_to_cpu(formula->usVoltageStep); |
||
3510 | return 0; |
||
3511 | } |
||
3512 | break; |
||
3513 | case 2: |
||
3514 | voltage_object = (union voltage_object *) |
||
3515 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); |
||
3516 | if (voltage_object) { |
||
3517 | ATOM_VOLTAGE_FORMULA_V2 *formula = |
||
3518 | &voltage_object->v2.asFormula; |
||
3519 | if (formula->ucNumOfVoltageEntries) { |
||
3520 | VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) |
||
3521 | ((u8 *)&formula->asVIDAdjustEntries[0] + |
||
3522 | (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); |
||
3523 | *max_voltage = |
||
3524 | le16_to_cpu(lut->usVoltageValue); |
||
3525 | return 0; |
||
3526 | } |
||
3527 | } |
||
3528 | break; |
||
3529 | default: |
||
3530 | DRM_ERROR("unknown voltage object table\n"); |
||
3531 | return -EINVAL; |
||
3532 | } |
||
3533 | |||
3534 | } |
||
3535 | return -EINVAL; |
||
3536 | } |
||
3537 | |||
3538 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
||
3539 | u8 voltage_type, u16 *min_voltage) |
||
3540 | { |
||
3541 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); |
||
3542 | u8 frev, crev; |
||
3543 | u16 data_offset, size; |
||
3544 | union voltage_object_info *voltage_info; |
||
3545 | union voltage_object *voltage_object = NULL; |
||
3546 | |||
3547 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3548 | &frev, &crev, &data_offset)) { |
||
3549 | voltage_info = (union voltage_object_info *) |
||
3550 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3551 | |||
3552 | switch (crev) { |
||
3553 | case 1: |
||
3554 | voltage_object = (union voltage_object *) |
||
3555 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); |
||
3556 | if (voltage_object) { |
||
3557 | ATOM_VOLTAGE_FORMULA *formula = |
||
3558 | &voltage_object->v1.asFormula; |
||
3559 | *min_voltage = |
||
3560 | le16_to_cpu(formula->usVoltageBaseLevel); |
||
3561 | return 0; |
||
3562 | } |
||
3563 | break; |
||
3564 | case 2: |
||
3565 | voltage_object = (union voltage_object *) |
||
3566 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); |
||
3567 | if (voltage_object) { |
||
3568 | ATOM_VOLTAGE_FORMULA_V2 *formula = |
||
3569 | &voltage_object->v2.asFormula; |
||
3570 | if (formula->ucNumOfVoltageEntries) { |
||
3571 | *min_voltage = |
||
3572 | le16_to_cpu(formula->asVIDAdjustEntries[ |
||
3573 | |||
3574 | ].usVoltageValue); |
||
3575 | return 0; |
||
3576 | } |
||
3577 | } |
||
3578 | break; |
||
3579 | default: |
||
3580 | DRM_ERROR("unknown voltage object table\n"); |
||
3581 | return -EINVAL; |
||
3582 | } |
||
3583 | |||
3584 | } |
||
3585 | return -EINVAL; |
||
3586 | } |
||
3587 | |||
3588 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
||
3589 | u8 voltage_type, u16 *voltage_step) |
||
3590 | { |
||
3591 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); |
||
3592 | u8 frev, crev; |
||
3593 | u16 data_offset, size; |
||
3594 | union voltage_object_info *voltage_info; |
||
3595 | union voltage_object *voltage_object = NULL; |
||
3596 | |||
3597 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3598 | &frev, &crev, &data_offset)) { |
||
3599 | voltage_info = (union voltage_object_info *) |
||
3600 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3601 | |||
3602 | switch (crev) { |
||
3603 | case 1: |
||
3604 | voltage_object = (union voltage_object *) |
||
3605 | atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); |
||
3606 | if (voltage_object) { |
||
3607 | ATOM_VOLTAGE_FORMULA *formula = |
||
3608 | &voltage_object->v1.asFormula; |
||
3609 | if (formula->ucFlag & 1) |
||
3610 | *voltage_step = |
||
3611 | (le16_to_cpu(formula->usVoltageStep) + 1) / 2; |
||
3612 | else |
||
3613 | *voltage_step = |
||
3614 | le16_to_cpu(formula->usVoltageStep); |
||
3615 | return 0; |
||
3616 | } |
||
3617 | break; |
||
3618 | case 2: |
||
3619 | return -EINVAL; |
||
3620 | default: |
||
3621 | DRM_ERROR("unknown voltage object table\n"); |
||
3622 | return -EINVAL; |
||
3623 | } |
||
3624 | |||
3625 | } |
||
3626 | return -EINVAL; |
||
3627 | } |
||
3628 | |||
3629 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
||
3630 | u8 voltage_type, |
||
3631 | u16 nominal_voltage, |
||
3632 | u16 *true_voltage) |
||
3633 | { |
||
3634 | u16 min_voltage, max_voltage, voltage_step; |
||
3635 | |||
3636 | if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) |
||
3637 | return -EINVAL; |
||
3638 | if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) |
||
3639 | return -EINVAL; |
||
3640 | if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) |
||
3641 | return -EINVAL; |
||
3642 | |||
3643 | if (nominal_voltage <= min_voltage) |
||
3644 | *true_voltage = min_voltage; |
||
3645 | else if (nominal_voltage >= max_voltage) |
||
3646 | *true_voltage = max_voltage; |
||
3647 | else |
||
3648 | *true_voltage = min_voltage + |
||
3649 | ((nominal_voltage - min_voltage) / voltage_step) * |
||
3650 | voltage_step; |
||
3651 | |||
3652 | return 0; |
||
3653 | } |
||
3654 | |||
3655 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
||
3656 | u8 voltage_type, u8 voltage_mode, |
||
3657 | struct atom_voltage_table *voltage_table) |
||
3658 | { |
||
3659 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); |
||
3660 | u8 frev, crev; |
||
3661 | u16 data_offset, size; |
||
3662 | int i, ret; |
||
3663 | union voltage_object_info *voltage_info; |
||
3664 | union voltage_object *voltage_object = NULL; |
||
3665 | |||
3666 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3667 | &frev, &crev, &data_offset)) { |
||
3668 | voltage_info = (union voltage_object_info *) |
||
3669 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3670 | |||
3671 | switch (frev) { |
||
3672 | case 1: |
||
3673 | case 2: |
||
3674 | switch (crev) { |
||
3675 | case 1: |
||
3676 | DRM_ERROR("old table version %d, %d\n", frev, crev); |
||
3677 | return -EINVAL; |
||
3678 | case 2: |
||
3679 | voltage_object = (union voltage_object *) |
||
3680 | atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); |
||
3681 | if (voltage_object) { |
||
3682 | ATOM_VOLTAGE_FORMULA_V2 *formula = |
||
3683 | &voltage_object->v2.asFormula; |
||
3684 | VOLTAGE_LUT_ENTRY *lut; |
||
3685 | if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) |
||
3686 | return -EINVAL; |
||
3687 | lut = &formula->asVIDAdjustEntries[0]; |
||
3688 | for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { |
||
3689 | voltage_table->entries[i].value = |
||
3690 | le16_to_cpu(lut->usVoltageValue); |
||
3691 | ret = radeon_atom_get_voltage_gpio_settings(rdev, |
||
3692 | voltage_table->entries[i].value, |
||
3693 | voltage_type, |
||
3694 | &voltage_table->entries[i].smio_low, |
||
3695 | &voltage_table->mask_low); |
||
3696 | if (ret) |
||
3697 | return ret; |
||
3698 | lut = (VOLTAGE_LUT_ENTRY *) |
||
3699 | ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); |
||
3700 | } |
||
3701 | voltage_table->count = formula->ucNumOfVoltageEntries; |
||
3702 | return 0; |
||
3703 | } |
||
3704 | break; |
||
3705 | default: |
||
3706 | DRM_ERROR("unknown voltage object table\n"); |
||
3707 | return -EINVAL; |
||
3708 | } |
||
3709 | break; |
||
3710 | case 3: |
||
3711 | switch (crev) { |
||
3712 | case 1: |
||
3713 | voltage_object = (union voltage_object *) |
||
3714 | atom_lookup_voltage_object_v3(&voltage_info->v3, |
||
3715 | voltage_type, voltage_mode); |
||
3716 | if (voltage_object) { |
||
3717 | ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = |
||
3718 | &voltage_object->v3.asGpioVoltageObj; |
||
3719 | VOLTAGE_LUT_ENTRY_V2 *lut; |
||
3720 | if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) |
||
3721 | return -EINVAL; |
||
3722 | lut = &gpio->asVolGpioLut[0]; |
||
3723 | for (i = 0; i < gpio->ucGpioEntryNum; i++) { |
||
3724 | voltage_table->entries[i].value = |
||
3725 | le16_to_cpu(lut->usVoltageValue); |
||
3726 | voltage_table->entries[i].smio_low = |
||
3727 | le32_to_cpu(lut->ulVoltageId); |
||
3728 | lut = (VOLTAGE_LUT_ENTRY_V2 *) |
||
3729 | ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); |
||
3730 | } |
||
3731 | voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); |
||
3732 | voltage_table->count = gpio->ucGpioEntryNum; |
||
3733 | voltage_table->phase_delay = gpio->ucPhaseDelay; |
||
3734 | return 0; |
||
3735 | } |
||
3736 | break; |
||
3737 | default: |
||
3738 | DRM_ERROR("unknown voltage object table\n"); |
||
3739 | return -EINVAL; |
||
3740 | } |
||
3741 | break; |
||
3742 | default: |
||
3743 | DRM_ERROR("unknown voltage object table\n"); |
||
3744 | return -EINVAL; |
||
3745 | } |
||
3746 | } |
||
3747 | return -EINVAL; |
||
3748 | } |
||
3749 | |||
3750 | union vram_info { |
||
3751 | struct _ATOM_VRAM_INFO_V3 v1_3; |
||
3752 | struct _ATOM_VRAM_INFO_V4 v1_4; |
||
3753 | struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; |
||
3754 | }; |
||
3755 | |||
3756 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
||
3757 | u8 module_index, struct atom_memory_info *mem_info) |
||
3758 | { |
||
3759 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); |
||
3760 | u8 frev, crev, i; |
||
3761 | u16 data_offset, size; |
||
3762 | union vram_info *vram_info; |
||
3763 | |||
3764 | memset(mem_info, 0, sizeof(struct atom_memory_info)); |
||
3765 | |||
3766 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3767 | &frev, &crev, &data_offset)) { |
||
3768 | vram_info = (union vram_info *) |
||
3769 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3770 | switch (frev) { |
||
3771 | case 1: |
||
3772 | switch (crev) { |
||
3773 | case 3: |
||
3774 | /* r6xx */ |
||
3775 | if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { |
||
3776 | ATOM_VRAM_MODULE_V3 *vram_module = |
||
3777 | (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; |
||
3778 | |||
3779 | for (i = 0; i < module_index; i++) { |
||
3780 | if (le16_to_cpu(vram_module->usSize) == 0) |
||
3781 | return -EINVAL; |
||
3782 | vram_module = (ATOM_VRAM_MODULE_V3 *) |
||
3783 | ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); |
||
3784 | } |
||
3785 | mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; |
||
3786 | mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; |
||
3787 | } else |
||
3788 | return -EINVAL; |
||
3789 | break; |
||
3790 | case 4: |
||
3791 | /* r7xx, evergreen */ |
||
3792 | if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { |
||
3793 | ATOM_VRAM_MODULE_V4 *vram_module = |
||
3794 | (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; |
||
3795 | |||
3796 | for (i = 0; i < module_index; i++) { |
||
3797 | if (le16_to_cpu(vram_module->usModuleSize) == 0) |
||
3798 | return -EINVAL; |
||
3799 | vram_module = (ATOM_VRAM_MODULE_V4 *) |
||
3800 | ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); |
||
3801 | } |
||
3802 | mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; |
||
3803 | mem_info->mem_type = vram_module->ucMemoryType & 0xf0; |
||
3804 | } else |
||
3805 | return -EINVAL; |
||
3806 | break; |
||
3807 | default: |
||
3808 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3809 | return -EINVAL; |
||
3810 | } |
||
3811 | break; |
||
3812 | case 2: |
||
3813 | switch (crev) { |
||
3814 | case 1: |
||
3815 | /* ni */ |
||
3816 | if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { |
||
3817 | ATOM_VRAM_MODULE_V7 *vram_module = |
||
3818 | (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; |
||
3819 | |||
3820 | for (i = 0; i < module_index; i++) { |
||
3821 | if (le16_to_cpu(vram_module->usModuleSize) == 0) |
||
3822 | return -EINVAL; |
||
3823 | vram_module = (ATOM_VRAM_MODULE_V7 *) |
||
3824 | ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); |
||
3825 | } |
||
3826 | mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; |
||
3827 | mem_info->mem_type = vram_module->ucMemoryType & 0xf0; |
||
3828 | } else |
||
3829 | return -EINVAL; |
||
3830 | break; |
||
3831 | default: |
||
3832 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3833 | return -EINVAL; |
||
3834 | } |
||
3835 | break; |
||
3836 | default: |
||
3837 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3838 | return -EINVAL; |
||
3839 | } |
||
3840 | return 0; |
||
3841 | } |
||
3842 | return -EINVAL; |
||
3843 | } |
||
3844 | |||
3845 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
||
3846 | bool gddr5, u8 module_index, |
||
3847 | struct atom_memory_clock_range_table *mclk_range_table) |
||
3848 | { |
||
3849 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); |
||
3850 | u8 frev, crev, i; |
||
3851 | u16 data_offset, size; |
||
3852 | union vram_info *vram_info; |
||
3853 | u32 mem_timing_size = gddr5 ? |
||
3854 | sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); |
||
3855 | |||
3856 | memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); |
||
3857 | |||
3858 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3859 | &frev, &crev, &data_offset)) { |
||
3860 | vram_info = (union vram_info *) |
||
3861 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3862 | switch (frev) { |
||
3863 | case 1: |
||
3864 | switch (crev) { |
||
3865 | case 3: |
||
3866 | DRM_ERROR("old table version %d, %d\n", frev, crev); |
||
3867 | return -EINVAL; |
||
3868 | case 4: |
||
3869 | /* r7xx, evergreen */ |
||
3870 | if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { |
||
3871 | ATOM_VRAM_MODULE_V4 *vram_module = |
||
3872 | (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; |
||
3873 | ATOM_MEMORY_TIMING_FORMAT *format; |
||
3874 | |||
3875 | for (i = 0; i < module_index; i++) { |
||
3876 | if (le16_to_cpu(vram_module->usModuleSize) == 0) |
||
3877 | return -EINVAL; |
||
3878 | vram_module = (ATOM_VRAM_MODULE_V4 *) |
||
3879 | ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); |
||
3880 | } |
||
3881 | mclk_range_table->num_entries = (u8) |
||
3882 | ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / |
||
3883 | mem_timing_size); |
||
3884 | format = &vram_module->asMemTiming[0]; |
||
3885 | for (i = 0; i < mclk_range_table->num_entries; i++) { |
||
3886 | mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); |
||
3887 | format = (ATOM_MEMORY_TIMING_FORMAT *) |
||
3888 | ((u8 *)format + mem_timing_size); |
||
3889 | } |
||
3890 | } else |
||
3891 | return -EINVAL; |
||
3892 | break; |
||
3893 | default: |
||
3894 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3895 | return -EINVAL; |
||
3896 | } |
||
3897 | break; |
||
3898 | case 2: |
||
3899 | DRM_ERROR("new table version %d, %d\n", frev, crev); |
||
3900 | return -EINVAL; |
||
3901 | default: |
||
3902 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3903 | return -EINVAL; |
||
3904 | } |
||
3905 | return 0; |
||
3906 | } |
||
3907 | return -EINVAL; |
||
3908 | } |
||
3909 | |||
3910 | #define MEM_ID_MASK 0xff000000 |
||
3911 | #define MEM_ID_SHIFT 24 |
||
3912 | #define CLOCK_RANGE_MASK 0x00ffffff |
||
3913 | #define CLOCK_RANGE_SHIFT 0 |
||
3914 | #define LOW_NIBBLE_MASK 0xf |
||
3915 | #define DATA_EQU_PREV 0 |
||
3916 | #define DATA_FROM_TABLE 4 |
||
3917 | |||
3918 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
||
3919 | u8 module_index, |
||
3920 | struct atom_mc_reg_table *reg_table) |
||
3921 | { |
||
3922 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); |
||
3923 | u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; |
||
3924 | u32 i = 0, j; |
||
3925 | u16 data_offset, size; |
||
3926 | union vram_info *vram_info; |
||
3927 | |||
3928 | memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); |
||
3929 | |||
3930 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
||
3931 | &frev, &crev, &data_offset)) { |
||
3932 | vram_info = (union vram_info *) |
||
3933 | (rdev->mode_info.atom_context->bios + data_offset); |
||
3934 | switch (frev) { |
||
3935 | case 1: |
||
3936 | DRM_ERROR("old table version %d, %d\n", frev, crev); |
||
3937 | return -EINVAL; |
||
3938 | case 2: |
||
3939 | switch (crev) { |
||
3940 | case 1: |
||
3941 | if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { |
||
3942 | ATOM_INIT_REG_BLOCK *reg_block = |
||
3943 | (ATOM_INIT_REG_BLOCK *) |
||
3944 | ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); |
||
3945 | ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = |
||
3946 | (ATOM_MEMORY_SETTING_DATA_BLOCK *) |
||
3947 | ((u8 *)reg_block + (2 * sizeof(u16)) + |
||
3948 | le16_to_cpu(reg_block->usRegIndexTblSize)); |
||
3949 | ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; |
||
3950 | num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / |
||
3951 | sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; |
||
3952 | if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) |
||
3953 | return -EINVAL; |
||
3954 | while (i < num_entries) { |
||
3955 | if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) |
||
3956 | break; |
||
3957 | reg_table->mc_reg_address[i].s1 = |
||
3958 | (u16)(le16_to_cpu(format->usRegIndex)); |
||
3959 | reg_table->mc_reg_address[i].pre_reg_data = |
||
3960 | (u8)(format->ucPreRegDataLength); |
||
3961 | i++; |
||
3962 | format = (ATOM_INIT_REG_INDEX_FORMAT *) |
||
3963 | ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); |
||
3964 | } |
||
3965 | reg_table->last = i; |
||
3966 | while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && |
||
3967 | (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { |
||
3968 | t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) |
||
3969 | >> MEM_ID_SHIFT); |
||
3970 | if (module_index == t_mem_id) { |
||
3971 | reg_table->mc_reg_table_entry[num_ranges].mclk_max = |
||
3972 | (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) |
||
3973 | >> CLOCK_RANGE_SHIFT); |
||
3974 | for (i = 0, j = 1; i < reg_table->last; i++) { |
||
3975 | if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { |
||
3976 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = |
||
3977 | (u32)le32_to_cpu(*((u32 *)reg_data + j)); |
||
3978 | j++; |
||
3979 | } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { |
||
3980 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = |
||
3981 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; |
||
3982 | } |
||
3983 | } |
||
3984 | num_ranges++; |
||
3985 | } |
||
3986 | reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) |
||
3987 | ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); |
||
3988 | } |
||
3989 | if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) |
||
3990 | return -EINVAL; |
||
3991 | reg_table->num_entries = num_ranges; |
||
3992 | } else |
||
3993 | return -EINVAL; |
||
3994 | break; |
||
3995 | default: |
||
3996 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
3997 | return -EINVAL; |
||
3998 | } |
||
3999 | break; |
||
4000 | default: |
||
4001 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
||
4002 | return -EINVAL; |
||
4003 | } |
||
4004 | return 0; |
||
4005 | } |
||
4006 | return -EINVAL; |
||
4007 | } |
||
4008 | |||
1117 | serge | 4009 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
4010 | { |
||
4011 | struct radeon_device *rdev = dev->dev_private; |
||
4012 | uint32_t bios_2_scratch, bios_6_scratch; |
||
4013 | |||
4014 | if (rdev->family >= CHIP_R600) { |
||
1179 | serge | 4015 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
1117 | serge | 4016 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
4017 | } else { |
||
1179 | serge | 4018 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
1117 | serge | 4019 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
4020 | } |
||
4021 | |||
4022 | /* let the bios control the backlight */ |
||
4023 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; |
||
4024 | |||
4025 | /* tell the bios not to handle mode switching */ |
||
1963 | serge | 4026 | bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; |
1117 | serge | 4027 | |
5078 | serge | 4028 | /* clear the vbios dpms state */ |
4029 | if (ASIC_IS_DCE4(rdev)) |
||
4030 | bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; |
||
4031 | |||
1117 | serge | 4032 | if (rdev->family >= CHIP_R600) { |
4033 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
||
4034 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
||
4035 | } else { |
||
4036 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
||
4037 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
||
4038 | } |
||
4039 | |||
4040 | } |
||
4041 | |||
1179 | serge | 4042 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
4043 | { |
||
4044 | uint32_t scratch_reg; |
||
4045 | int i; |
||
4046 | |||
4047 | if (rdev->family >= CHIP_R600) |
||
4048 | scratch_reg = R600_BIOS_0_SCRATCH; |
||
4049 | else |
||
4050 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
||
4051 | |||
4052 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
||
4053 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); |
||
4054 | } |
||
4055 | |||
4056 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) |
||
4057 | { |
||
4058 | uint32_t scratch_reg; |
||
4059 | int i; |
||
4060 | |||
4061 | if (rdev->family >= CHIP_R600) |
||
4062 | scratch_reg = R600_BIOS_0_SCRATCH; |
||
4063 | else |
||
4064 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
||
4065 | |||
4066 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
||
4067 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); |
||
4068 | } |
||
4069 | |||
1117 | serge | 4070 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
4071 | { |
||
4072 | struct drm_device *dev = encoder->dev; |
||
4073 | struct radeon_device *rdev = dev->dev_private; |
||
4074 | uint32_t bios_6_scratch; |
||
4075 | |||
4076 | if (rdev->family >= CHIP_R600) |
||
4077 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
||
4078 | else |
||
4079 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
||
4080 | |||
1963 | serge | 4081 | if (lock) { |
1117 | serge | 4082 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; |
1963 | serge | 4083 | bios_6_scratch &= ~ATOM_S6_ACC_MODE; |
4084 | } else { |
||
1117 | serge | 4085 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; |
1963 | serge | 4086 | bios_6_scratch |= ATOM_S6_ACC_MODE; |
4087 | } |
||
1117 | serge | 4088 | |
4089 | if (rdev->family >= CHIP_R600) |
||
4090 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
||
4091 | else |
||
4092 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
||
4093 | } |
||
4094 | |||
4095 | /* at some point we may want to break this out into individual functions */ |
||
4096 | void |
||
4097 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
||
4098 | struct drm_encoder *encoder, |
||
4099 | bool connected) |
||
4100 | { |
||
4101 | struct drm_device *dev = connector->dev; |
||
4102 | struct radeon_device *rdev = dev->dev_private; |
||
4103 | struct radeon_connector *radeon_connector = |
||
4104 | to_radeon_connector(connector); |
||
4105 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
4106 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; |
||
4107 | |||
4108 | if (rdev->family >= CHIP_R600) { |
||
4109 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
||
4110 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
||
4111 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
||
4112 | } else { |
||
4113 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
||
4114 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
||
4115 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
||
4116 | } |
||
4117 | |||
4118 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
||
4119 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
||
4120 | if (connected) { |
||
1963 | serge | 4121 | DRM_DEBUG_KMS("TV1 connected\n"); |
1117 | serge | 4122 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
4123 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; |
||
4124 | } else { |
||
1963 | serge | 4125 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
1117 | serge | 4126 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
4127 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; |
||
4128 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; |
||
4129 | } |
||
4130 | } |
||
4131 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && |
||
4132 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { |
||
4133 | if (connected) { |
||
1963 | serge | 4134 | DRM_DEBUG_KMS("CV connected\n"); |
1117 | serge | 4135 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
4136 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; |
||
4137 | } else { |
||
1963 | serge | 4138 | DRM_DEBUG_KMS("CV disconnected\n"); |
1117 | serge | 4139 | bios_0_scratch &= ~ATOM_S0_CV_MASK; |
4140 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; |
||
4141 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; |
||
4142 | } |
||
4143 | } |
||
4144 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
||
4145 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
||
4146 | if (connected) { |
||
1963 | serge | 4147 | DRM_DEBUG_KMS("LCD1 connected\n"); |
1117 | serge | 4148 | bios_0_scratch |= ATOM_S0_LCD1; |
4149 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; |
||
4150 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; |
||
4151 | } else { |
||
1963 | serge | 4152 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
1117 | serge | 4153 | bios_0_scratch &= ~ATOM_S0_LCD1; |
4154 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; |
||
4155 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; |
||
4156 | } |
||
4157 | } |
||
4158 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
||
4159 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
||
4160 | if (connected) { |
||
1963 | serge | 4161 | DRM_DEBUG_KMS("CRT1 connected\n"); |
1117 | serge | 4162 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
4163 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; |
||
4164 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; |
||
4165 | } else { |
||
1963 | serge | 4166 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
1117 | serge | 4167 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
4168 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; |
||
4169 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; |
||
4170 | } |
||
4171 | } |
||
4172 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
||
4173 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
||
4174 | if (connected) { |
||
1963 | serge | 4175 | DRM_DEBUG_KMS("CRT2 connected\n"); |
1117 | serge | 4176 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
4177 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; |
||
4178 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; |
||
4179 | } else { |
||
1963 | serge | 4180 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
1117 | serge | 4181 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
4182 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; |
||
4183 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; |
||
4184 | } |
||
4185 | } |
||
4186 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
||
4187 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
||
4188 | if (connected) { |
||
1963 | serge | 4189 | DRM_DEBUG_KMS("DFP1 connected\n"); |
1117 | serge | 4190 | bios_0_scratch |= ATOM_S0_DFP1; |
4191 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; |
||
4192 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; |
||
4193 | } else { |
||
1963 | serge | 4194 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
1117 | serge | 4195 | bios_0_scratch &= ~ATOM_S0_DFP1; |
4196 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; |
||
4197 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; |
||
4198 | } |
||
4199 | } |
||
4200 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
||
4201 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
||
4202 | if (connected) { |
||
1963 | serge | 4203 | DRM_DEBUG_KMS("DFP2 connected\n"); |
1117 | serge | 4204 | bios_0_scratch |= ATOM_S0_DFP2; |
4205 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; |
||
4206 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; |
||
4207 | } else { |
||
1963 | serge | 4208 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
1117 | serge | 4209 | bios_0_scratch &= ~ATOM_S0_DFP2; |
4210 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; |
||
4211 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; |
||
4212 | } |
||
4213 | } |
||
4214 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && |
||
4215 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { |
||
4216 | if (connected) { |
||
1963 | serge | 4217 | DRM_DEBUG_KMS("DFP3 connected\n"); |
1117 | serge | 4218 | bios_0_scratch |= ATOM_S0_DFP3; |
4219 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; |
||
4220 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; |
||
4221 | } else { |
||
1963 | serge | 4222 | DRM_DEBUG_KMS("DFP3 disconnected\n"); |
1117 | serge | 4223 | bios_0_scratch &= ~ATOM_S0_DFP3; |
4224 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; |
||
4225 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; |
||
4226 | } |
||
4227 | } |
||
4228 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && |
||
4229 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { |
||
4230 | if (connected) { |
||
1963 | serge | 4231 | DRM_DEBUG_KMS("DFP4 connected\n"); |
1117 | serge | 4232 | bios_0_scratch |= ATOM_S0_DFP4; |
4233 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; |
||
4234 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; |
||
4235 | } else { |
||
1963 | serge | 4236 | DRM_DEBUG_KMS("DFP4 disconnected\n"); |
1117 | serge | 4237 | bios_0_scratch &= ~ATOM_S0_DFP4; |
4238 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; |
||
4239 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; |
||
4240 | } |
||
4241 | } |
||
4242 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && |
||
4243 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { |
||
4244 | if (connected) { |
||
1963 | serge | 4245 | DRM_DEBUG_KMS("DFP5 connected\n"); |
1117 | serge | 4246 | bios_0_scratch |= ATOM_S0_DFP5; |
4247 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; |
||
4248 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; |
||
4249 | } else { |
||
1963 | serge | 4250 | DRM_DEBUG_KMS("DFP5 disconnected\n"); |
1117 | serge | 4251 | bios_0_scratch &= ~ATOM_S0_DFP5; |
4252 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; |
||
4253 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; |
||
4254 | } |
||
4255 | } |
||
2997 | Serge | 4256 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && |
4257 | (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { |
||
4258 | if (connected) { |
||
4259 | DRM_DEBUG_KMS("DFP6 connected\n"); |
||
4260 | bios_0_scratch |= ATOM_S0_DFP6; |
||
4261 | bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; |
||
4262 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; |
||
4263 | } else { |
||
4264 | DRM_DEBUG_KMS("DFP6 disconnected\n"); |
||
4265 | bios_0_scratch &= ~ATOM_S0_DFP6; |
||
4266 | bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; |
||
4267 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; |
||
4268 | } |
||
4269 | } |
||
1117 | serge | 4270 | |
4271 | if (rdev->family >= CHIP_R600) { |
||
4272 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); |
||
4273 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
||
4274 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
||
4275 | } else { |
||
4276 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
||
4277 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
||
4278 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
||
4279 | } |
||
4280 | } |
||
4281 | |||
4282 | void |
||
4283 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
||
4284 | { |
||
4285 | struct drm_device *dev = encoder->dev; |
||
4286 | struct radeon_device *rdev = dev->dev_private; |
||
4287 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
4288 | uint32_t bios_3_scratch; |
||
4289 | |||
2997 | Serge | 4290 | if (ASIC_IS_DCE4(rdev)) |
4291 | return; |
||
4292 | |||
1117 | serge | 4293 | if (rdev->family >= CHIP_R600) |
4294 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
||
4295 | else |
||
4296 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
||
4297 | |||
4298 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
||
4299 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; |
||
4300 | bios_3_scratch |= (crtc << 18); |
||
4301 | } |
||
4302 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
||
4303 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; |
||
4304 | bios_3_scratch |= (crtc << 24); |
||
4305 | } |
||
4306 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
||
4307 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; |
||
4308 | bios_3_scratch |= (crtc << 16); |
||
4309 | } |
||
4310 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
||
4311 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; |
||
4312 | bios_3_scratch |= (crtc << 20); |
||
4313 | } |
||
4314 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
||
4315 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; |
||
4316 | bios_3_scratch |= (crtc << 17); |
||
4317 | } |
||
4318 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
||
4319 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; |
||
4320 | bios_3_scratch |= (crtc << 19); |
||
4321 | } |
||
4322 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
||
4323 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; |
||
4324 | bios_3_scratch |= (crtc << 23); |
||
4325 | } |
||
4326 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
||
4327 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; |
||
4328 | bios_3_scratch |= (crtc << 25); |
||
4329 | } |
||
4330 | |||
4331 | if (rdev->family >= CHIP_R600) |
||
4332 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
||
4333 | else |
||
4334 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
||
4335 | } |
||
4336 | |||
4337 | void |
||
4338 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
||
4339 | { |
||
4340 | struct drm_device *dev = encoder->dev; |
||
4341 | struct radeon_device *rdev = dev->dev_private; |
||
4342 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
4343 | uint32_t bios_2_scratch; |
||
4344 | |||
2997 | Serge | 4345 | if (ASIC_IS_DCE4(rdev)) |
4346 | return; |
||
4347 | |||
1117 | serge | 4348 | if (rdev->family >= CHIP_R600) |
4349 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
||
4350 | else |
||
4351 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
||
4352 | |||
4353 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
||
4354 | if (on) |
||
4355 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; |
||
4356 | else |
||
4357 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; |
||
4358 | } |
||
4359 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
||
4360 | if (on) |
||
4361 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; |
||
4362 | else |
||
4363 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; |
||
4364 | } |
||
4365 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
||
4366 | if (on) |
||
4367 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; |
||
4368 | else |
||
4369 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; |
||
4370 | } |
||
4371 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
||
4372 | if (on) |
||
4373 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; |
||
4374 | else |
||
4375 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; |
||
4376 | } |
||
4377 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
||
4378 | if (on) |
||
4379 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; |
||
4380 | else |
||
4381 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; |
||
4382 | } |
||
4383 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
||
4384 | if (on) |
||
4385 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; |
||
4386 | else |
||
4387 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; |
||
4388 | } |
||
4389 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
||
4390 | if (on) |
||
4391 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; |
||
4392 | else |
||
4393 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; |
||
4394 | } |
||
4395 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
||
4396 | if (on) |
||
4397 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; |
||
4398 | else |
||
4399 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; |
||
4400 | } |
||
4401 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { |
||
4402 | if (on) |
||
4403 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; |
||
4404 | else |
||
4405 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; |
||
4406 | } |
||
4407 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { |
||
4408 | if (on) |
||
4409 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; |
||
4410 | else |
||
4411 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; |
||
4412 | } |
||
4413 | |||
4414 | if (rdev->family >= CHIP_R600) |
||
4415 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
||
4416 | else |
||
4417 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
||
4418 | }><>><>><>><>><>><>><>><>>>>>>>>>>>>>>>>>>=>>>>>=>>>=>>>>><>><>><>><>><>><>=>>>>>>>><>><>><>><>><>><>><>><>><>><>>>>>><>><>><>><>><>><>><>>=>>=>>=>>>><>><>><>>>>>>>><>><>><>><>><>><>><>>=>>=>>>=>>>>>><>><>><>><>><>><>><>>>>><>><>><>><>><>><>><>><> |