WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
1117	serge	28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
1963	serge	35	radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
1117	serge	36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
1963	serge	39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
		40	uint32_t supported_device, u16 caps);
1117	serge	41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
1963	serge	49	uint32_t igp_lane_info,
1321	serge	50	uint16_t connector_object_id,
1963	serge	51	struct radeon_hpd *hpd,
		52	struct radeon_router *router);
1117	serge	53
		54	/* from radeon_legacy_encoder.c */
		55	extern void
1963	serge	56	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
1117	serge	57	uint32_t supported_device);
		58
2997	Serge	59	/* local */
		60	static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		61	u16 voltage_id, u16 *voltage);
		62
1117	serge	63	union atom_supported_devices {
		64	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		65	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		66	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		67	};
		68
2997	Serge	69	static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
		70	ATOM_GPIO_I2C_ASSIGMENT *gpio,
		71	u8 index)
1117	serge	72	{
2997	Serge	73	/* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
		74	if ((rdev->family == CHIP_R420) \|\|
		75	(rdev->family == CHIP_R423) \|\|
		76	(rdev->family == CHIP_RV410)) {
		77	if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) \|\|
		78	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) \|\|
		79	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
		80	gpio->ucClkMaskShift = 0x19;
		81	gpio->ucDataMaskShift = 0x18;
		82	}
		83	}
1117	serge	84
1963	serge	85	/* some evergreen boards have bad data for this entry */
		86	if (ASIC_IS_DCE4(rdev)) {
2997	Serge	87	if ((index == 7) &&
1963	serge	88	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
		89	(gpio->sucI2cId.ucAccess == 0)) {
		90	gpio->sucI2cId.ucAccess = 0x97;
		91	gpio->ucDataMaskShift = 8;
		92	gpio->ucDataEnShift = 8;
		93	gpio->ucDataY_Shift = 8;
		94	gpio->ucDataA_Shift = 8;
		95	}
		96	}
		97
		98	/* some DCE3 boards have bad data for this entry */
		99	if (ASIC_IS_DCE3(rdev)) {
2997	Serge	100	if ((index == 4) &&
1963	serge	101	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
		102	(gpio->sucI2cId.ucAccess == 0x94))
		103	gpio->sucI2cId.ucAccess = 0x14;
		104	}
2997	Serge	105	}
1963	serge	106
2997	Serge	107	static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
		108	{
		109	struct radeon_i2c_bus_rec i2c;
		110
		111	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		112
1321	serge	113	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		114	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		115	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		116	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		117	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		118	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		119	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		120	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		121	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		122	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		123	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		124	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		125	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		126	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		127	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		128	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		129
		130	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		131	i2c.hw_capable = true;
		132	else
		133	i2c.hw_capable = false;
		134
		135	if (gpio->sucI2cId.ucAccess == 0xa0)
		136	i2c.mm_i2c = true;
		137	else
		138	i2c.mm_i2c = false;
		139
		140	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		141
1963	serge	142	if (i2c.mask_clk_reg)
1117	serge	143	i2c.valid = true;
2997	Serge	144	else
		145	i2c.valid = false;
1117	serge	146
		147	return i2c;
		148	}
		149
2997	Serge	150	static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
		151	uint8_t id)
1963	serge	152	{
		153	struct atom_context *ctx = rdev->mode_info.atom_context;
		154	ATOM_GPIO_I2C_ASSIGMENT *gpio;
		155	struct radeon_i2c_bus_rec i2c;
		156	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		157	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		158	uint16_t data_offset, size;
		159	int i, num_indices;
		160
		161	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
2997	Serge	162	i2c.valid = false;
1963	serge	163
		164	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
		165	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		166
		167	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		168	sizeof(ATOM_GPIO_I2C_ASSIGMENT);
		169
		170	for (i = 0; i < num_indices; i++) {
		171	gpio = &i2c_info->asGPIO_Info[i];
		172
2997	Serge	173	radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
		174
		175	if (gpio->sucI2cId.ucAccess == id) {
		176	i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
		177	break;
		178	}
1963	serge	179	}
		180	}
		181
2997	Serge	182	return i2c;
		183	}
1963	serge	184
2997	Serge	185	void radeon_atombios_i2c_init(struct radeon_device *rdev)
		186	{
		187	struct atom_context *ctx = rdev->mode_info.atom_context;
		188	ATOM_GPIO_I2C_ASSIGMENT *gpio;
		189	struct radeon_i2c_bus_rec i2c;
		190	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		191	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		192	uint16_t data_offset, size;
		193	int i, num_indices;
		194	char stmp[32];
1963	serge	195
2997	Serge	196	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
		197	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
1963	serge	198
2997	Serge	199	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		200	sizeof(ATOM_GPIO_I2C_ASSIGMENT);
1963	serge	201
2997	Serge	202	for (i = 0; i < num_indices; i++) {
		203	gpio = &i2c_info->asGPIO_Info[i];
1963	serge	204
2997	Serge	205	radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
		206
		207	i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
		208
		209	if (i2c.valid) {
1963	serge	210	sprintf(stmp, "0x%x", i2c.i2c_id);
		211	rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
		212	}
		213	}
		214	}
		215	}
		216
2997	Serge	217	static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
1321	serge	218	u8 id)
		219	{
		220	struct atom_context *ctx = rdev->mode_info.atom_context;
		221	struct radeon_gpio_rec gpio;
		222	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
		223	struct _ATOM_GPIO_PIN_LUT *gpio_info;
		224	ATOM_GPIO_PIN_ASSIGNMENT *pin;
		225	u16 data_offset, size;
		226	int i, num_indices;
		227
		228	memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
		229	gpio.valid = false;
		230
1963	serge	231	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
1321	serge	232	gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
		233
1963	serge	234	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		235	sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
1321	serge	236
		237	for (i = 0; i < num_indices; i++) {
		238	pin = &gpio_info->asGPIO_Pin[i];
		239	if (id == pin->ucGPIO_ID) {
		240	gpio.id = pin->ucGPIO_ID;
1963	serge	241	gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
1321	serge	242	gpio.mask = (1 << pin->ucGpioPinBitShift);
		243	gpio.valid = true;
		244	break;
		245	}
		246	}
1963	serge	247	}
1321	serge	248
		249	return gpio;
		250	}
		251
		252	static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
		253	struct radeon_gpio_rec *gpio)
		254	{
		255	struct radeon_hpd hpd;
1430	serge	256	u32 reg;
		257
1963	serge	258	memset(&hpd, 0, sizeof(struct radeon_hpd));
		259
2997	Serge	260	if (ASIC_IS_DCE6(rdev))
		261	reg = SI_DC_GPIO_HPD_A;
		262	else if (ASIC_IS_DCE4(rdev))
1430	serge	263	reg = EVERGREEN_DC_GPIO_HPD_A;
		264	else
		265	reg = AVIVO_DC_GPIO_HPD_A;
		266
1321	serge	267	hpd.gpio = *gpio;
1430	serge	268	if (gpio->reg == reg) {
1321	serge	269	switch(gpio->mask) {
		270	case (1 << 0):
		271	hpd.hpd = RADEON_HPD_1;
		272	break;
		273	case (1 << 8):
		274	hpd.hpd = RADEON_HPD_2;
		275	break;
		276	case (1 << 16):
		277	hpd.hpd = RADEON_HPD_3;
		278	break;
		279	case (1 << 24):
		280	hpd.hpd = RADEON_HPD_4;
		281	break;
		282	case (1 << 26):
		283	hpd.hpd = RADEON_HPD_5;
		284	break;
		285	case (1 << 28):
		286	hpd.hpd = RADEON_HPD_6;
		287	break;
		288	default:
		289	hpd.hpd = RADEON_HPD_NONE;
		290	break;
		291	}
		292	} else
		293	hpd.hpd = RADEON_HPD_NONE;
		294	return hpd;
		295	}
		296
1117	serge	297	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		298	uint32_t supported_device,
		299	int *connector_type,
1179	serge	300	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	301	uint16_t *line_mux,
		302	struct radeon_hpd *hpd)
1117	serge	303	{
		304
		305	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		306	if ((dev->pdev->device == 0x791e) &&
		307	(dev->pdev->subsystem_vendor == 0x1043) &&
		308	(dev->pdev->subsystem_device == 0x826d)) {
		309	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		310	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		311	*connector_type = DRM_MODE_CONNECTOR_DVID;
		312	}
		313
1428	serge	314	/* Asrock RS600 board lists the DVI port as HDMI */
		315	if ((dev->pdev->device == 0x7941) &&
		316	(dev->pdev->subsystem_vendor == 0x1849) &&
		317	(dev->pdev->subsystem_device == 0x7941)) {
		318	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		319	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		320	*connector_type = DRM_MODE_CONNECTOR_DVID;
		321	}
		322
1963	serge	323	/* MSI K9A2GM V2/V3 board has no HDMI or DVI */
		324	if ((dev->pdev->device == 0x796e) &&
		325	(dev->pdev->subsystem_vendor == 0x1462) &&
		326	(dev->pdev->subsystem_device == 0x7302)) {
		327	if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) \|\|
		328	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		329	return false;
		330	}
		331
1117	serge	332	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		333	if ((dev->pdev->device == 0x7941) &&
		334	(dev->pdev->subsystem_vendor == 0x147b) &&
		335	(dev->pdev->subsystem_device == 0x2412)) {
		336	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		337	return false;
		338	}
		339
		340	/* Falcon NW laptop lists vga ddc line for LVDS */
		341	if ((dev->pdev->device == 0x5653) &&
		342	(dev->pdev->subsystem_vendor == 0x1462) &&
		343	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	344	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	345	i2c_bus->valid = false;
1179	serge	346	*line_mux = 53;
		347	}
1117	serge	348	}
		349
1321	serge	350	/* HIS X1300 is DVI+VGA, not DVI+DVI */
		351	if ((dev->pdev->device == 0x7146) &&
		352	(dev->pdev->subsystem_vendor == 0x17af) &&
		353	(dev->pdev->subsystem_device == 0x2058)) {
		354	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		355	return false;
		356	}
		357
		358	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
		359	if ((dev->pdev->device == 0x7142) &&
		360	(dev->pdev->subsystem_vendor == 0x1458) &&
		361	(dev->pdev->subsystem_device == 0x2134)) {
		362	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		363	return false;
		364	}
		365
		366
1117	serge	367	/* Funky macbooks */
		368	if ((dev->pdev->device == 0x71C5) &&
		369	(dev->pdev->subsystem_vendor == 0x106b) &&
		370	(dev->pdev->subsystem_device == 0x0080)) {
		371	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		372	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		373	return false;
1963	serge	374	if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
		375	*line_mux = 0x90;
1117	serge	376	}
		377
1963	serge	378	/* mac rv630, rv730, others */
		379	if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
		380	(*connector_type == DRM_MODE_CONNECTOR_DVII)) {
		381	*connector_type = DRM_MODE_CONNECTOR_9PinDIN;
		382	*line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
		383	}
		384
1117	serge	385	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		386	if ((dev->pdev->device == 0x9598) &&
		387	(dev->pdev->subsystem_vendor == 0x1043) &&
		388	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	389	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		390	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	391	}
		392	}
		393
1963	serge	394	/* ASUS HD 3600 board lists the DVI port as HDMI */
		395	if ((dev->pdev->device == 0x9598) &&
		396	(dev->pdev->subsystem_vendor == 0x1043) &&
		397	(dev->pdev->subsystem_device == 0x01e4)) {
		398	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		399	*connector_type = DRM_MODE_CONNECTOR_DVII;
		400	}
		401	}
		402
1179	serge	403	/* ASUS HD 3450 board lists the DVI port as HDMI */
		404	if ((dev->pdev->device == 0x95C5) &&
		405	(dev->pdev->subsystem_vendor == 0x1043) &&
		406	(dev->pdev->subsystem_device == 0x01e2)) {
		407	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		408	*connector_type = DRM_MODE_CONNECTOR_DVII;
		409	}
		410	}
		411
		412	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		413	* HDMI + VGA reporting as HDMI
		414	*/
		415	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		416	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		417	*connector_type = DRM_MODE_CONNECTOR_VGA;
		418	*line_mux = 0;
		419	}
		420	}
		421
1963	serge	422	/* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
		423	* on the laptop and a DVI port on the docking station and
		424	* both share the same encoder, hpd pin, and ddc line.
		425	* So while the bios table is technically correct,
		426	* we drop the DVI port here since xrandr has no concept of
		427	* encoders and will try and drive both connectors
		428	* with different crtcs which isn't possible on the hardware
		429	* side and leaves no crtcs for LVDS or VGA.
		430	*/
		431	if (((dev->pdev->device == 0x95c4) \|\| (dev->pdev->device == 0x9591)) &&
1321	serge	432	(dev->pdev->subsystem_vendor == 0x1025) &&
		433	(dev->pdev->subsystem_device == 0x013c)) {
		434	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
1963	serge	435	(supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
		436	/* actually it's a DVI-D port not DVI-I */
1321	serge	437	*connector_type = DRM_MODE_CONNECTOR_DVID;
1963	serge	438	return false;
		439	}
1321	serge	440	}
		441
1412	serge	442	/* XFX Pine Group device rv730 reports no VGA DDC lines
		443	* even though they are wired up to record 0x93
		444	*/
		445	if ((dev->pdev->device == 0x9498) &&
		446	(dev->pdev->subsystem_vendor == 0x1682) &&
2997	Serge	447	(dev->pdev->subsystem_device == 0x2452) &&
		448	(i2c_bus->valid == false) &&
		449	!(supported_device & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))) {
1412	serge	450	struct radeon_device *rdev = dev->dev_private;
		451	*i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
		452	}
2997	Serge	453
		454	/* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
		455	if (((dev->pdev->device == 0x9802) \|\| (dev->pdev->device == 0x9806)) &&
		456	(dev->pdev->subsystem_vendor == 0x1734) &&
		457	(dev->pdev->subsystem_device == 0x11bd)) {
		458	if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
		459	*connector_type = DRM_MODE_CONNECTOR_DVII;
		460	*line_mux = 0x3103;
		461	} else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
		462	*connector_type = DRM_MODE_CONNECTOR_DVII;
		463	}
		464	}
		465
		466
1117	serge	467	return true;
		468	}
		469
		470	const int supported_devices_connector_convert[] = {
		471	DRM_MODE_CONNECTOR_Unknown,
		472	DRM_MODE_CONNECTOR_VGA,
		473	DRM_MODE_CONNECTOR_DVII,
		474	DRM_MODE_CONNECTOR_DVID,
		475	DRM_MODE_CONNECTOR_DVIA,
		476	DRM_MODE_CONNECTOR_SVIDEO,
		477	DRM_MODE_CONNECTOR_Composite,
		478	DRM_MODE_CONNECTOR_LVDS,
		479	DRM_MODE_CONNECTOR_Unknown,
		480	DRM_MODE_CONNECTOR_Unknown,
		481	DRM_MODE_CONNECTOR_HDMIA,
		482	DRM_MODE_CONNECTOR_HDMIB,
		483	DRM_MODE_CONNECTOR_Unknown,
		484	DRM_MODE_CONNECTOR_Unknown,
		485	DRM_MODE_CONNECTOR_9PinDIN,
		486	DRM_MODE_CONNECTOR_DisplayPort
		487	};
		488
1268	serge	489	const uint16_t supported_devices_connector_object_id_convert[] = {
		490	CONNECTOR_OBJECT_ID_NONE,
		491	CONNECTOR_OBJECT_ID_VGA,
		492	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
		493	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
		494	CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
		495	CONNECTOR_OBJECT_ID_COMPOSITE,
		496	CONNECTOR_OBJECT_ID_SVIDEO,
		497	CONNECTOR_OBJECT_ID_LVDS,
		498	CONNECTOR_OBJECT_ID_9PIN_DIN,
		499	CONNECTOR_OBJECT_ID_9PIN_DIN,
		500	CONNECTOR_OBJECT_ID_DISPLAYPORT,
		501	CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
		502	CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
		503	CONNECTOR_OBJECT_ID_SVIDEO
		504	};
		505
1117	serge	506	const int object_connector_convert[] = {
		507	DRM_MODE_CONNECTOR_Unknown,
		508	DRM_MODE_CONNECTOR_DVII,
		509	DRM_MODE_CONNECTOR_DVII,
		510	DRM_MODE_CONNECTOR_DVID,
		511	DRM_MODE_CONNECTOR_DVID,
		512	DRM_MODE_CONNECTOR_VGA,
		513	DRM_MODE_CONNECTOR_Composite,
		514	DRM_MODE_CONNECTOR_SVIDEO,
		515	DRM_MODE_CONNECTOR_Unknown,
1179	serge	516	DRM_MODE_CONNECTOR_Unknown,
1117	serge	517	DRM_MODE_CONNECTOR_9PinDIN,
		518	DRM_MODE_CONNECTOR_Unknown,
		519	DRM_MODE_CONNECTOR_HDMIA,
		520	DRM_MODE_CONNECTOR_HDMIB,
		521	DRM_MODE_CONNECTOR_LVDS,
		522	DRM_MODE_CONNECTOR_9PinDIN,
		523	DRM_MODE_CONNECTOR_Unknown,
		524	DRM_MODE_CONNECTOR_Unknown,
		525	DRM_MODE_CONNECTOR_Unknown,
1404	serge	526	DRM_MODE_CONNECTOR_DisplayPort,
		527	DRM_MODE_CONNECTOR_eDP,
		528	DRM_MODE_CONNECTOR_Unknown
1117	serge	529	};
		530
		531	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		532	{
		533	struct radeon_device *rdev = dev->dev_private;
		534	struct radeon_mode_info *mode_info = &rdev->mode_info;
		535	struct atom_context *ctx = mode_info->atom_context;
		536	int index = GetIndexIntoMasterTable(DATA, Object_Header);
1321	serge	537	u16 size, data_offset;
		538	u8 frev, crev;
1117	serge	539	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
1963	serge	540	ATOM_ENCODER_OBJECT_TABLE *enc_obj;
		541	ATOM_OBJECT_TABLE *router_obj;
1117	serge	542	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		543	ATOM_OBJECT_HEADER *obj_header;
1963	serge	544	int i, j, k, path_size, device_support;
1117	serge	545	int connector_type;
1321	serge	546	u16 igp_lane_info, conn_id, connector_object_id;
1117	serge	547	struct radeon_i2c_bus_rec ddc_bus;
1963	serge	548	struct radeon_router router;
1321	serge	549	struct radeon_gpio_rec gpio;
		550	struct radeon_hpd hpd;
1117	serge	551
1963	serge	552	if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
1117	serge	553	return false;
		554
		555	if (crev < 2)
		556	return false;
		557
		558	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		559	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		560	(ctx->bios + data_offset +
		561	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		562	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		563	(ctx->bios + data_offset +
		564	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
1963	serge	565	enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
		566	(ctx->bios + data_offset +
		567	le16_to_cpu(obj_header->usEncoderObjectTableOffset));
		568	router_obj = (ATOM_OBJECT_TABLE *)
		569	(ctx->bios + data_offset +
		570	le16_to_cpu(obj_header->usRouterObjectTableOffset));
1117	serge	571	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		572
		573	path_size = 0;
		574	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		575	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		576	ATOM_DISPLAY_OBJECT_PATH *path;
		577	addr += path_size;
		578	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		579	path_size += le16_to_cpu(path->usSize);
1963	serge	580
1117	serge	581	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		582	uint8_t con_obj_id, con_obj_num, con_obj_type;
		583
		584	con_obj_id =
		585	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		586	>> OBJECT_ID_SHIFT;
		587	con_obj_num =
		588	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		589	>> ENUM_ID_SHIFT;
		590	con_obj_type =
		591	(le16_to_cpu(path->usConnObjectId) &
		592	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		593
1221	serge	594	/* TODO CV support */
		595	if (le16_to_cpu(path->usDeviceTag) ==
		596	ATOM_DEVICE_CV_SUPPORT)
1117	serge	597	continue;
		598
1268	serge	599	/* IGP chips */
		600	if ((rdev->flags & RADEON_IS_IGP) &&
1117	serge	601	(con_obj_id ==
		602	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		603	uint16_t igp_offset = 0;
		604	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		605
		606	index =
		607	GetIndexIntoMasterTable(DATA,
		608	IntegratedSystemInfo);
		609
1963	serge	610	if (atom_parse_data_header(ctx, index, &size, &frev,
		611	&crev, &igp_offset)) {
1117	serge	612
		613	if (crev >= 2) {
		614	igp_obj =
		615	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		616	*) (ctx->bios + igp_offset);
		617
		618	if (igp_obj) {
		619	uint32_t slot_config, ct;
		620
		621	if (con_obj_num == 1)
		622	slot_config =
		623	igp_obj->
		624	ulDDISlot1Config;
		625	else
		626	slot_config =
		627	igp_obj->
		628	ulDDISlot2Config;
		629
		630	ct = (slot_config >> 16) & 0xff;
		631	connector_type =
		632	object_connector_convert
		633	[ct];
1268	serge	634	connector_object_id = ct;
1117	serge	635	igp_lane_info =
		636	slot_config & 0xffff;
		637	} else
		638	continue;
		639	} else
		640	continue;
		641	} else {
		642	igp_lane_info = 0;
		643	connector_type =
		644	object_connector_convert[con_obj_id];
1268	serge	645	connector_object_id = con_obj_id;
1117	serge	646	}
1963	serge	647	} else {
		648	igp_lane_info = 0;
		649	connector_type =
		650	object_connector_convert[con_obj_id];
		651	connector_object_id = con_obj_id;
		652	}
1117	serge	653
		654	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		655	continue;
		656
1963	serge	657	router.ddc_valid = false;
		658	router.cd_valid = false;
		659	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
		660	uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
1117	serge	661
1963	serge	662	grph_obj_id =
1117	serge	663	(le16_to_cpu(path->usGraphicObjIds[j]) &
		664	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1963	serge	665	grph_obj_num =
1117	serge	666	(le16_to_cpu(path->usGraphicObjIds[j]) &
		667	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1963	serge	668	grph_obj_type =
1117	serge	669	(le16_to_cpu(path->usGraphicObjIds[j]) &
		670	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		671
1963	serge	672	if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		673	for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
		674	u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
		675	if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
		676	ATOM_COMMON_RECORD_HEADER record = (ATOM_COMMON_RECORD_HEADER )
		677	(ctx->bios + data_offset +
		678	le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
		679	ATOM_ENCODER_CAP_RECORD *cap_record;
		680	u16 caps = 0;
1117	serge	681
1963	serge	682	while (record->ucRecordSize > 0 &&
		683	record->ucRecordType > 0 &&
		684	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
		685	switch (record->ucRecordType) {
		686	case ATOM_ENCODER_CAP_RECORD_TYPE:
		687	cap_record =(ATOM_ENCODER_CAP_RECORD *)
		688	record;
		689	caps = le16_to_cpu(cap_record->usEncoderCap);
		690	break;
		691	}
		692	record = (ATOM_COMMON_RECORD_HEADER *)
		693	((char *)record + record->ucRecordSize);
		694	}
1123	serge	695	radeon_add_atom_encoder(dev,
1963	serge	696	encoder_obj,
1123	serge	697	le16_to_cpu
		698	(path->
1963	serge	699	usDeviceTag),
		700	caps);
		701	}
		702	}
		703	} else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
		704	for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
		705	u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
		706	if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
		707	ATOM_COMMON_RECORD_HEADER record = (ATOM_COMMON_RECORD_HEADER )
		708	(ctx->bios + data_offset +
		709	le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
		710	ATOM_I2C_RECORD *i2c_record;
		711	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
		712	ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
		713	ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
		714	ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
		715	(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
		716	(ctx->bios + data_offset +
		717	le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
		718	int enum_id;
1117	serge	719
1963	serge	720	router.router_id = router_obj_id;
		721	for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
		722	enum_id++) {
		723	if (le16_to_cpu(path->usConnObjectId) ==
		724	le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
		725	break;
		726	}
		727
		728	while (record->ucRecordSize > 0 &&
		729	record->ucRecordType > 0 &&
		730	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
		731	switch (record->ucRecordType) {
		732	case ATOM_I2C_RECORD_TYPE:
		733	i2c_record =
		734	(ATOM_I2C_RECORD *)
		735	record;
		736	i2c_config =
		737	(ATOM_I2C_ID_CONFIG_ACCESS *)
		738	&i2c_record->sucI2cId;
		739	router.i2c_info =
		740	radeon_lookup_i2c_gpio(rdev,
		741	i2c_config->
		742	ucAccess);
		743	router.i2c_addr = i2c_record->ucI2CAddr >> 1;
		744	break;
		745	case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
		746	ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
		747	record;
		748	router.ddc_valid = true;
		749	router.ddc_mux_type = ddc_path->ucMuxType;
		750	router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
		751	router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
		752	break;
		753	case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
		754	cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
		755	record;
		756	router.cd_valid = true;
		757	router.cd_mux_type = cd_path->ucMuxType;
		758	router.cd_mux_control_pin = cd_path->ucMuxControlPin;
		759	router.cd_mux_state = cd_path->ucMuxState[enum_id];
		760	break;
		761	}
		762	record = (ATOM_COMMON_RECORD_HEADER *)
		763	((char *)record + record->ucRecordSize);
		764	}
		765	}
		766	}
1117	serge	767	}
		768	}
		769
1321	serge	770	/* look up gpio for ddc, hpd */
1963	serge	771	ddc_bus.valid = false;
		772	hpd.hpd = RADEON_HPD_NONE;
1117	serge	773	if ((le16_to_cpu(path->usDeviceTag) &
1321	serge	774	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) == 0) {
1117	serge	775	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		776	if (le16_to_cpu(path->usConnObjectId) ==
		777	le16_to_cpu(con_obj->asObjects[j].
		778	usObjectID)) {
		779	ATOM_COMMON_RECORD_HEADER
		780	*record =
		781	(ATOM_COMMON_RECORD_HEADER
		782	*)
		783	(ctx->bios + data_offset +
		784	le16_to_cpu(con_obj->
		785	asObjects[j].
		786	usRecordOffset));
		787	ATOM_I2C_RECORD *i2c_record;
1321	serge	788	ATOM_HPD_INT_RECORD *hpd_record;
		789	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
1117	serge	790
1963	serge	791	while (record->ucRecordSize > 0 &&
		792	record->ucRecordType > 0 &&
		793	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
1321	serge	794	switch (record->ucRecordType) {
1117	serge	795	case ATOM_I2C_RECORD_TYPE:
		796	i2c_record =
1321	serge	797	(ATOM_I2C_RECORD *)
		798	record;
		799	i2c_config =
		800	(ATOM_I2C_ID_CONFIG_ACCESS *)
		801	&i2c_record->sucI2cId;
		802	ddc_bus = radeon_lookup_i2c_gpio(rdev,
		803	i2c_config->
		804	ucAccess);
1117	serge	805	break;
1321	serge	806	case ATOM_HPD_INT_RECORD_TYPE:
		807	hpd_record =
		808	(ATOM_HPD_INT_RECORD *)
		809	record;
		810	gpio = radeon_lookup_gpio(rdev,
		811	hpd_record->ucHPDIntGPIOID);
		812	hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
		813	hpd.plugged_state = hpd_record->ucPlugged_PinState;
		814	break;
1117	serge	815	}
		816	record =
		817	(ATOM_COMMON_RECORD_HEADER
		818	) ((char )record
		819	+
		820	record->
		821	ucRecordSize);
		822	}
		823	break;
		824	}
		825	}
1321	serge	826	}
1117	serge	827
1430	serge	828	/* needed for aux chan transactions */
1963	serge	829	ddc_bus.hpd = hpd.hpd;
1430	serge	830
1179	serge	831	conn_id = le16_to_cpu(path->usConnObjectId);
		832
		833	if (!radeon_atom_apply_quirks
		834	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
1321	serge	835	&ddc_bus, &conn_id, &hpd))
1179	serge	836	continue;
		837
1123	serge	838	radeon_add_atom_connector(dev,
1179	serge	839	conn_id,
1123	serge	840	le16_to_cpu(path->
		841	usDeviceTag),
		842	connector_type, &ddc_bus,
1963	serge	843	igp_lane_info,
1321	serge	844	connector_object_id,
1963	serge	845	&hpd,
		846	&router);
1117	serge	847
		848	}
		849	}
		850
1123	serge	851	radeon_link_encoder_connector(dev);
1117	serge	852
		853	return true;
		854	}
		855
1268	serge	856	static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
		857	int connector_type,
		858	uint16_t devices)
		859	{
		860	struct radeon_device *rdev = dev->dev_private;
		861
		862	if (rdev->flags & RADEON_IS_IGP) {
		863	return supported_devices_connector_object_id_convert
		864	[connector_type];
		865	} else if (((connector_type == DRM_MODE_CONNECTOR_DVII) \|\|
		866	(connector_type == DRM_MODE_CONNECTOR_DVID)) &&
		867	(devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		868	struct radeon_mode_info *mode_info = &rdev->mode_info;
		869	struct atom_context *ctx = mode_info->atom_context;
		870	int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
		871	uint16_t size, data_offset;
		872	uint8_t frev, crev;
		873	ATOM_XTMDS_INFO *xtmds;
		874
1963	serge	875	if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
1268	serge	876	xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
		877
		878	if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
		879	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		880	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		881	else
		882	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		883	} else {
		884	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		885	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		886	else
		887	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		888	}
1963	serge	889	} else
		890	return supported_devices_connector_object_id_convert
		891	[connector_type];
1268	serge	892	} else {
		893	return supported_devices_connector_object_id_convert
		894	[connector_type];
		895	}
		896	}
		897
1117	serge	898	struct bios_connector {
		899	bool valid;
1179	serge	900	uint16_t line_mux;
1117	serge	901	uint16_t devices;
		902	int connector_type;
		903	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	904	struct radeon_hpd hpd;
1117	serge	905	};
		906
		907	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		908	drm_device
		909	*dev)
		910	{
		911	struct radeon_device *rdev = dev->dev_private;
		912	struct radeon_mode_info *mode_info = &rdev->mode_info;
		913	struct atom_context *ctx = mode_info->atom_context;
		914	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		915	uint16_t size, data_offset;
		916	uint8_t frev, crev;
		917	uint16_t device_support;
		918	uint8_t dac;
		919	union atom_supported_devices *supported_devices;
1321	serge	920	int i, j, max_device;
1963	serge	921	struct bios_connector *bios_connectors;
		922	size_t bc_size = sizeof(bios_connectors) ATOM_MAX_SUPPORTED_DEVICE;
		923	struct radeon_router router;
1117	serge	924
1963	serge	925	router.ddc_valid = false;
		926	router.cd_valid = false;
1128	serge	927
1963	serge	928	bios_connectors = kzalloc(bc_size, GFP_KERNEL);
		929	if (!bios_connectors)
		930	return false;
		931
		932	if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
		933	&data_offset)) {
		934	kfree(bios_connectors);
		935	return false;
		936	}
		937
1117	serge	938	supported_devices =
		939	(union atom_supported_devices *)(ctx->bios + data_offset);
		940
		941	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		942
1321	serge	943	if (frev > 1)
		944	max_device = ATOM_MAX_SUPPORTED_DEVICE;
		945	else
		946	max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
		947
		948	for (i = 0; i < max_device; i++) {
1117	serge	949	ATOM_CONNECTOR_INFO_I2C ci =
		950	supported_devices->info.asConnInfo[i];
		951
		952	bios_connectors[i].valid = false;
		953
		954	if (!(device_support & (1 << i))) {
		955	continue;
		956	}
		957
		958	if (i == ATOM_DEVICE_CV_INDEX) {
1963	serge	959	DRM_DEBUG_KMS("Skipping Component Video\n");
1117	serge	960	continue;
		961	}
		962
		963	bios_connectors[i].connector_type =
		964	supported_devices_connector_convert[ci.sucConnectorInfo.
		965	sbfAccess.
		966	bfConnectorType];
		967
		968	if (bios_connectors[i].connector_type ==
		969	DRM_MODE_CONNECTOR_Unknown)
		970	continue;
		971
		972	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		973
		974	bios_connectors[i].line_mux =
1321	serge	975	ci.sucI2cId.ucAccess;
1117	serge	976
		977	/* give tv unique connector ids */
		978	if (i == ATOM_DEVICE_TV1_INDEX) {
		979	bios_connectors[i].ddc_bus.valid = false;
		980	bios_connectors[i].line_mux = 50;
		981	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		982	bios_connectors[i].ddc_bus.valid = false;
		983	bios_connectors[i].line_mux = 51;
		984	} else if (i == ATOM_DEVICE_CV_INDEX) {
		985	bios_connectors[i].ddc_bus.valid = false;
		986	bios_connectors[i].line_mux = 52;
		987	} else
		988	bios_connectors[i].ddc_bus =
1321	serge	989	radeon_lookup_i2c_gpio(rdev,
1117	serge	990	bios_connectors[i].line_mux);
		991
1321	serge	992	if ((crev > 1) && (frev > 1)) {
		993	u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
		994	switch (isb) {
		995	case 0x4:
		996	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		997	break;
		998	case 0xa:
		999	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		1000	break;
		1001	default:
		1002	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		1003	break;
		1004	}
		1005	} else {
		1006	if (i == ATOM_DEVICE_DFP1_INDEX)
		1007	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		1008	else if (i == ATOM_DEVICE_DFP2_INDEX)
		1009	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		1010	else
		1011	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		1012	}
		1013
1117	serge	1014	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		1015	* shared with a DVI port, we'll pick up the DVI connector when we
		1016	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		1017	*/
		1018	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		1019	bios_connectors[i].connector_type =
		1020	DRM_MODE_CONNECTOR_VGA;
		1021
		1022	if (!radeon_atom_apply_quirks
		1023	(dev, (1 << i), &bios_connectors[i].connector_type,
1321	serge	1024	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
		1025	&bios_connectors[i].hpd))
1117	serge	1026	continue;
		1027
		1028	bios_connectors[i].valid = true;
		1029	bios_connectors[i].devices = (1 << i);
		1030
1123	serge	1031	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		1032	radeon_add_atom_encoder(dev,
1963	serge	1033	radeon_get_encoder_enum(dev,
1123	serge	1034	(1 << i),
		1035	dac),
1963	serge	1036	(1 << i),
		1037	0);
1123	serge	1038	else
		1039	radeon_add_legacy_encoder(dev,
1963	serge	1040	radeon_get_encoder_enum(dev,
1404	serge	1041	(1 << i),
1123	serge	1042	dac),
		1043	(1 << i));
1117	serge	1044	}
		1045
		1046	/* combine shared connectors */
1321	serge	1047	for (i = 0; i < max_device; i++) {
1117	serge	1048	if (bios_connectors[i].valid) {
1321	serge	1049	for (j = 0; j < max_device; j++) {
1117	serge	1050	if (bios_connectors[j].valid && (i != j)) {
		1051	if (bios_connectors[i].line_mux ==
		1052	bios_connectors[j].line_mux) {
1404	serge	1053	/* make sure not to combine LVDS */
		1054	if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1055	bios_connectors[i].line_mux = 53;
		1056	bios_connectors[i].ddc_bus.valid = false;
		1057	continue;
		1058	}
		1059	if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1060	bios_connectors[j].line_mux = 53;
		1061	bios_connectors[j].ddc_bus.valid = false;
		1062	continue;
		1063	}
		1064	/* combine analog and digital for DVI-I */
		1065	if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		1066	(bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) \|\|
		1067	((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		1068	(bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
		1069	bios_connectors[i].devices \|=
		1070	bios_connectors[j].devices;
		1071	bios_connectors[i].connector_type =
1117	serge	1072	DRM_MODE_CONNECTOR_DVII;
1404	serge	1073	if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1321	serge	1074	bios_connectors[i].hpd =
		1075	bios_connectors[j].hpd;
1404	serge	1076	bios_connectors[j].valid = false;
1117	serge	1077	}
		1078	}
		1079	}
		1080	}
		1081	}
		1082	}
		1083
		1084	/* add the connectors */
1321	serge	1085	for (i = 0; i < max_device; i++) {
1268	serge	1086	if (bios_connectors[i].valid) {
		1087	uint16_t connector_object_id =
		1088	atombios_get_connector_object_id(dev,
		1089	bios_connectors[i].connector_type,
		1090	bios_connectors[i].devices);
1123	serge	1091	radeon_add_atom_connector(dev,
		1092	bios_connectors[i].line_mux,
		1093	bios_connectors[i].devices,
		1094	bios_connectors[i].
		1095	connector_type,
		1096	&bios_connectors[i].ddc_bus,
1963	serge	1097	0,
1321	serge	1098	connector_object_id,
1963	serge	1099	&bios_connectors[i].hpd,
		1100	&router);
1268	serge	1101	}
1123	serge	1102	}
1117	serge	1103
1123	serge	1104	radeon_link_encoder_connector(dev);
1128	serge	1105
1963	serge	1106	kfree(bios_connectors);
1117	serge	1107	return true;
		1108	}
		1109
		1110	union firmware_info {
		1111	ATOM_FIRMWARE_INFO info;
		1112	ATOM_FIRMWARE_INFO_V1_2 info_12;
		1113	ATOM_FIRMWARE_INFO_V1_3 info_13;
		1114	ATOM_FIRMWARE_INFO_V1_4 info_14;
1430	serge	1115	ATOM_FIRMWARE_INFO_V2_1 info_21;
1963	serge	1116	ATOM_FIRMWARE_INFO_V2_2 info_22;
1117	serge	1117	};
		1118
		1119	bool radeon_atom_get_clock_info(struct drm_device *dev)
		1120	{
		1121	struct radeon_device *rdev = dev->dev_private;
		1122	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1123	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		1124	union firmware_info *firmware_info;
		1125	uint8_t frev, crev;
		1126	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		1127	struct radeon_pll *p2pll = &rdev->clock.p2pll;
1430	serge	1128	struct radeon_pll *dcpll = &rdev->clock.dcpll;
1117	serge	1129	struct radeon_pll *spll = &rdev->clock.spll;
		1130	struct radeon_pll *mpll = &rdev->clock.mpll;
		1131	uint16_t data_offset;
		1132
1963	serge	1133	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1134	&frev, &crev, &data_offset)) {
1117	serge	1135	firmware_info =
		1136	(union firmware_info *)(mode_info->atom_context->bios +
		1137	data_offset);
		1138	/* pixel clocks */
		1139	p1pll->reference_freq =
		1140	le16_to_cpu(firmware_info->info.usReferenceClock);
		1141	p1pll->reference_div = 0;
		1142
1268	serge	1143	if (crev < 2)
1117	serge	1144	p1pll->pll_out_min =
		1145	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1268	serge	1146	else
		1147	p1pll->pll_out_min =
		1148	le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117	serge	1149	p1pll->pll_out_max =
		1150	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		1151
1963	serge	1152	if (crev >= 4) {
		1153	p1pll->lcd_pll_out_min =
		1154	le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
		1155	if (p1pll->lcd_pll_out_min == 0)
		1156	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		1157	p1pll->lcd_pll_out_max =
		1158	le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
		1159	if (p1pll->lcd_pll_out_max == 0)
		1160	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
		1161	} else {
		1162	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		1163	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
		1164	}
		1165
1117	serge	1166	if (p1pll->pll_out_min == 0) {
		1167	if (ASIC_IS_AVIVO(rdev))
		1168	p1pll->pll_out_min = 64800;
		1169	else
		1170	p1pll->pll_out_min = 20000;
		1171	}
		1172
		1173	p1pll->pll_in_min =
		1174	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		1175	p1pll->pll_in_max =
		1176	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		1177
		1178	p2pll = p1pll;
		1179
		1180	/* system clock */
1963	serge	1181	if (ASIC_IS_DCE4(rdev))
		1182	spll->reference_freq =
		1183	le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
		1184	else
1117	serge	1185	spll->reference_freq =
		1186	le16_to_cpu(firmware_info->info.usReferenceClock);
		1187	spll->reference_div = 0;
		1188
		1189	spll->pll_out_min =
		1190	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		1191	spll->pll_out_max =
		1192	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		1193
		1194	/* ??? */
		1195	if (spll->pll_out_min == 0) {
		1196	if (ASIC_IS_AVIVO(rdev))
		1197	spll->pll_out_min = 64800;
		1198	else
		1199	spll->pll_out_min = 20000;
		1200	}
		1201
		1202	spll->pll_in_min =
		1203	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		1204	spll->pll_in_max =
		1205	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		1206
		1207	/* memory clock */
1963	serge	1208	if (ASIC_IS_DCE4(rdev))
		1209	mpll->reference_freq =
		1210	le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
		1211	else
1117	serge	1212	mpll->reference_freq =
		1213	le16_to_cpu(firmware_info->info.usReferenceClock);
		1214	mpll->reference_div = 0;
		1215
		1216	mpll->pll_out_min =
		1217	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		1218	mpll->pll_out_max =
		1219	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		1220
		1221	/* ??? */
		1222	if (mpll->pll_out_min == 0) {
		1223	if (ASIC_IS_AVIVO(rdev))
		1224	mpll->pll_out_min = 64800;
		1225	else
		1226	mpll->pll_out_min = 20000;
		1227	}
		1228
		1229	mpll->pll_in_min =
		1230	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		1231	mpll->pll_in_max =
		1232	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		1233
		1234	rdev->clock.default_sclk =
		1235	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		1236	rdev->clock.default_mclk =
		1237	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		1238
1430	serge	1239	if (ASIC_IS_DCE4(rdev)) {
		1240	rdev->clock.default_dispclk =
		1241	le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1963	serge	1242	if (rdev->clock.default_dispclk == 0) {
		1243	if (ASIC_IS_DCE5(rdev))
		1244	rdev->clock.default_dispclk = 54000; /* 540 Mhz */
		1245	else
1430	serge	1246	rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1963	serge	1247	}
1430	serge	1248	rdev->clock.dp_extclk =
		1249	le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
		1250	}
		1251	dcpll = p1pll;
		1252
1963	serge	1253	rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
		1254	if (rdev->clock.max_pixel_clock == 0)
		1255	rdev->clock.max_pixel_clock = 40000;
		1256
2997	Serge	1257	/* not technically a clock, but... */
		1258	rdev->mode_info.firmware_flags =
		1259	le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
		1260
1117	serge	1261	return true;
		1262	}
1430	serge	1263
1117	serge	1264	return false;
		1265	}
		1266
1404	serge	1267	union igp_info {
		1268	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
		1269	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2997	Serge	1270	struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
		1271	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1404	serge	1272	};
		1273
		1274	bool radeon_atombios_sideport_present(struct radeon_device *rdev)
		1275	{
		1276	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1277	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		1278	union igp_info *igp_info;
		1279	u8 frev, crev;
		1280	u16 data_offset;
		1281
1963	serge	1282	/* sideport is AMD only */
		1283	if (rdev->family == CHIP_RS600)
		1284	return false;
1404	serge	1285
1963	serge	1286	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1287	&frev, &crev, &data_offset)) {
1404	serge	1288	igp_info = (union igp_info *)(mode_info->atom_context->bios +
		1289	data_offset);
		1290	switch (crev) {
		1291	case 1:
1963	serge	1292	if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1404	serge	1293	return true;
		1294	break;
		1295	case 2:
1963	serge	1296	if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1404	serge	1297	return true;
		1298	break;
		1299	default:
		1300	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		1301	break;
		1302	}
		1303	}
		1304	return false;
		1305	}
		1306
1179	serge	1307	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		1308	struct radeon_encoder_int_tmds *tmds)
1117	serge	1309	{
		1310	struct drm_device *dev = encoder->base.dev;
		1311	struct radeon_device *rdev = dev->dev_private;
		1312	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1313	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		1314	uint16_t data_offset;
		1315	struct _ATOM_TMDS_INFO *tmds_info;
		1316	uint8_t frev, crev;
		1317	uint16_t maxfreq;
		1318	int i;
		1319
1963	serge	1320	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1321	&frev, &crev, &data_offset)) {
1117	serge	1322	tmds_info =
		1323	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		1324	data_offset);
		1325
		1326	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		1327	for (i = 0; i < 4; i++) {
		1328	tmds->tmds_pll[i].freq =
		1329	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		1330	tmds->tmds_pll[i].value =
		1331	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		1332	tmds->tmds_pll[i].value \|=
		1333	(tmds_info->asMiscInfo[i].
		1334	ucPLL_VCO_Gain & 0x3f) << 6;
		1335	tmds->tmds_pll[i].value \|=
		1336	(tmds_info->asMiscInfo[i].
		1337	ucPLL_DutyCycle & 0xf) << 12;
		1338	tmds->tmds_pll[i].value \|=
		1339	(tmds_info->asMiscInfo[i].
		1340	ucPLL_VoltageSwing & 0xf) << 16;
		1341
1963	serge	1342	DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1117	serge	1343	tmds->tmds_pll[i].freq,
		1344	tmds->tmds_pll[i].value);
		1345
		1346	if (maxfreq == tmds->tmds_pll[i].freq) {
		1347	tmds->tmds_pll[i].freq = 0xffffffff;
		1348	break;
		1349	}
		1350	}
1179	serge	1351	return true;
1117	serge	1352	}
1179	serge	1353	return false;
1117	serge	1354	}
		1355
1963	serge	1356	bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
		1357	struct radeon_atom_ss *ss,
1268	serge	1358	int id)
		1359	{
		1360	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1361	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1963	serge	1362	uint16_t data_offset, size;
1268	serge	1363	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
		1364	uint8_t frev, crev;
1963	serge	1365	int i, num_indices;
1268	serge	1366
1963	serge	1367	memset(ss, 0, sizeof(struct radeon_atom_ss));
		1368	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1369	&frev, &crev, &data_offset)) {
1268	serge	1370	ss_info =
		1371	(struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
		1372
1963	serge	1373	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1374	sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1268	serge	1375
1963	serge	1376	for (i = 0; i < num_indices; i++) {
1321	serge	1377	if (ss_info->asSS_Info[i].ucSS_Id == id) {
		1378	ss->percentage =
		1379	le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
		1380	ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
		1381	ss->step = ss_info->asSS_Info[i].ucSS_Step;
		1382	ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
		1383	ss->range = ss_info->asSS_Info[i].ucSS_Range;
		1384	ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1963	serge	1385	return true;
		1386	}
		1387	}
1268	serge	1388	}
1963	serge	1389	return false;
		1390	}
		1391
		1392	static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
		1393	struct radeon_atom_ss *ss,
		1394	int id)
		1395	{
		1396	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1397	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		1398	u16 data_offset, size;
2997	Serge	1399	union igp_info *igp_info;
1963	serge	1400	u8 frev, crev;
		1401	u16 percentage = 0, rate = 0;
		1402
		1403	/* get any igp specific overrides */
		1404	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1405	&frev, &crev, &data_offset)) {
2997	Serge	1406	igp_info = (union igp_info *)
1963	serge	1407	(mode_info->atom_context->bios + data_offset);
2997	Serge	1408	switch (crev) {
		1409	case 6:
		1410	switch (id) {
		1411	case ASIC_INTERNAL_SS_ON_TMDS:
		1412	percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
		1413	rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
		1414	break;
		1415	case ASIC_INTERNAL_SS_ON_HDMI:
		1416	percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
		1417	rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
		1418	break;
		1419	case ASIC_INTERNAL_SS_ON_LVDS:
		1420	percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
		1421	rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
		1422	break;
		1423	}
		1424	break;
		1425	case 7:
1963	serge	1426	switch (id) {
		1427	case ASIC_INTERNAL_SS_ON_TMDS:
2997	Serge	1428	percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
		1429	rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1963	serge	1430	break;
		1431	case ASIC_INTERNAL_SS_ON_HDMI:
2997	Serge	1432	percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
		1433	rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1963	serge	1434	break;
		1435	case ASIC_INTERNAL_SS_ON_LVDS:
2997	Serge	1436	percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
		1437	rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
		1438	break;
		1439	}
1963	serge	1440	break;
2997	Serge	1441	default:
		1442	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		1443	break;
1321	serge	1444	}
1963	serge	1445	if (percentage)
		1446	ss->percentage = percentage;
		1447	if (rate)
		1448	ss->rate = rate;
1321	serge	1449	}
1268	serge	1450	}
		1451
1963	serge	1452	union asic_ss_info {
		1453	struct _ATOM_ASIC_INTERNAL_SS_INFO info;
		1454	struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
		1455	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
		1456	};
		1457
		1458	bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
		1459	struct radeon_atom_ss *ss,
		1460	int id, u32 clock)
1430	serge	1461	{
1963	serge	1462	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1463	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
		1464	uint16_t data_offset, size;
		1465	union asic_ss_info *ss_info;
		1466	uint8_t frev, crev;
		1467	int i, num_indices;
1430	serge	1468
1963	serge	1469	memset(ss, 0, sizeof(struct radeon_atom_ss));
		1470	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1471	&frev, &crev, &data_offset)) {
		1472
		1473	ss_info =
		1474	(union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
		1475
		1476	switch (frev) {
		1477	case 1:
		1478	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1479	sizeof(ATOM_ASIC_SS_ASSIGNMENT);
		1480
		1481	for (i = 0; i < num_indices; i++) {
		1482	if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
		1483	(clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
		1484	ss->percentage =
		1485	le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
		1486	ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
		1487	ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
		1488	return true;
		1489	}
		1490	}
		1491	break;
		1492	case 2:
		1493	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1494	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
		1495	for (i = 0; i < num_indices; i++) {
		1496	if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
		1497	(clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
		1498	ss->percentage =
		1499	le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
		1500	ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
		1501	ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
		1502	return true;
		1503	}
1430	serge	1504	}
1963	serge	1505	break;
		1506	case 3:
		1507	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1508	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
		1509	for (i = 0; i < num_indices; i++) {
		1510	if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
		1511	(clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
		1512	ss->percentage =
		1513	le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
		1514	ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
		1515	ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
		1516	if (rdev->flags & RADEON_IS_IGP)
		1517	radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
		1518	return true;
		1519	}
		1520	}
		1521	break;
		1522	default:
		1523	DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
		1524	break;
		1525	}
1430	serge	1526
		1527	}
1963	serge	1528	return false;
1430	serge	1529	}
		1530
1117	serge	1531	union lvds_info {
		1532	struct _ATOM_LVDS_INFO info;
		1533	struct _ATOM_LVDS_INFO_V12 info_12;
		1534	};
		1535
		1536	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		1537	radeon_encoder
		1538	*encoder)
		1539	{
		1540	struct drm_device *dev = encoder->base.dev;
		1541	struct radeon_device *rdev = dev->dev_private;
		1542	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1543	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1321	serge	1544	uint16_t data_offset, misc;
1117	serge	1545	union lvds_info *lvds_info;
		1546	uint8_t frev, crev;
		1547	struct radeon_encoder_atom_dig *lvds = NULL;
1963	serge	1548	int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1117	serge	1549
1963	serge	1550	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1551	&frev, &crev, &data_offset)) {
1117	serge	1552	lvds_info =
		1553	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		1554	lvds =
		1555	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1556
		1557	if (!lvds)
		1558	return NULL;
		1559
1268	serge	1560	lvds->native_mode.clock =
1117	serge	1561	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1268	serge	1562	lvds->native_mode.hdisplay =
1117	serge	1563	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1268	serge	1564	lvds->native_mode.vdisplay =
1117	serge	1565	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1268	serge	1566	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1117	serge	1567	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1268	serge	1568	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1117	serge	1569	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1268	serge	1570	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1117	serge	1571	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1268	serge	1572	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1117	serge	1573	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1268	serge	1574	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1963	serge	1575	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1268	serge	1576	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1117	serge	1577	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1578	lvds->panel_pwr_delay =
		1579	le16_to_cpu(lvds_info->info.usOffDelayInMs);
1963	serge	1580	lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1321	serge	1581
		1582	misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
		1583	if (misc & ATOM_VSYNC_POLARITY)
		1584	lvds->native_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		1585	if (misc & ATOM_HSYNC_POLARITY)
		1586	lvds->native_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		1587	if (misc & ATOM_COMPOSITESYNC)
		1588	lvds->native_mode.flags \|= DRM_MODE_FLAG_CSYNC;
		1589	if (misc & ATOM_INTERLACE)
		1590	lvds->native_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		1591	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1592	lvds->native_mode.flags \|= DRM_MODE_FLAG_DBLSCAN;
		1593
1963	serge	1594	lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
		1595	lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
		1596
1268	serge	1597	/* set crtc values */
		1598	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1117	serge	1599
1963	serge	1600	lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1268	serge	1601
1963	serge	1602	encoder->native_mode = lvds->native_mode;
		1603
		1604	if (encoder_enum == 2)
		1605	lvds->linkb = true;
		1606	else
		1607	lvds->linkb = false;
		1608
		1609	/* parse the lcd record table */
		1610	if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
		1611	ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
		1612	ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
		1613	bool bad_record = false;
		1614	u8 *record;
		1615
		1616	if ((frev == 1) && (crev < 2))
		1617	/* absolute */
		1618	record = (u8 *)(mode_info->atom_context->bios +
		1619	le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1430	serge	1620	else
1963	serge	1621	/* relative */
		1622	record = (u8 *)(mode_info->atom_context->bios +
		1623	data_offset +
		1624	le16_to_cpu(lvds_info->info.usModePatchTableOffset));
		1625	while (*record != ATOM_RECORD_END_TYPE) {
		1626	switch (*record) {
		1627	case LCD_MODE_PATCH_RECORD_MODE_TYPE:
		1628	record += sizeof(ATOM_PATCH_RECORD_MODE);
		1629	break;
		1630	case LCD_RTS_RECORD_TYPE:
		1631	record += sizeof(ATOM_LCD_RTS_RECORD);
		1632	break;
		1633	case LCD_CAP_RECORD_TYPE:
		1634	record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
		1635	break;
		1636	case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
		1637	fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
		1638	if (fake_edid_record->ucFakeEDIDLength) {
		1639	struct edid *edid;
		1640	int edid_size =
		1641	max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
		1642	edid = kmalloc(edid_size, GFP_KERNEL);
		1643	if (edid) {
		1644	memcpy((u8 )edid, (u8 )&fake_edid_record->ucFakeEDIDString[0],
		1645	fake_edid_record->ucFakeEDIDLength);
		1646
		1647	if (drm_edid_is_valid(edid)) {
		1648	rdev->mode_info.bios_hardcoded_edid = edid;
		1649	rdev->mode_info.bios_hardcoded_edid_size = edid_size;
		1650	} else
		1651	kfree(edid);
		1652	}
		1653	}
		1654	record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
		1655	break;
		1656	case LCD_PANEL_RESOLUTION_RECORD_TYPE:
		1657	panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
		1658	lvds->native_mode.width_mm = panel_res_record->usHSize;
		1659	lvds->native_mode.height_mm = panel_res_record->usVSize;
		1660	record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
		1661	break;
		1662	default:
		1663	DRM_ERROR("Bad LCD record %d\n", *record);
		1664	bad_record = true;
		1665	break;
		1666	}
		1667	if (bad_record)
		1668	break;
		1669	}
1430	serge	1670	}
1117	serge	1671	}
		1672	return lvds;
		1673	}
		1674
		1675	struct radeon_encoder_primary_dac *
		1676	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		1677	{
		1678	struct drm_device *dev = encoder->base.dev;
		1679	struct radeon_device *rdev = dev->dev_private;
		1680	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1681	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1682	uint16_t data_offset;
		1683	struct _COMPASSIONATE_DATA *dac_info;
		1684	uint8_t frev, crev;
		1685	uint8_t bg, dac;
		1686	struct radeon_encoder_primary_dac *p_dac = NULL;
		1687
1963	serge	1688	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1689	&frev, &crev, &data_offset)) {
		1690	dac_info = (struct _COMPASSIONATE_DATA *)
		1691	(mode_info->atom_context->bios + data_offset);
1117	serge	1692
		1693	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		1694
		1695	if (!p_dac)
		1696	return NULL;
		1697
		1698	bg = dac_info->ucDAC1_BG_Adjustment;
		1699	dac = dac_info->ucDAC1_DAC_Adjustment;
		1700	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		1701
		1702	}
		1703	return p_dac;
		1704	}
		1705
1179	serge	1706	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1268	serge	1707	struct drm_display_mode *mode)
1179	serge	1708	{
		1709	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1710	ATOM_ANALOG_TV_INFO *tv_info;
		1711	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		1712	ATOM_DTD_FORMAT *dtd_timings;
		1713	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1714	u8 frev, crev;
1268	serge	1715	u16 data_offset, misc;
1179	serge	1716
1963	serge	1717	if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
		1718	&frev, &crev, &data_offset))
		1719	return false;
1179	serge	1720
		1721	switch (crev) {
		1722	case 1:
		1723	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1963	serge	1724	if (index >= MAX_SUPPORTED_TV_TIMING)
1179	serge	1725	return false;
		1726
1268	serge	1727	mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		1728	mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		1729	mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		1730	mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
		1731	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1179	serge	1732
1268	serge	1733	mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		1734	mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		1735	mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		1736	mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
		1737	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1179	serge	1738
1268	serge	1739	mode->flags = 0;
		1740	misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
		1741	if (misc & ATOM_VSYNC_POLARITY)
		1742	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1743	if (misc & ATOM_HSYNC_POLARITY)
		1744	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1745	if (misc & ATOM_COMPOSITESYNC)
		1746	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1747	if (misc & ATOM_INTERLACE)
		1748	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1749	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1750	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
1179	serge	1751
1268	serge	1752	mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1179	serge	1753
		1754	if (index == 1) {
		1755	/* PAL timings appear to have wrong values for totals */
1268	serge	1756	mode->crtc_htotal -= 1;
		1757	mode->crtc_vtotal -= 1;
1179	serge	1758	}
		1759	break;
		1760	case 2:
		1761	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1963	serge	1762	if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1179	serge	1763	return false;
		1764
		1765	dtd_timings = &tv_info_v1_2->aModeTimings[index];
1268	serge	1766	mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
		1767	le16_to_cpu(dtd_timings->usHBlanking_Time);
		1768	mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
		1769	mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
		1770	le16_to_cpu(dtd_timings->usHSyncOffset);
		1771	mode->crtc_hsync_end = mode->crtc_hsync_start +
		1772	le16_to_cpu(dtd_timings->usHSyncWidth);
1179	serge	1773
1268	serge	1774	mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
		1775	le16_to_cpu(dtd_timings->usVBlanking_Time);
		1776	mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
		1777	mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
		1778	le16_to_cpu(dtd_timings->usVSyncOffset);
		1779	mode->crtc_vsync_end = mode->crtc_vsync_start +
		1780	le16_to_cpu(dtd_timings->usVSyncWidth);
		1781
		1782	mode->flags = 0;
		1783	misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		1784	if (misc & ATOM_VSYNC_POLARITY)
		1785	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1786	if (misc & ATOM_HSYNC_POLARITY)
		1787	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1788	if (misc & ATOM_COMPOSITESYNC)
		1789	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1790	if (misc & ATOM_INTERLACE)
		1791	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1792	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1793	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
		1794
		1795	mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1179	serge	1796	break;
		1797	}
		1798	return true;
		1799	}
		1800
1404	serge	1801	enum radeon_tv_std
		1802	radeon_atombios_get_tv_info(struct radeon_device *rdev)
		1803	{
		1804	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1805	int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1806	uint16_t data_offset;
		1807	uint8_t frev, crev;
		1808	struct _ATOM_ANALOG_TV_INFO *tv_info;
		1809	enum radeon_tv_std tv_std = TV_STD_NTSC;
		1810
1963	serge	1811	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1812	&frev, &crev, &data_offset)) {
1404	serge	1813
1963	serge	1814	tv_info = (struct _ATOM_ANALOG_TV_INFO *)
		1815	(mode_info->atom_context->bios + data_offset);
1404	serge	1816
		1817	switch (tv_info->ucTV_BootUpDefaultStandard) {
		1818	case ATOM_TV_NTSC:
		1819	tv_std = TV_STD_NTSC;
1963	serge	1820	DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1404	serge	1821	break;
		1822	case ATOM_TV_NTSCJ:
		1823	tv_std = TV_STD_NTSC_J;
1963	serge	1824	DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1404	serge	1825	break;
		1826	case ATOM_TV_PAL:
		1827	tv_std = TV_STD_PAL;
1963	serge	1828	DRM_DEBUG_KMS("Default TV standard: PAL\n");
1404	serge	1829	break;
		1830	case ATOM_TV_PALM:
		1831	tv_std = TV_STD_PAL_M;
1963	serge	1832	DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1404	serge	1833	break;
		1834	case ATOM_TV_PALN:
		1835	tv_std = TV_STD_PAL_N;
1963	serge	1836	DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1404	serge	1837	break;
		1838	case ATOM_TV_PALCN:
		1839	tv_std = TV_STD_PAL_CN;
1963	serge	1840	DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1404	serge	1841	break;
		1842	case ATOM_TV_PAL60:
		1843	tv_std = TV_STD_PAL_60;
1963	serge	1844	DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1404	serge	1845	break;
		1846	case ATOM_TV_SECAM:
		1847	tv_std = TV_STD_SECAM;
1963	serge	1848	DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1404	serge	1849	break;
		1850	default:
		1851	tv_std = TV_STD_NTSC;
1963	serge	1852	DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1404	serge	1853	break;
		1854	}
1963	serge	1855	}
1404	serge	1856	return tv_std;
		1857	}
		1858
1117	serge	1859	struct radeon_encoder_tv_dac *
		1860	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		1861	{
		1862	struct drm_device *dev = encoder->base.dev;
		1863	struct radeon_device *rdev = dev->dev_private;
		1864	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1865	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1866	uint16_t data_offset;
		1867	struct _COMPASSIONATE_DATA *dac_info;
		1868	uint8_t frev, crev;
		1869	uint8_t bg, dac;
		1870	struct radeon_encoder_tv_dac *tv_dac = NULL;
		1871
1963	serge	1872	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1873	&frev, &crev, &data_offset)) {
1117	serge	1874
1963	serge	1875	dac_info = (struct _COMPASSIONATE_DATA *)
		1876	(mode_info->atom_context->bios + data_offset);
1117	serge	1877
		1878	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1879
		1880	if (!tv_dac)
		1881	return NULL;
		1882
		1883	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		1884	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		1885	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1886
		1887	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		1888	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		1889	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1890
		1891	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		1892	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		1893	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		1894
1404	serge	1895	tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1117	serge	1896	}
		1897	return tv_dac;
		1898	}
		1899
1963	serge	1900	static const char *thermal_controller_names[] = {
		1901	"NONE",
		1902	"lm63",
		1903	"adm1032",
		1904	"adm1030",
		1905	"max6649",
		1906	"lm64",
		1907	"f75375",
		1908	"asc7xxx",
		1909	};
		1910
		1911	static const char *pp_lib_thermal_controller_names[] = {
		1912	"NONE",
		1913	"lm63",
		1914	"adm1032",
		1915	"adm1030",
		1916	"max6649",
		1917	"lm64",
		1918	"f75375",
		1919	"RV6xx",
		1920	"RV770",
		1921	"adt7473",
		1922	"NONE",
		1923	"External GPIO",
		1924	"Evergreen",
		1925	"emc2103",
		1926	"Sumo",
		1927	"Northern Islands",
2997	Serge	1928	"Southern Islands",
		1929	"lm96163",
1963	serge	1930	};
		1931
1430	serge	1932	union power_info {
		1933	struct _ATOM_POWERPLAY_INFO info;
		1934	struct _ATOM_POWERPLAY_INFO_V2 info_2;
		1935	struct _ATOM_POWERPLAY_INFO_V3 info_3;
1963	serge	1936	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
		1937	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
		1938	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1430	serge	1939	};
		1940
1963	serge	1941	union pplib_clock_info {
		1942	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
		1943	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
		1944	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
		1945	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2997	Serge	1946	struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1963	serge	1947	};
		1948
		1949	union pplib_power_state {
		1950	struct _ATOM_PPLIB_STATE v1;
		1951	struct _ATOM_PPLIB_STATE_V2 v2;
		1952	};
		1953
		1954	static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
		1955	int state_index,
		1956	u32 misc, u32 misc2)
1117	serge	1957	{
1963	serge	1958	rdev->pm.power_state[state_index].misc = misc;
		1959	rdev->pm.power_state[state_index].misc2 = misc2;
		1960	/* order matters! */
		1961	if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
		1962	rdev->pm.power_state[state_index].type =
		1963	POWER_STATE_TYPE_POWERSAVE;
		1964	if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
		1965	rdev->pm.power_state[state_index].type =
		1966	POWER_STATE_TYPE_BATTERY;
		1967	if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
		1968	rdev->pm.power_state[state_index].type =
		1969	POWER_STATE_TYPE_BATTERY;
		1970	if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
		1971	rdev->pm.power_state[state_index].type =
		1972	POWER_STATE_TYPE_BALANCED;
		1973	if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
		1974	rdev->pm.power_state[state_index].type =
		1975	POWER_STATE_TYPE_PERFORMANCE;
		1976	rdev->pm.power_state[state_index].flags &=
		1977	~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		1978	}
		1979	if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
		1980	rdev->pm.power_state[state_index].type =
		1981	POWER_STATE_TYPE_BALANCED;
		1982	if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
		1983	rdev->pm.power_state[state_index].type =
		1984	POWER_STATE_TYPE_DEFAULT;
		1985	rdev->pm.default_power_state_index = state_index;
		1986	rdev->pm.power_state[state_index].default_clock_mode =
		1987	&rdev->pm.power_state[state_index].clock_info[0];
		1988	} else if (state_index == 0) {
		1989	rdev->pm.power_state[state_index].clock_info[0].flags \|=
		1990	RADEON_PM_MODE_NO_DISPLAY;
		1991	}
		1992	}
		1993
		1994	static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
		1995	{
1430	serge	1996	struct radeon_mode_info *mode_info = &rdev->mode_info;
1963	serge	1997	u32 misc, misc2 = 0;
		1998	int num_modes = 0, i;
		1999	int state_index = 0;
		2000	struct radeon_i2c_bus_rec i2c_bus;
		2001	union power_info *power_info;
1430	serge	2002	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2003	u16 data_offset;
		2004	u8 frev, crev;
1117	serge	2005
1963	serge	2006	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2007	&frev, &crev, &data_offset))
		2008	return state_index;
1430	serge	2009	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2010
1963	serge	2011	/* add the i2c bus for thermal/fan chip */
2997	Serge	2012	if ((power_info->info.ucOverdriveThermalController > 0) &&
		2013	(power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
1963	serge	2014	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2015	thermal_controller_names[power_info->info.ucOverdriveThermalController],
		2016	power_info->info.ucOverdriveControllerAddress >> 1);
		2017	i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
		2018	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2019	if (rdev->pm.i2c_bus) {
		2020	struct i2c_board_info info = { };
		2021	const char *name = thermal_controller_names[power_info->info.
		2022	ucOverdriveThermalController];
		2023	info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
		2024	strlcpy(info.type, name, sizeof(info.type));
		2025	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2026	}
		2027	}
1430	serge	2028	num_modes = power_info->info.ucNumOfPowerModeEntries;
		2029	if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
		2030	num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
3764	Serge	2031	if (num_modes == 0)
		2032	return state_index;
1963	serge	2033	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
		2034	if (!rdev->pm.power_state)
		2035	return state_index;
		2036	/* last mode is usually default, array is low to high */
1430	serge	2037	for (i = 0; i < num_modes; i++) {
2997	Serge	2038	rdev->pm.power_state[state_index].clock_info =
		2039	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2040	if (!rdev->pm.power_state[state_index].clock_info)
		2041	return state_index;
		2042	rdev->pm.power_state[state_index].num_clock_modes = 1;
1430	serge	2043	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
		2044	switch (frev) {
		2045	case 1:
		2046	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2047	le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
		2048	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2049	le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
		2050	/* skip invalid modes */
		2051	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2052	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2053	continue;
1963	serge	2054	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2055	power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
		2056	misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1963	serge	2057	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2058	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2059	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2060	VOLTAGE_GPIO;
		2061	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2062	radeon_lookup_gpio(rdev,
		2063	power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
		2064	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2065	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2066	true;
		2067	else
		2068	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2069	false;
		2070	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2071	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2072	VOLTAGE_VDDC;
		2073	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2074	power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
		2075	}
1963	serge	2076	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2077	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1430	serge	2078	state_index++;
		2079	break;
		2080	case 2:
		2081	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2082	le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
		2083	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2084	le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
		2085	/* skip invalid modes */
		2086	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2087	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2088	continue;
1963	serge	2089	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2090	power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
		2091	misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
		2092	misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1963	serge	2093	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2094	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2095	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2096	VOLTAGE_GPIO;
		2097	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2098	radeon_lookup_gpio(rdev,
		2099	power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
		2100	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2101	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2102	true;
		2103	else
		2104	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2105	false;
		2106	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2107	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2108	VOLTAGE_VDDC;
		2109	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2110	power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
		2111	}
1963	serge	2112	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2113	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1430	serge	2114	state_index++;
		2115	break;
		2116	case 3:
		2117	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2118	le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
		2119	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2120	le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
		2121	/* skip invalid modes */
		2122	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2123	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2124	continue;
1963	serge	2125	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2126	power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
		2127	misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
		2128	misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1963	serge	2129	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2130	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2131	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2132	VOLTAGE_GPIO;
		2133	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2134	radeon_lookup_gpio(rdev,
		2135	power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
		2136	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2137	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2138	true;
		2139	else
		2140	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2141	false;
		2142	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2143	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2144	VOLTAGE_VDDC;
		2145	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2146	power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
		2147	if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
		2148	rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
		2149	true;
		2150	rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
		2151	power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
		2152	}
		2153	}
1963	serge	2154	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2155	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1430	serge	2156	state_index++;
		2157	break;
		2158	}
		2159	}
1963	serge	2160	/* last mode is usually default */
		2161	if (rdev->pm.default_power_state_index == -1) {
		2162	rdev->pm.power_state[state_index - 1].type =
		2163	POWER_STATE_TYPE_DEFAULT;
		2164	rdev->pm.default_power_state_index = state_index - 1;
		2165	rdev->pm.power_state[state_index - 1].default_clock_mode =
		2166	&rdev->pm.power_state[state_index - 1].clock_info[0];
		2167	rdev->pm.power_state[state_index].flags &=
		2168	~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2169	rdev->pm.power_state[state_index].misc = 0;
		2170	rdev->pm.power_state[state_index].misc2 = 0;
		2171	}
		2172	return state_index;
		2173	}
		2174
		2175	static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
		2176	ATOM_PPLIB_THERMALCONTROLLER *controller)
		2177	{
		2178	struct radeon_i2c_bus_rec i2c_bus;
		2179
		2180	/* add the i2c bus for thermal/fan chip */
		2181	if (controller->ucType > 0) {
		2182	if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
		2183	DRM_INFO("Internal thermal controller %s fan control\n",
		2184	(controller->ucFanParameters &
		2185	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2186	rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
		2187	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
		2188	DRM_INFO("Internal thermal controller %s fan control\n",
		2189	(controller->ucFanParameters &
		2190	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2191	rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
		2192	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
		2193	DRM_INFO("Internal thermal controller %s fan control\n",
		2194	(controller->ucFanParameters &
		2195	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2196	rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
		2197	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
		2198	DRM_INFO("Internal thermal controller %s fan control\n",
		2199	(controller->ucFanParameters &
		2200	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2201	rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
		2202	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
		2203	DRM_INFO("Internal thermal controller %s fan control\n",
		2204	(controller->ucFanParameters &
		2205	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2206	rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2997	Serge	2207	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
		2208	DRM_INFO("Internal thermal controller %s fan control\n",
		2209	(controller->ucFanParameters &
		2210	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2211	rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
1963	serge	2212	} else if ((controller->ucType ==
		2213	ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) \|\|
		2214	(controller->ucType ==
		2215	ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) \|\|
		2216	(controller->ucType ==
		2217	ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
		2218	DRM_INFO("Special thermal controller config\n");
2997	Serge	2219	} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
1963	serge	2220	DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
		2221	pp_lib_thermal_controller_names[controller->ucType],
		2222	controller->ucI2cAddress >> 1,
		2223	(controller->ucFanParameters &
		2224	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2225	i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
		2226	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2227	if (rdev->pm.i2c_bus) {
		2228	struct i2c_board_info info = { };
		2229	const char *name = pp_lib_thermal_controller_names[controller->ucType];
		2230	info.addr = controller->ucI2cAddress >> 1;
		2231	strlcpy(info.type, name, sizeof(info.type));
		2232	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1430	serge	2233	}
2997	Serge	2234	} else {
		2235	DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
		2236	controller->ucType,
		2237	controller->ucI2cAddress >> 1,
		2238	(controller->ucFanParameters &
		2239	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1430	serge	2240	}
1963	serge	2241	}
		2242	}
		2243
		2244	static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
		2245	u16 vddc, u16 vddci)
		2246	{
		2247	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2248	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		2249	u8 frev, crev;
		2250	u16 data_offset;
		2251	union firmware_info *firmware_info;
		2252
		2253	*vddc = 0;
		2254	*vddci = 0;
		2255
		2256	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		2257	&frev, &crev, &data_offset)) {
		2258	firmware_info =
		2259	(union firmware_info *)(mode_info->atom_context->bios +
		2260	data_offset);
		2261	*vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
		2262	if ((frev == 2) && (crev >= 2))
		2263	*vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
		2264	}
		2265	}
		2266
		2267	static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
		2268	int state_index, int mode_index,
		2269	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
		2270	{
		2271	int j;
		2272	u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
		2273	u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
		2274	u16 vddc, vddci;
		2275
		2276	radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
		2277
		2278	rdev->pm.power_state[state_index].misc = misc;
		2279	rdev->pm.power_state[state_index].misc2 = misc2;
		2280	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2281	((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
		2282	ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
		2283	switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
		2284	case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
		2285	rdev->pm.power_state[state_index].type =
		2286	POWER_STATE_TYPE_BATTERY;
		2287	break;
		2288	case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
		2289	rdev->pm.power_state[state_index].type =
		2290	POWER_STATE_TYPE_BALANCED;
		2291	break;
		2292	case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
		2293	rdev->pm.power_state[state_index].type =
		2294	POWER_STATE_TYPE_PERFORMANCE;
		2295	break;
1963	serge	2296	case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
		2297	if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
		2298	rdev->pm.power_state[state_index].type =
		2299	POWER_STATE_TYPE_PERFORMANCE;
		2300	break;
1430	serge	2301	}
1963	serge	2302	rdev->pm.power_state[state_index].flags = 0;
		2303	if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
		2304	rdev->pm.power_state[state_index].flags \|=
		2305	RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1430	serge	2306	if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
		2307	rdev->pm.power_state[state_index].type =
		2308	POWER_STATE_TYPE_DEFAULT;
1963	serge	2309	rdev->pm.default_power_state_index = state_index;
1430	serge	2310	rdev->pm.power_state[state_index].default_clock_mode =
		2311	&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
3764	Serge	2312	if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
1963	serge	2313	/* NI chips post without MC ucode, so default clocks are strobe mode only */
		2314	rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
		2315	rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
		2316	rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
		2317	rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
		2318	} else {
		2319	/* patch the table values with the default slck/mclk from firmware info */
		2320	for (j = 0; j < mode_index; j++) {
		2321	rdev->pm.power_state[state_index].clock_info[j].mclk =
		2322	rdev->clock.default_mclk;
		2323	rdev->pm.power_state[state_index].clock_info[j].sclk =
		2324	rdev->clock.default_sclk;
		2325	if (vddc)
		2326	rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
		2327	vddc;
		2328	}
1430	serge	2329	}
1963	serge	2330	}
		2331	}
		2332
		2333	static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
		2334	int state_index, int mode_index,
		2335	union pplib_clock_info *clock_info)
		2336	{
		2337	u32 sclk, mclk;
2997	Serge	2338	u16 vddc;
1963	serge	2339
		2340	if (rdev->flags & RADEON_IS_IGP) {
		2341	if (rdev->family >= CHIP_PALM) {
		2342	sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
		2343	sclk \|= clock_info->sumo.ucEngineClockHigh << 16;
		2344	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2345	} else {
		2346	sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
		2347	sclk \|= clock_info->rs780.ucLowEngineClockHigh << 16;
		2348	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2349	}
3764	Serge	2350	} else if (rdev->family >= CHIP_TAHITI) {
2997	Serge	2351	sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
		2352	sclk \|= clock_info->si.ucEngineClockHigh << 16;
		2353	mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
		2354	mclk \|= clock_info->si.ucMemoryClockHigh << 16;
		2355	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2356	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2357	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2358	VOLTAGE_SW;
		2359	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2360	le16_to_cpu(clock_info->si.usVDDC);
		2361	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
		2362	le16_to_cpu(clock_info->si.usVDDCI);
3764	Serge	2363	} else if (rdev->family >= CHIP_CEDAR) {
1963	serge	2364	sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
		2365	sclk \|= clock_info->evergreen.ucEngineClockHigh << 16;
		2366	mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
		2367	mclk \|= clock_info->evergreen.ucMemoryClockHigh << 16;
		2368	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2369	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2370	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2371	VOLTAGE_SW;
		2372	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2373	le16_to_cpu(clock_info->evergreen.usVDDC);
		2374	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
		2375	le16_to_cpu(clock_info->evergreen.usVDDCI);
		2376	} else {
		2377	sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
		2378	sclk \|= clock_info->r600.ucEngineClockHigh << 16;
		2379	mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
		2380	mclk \|= clock_info->r600.ucMemoryClockHigh << 16;
		2381	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2382	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2383	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2384	VOLTAGE_SW;
		2385	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2386	le16_to_cpu(clock_info->r600.usVDDC);
		2387	}
		2388
1986	serge	2389	/* patch up vddc if necessary */
2997	Serge	2390	switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
		2391	case ATOM_VIRTUAL_VOLTAGE_ID0:
		2392	case ATOM_VIRTUAL_VOLTAGE_ID1:
		2393	case ATOM_VIRTUAL_VOLTAGE_ID2:
		2394	case ATOM_VIRTUAL_VOLTAGE_ID3:
		2395	if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
		2396	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
		2397	&vddc) == 0)
1986	serge	2398	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2997	Serge	2399	break;
		2400	default:
		2401	break;
1986	serge	2402	}
		2403
1963	serge	2404	if (rdev->flags & RADEON_IS_IGP) {
		2405	/* skip invalid modes */
		2406	if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
		2407	return false;
		2408	} else {
		2409	/* skip invalid modes */
		2410	if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) \|\|
		2411	(rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
		2412	return false;
		2413	}
		2414	return true;
		2415	}
		2416
		2417	static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
		2418	{
		2419	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2420	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		2421	union pplib_power_state *power_state;
		2422	int i, j;
		2423	int state_index = 0, mode_index = 0;
		2424	union pplib_clock_info *clock_info;
		2425	bool valid;
		2426	union power_info *power_info;
		2427	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2428	u16 data_offset;
		2429	u8 frev, crev;
		2430
		2431	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2432	&frev, &crev, &data_offset))
		2433	return state_index;
		2434	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2435
		2436	radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
3764	Serge	2437	if (power_info->pplib.ucNumStates == 0)
		2438	return state_index;
1963	serge	2439	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
		2440	power_info->pplib.ucNumStates, GFP_KERNEL);
		2441	if (!rdev->pm.power_state)
		2442	return state_index;
		2443	/* first mode is usually default, followed by low to high */
		2444	for (i = 0; i < power_info->pplib.ucNumStates; i++) {
		2445	mode_index = 0;
		2446	power_state = (union pplib_power_state *)
		2447	(mode_info->atom_context->bios + data_offset +
		2448	le16_to_cpu(power_info->pplib.usStateArrayOffset) +
		2449	i * power_info->pplib.ucStateEntrySize);
		2450	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		2451	(mode_info->atom_context->bios + data_offset +
		2452	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
		2453	(power_state->v1.ucNonClockStateIndex *
		2454	power_info->pplib.ucNonClockSize));
2997	Serge	2455	rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
		2456	((power_info->pplib.ucStateEntrySize - 1) ?
		2457	(power_info->pplib.ucStateEntrySize - 1) : 1),
		2458	GFP_KERNEL);
		2459	if (!rdev->pm.power_state[i].clock_info)
		2460	return state_index;
		2461	if (power_info->pplib.ucStateEntrySize - 1) {
1963	serge	2462	for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
		2463	clock_info = (union pplib_clock_info *)
		2464	(mode_info->atom_context->bios + data_offset +
		2465	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
		2466	(power_state->v1.ucClockStateIndices[j] *
		2467	power_info->pplib.ucClockInfoSize));
		2468	valid = radeon_atombios_parse_pplib_clock_info(rdev,
		2469	state_index, mode_index,
		2470	clock_info);
		2471	if (valid)
		2472	mode_index++;
		2473	}
2997	Serge	2474	} else {
		2475	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2476	rdev->clock.default_mclk;
		2477	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2478	rdev->clock.default_sclk;
		2479	mode_index++;
		2480	}
1963	serge	2481	rdev->pm.power_state[state_index].num_clock_modes = mode_index;
		2482	if (mode_index) {
		2483	radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
		2484	non_clock_info);
		2485	state_index++;
		2486	}
		2487	}
		2488	/* if multiple clock modes, mark the lowest as no display */
		2489	for (i = 0; i < state_index; i++) {
		2490	if (rdev->pm.power_state[i].num_clock_modes > 1)
		2491	rdev->pm.power_state[i].clock_info[0].flags \|=
		2492	RADEON_PM_MODE_NO_DISPLAY;
		2493	}
		2494	/* first mode is usually default */
		2495	if (rdev->pm.default_power_state_index == -1) {
		2496	rdev->pm.power_state[0].type =
		2497	POWER_STATE_TYPE_DEFAULT;
		2498	rdev->pm.default_power_state_index = 0;
		2499	rdev->pm.power_state[0].default_clock_mode =
		2500	&rdev->pm.power_state[0].clock_info[0];
		2501	}
		2502	return state_index;
		2503	}
		2504
		2505	static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
		2506	{
		2507	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2508	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		2509	union pplib_power_state *power_state;
		2510	int i, j, non_clock_array_index, clock_array_index;
		2511	int state_index = 0, mode_index = 0;
		2512	union pplib_clock_info *clock_info;
2997	Serge	2513	struct _StateArray *state_array;
		2514	struct _ClockInfoArray *clock_info_array;
		2515	struct _NonClockInfoArray *non_clock_info_array;
1963	serge	2516	bool valid;
		2517	union power_info *power_info;
		2518	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2519	u16 data_offset;
		2520	u8 frev, crev;
3764	Serge	2521	u8 *power_state_offset;
1963	serge	2522
		2523	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2524	&frev, &crev, &data_offset))
		2525	return state_index;
		2526	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2527
		2528	radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2997	Serge	2529	state_array = (struct _StateArray *)
1963	serge	2530	(mode_info->atom_context->bios + data_offset +
		2531	le16_to_cpu(power_info->pplib.usStateArrayOffset));
2997	Serge	2532	clock_info_array = (struct _ClockInfoArray *)
1963	serge	2533	(mode_info->atom_context->bios + data_offset +
		2534	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2997	Serge	2535	non_clock_info_array = (struct _NonClockInfoArray *)
1963	serge	2536	(mode_info->atom_context->bios + data_offset +
		2537	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
3764	Serge	2538	if (state_array->ucNumEntries == 0)
		2539	return state_index;
1963	serge	2540	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
		2541	state_array->ucNumEntries, GFP_KERNEL);
		2542	if (!rdev->pm.power_state)
		2543	return state_index;
3764	Serge	2544	power_state_offset = (u8 *)state_array->states;
1963	serge	2545	for (i = 0; i < state_array->ucNumEntries; i++) {
		2546	mode_index = 0;
3764	Serge	2547	power_state = (union pplib_power_state *)power_state_offset;
		2548	non_clock_array_index = power_state->v2.nonClockInfoIndex;
1963	serge	2549	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		2550	&non_clock_info_array->nonClockInfo[non_clock_array_index];
2997	Serge	2551	rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
		2552	(power_state->v2.ucNumDPMLevels ?
		2553	power_state->v2.ucNumDPMLevels : 1),
		2554	GFP_KERNEL);
		2555	if (!rdev->pm.power_state[i].clock_info)
		2556	return state_index;
		2557	if (power_state->v2.ucNumDPMLevels) {
1963	serge	2558	for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
		2559	clock_array_index = power_state->v2.clockInfoIndex[j];
		2560	clock_info = (union pplib_clock_info *)
2997	Serge	2561	&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
1963	serge	2562	valid = radeon_atombios_parse_pplib_clock_info(rdev,
		2563	state_index, mode_index,
		2564	clock_info);
		2565	if (valid)
		2566	mode_index++;
		2567	}
2997	Serge	2568	} else {
		2569	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2570	rdev->clock.default_mclk;
		2571	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2572	rdev->clock.default_sclk;
		2573	mode_index++;
		2574	}
1963	serge	2575	rdev->pm.power_state[state_index].num_clock_modes = mode_index;
		2576	if (mode_index) {
		2577	radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
		2578	non_clock_info);
1430	serge	2579	state_index++;
		2580	}
3764	Serge	2581	power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1430	serge	2582	}
1963	serge	2583	/* if multiple clock modes, mark the lowest as no display */
		2584	for (i = 0; i < state_index; i++) {
		2585	if (rdev->pm.power_state[i].num_clock_modes > 1)
		2586	rdev->pm.power_state[i].clock_info[0].flags \|=
		2587	RADEON_PM_MODE_NO_DISPLAY;
		2588	}
		2589	/* first mode is usually default */
		2590	if (rdev->pm.default_power_state_index == -1) {
		2591	rdev->pm.power_state[0].type =
		2592	POWER_STATE_TYPE_DEFAULT;
		2593	rdev->pm.default_power_state_index = 0;
		2594	rdev->pm.power_state[0].default_clock_mode =
		2595	&rdev->pm.power_state[0].clock_info[0];
		2596	}
		2597	return state_index;
		2598	}
		2599
		2600	void radeon_atombios_get_power_modes(struct radeon_device *rdev)
		2601	{
		2602	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2603	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2604	u16 data_offset;
		2605	u8 frev, crev;
		2606	int state_index = 0;
		2607
		2608	rdev->pm.default_power_state_index = -1;
		2609
		2610	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		2611	&frev, &crev, &data_offset)) {
		2612	switch (frev) {
		2613	case 1:
		2614	case 2:
		2615	case 3:
		2616	state_index = radeon_atombios_parse_power_table_1_3(rdev);
		2617	break;
		2618	case 4:
		2619	case 5:
		2620	state_index = radeon_atombios_parse_power_table_4_5(rdev);
		2621	break;
		2622	case 6:
		2623	state_index = radeon_atombios_parse_power_table_6(rdev);
		2624	break;
		2625	default:
		2626	break;
1430	serge	2627	}
3764	Serge	2628	}
		2629
		2630	if (state_index == 0) {
1963	serge	2631	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
		2632	if (rdev->pm.power_state) {
2997	Serge	2633	rdev->pm.power_state[0].clock_info =
		2634	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2635	if (rdev->pm.power_state[0].clock_info) {
1430	serge	2636	/* add the default mode */
		2637	rdev->pm.power_state[state_index].type =
		2638	POWER_STATE_TYPE_DEFAULT;
		2639	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2640	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
		2641	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
		2642	rdev->pm.power_state[state_index].default_clock_mode =
		2643	&rdev->pm.power_state[state_index].clock_info[0];
		2644	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1963	serge	2645	rdev->pm.power_state[state_index].pcie_lanes = 16;
		2646	rdev->pm.default_power_state_index = state_index;
		2647	rdev->pm.power_state[state_index].flags = 0;
1430	serge	2648	state_index++;
		2649	}
1963	serge	2650	}
2997	Serge	2651	}
1963	serge	2652
1430	serge	2653	rdev->pm.num_power_states = state_index;
		2654
1963	serge	2655	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2656	rdev->pm.current_clock_mode_index = 0;
2997	Serge	2657	if (rdev->pm.default_power_state_index >= 0)
		2658	rdev->pm.current_vddc =
		2659	rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
		2660	else
		2661	rdev->pm.current_vddc = 0;
1117	serge	2662	}
		2663
3764	Serge	2664	union get_clock_dividers {
		2665	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
		2666	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
		2667	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
		2668	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
		2669	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
		2670	};
		2671
		2672	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
		2673	u8 clock_type,
		2674	u32 clock,
		2675	bool strobe_mode,
		2676	struct atom_clock_dividers *dividers)
		2677	{
		2678	union get_clock_dividers args;
		2679	int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
		2680	u8 frev, crev;
		2681
		2682	memset(&args, 0, sizeof(args));
		2683	memset(dividers, 0, sizeof(struct atom_clock_dividers));
		2684
		2685	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2686	return -EINVAL;
		2687
		2688	switch (crev) {
		2689	case 1:
		2690	/* r4xx, r5xx */
		2691	args.v1.ucAction = clock_type;
		2692	args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
		2693
		2694	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2695
		2696	dividers->post_div = args.v1.ucPostDiv;
		2697	dividers->fb_div = args.v1.ucFbDiv;
		2698	dividers->enable_post_div = true;
		2699	break;
		2700	case 2:
		2701	case 3:
		2702	/* r6xx, r7xx, evergreen, ni */
		2703	if (rdev->family <= CHIP_RV770) {
		2704	args.v2.ucAction = clock_type;
		2705	args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
		2706
		2707	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2708
		2709	dividers->post_div = args.v2.ucPostDiv;
		2710	dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
		2711	dividers->ref_div = args.v2.ucAction;
		2712	if (rdev->family == CHIP_RV770) {
		2713	dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
		2714	true : false;
		2715	dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
		2716	} else
		2717	dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
		2718	} else {
		2719	if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
		2720	args.v3.ulClockParams = cpu_to_le32((clock_type << 24) \| clock);
		2721
		2722	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2723
		2724	dividers->post_div = args.v3.ucPostDiv;
		2725	dividers->enable_post_div = (args.v3.ucCntlFlag &
		2726	ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
		2727	dividers->enable_dithen = (args.v3.ucCntlFlag &
		2728	ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
		2729	dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
		2730	dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
		2731	dividers->ref_div = args.v3.ucRefDiv;
		2732	dividers->vco_mode = (args.v3.ucCntlFlag &
		2733	ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
		2734	} else {
		2735	args.v5.ulClockParams = cpu_to_le32((clock_type << 24) \| clock);
		2736	if (strobe_mode)
		2737	args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
		2738
		2739	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2740
		2741	dividers->post_div = args.v5.ucPostDiv;
		2742	dividers->enable_post_div = (args.v5.ucCntlFlag &
		2743	ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
		2744	dividers->enable_dithen = (args.v5.ucCntlFlag &
		2745	ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
		2746	dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
		2747	dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
		2748	dividers->ref_div = args.v5.ucRefDiv;
		2749	dividers->vco_mode = (args.v5.ucCntlFlag &
		2750	ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
		2751	}
		2752	}
		2753	break;
		2754	case 4:
		2755	/* fusion */
		2756	args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
		2757
		2758	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2759
		2760	dividers->post_div = args.v4.ucPostDiv;
		2761	dividers->real_clock = le32_to_cpu(args.v4.ulClock);
		2762	break;
		2763	default:
		2764	return -EINVAL;
		2765	}
		2766	return 0;
		2767	}
		2768
1430	serge	2769	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1117	serge	2770	{
1430	serge	2771	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		2772	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1117	serge	2773
		2774	args.ucEnable = enable;
		2775
		2776	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2777	}
		2778
1268	serge	2779	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
		2780	{
		2781	GET_ENGINE_CLOCK_PS_ALLOCATION args;
		2782	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
		2783
		2784	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963	serge	2785	return le32_to_cpu(args.ulReturnEngineClock);
1268	serge	2786	}
		2787
		2788	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
		2789	{
		2790	GET_MEMORY_CLOCK_PS_ALLOCATION args;
		2791	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
		2792
		2793	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963	serge	2794	return le32_to_cpu(args.ulReturnMemoryClock);
1268	serge	2795	}
		2796
1117	serge	2797	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		2798	uint32_t eng_clock)
		2799	{
		2800	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		2801	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		2802
1963	serge	2803	args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
1117	serge	2804
		2805	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2806	}
		2807
		2808	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		2809	uint32_t mem_clock)
		2810	{
		2811	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		2812	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		2813
		2814	if (rdev->flags & RADEON_IS_IGP)
		2815	return;
		2816
1963	serge	2817	args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
1117	serge	2818
		2819	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2820	}
		2821
1963	serge	2822	union set_voltage {
		2823	struct _SET_VOLTAGE_PS_ALLOCATION alloc;
		2824	struct _SET_VOLTAGE_PARAMETERS v1;
		2825	struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2997	Serge	2826	struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1963	serge	2827	};
		2828
		2829	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
		2830	{
		2831	union set_voltage args;
		2832	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		2833	u8 frev, crev, volt_index = voltage_level;
		2834
		2835	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2836	return;
		2837
1986	serge	2838	/* 0xff01 is a flag rather then an actual voltage */
		2839	if (voltage_level == 0xff01)
		2840	return;
		2841
1963	serge	2842	switch (crev) {
		2843	case 1:
		2844	args.v1.ucVoltageType = voltage_type;
		2845	args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
		2846	args.v1.ucVoltageIndex = volt_index;
		2847	break;
		2848	case 2:
		2849	args.v2.ucVoltageType = voltage_type;
		2850	args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
		2851	args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
		2852	break;
2997	Serge	2853	case 3:
		2854	args.v3.ucVoltageType = voltage_type;
		2855	args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
		2856	args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
		2857	break;
1963	serge	2858	default:
		2859	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		2860	return;
		2861	}
		2862
		2863	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2864	}
		2865
2997	Serge	2866	static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		2867	u16 voltage_id, u16 *voltage)
1986	serge	2868	{
		2869	union set_voltage args;
		2870	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		2871	u8 frev, crev;
1963	serge	2872
1986	serge	2873	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2874	return -EINVAL;
1963	serge	2875
1986	serge	2876	switch (crev) {
		2877	case 1:
		2878	return -EINVAL;
		2879	case 2:
		2880	args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
		2881	args.v2.ucVoltageMode = 0;
		2882	args.v2.usVoltageLevel = 0;
		2883
		2884	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2885
		2886	*voltage = le16_to_cpu(args.v2.usVoltageLevel);
		2887	break;
2997	Serge	2888	case 3:
		2889	args.v3.ucVoltageType = voltage_type;
		2890	args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
		2891	args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
		2892
		2893	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2894
		2895	*voltage = le16_to_cpu(args.v3.usVoltageLevel);
		2896	break;
1986	serge	2897	default:
		2898	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		2899	return -EINVAL;
		2900	}
		2901
		2902	return 0;
		2903	}
		2904
1117	serge	2905	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		2906	{
		2907	struct radeon_device *rdev = dev->dev_private;
		2908	uint32_t bios_2_scratch, bios_6_scratch;
		2909
		2910	if (rdev->family >= CHIP_R600) {
1179	serge	2911	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	2912	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		2913	} else {
1179	serge	2914	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	2915	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2916	}
		2917
		2918	/* let the bios control the backlight */
		2919	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		2920
		2921	/* tell the bios not to handle mode switching */
1963	serge	2922	bios_6_scratch \|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1117	serge	2923
		2924	if (rdev->family >= CHIP_R600) {
		2925	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		2926	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		2927	} else {
		2928	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		2929	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2930	}
		2931
		2932	}
		2933
1179	serge	2934	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		2935	{
		2936	uint32_t scratch_reg;
		2937	int i;
		2938
		2939	if (rdev->family >= CHIP_R600)
		2940	scratch_reg = R600_BIOS_0_SCRATCH;
		2941	else
		2942	scratch_reg = RADEON_BIOS_0_SCRATCH;
		2943
		2944	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		2945	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		2946	}
		2947
		2948	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		2949	{
		2950	uint32_t scratch_reg;
		2951	int i;
		2952
		2953	if (rdev->family >= CHIP_R600)
		2954	scratch_reg = R600_BIOS_0_SCRATCH;
		2955	else
		2956	scratch_reg = RADEON_BIOS_0_SCRATCH;
		2957
		2958	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		2959	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		2960	}
		2961
1117	serge	2962	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		2963	{
		2964	struct drm_device *dev = encoder->dev;
		2965	struct radeon_device *rdev = dev->dev_private;
		2966	uint32_t bios_6_scratch;
		2967
		2968	if (rdev->family >= CHIP_R600)
		2969	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		2970	else
		2971	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2972
1963	serge	2973	if (lock) {
1117	serge	2974	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
1963	serge	2975	bios_6_scratch &= ~ATOM_S6_ACC_MODE;
		2976	} else {
1117	serge	2977	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1963	serge	2978	bios_6_scratch \|= ATOM_S6_ACC_MODE;
		2979	}
1117	serge	2980
		2981	if (rdev->family >= CHIP_R600)
		2982	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		2983	else
		2984	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2985	}
		2986
		2987	/* at some point we may want to break this out into individual functions */
		2988	void
		2989	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		2990	struct drm_encoder *encoder,
		2991	bool connected)
		2992	{
		2993	struct drm_device *dev = connector->dev;
		2994	struct radeon_device *rdev = dev->dev_private;
		2995	struct radeon_connector *radeon_connector =
		2996	to_radeon_connector(connector);
		2997	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2998	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		2999
		3000	if (rdev->family >= CHIP_R600) {
		3001	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		3002	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		3003	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		3004	} else {
		3005	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		3006	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		3007	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3008	}
		3009
		3010	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		3011	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		3012	if (connected) {
1963	serge	3013	DRM_DEBUG_KMS("TV1 connected\n");
1117	serge	3014	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		3015	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		3016	} else {
1963	serge	3017	DRM_DEBUG_KMS("TV1 disconnected\n");
1117	serge	3018	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		3019	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		3020	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		3021	}
		3022	}
		3023	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		3024	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		3025	if (connected) {
1963	serge	3026	DRM_DEBUG_KMS("CV connected\n");
1117	serge	3027	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		3028	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		3029	} else {
1963	serge	3030	DRM_DEBUG_KMS("CV disconnected\n");
1117	serge	3031	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		3032	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		3033	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		3034	}
		3035	}
		3036	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		3037	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		3038	if (connected) {
1963	serge	3039	DRM_DEBUG_KMS("LCD1 connected\n");
1117	serge	3040	bios_0_scratch \|= ATOM_S0_LCD1;
		3041	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		3042	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		3043	} else {
1963	serge	3044	DRM_DEBUG_KMS("LCD1 disconnected\n");
1117	serge	3045	bios_0_scratch &= ~ATOM_S0_LCD1;
		3046	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		3047	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		3048	}
		3049	}
		3050	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		3051	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		3052	if (connected) {
1963	serge	3053	DRM_DEBUG_KMS("CRT1 connected\n");
1117	serge	3054	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		3055	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		3056	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		3057	} else {
1963	serge	3058	DRM_DEBUG_KMS("CRT1 disconnected\n");
1117	serge	3059	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		3060	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		3061	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		3062	}
		3063	}
		3064	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		3065	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		3066	if (connected) {
1963	serge	3067	DRM_DEBUG_KMS("CRT2 connected\n");
1117	serge	3068	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		3069	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		3070	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		3071	} else {
1963	serge	3072	DRM_DEBUG_KMS("CRT2 disconnected\n");
1117	serge	3073	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		3074	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		3075	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		3076	}
		3077	}
		3078	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		3079	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		3080	if (connected) {
1963	serge	3081	DRM_DEBUG_KMS("DFP1 connected\n");
1117	serge	3082	bios_0_scratch \|= ATOM_S0_DFP1;
		3083	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		3084	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		3085	} else {
1963	serge	3086	DRM_DEBUG_KMS("DFP1 disconnected\n");
1117	serge	3087	bios_0_scratch &= ~ATOM_S0_DFP1;
		3088	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		3089	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		3090	}
		3091	}
		3092	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		3093	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		3094	if (connected) {
1963	serge	3095	DRM_DEBUG_KMS("DFP2 connected\n");
1117	serge	3096	bios_0_scratch \|= ATOM_S0_DFP2;
		3097	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		3098	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		3099	} else {
1963	serge	3100	DRM_DEBUG_KMS("DFP2 disconnected\n");
1117	serge	3101	bios_0_scratch &= ~ATOM_S0_DFP2;
		3102	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		3103	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		3104	}
		3105	}
		3106	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		3107	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		3108	if (connected) {
1963	serge	3109	DRM_DEBUG_KMS("DFP3 connected\n");
1117	serge	3110	bios_0_scratch \|= ATOM_S0_DFP3;
		3111	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		3112	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		3113	} else {
1963	serge	3114	DRM_DEBUG_KMS("DFP3 disconnected\n");
1117	serge	3115	bios_0_scratch &= ~ATOM_S0_DFP3;
		3116	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		3117	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		3118	}
		3119	}
		3120	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		3121	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		3122	if (connected) {
1963	serge	3123	DRM_DEBUG_KMS("DFP4 connected\n");
1117	serge	3124	bios_0_scratch \|= ATOM_S0_DFP4;
		3125	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		3126	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		3127	} else {
1963	serge	3128	DRM_DEBUG_KMS("DFP4 disconnected\n");
1117	serge	3129	bios_0_scratch &= ~ATOM_S0_DFP4;
		3130	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		3131	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		3132	}
		3133	}
		3134	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		3135	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		3136	if (connected) {
1963	serge	3137	DRM_DEBUG_KMS("DFP5 connected\n");
1117	serge	3138	bios_0_scratch \|= ATOM_S0_DFP5;
		3139	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		3140	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		3141	} else {
1963	serge	3142	DRM_DEBUG_KMS("DFP5 disconnected\n");
1117	serge	3143	bios_0_scratch &= ~ATOM_S0_DFP5;
		3144	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		3145	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		3146	}
		3147	}
2997	Serge	3148	if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
		3149	(radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
		3150	if (connected) {
		3151	DRM_DEBUG_KMS("DFP6 connected\n");
		3152	bios_0_scratch \|= ATOM_S0_DFP6;
		3153	bios_3_scratch \|= ATOM_S3_DFP6_ACTIVE;
		3154	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP6;
		3155	} else {
		3156	DRM_DEBUG_KMS("DFP6 disconnected\n");
		3157	bios_0_scratch &= ~ATOM_S0_DFP6;
		3158	bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
		3159	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
		3160	}
		3161	}
1117	serge	3162
		3163	if (rdev->family >= CHIP_R600) {
		3164	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		3165	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		3166	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		3167	} else {
		3168	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		3169	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		3170	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3171	}
		3172	}
		3173
		3174	void
		3175	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		3176	{
		3177	struct drm_device *dev = encoder->dev;
		3178	struct radeon_device *rdev = dev->dev_private;
		3179	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3180	uint32_t bios_3_scratch;
		3181
2997	Serge	3182	if (ASIC_IS_DCE4(rdev))
		3183	return;
		3184
1117	serge	3185	if (rdev->family >= CHIP_R600)
		3186	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		3187	else
		3188	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		3189
		3190	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		3191	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		3192	bios_3_scratch \|= (crtc << 18);
		3193	}
		3194	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		3195	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		3196	bios_3_scratch \|= (crtc << 24);
		3197	}
		3198	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		3199	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		3200	bios_3_scratch \|= (crtc << 16);
		3201	}
		3202	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		3203	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		3204	bios_3_scratch \|= (crtc << 20);
		3205	}
		3206	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		3207	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		3208	bios_3_scratch \|= (crtc << 17);
		3209	}
		3210	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		3211	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		3212	bios_3_scratch \|= (crtc << 19);
		3213	}
		3214	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		3215	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		3216	bios_3_scratch \|= (crtc << 23);
		3217	}
		3218	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		3219	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		3220	bios_3_scratch \|= (crtc << 25);
		3221	}
		3222
		3223	if (rdev->family >= CHIP_R600)
		3224	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		3225	else
		3226	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		3227	}
		3228
		3229	void
		3230	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		3231	{
		3232	struct drm_device *dev = encoder->dev;
		3233	struct radeon_device *rdev = dev->dev_private;
		3234	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3235	uint32_t bios_2_scratch;
		3236
2997	Serge	3237	if (ASIC_IS_DCE4(rdev))
		3238	return;
		3239
1117	serge	3240	if (rdev->family >= CHIP_R600)
		3241	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		3242	else
		3243	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		3244
		3245	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		3246	if (on)
		3247	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		3248	else
		3249	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		3250	}
		3251	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		3252	if (on)
		3253	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		3254	else
		3255	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		3256	}
		3257	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		3258	if (on)
		3259	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		3260	else
		3261	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		3262	}
		3263	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		3264	if (on)
		3265	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		3266	else
		3267	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		3268	}
		3269	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		3270	if (on)
		3271	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		3272	else
		3273	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		3274	}
		3275	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		3276	if (on)
		3277	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		3278	else
		3279	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		3280	}
		3281	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		3282	if (on)
		3283	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		3284	else
		3285	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		3286	}
		3287	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		3288	if (on)
		3289	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		3290	else
		3291	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		3292	}
		3293	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		3294	if (on)
		3295	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		3296	else
		3297	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		3298	}
		3299	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		3300	if (on)
		3301	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		3302	else
		3303	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		3304	}
		3305
		3306	if (rdev->family >= CHIP_R600)
		3307	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		3308	else
		3309	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		3310	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 3764