WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1123	serge	26	#include "drmP.h"
1117	serge	27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
		35	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
		39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
		40	uint32_t supported_device);
		41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
1268	serge	49	bool linkb, uint32_t igp_lane_info,
1321	serge	50	uint16_t connector_object_id,
		51	struct radeon_hpd *hpd);
1117	serge	52
		53	/* from radeon_legacy_encoder.c */
		54	extern void
		55	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		56	uint32_t supported_device);
		57
		58	union atom_supported_devices {
		59	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		60	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		61	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		62	};
		63
1321	serge	64	static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
		65	uint8_t id)
1117	serge	66	{
		67	struct atom_context *ctx = rdev->mode_info.atom_context;
1321	serge	68	ATOM_GPIO_I2C_ASSIGMENT *gpio;
1117	serge	69	struct radeon_i2c_bus_rec i2c;
		70	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		71	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		72	uint16_t data_offset;
1321	serge	73	int i;
1117	serge	74
		75	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		76	i2c.valid = false;
		77
		78	atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
		79
		80	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		81
		82
1321	serge	83	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		84	gpio = &i2c_info->asGPIO_Info[i];
		85
		86	if (gpio->sucI2cId.ucAccess == id) {
		87	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		88	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		89	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		90	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		91	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		92	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		93	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		94	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		95	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		96	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		97	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		98	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		99	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		100	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		101	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		102	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		103
		104	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		105	i2c.hw_capable = true;
		106	else
		107	i2c.hw_capable = false;
		108
		109	if (gpio->sucI2cId.ucAccess == 0xa0)
		110	i2c.mm_i2c = true;
		111	else
		112	i2c.mm_i2c = false;
		113
		114	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		115
1117	serge	116	i2c.valid = true;
1404	serge	117	break;
1321	serge	118	}
		119	}
1117	serge	120
		121	return i2c;
		122	}
		123
1321	serge	124	static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
		125	u8 id)
		126	{
		127	struct atom_context *ctx = rdev->mode_info.atom_context;
		128	struct radeon_gpio_rec gpio;
		129	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
		130	struct _ATOM_GPIO_PIN_LUT *gpio_info;
		131	ATOM_GPIO_PIN_ASSIGNMENT *pin;
		132	u16 data_offset, size;
		133	int i, num_indices;
		134
		135	memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
		136	gpio.valid = false;
		137
		138	atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
		139
		140	gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
		141
		142	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
		143
		144	for (i = 0; i < num_indices; i++) {
		145	pin = &gpio_info->asGPIO_Pin[i];
		146	if (id == pin->ucGPIO_ID) {
		147	gpio.id = pin->ucGPIO_ID;
		148	gpio.reg = pin->usGpioPin_AIndex * 4;
		149	gpio.mask = (1 << pin->ucGpioPinBitShift);
		150	gpio.valid = true;
		151	break;
		152	}
		153	}
		154
		155	return gpio;
		156	}
		157
		158	static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
		159	struct radeon_gpio_rec *gpio)
		160	{
		161	struct radeon_hpd hpd;
		162	hpd.gpio = *gpio;
		163	if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
		164	switch(gpio->mask) {
		165	case (1 << 0):
		166	hpd.hpd = RADEON_HPD_1;
		167	break;
		168	case (1 << 8):
		169	hpd.hpd = RADEON_HPD_2;
		170	break;
		171	case (1 << 16):
		172	hpd.hpd = RADEON_HPD_3;
		173	break;
		174	case (1 << 24):
		175	hpd.hpd = RADEON_HPD_4;
		176	break;
		177	case (1 << 26):
		178	hpd.hpd = RADEON_HPD_5;
		179	break;
		180	case (1 << 28):
		181	hpd.hpd = RADEON_HPD_6;
		182	break;
		183	default:
		184	hpd.hpd = RADEON_HPD_NONE;
		185	break;
		186	}
		187	} else
		188	hpd.hpd = RADEON_HPD_NONE;
		189	return hpd;
		190	}
		191
1117	serge	192	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		193	uint32_t supported_device,
		194	int *connector_type,
1179	serge	195	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	196	uint16_t *line_mux,
		197	struct radeon_hpd *hpd)
1117	serge	198	{
		199
		200	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		201	if ((dev->pdev->device == 0x791e) &&
		202	(dev->pdev->subsystem_vendor == 0x1043) &&
		203	(dev->pdev->subsystem_device == 0x826d)) {
		204	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		205	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		206	*connector_type = DRM_MODE_CONNECTOR_DVID;
		207	}
		208
1428	serge	209	/* Asrock RS600 board lists the DVI port as HDMI */
		210	if ((dev->pdev->device == 0x7941) &&
		211	(dev->pdev->subsystem_vendor == 0x1849) &&
		212	(dev->pdev->subsystem_device == 0x7941)) {
		213	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		214	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		215	*connector_type = DRM_MODE_CONNECTOR_DVID;
		216	}
		217
1117	serge	218	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		219	if ((dev->pdev->device == 0x7941) &&
		220	(dev->pdev->subsystem_vendor == 0x147b) &&
		221	(dev->pdev->subsystem_device == 0x2412)) {
		222	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		223	return false;
		224	}
		225
		226	/* Falcon NW laptop lists vga ddc line for LVDS */
		227	if ((dev->pdev->device == 0x5653) &&
		228	(dev->pdev->subsystem_vendor == 0x1462) &&
		229	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	230	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	231	i2c_bus->valid = false;
1179	serge	232	*line_mux = 53;
		233	}
1117	serge	234	}
		235
1321	serge	236	/* HIS X1300 is DVI+VGA, not DVI+DVI */
		237	if ((dev->pdev->device == 0x7146) &&
		238	(dev->pdev->subsystem_vendor == 0x17af) &&
		239	(dev->pdev->subsystem_device == 0x2058)) {
		240	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		241	return false;
		242	}
		243
		244	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
		245	if ((dev->pdev->device == 0x7142) &&
		246	(dev->pdev->subsystem_vendor == 0x1458) &&
		247	(dev->pdev->subsystem_device == 0x2134)) {
		248	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		249	return false;
		250	}
		251
		252
1117	serge	253	/* Funky macbooks */
		254	if ((dev->pdev->device == 0x71C5) &&
		255	(dev->pdev->subsystem_vendor == 0x106b) &&
		256	(dev->pdev->subsystem_device == 0x0080)) {
		257	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		258	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		259	return false;
		260	}
		261
		262	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		263	if ((dev->pdev->device == 0x9598) &&
		264	(dev->pdev->subsystem_vendor == 0x1043) &&
		265	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	266	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		267	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	268	}
		269	}
		270
1179	serge	271	/* ASUS HD 3450 board lists the DVI port as HDMI */
		272	if ((dev->pdev->device == 0x95C5) &&
		273	(dev->pdev->subsystem_vendor == 0x1043) &&
		274	(dev->pdev->subsystem_device == 0x01e2)) {
		275	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		276	*connector_type = DRM_MODE_CONNECTOR_DVII;
		277	}
		278	}
		279
		280	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		281	* HDMI + VGA reporting as HDMI
		282	*/
		283	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		284	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		285	*connector_type = DRM_MODE_CONNECTOR_VGA;
		286	*line_mux = 0;
		287	}
		288	}
		289
1321	serge	290	/* Acer laptop reports DVI-D as DVI-I */
		291	if ((dev->pdev->device == 0x95c4) &&
		292	(dev->pdev->subsystem_vendor == 0x1025) &&
		293	(dev->pdev->subsystem_device == 0x013c)) {
		294	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
		295	(supported_device == ATOM_DEVICE_DFP1_SUPPORT))
		296	*connector_type = DRM_MODE_CONNECTOR_DVID;
		297	}
		298
1412	serge	299	/* XFX Pine Group device rv730 reports no VGA DDC lines
		300	* even though they are wired up to record 0x93
		301	*/
		302	if ((dev->pdev->device == 0x9498) &&
		303	(dev->pdev->subsystem_vendor == 0x1682) &&
		304	(dev->pdev->subsystem_device == 0x2452)) {
		305	struct radeon_device *rdev = dev->dev_private;
		306	*i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
		307	}
1117	serge	308	return true;
		309	}
		310
		311	const int supported_devices_connector_convert[] = {
		312	DRM_MODE_CONNECTOR_Unknown,
		313	DRM_MODE_CONNECTOR_VGA,
		314	DRM_MODE_CONNECTOR_DVII,
		315	DRM_MODE_CONNECTOR_DVID,
		316	DRM_MODE_CONNECTOR_DVIA,
		317	DRM_MODE_CONNECTOR_SVIDEO,
		318	DRM_MODE_CONNECTOR_Composite,
		319	DRM_MODE_CONNECTOR_LVDS,
		320	DRM_MODE_CONNECTOR_Unknown,
		321	DRM_MODE_CONNECTOR_Unknown,
		322	DRM_MODE_CONNECTOR_HDMIA,
		323	DRM_MODE_CONNECTOR_HDMIB,
		324	DRM_MODE_CONNECTOR_Unknown,
		325	DRM_MODE_CONNECTOR_Unknown,
		326	DRM_MODE_CONNECTOR_9PinDIN,
		327	DRM_MODE_CONNECTOR_DisplayPort
		328	};
		329
1268	serge	330	const uint16_t supported_devices_connector_object_id_convert[] = {
		331	CONNECTOR_OBJECT_ID_NONE,
		332	CONNECTOR_OBJECT_ID_VGA,
		333	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
		334	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
		335	CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
		336	CONNECTOR_OBJECT_ID_COMPOSITE,
		337	CONNECTOR_OBJECT_ID_SVIDEO,
		338	CONNECTOR_OBJECT_ID_LVDS,
		339	CONNECTOR_OBJECT_ID_9PIN_DIN,
		340	CONNECTOR_OBJECT_ID_9PIN_DIN,
		341	CONNECTOR_OBJECT_ID_DISPLAYPORT,
		342	CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
		343	CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
		344	CONNECTOR_OBJECT_ID_SVIDEO
		345	};
		346
1117	serge	347	const int object_connector_convert[] = {
		348	DRM_MODE_CONNECTOR_Unknown,
		349	DRM_MODE_CONNECTOR_DVII,
		350	DRM_MODE_CONNECTOR_DVII,
		351	DRM_MODE_CONNECTOR_DVID,
		352	DRM_MODE_CONNECTOR_DVID,
		353	DRM_MODE_CONNECTOR_VGA,
		354	DRM_MODE_CONNECTOR_Composite,
		355	DRM_MODE_CONNECTOR_SVIDEO,
		356	DRM_MODE_CONNECTOR_Unknown,
1179	serge	357	DRM_MODE_CONNECTOR_Unknown,
1117	serge	358	DRM_MODE_CONNECTOR_9PinDIN,
		359	DRM_MODE_CONNECTOR_Unknown,
		360	DRM_MODE_CONNECTOR_HDMIA,
		361	DRM_MODE_CONNECTOR_HDMIB,
		362	DRM_MODE_CONNECTOR_LVDS,
		363	DRM_MODE_CONNECTOR_9PinDIN,
		364	DRM_MODE_CONNECTOR_Unknown,
		365	DRM_MODE_CONNECTOR_Unknown,
		366	DRM_MODE_CONNECTOR_Unknown,
1404	serge	367	DRM_MODE_CONNECTOR_DisplayPort,
		368	DRM_MODE_CONNECTOR_eDP,
		369	DRM_MODE_CONNECTOR_Unknown
1117	serge	370	};
		371
		372	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		373	{
		374	struct radeon_device *rdev = dev->dev_private;
		375	struct radeon_mode_info *mode_info = &rdev->mode_info;
		376	struct atom_context *ctx = mode_info->atom_context;
		377	int index = GetIndexIntoMasterTable(DATA, Object_Header);
1321	serge	378	u16 size, data_offset;
		379	u8 frev, crev;
1117	serge	380	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
		381	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		382	ATOM_OBJECT_HEADER *obj_header;
		383	int i, j, path_size, device_support;
		384	int connector_type;
1321	serge	385	u16 igp_lane_info, conn_id, connector_object_id;
1117	serge	386	bool linkb;
		387	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	388	struct radeon_gpio_rec gpio;
		389	struct radeon_hpd hpd;
1117	serge	390
		391	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		392
		393	if (data_offset == 0)
		394	return false;
		395
		396	if (crev < 2)
		397	return false;
		398
		399	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		400	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		401	(ctx->bios + data_offset +
		402	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		403	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		404	(ctx->bios + data_offset +
		405	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
		406	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		407
		408	path_size = 0;
		409	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		410	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		411	ATOM_DISPLAY_OBJECT_PATH *path;
		412	addr += path_size;
		413	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		414	path_size += le16_to_cpu(path->usSize);
		415	linkb = false;
		416	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		417	uint8_t con_obj_id, con_obj_num, con_obj_type;
		418
		419	con_obj_id =
		420	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		421	>> OBJECT_ID_SHIFT;
		422	con_obj_num =
		423	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		424	>> ENUM_ID_SHIFT;
		425	con_obj_type =
		426	(le16_to_cpu(path->usConnObjectId) &
		427	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		428
1221	serge	429	/* TODO CV support */
		430	if (le16_to_cpu(path->usDeviceTag) ==
		431	ATOM_DEVICE_CV_SUPPORT)
1117	serge	432	continue;
		433
1268	serge	434	/* IGP chips */
		435	if ((rdev->flags & RADEON_IS_IGP) &&
1117	serge	436	(con_obj_id ==
		437	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		438	uint16_t igp_offset = 0;
		439	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		440
		441	index =
		442	GetIndexIntoMasterTable(DATA,
		443	IntegratedSystemInfo);
		444
		445	atom_parse_data_header(ctx, index, &size, &frev,
		446	&crev, &igp_offset);
		447
		448	if (crev >= 2) {
		449	igp_obj =
		450	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		451	*) (ctx->bios + igp_offset);
		452
		453	if (igp_obj) {
		454	uint32_t slot_config, ct;
		455
		456	if (con_obj_num == 1)
		457	slot_config =
		458	igp_obj->
		459	ulDDISlot1Config;
		460	else
		461	slot_config =
		462	igp_obj->
		463	ulDDISlot2Config;
		464
		465	ct = (slot_config >> 16) & 0xff;
		466	connector_type =
		467	object_connector_convert
		468	[ct];
1268	serge	469	connector_object_id = ct;
1117	serge	470	igp_lane_info =
		471	slot_config & 0xffff;
		472	} else
		473	continue;
		474	} else
		475	continue;
		476	} else {
		477	igp_lane_info = 0;
		478	connector_type =
		479	object_connector_convert[con_obj_id];
1268	serge	480	connector_object_id = con_obj_id;
1117	serge	481	}
		482
		483	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		484	continue;
		485
		486	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
		487	j++) {
		488	uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
		489
		490	enc_obj_id =
		491	(le16_to_cpu(path->usGraphicObjIds[j]) &
		492	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		493	enc_obj_num =
		494	(le16_to_cpu(path->usGraphicObjIds[j]) &
		495	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		496	enc_obj_type =
		497	(le16_to_cpu(path->usGraphicObjIds[j]) &
		498	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		499
		500	/* FIXME: add support for router objects */
		501	if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		502	if (enc_obj_num == 2)
		503	linkb = true;
		504	else
		505	linkb = false;
		506
1123	serge	507	radeon_add_atom_encoder(dev,
		508	enc_obj_id,
		509	le16_to_cpu
		510	(path->
		511	usDeviceTag));
1117	serge	512
		513	}
		514	}
		515
1321	serge	516	/* look up gpio for ddc, hpd */
1117	serge	517	if ((le16_to_cpu(path->usDeviceTag) &
1321	serge	518	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) == 0) {
1117	serge	519	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		520	if (le16_to_cpu(path->usConnObjectId) ==
		521	le16_to_cpu(con_obj->asObjects[j].
		522	usObjectID)) {
		523	ATOM_COMMON_RECORD_HEADER
		524	*record =
		525	(ATOM_COMMON_RECORD_HEADER
		526	*)
		527	(ctx->bios + data_offset +
		528	le16_to_cpu(con_obj->
		529	asObjects[j].
		530	usRecordOffset));
		531	ATOM_I2C_RECORD *i2c_record;
1321	serge	532	ATOM_HPD_INT_RECORD *hpd_record;
		533	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
		534	hpd.hpd = RADEON_HPD_NONE;
1117	serge	535
		536	while (record->ucRecordType > 0
		537	&& record->
		538	ucRecordType <=
		539	ATOM_MAX_OBJECT_RECORD_NUMBER) {
1321	serge	540	switch (record->ucRecordType) {
1117	serge	541	case ATOM_I2C_RECORD_TYPE:
		542	i2c_record =
1321	serge	543	(ATOM_I2C_RECORD *)
		544	record;
		545	i2c_config =
		546	(ATOM_I2C_ID_CONFIG_ACCESS *)
		547	&i2c_record->sucI2cId;
		548	ddc_bus = radeon_lookup_i2c_gpio(rdev,
		549	i2c_config->
		550	ucAccess);
1117	serge	551	break;
1321	serge	552	case ATOM_HPD_INT_RECORD_TYPE:
		553	hpd_record =
		554	(ATOM_HPD_INT_RECORD *)
		555	record;
		556	gpio = radeon_lookup_gpio(rdev,
		557	hpd_record->ucHPDIntGPIOID);
		558	hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
		559	hpd.plugged_state = hpd_record->ucPlugged_PinState;
		560	break;
1117	serge	561	}
		562	record =
		563	(ATOM_COMMON_RECORD_HEADER
		564	) ((char )record
		565	+
		566	record->
		567	ucRecordSize);
		568	}
		569	break;
		570	}
		571	}
1321	serge	572	} else {
		573	hpd.hpd = RADEON_HPD_NONE;
1117	serge	574	ddc_bus.valid = false;
1321	serge	575	}
1117	serge	576
1179	serge	577	conn_id = le16_to_cpu(path->usConnObjectId);
		578
		579	if (!radeon_atom_apply_quirks
		580	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
1321	serge	581	&ddc_bus, &conn_id, &hpd))
1179	serge	582	continue;
		583
1123	serge	584	radeon_add_atom_connector(dev,
1179	serge	585	conn_id,
1123	serge	586	le16_to_cpu(path->
		587	usDeviceTag),
		588	connector_type, &ddc_bus,
1268	serge	589	linkb, igp_lane_info,
1321	serge	590	connector_object_id,
		591	&hpd);
1117	serge	592
		593	}
		594	}
		595
1123	serge	596	radeon_link_encoder_connector(dev);
1117	serge	597
		598	return true;
		599	}
		600
1268	serge	601	static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
		602	int connector_type,
		603	uint16_t devices)
		604	{
		605	struct radeon_device *rdev = dev->dev_private;
		606
		607	if (rdev->flags & RADEON_IS_IGP) {
		608	return supported_devices_connector_object_id_convert
		609	[connector_type];
		610	} else if (((connector_type == DRM_MODE_CONNECTOR_DVII) \|\|
		611	(connector_type == DRM_MODE_CONNECTOR_DVID)) &&
		612	(devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		613	struct radeon_mode_info *mode_info = &rdev->mode_info;
		614	struct atom_context *ctx = mode_info->atom_context;
		615	int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
		616	uint16_t size, data_offset;
		617	uint8_t frev, crev;
		618	ATOM_XTMDS_INFO *xtmds;
		619
		620	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		621	xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
		622
		623	if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
		624	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		625	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		626	else
		627	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		628	} else {
		629	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		630	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		631	else
		632	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		633	}
		634	} else {
		635	return supported_devices_connector_object_id_convert
		636	[connector_type];
		637	}
		638	}
		639
1117	serge	640	struct bios_connector {
		641	bool valid;
1179	serge	642	uint16_t line_mux;
1117	serge	643	uint16_t devices;
		644	int connector_type;
		645	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	646	struct radeon_hpd hpd;
1117	serge	647	};
		648
		649	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		650	drm_device
		651	*dev)
		652	{
		653	struct radeon_device *rdev = dev->dev_private;
		654	struct radeon_mode_info *mode_info = &rdev->mode_info;
		655	struct atom_context *ctx = mode_info->atom_context;
		656	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		657	uint16_t size, data_offset;
		658	uint8_t frev, crev;
		659	uint16_t device_support;
		660	uint8_t dac;
		661	union atom_supported_devices *supported_devices;
1321	serge	662	int i, j, max_device;
1117	serge	663	struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
		664
		665	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
1128	serge	666
1117	serge	667	supported_devices =
		668	(union atom_supported_devices *)(ctx->bios + data_offset);
		669
		670	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		671
1321	serge	672	if (frev > 1)
		673	max_device = ATOM_MAX_SUPPORTED_DEVICE;
		674	else
		675	max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
		676
		677	for (i = 0; i < max_device; i++) {
1117	serge	678	ATOM_CONNECTOR_INFO_I2C ci =
		679	supported_devices->info.asConnInfo[i];
		680
		681	bios_connectors[i].valid = false;
		682
		683	if (!(device_support & (1 << i))) {
		684	continue;
		685	}
		686
		687	if (i == ATOM_DEVICE_CV_INDEX) {
		688	DRM_DEBUG("Skipping Component Video\n");
		689	continue;
		690	}
		691
		692	bios_connectors[i].connector_type =
		693	supported_devices_connector_convert[ci.sucConnectorInfo.
		694	sbfAccess.
		695	bfConnectorType];
		696
		697	if (bios_connectors[i].connector_type ==
		698	DRM_MODE_CONNECTOR_Unknown)
		699	continue;
		700
		701	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		702
		703	bios_connectors[i].line_mux =
1321	serge	704	ci.sucI2cId.ucAccess;
1117	serge	705
		706	/* give tv unique connector ids */
		707	if (i == ATOM_DEVICE_TV1_INDEX) {
		708	bios_connectors[i].ddc_bus.valid = false;
		709	bios_connectors[i].line_mux = 50;
		710	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		711	bios_connectors[i].ddc_bus.valid = false;
		712	bios_connectors[i].line_mux = 51;
		713	} else if (i == ATOM_DEVICE_CV_INDEX) {
		714	bios_connectors[i].ddc_bus.valid = false;
		715	bios_connectors[i].line_mux = 52;
		716	} else
		717	bios_connectors[i].ddc_bus =
1321	serge	718	radeon_lookup_i2c_gpio(rdev,
1117	serge	719	bios_connectors[i].line_mux);
		720
1321	serge	721	if ((crev > 1) && (frev > 1)) {
		722	u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
		723	switch (isb) {
		724	case 0x4:
		725	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		726	break;
		727	case 0xa:
		728	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		729	break;
		730	default:
		731	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		732	break;
		733	}
		734	} else {
		735	if (i == ATOM_DEVICE_DFP1_INDEX)
		736	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		737	else if (i == ATOM_DEVICE_DFP2_INDEX)
		738	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		739	else
		740	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		741	}
		742
1117	serge	743	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		744	* shared with a DVI port, we'll pick up the DVI connector when we
		745	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		746	*/
		747	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		748	bios_connectors[i].connector_type =
		749	DRM_MODE_CONNECTOR_VGA;
		750
		751	if (!radeon_atom_apply_quirks
		752	(dev, (1 << i), &bios_connectors[i].connector_type,
1321	serge	753	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
		754	&bios_connectors[i].hpd))
1117	serge	755	continue;
		756
		757	bios_connectors[i].valid = true;
		758	bios_connectors[i].devices = (1 << i);
		759
1123	serge	760	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		761	radeon_add_atom_encoder(dev,
		762	radeon_get_encoder_id(dev,
		763	(1 << i),
		764	dac),
		765	(1 << i));
		766	else
		767	radeon_add_legacy_encoder(dev,
		768	radeon_get_encoder_id(dev,
1404	serge	769	(1 << i),
1123	serge	770	dac),
		771	(1 << i));
1117	serge	772	}
		773
		774	/* combine shared connectors */
1321	serge	775	for (i = 0; i < max_device; i++) {
1117	serge	776	if (bios_connectors[i].valid) {
1321	serge	777	for (j = 0; j < max_device; j++) {
1117	serge	778	if (bios_connectors[j].valid && (i != j)) {
		779	if (bios_connectors[i].line_mux ==
		780	bios_connectors[j].line_mux) {
1404	serge	781	/* make sure not to combine LVDS */
		782	if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		783	bios_connectors[i].line_mux = 53;
		784	bios_connectors[i].ddc_bus.valid = false;
		785	continue;
		786	}
		787	if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		788	bios_connectors[j].line_mux = 53;
		789	bios_connectors[j].ddc_bus.valid = false;
		790	continue;
		791	}
		792	/* combine analog and digital for DVI-I */
		793	if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		794	(bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) \|\|
		795	((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		796	(bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
		797	bios_connectors[i].devices \|=
		798	bios_connectors[j].devices;
		799	bios_connectors[i].connector_type =
1117	serge	800	DRM_MODE_CONNECTOR_DVII;
1404	serge	801	if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1321	serge	802	bios_connectors[i].hpd =
		803	bios_connectors[j].hpd;
1404	serge	804	bios_connectors[j].valid = false;
1117	serge	805	}
		806	}
		807	}
		808	}
		809	}
		810	}
		811
		812	/* add the connectors */
1321	serge	813	for (i = 0; i < max_device; i++) {
1268	serge	814	if (bios_connectors[i].valid) {
		815	uint16_t connector_object_id =
		816	atombios_get_connector_object_id(dev,
		817	bios_connectors[i].connector_type,
		818	bios_connectors[i].devices);
1123	serge	819	radeon_add_atom_connector(dev,
		820	bios_connectors[i].line_mux,
		821	bios_connectors[i].devices,
		822	bios_connectors[i].
		823	connector_type,
		824	&bios_connectors[i].ddc_bus,
1268	serge	825	false, 0,
1321	serge	826	connector_object_id,
		827	&bios_connectors[i].hpd);
1268	serge	828	}
1123	serge	829	}
1117	serge	830
1123	serge	831	radeon_link_encoder_connector(dev);
1128	serge	832
1117	serge	833	return true;
		834	}
		835
		836	union firmware_info {
		837	ATOM_FIRMWARE_INFO info;
		838	ATOM_FIRMWARE_INFO_V1_2 info_12;
		839	ATOM_FIRMWARE_INFO_V1_3 info_13;
		840	ATOM_FIRMWARE_INFO_V1_4 info_14;
		841	};
		842
		843	bool radeon_atom_get_clock_info(struct drm_device *dev)
		844	{
		845	struct radeon_device *rdev = dev->dev_private;
		846	struct radeon_mode_info *mode_info = &rdev->mode_info;
		847	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		848	union firmware_info *firmware_info;
		849	uint8_t frev, crev;
		850	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		851	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		852	struct radeon_pll *spll = &rdev->clock.spll;
		853	struct radeon_pll *mpll = &rdev->clock.mpll;
		854	uint16_t data_offset;
		855
		856	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		857	&crev, &data_offset);
		858
		859	firmware_info =
		860	(union firmware_info *)(mode_info->atom_context->bios +
		861	data_offset);
		862
		863	if (firmware_info) {
		864	/* pixel clocks */
		865	p1pll->reference_freq =
		866	le16_to_cpu(firmware_info->info.usReferenceClock);
		867	p1pll->reference_div = 0;
		868
1268	serge	869	if (crev < 2)
1117	serge	870	p1pll->pll_out_min =
		871	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1268	serge	872	else
		873	p1pll->pll_out_min =
		874	le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117	serge	875	p1pll->pll_out_max =
		876	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		877
		878	if (p1pll->pll_out_min == 0) {
		879	if (ASIC_IS_AVIVO(rdev))
		880	p1pll->pll_out_min = 64800;
		881	else
		882	p1pll->pll_out_min = 20000;
1268	serge	883	} else if (p1pll->pll_out_min > 64800) {
		884	/* Limiting the pll output range is a good thing generally as
		885	* it limits the number of possible pll combinations for a given
		886	* frequency presumably to the ones that work best on each card.
		887	* However, certain duallink DVI monitors seem to like
		888	* pll combinations that would be limited by this at least on
		889	* pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
		890	* family.
		891	*/
1321	serge	892	if (!radeon_new_pll)
1268	serge	893	p1pll->pll_out_min = 64800;
1117	serge	894	}
		895
		896	p1pll->pll_in_min =
		897	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		898	p1pll->pll_in_max =
		899	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		900
		901	p2pll = p1pll;
		902
		903	/* system clock */
		904	spll->reference_freq =
		905	le16_to_cpu(firmware_info->info.usReferenceClock);
		906	spll->reference_div = 0;
		907
		908	spll->pll_out_min =
		909	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		910	spll->pll_out_max =
		911	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		912
		913	/* ??? */
		914	if (spll->pll_out_min == 0) {
		915	if (ASIC_IS_AVIVO(rdev))
		916	spll->pll_out_min = 64800;
		917	else
		918	spll->pll_out_min = 20000;
		919	}
		920
		921	spll->pll_in_min =
		922	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		923	spll->pll_in_max =
		924	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		925
		926	/* memory clock */
		927	mpll->reference_freq =
		928	le16_to_cpu(firmware_info->info.usReferenceClock);
		929	mpll->reference_div = 0;
		930
		931	mpll->pll_out_min =
		932	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		933	mpll->pll_out_max =
		934	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		935
		936	/* ??? */
		937	if (mpll->pll_out_min == 0) {
		938	if (ASIC_IS_AVIVO(rdev))
		939	mpll->pll_out_min = 64800;
		940	else
		941	mpll->pll_out_min = 20000;
		942	}
		943
		944	mpll->pll_in_min =
		945	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		946	mpll->pll_in_max =
		947	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		948
		949	rdev->clock.default_sclk =
		950	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		951	rdev->clock.default_mclk =
		952	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		953
		954	return true;
		955	}
		956	return false;
		957	}
		958
1404	serge	959	union igp_info {
		960	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
		961	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
		962	};
		963
		964	bool radeon_atombios_sideport_present(struct radeon_device *rdev)
		965	{
		966	struct radeon_mode_info *mode_info = &rdev->mode_info;
		967	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		968	union igp_info *igp_info;
		969	u8 frev, crev;
		970	u16 data_offset;
		971
		972	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		973	&crev, &data_offset);
		974
		975	igp_info = (union igp_info *)(mode_info->atom_context->bios +
		976	data_offset);
		977
		978	if (igp_info) {
		979	switch (crev) {
		980	case 1:
		981	if (igp_info->info.ucMemoryType & 0xf0)
		982	return true;
		983	break;
		984	case 2:
		985	if (igp_info->info_2.ucMemoryType & 0x0f)
		986	return true;
		987	break;
		988	default:
		989	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		990	break;
		991	}
		992	}
		993	return false;
		994	}
		995
1179	serge	996	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		997	struct radeon_encoder_int_tmds *tmds)
1117	serge	998	{
		999	struct drm_device *dev = encoder->base.dev;
		1000	struct radeon_device *rdev = dev->dev_private;
		1001	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1002	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		1003	uint16_t data_offset;
		1004	struct _ATOM_TMDS_INFO *tmds_info;
		1005	uint8_t frev, crev;
		1006	uint16_t maxfreq;
		1007	int i;
		1008
		1009	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1010	&crev, &data_offset);
		1011
		1012	tmds_info =
		1013	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		1014	data_offset);
		1015
		1016	if (tmds_info) {
		1017	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		1018	for (i = 0; i < 4; i++) {
		1019	tmds->tmds_pll[i].freq =
		1020	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		1021	tmds->tmds_pll[i].value =
		1022	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		1023	tmds->tmds_pll[i].value \|=
		1024	(tmds_info->asMiscInfo[i].
		1025	ucPLL_VCO_Gain & 0x3f) << 6;
		1026	tmds->tmds_pll[i].value \|=
		1027	(tmds_info->asMiscInfo[i].
		1028	ucPLL_DutyCycle & 0xf) << 12;
		1029	tmds->tmds_pll[i].value \|=
		1030	(tmds_info->asMiscInfo[i].
		1031	ucPLL_VoltageSwing & 0xf) << 16;
		1032
		1033	DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
		1034	tmds->tmds_pll[i].freq,
		1035	tmds->tmds_pll[i].value);
		1036
		1037	if (maxfreq == tmds->tmds_pll[i].freq) {
		1038	tmds->tmds_pll[i].freq = 0xffffffff;
		1039	break;
		1040	}
		1041	}
1179	serge	1042	return true;
1117	serge	1043	}
1179	serge	1044	return false;
1117	serge	1045	}
		1046
1268	serge	1047	static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
		1048	radeon_encoder
		1049	*encoder,
		1050	int id)
		1051	{
		1052	struct drm_device *dev = encoder->base.dev;
		1053	struct radeon_device *rdev = dev->dev_private;
		1054	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1055	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
		1056	uint16_t data_offset;
		1057	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
		1058	uint8_t frev, crev;
		1059	struct radeon_atom_ss *ss = NULL;
1321	serge	1060	int i;
1268	serge	1061
		1062	if (id > ATOM_MAX_SS_ENTRY)
		1063	return NULL;
		1064
		1065	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1066	&crev, &data_offset);
		1067
		1068	ss_info =
		1069	(struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
		1070
		1071	if (ss_info) {
		1072	ss =
		1073	kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
		1074
		1075	if (!ss)
		1076	return NULL;
		1077
1321	serge	1078	for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
		1079	if (ss_info->asSS_Info[i].ucSS_Id == id) {
		1080	ss->percentage =
		1081	le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
		1082	ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
		1083	ss->step = ss_info->asSS_Info[i].ucSS_Step;
		1084	ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
		1085	ss->range = ss_info->asSS_Info[i].ucSS_Range;
		1086	ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1404	serge	1087	break;
1268	serge	1088	}
1321	serge	1089	}
		1090	}
1268	serge	1091	return ss;
		1092	}
		1093
1117	serge	1094	union lvds_info {
		1095	struct _ATOM_LVDS_INFO info;
		1096	struct _ATOM_LVDS_INFO_V12 info_12;
		1097	};
		1098
		1099	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		1100	radeon_encoder
		1101	*encoder)
		1102	{
		1103	struct drm_device *dev = encoder->base.dev;
		1104	struct radeon_device *rdev = dev->dev_private;
		1105	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1106	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1321	serge	1107	uint16_t data_offset, misc;
1117	serge	1108	union lvds_info *lvds_info;
		1109	uint8_t frev, crev;
		1110	struct radeon_encoder_atom_dig *lvds = NULL;
		1111
		1112	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1113	&crev, &data_offset);
		1114
		1115	lvds_info =
		1116	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		1117
		1118	if (lvds_info) {
		1119	lvds =
		1120	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1121
		1122	if (!lvds)
		1123	return NULL;
		1124
1268	serge	1125	lvds->native_mode.clock =
1117	serge	1126	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1268	serge	1127	lvds->native_mode.hdisplay =
1117	serge	1128	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1268	serge	1129	lvds->native_mode.vdisplay =
1117	serge	1130	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1268	serge	1131	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1117	serge	1132	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1268	serge	1133	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1117	serge	1134	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1268	serge	1135	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1117	serge	1136	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1268	serge	1137	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1117	serge	1138	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1268	serge	1139	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
		1140	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1141	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1117	serge	1142	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1143	lvds->panel_pwr_delay =
		1144	le16_to_cpu(lvds_info->info.usOffDelayInMs);
		1145	lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1321	serge	1146
		1147	misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
		1148	if (misc & ATOM_VSYNC_POLARITY)
		1149	lvds->native_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		1150	if (misc & ATOM_HSYNC_POLARITY)
		1151	lvds->native_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		1152	if (misc & ATOM_COMPOSITESYNC)
		1153	lvds->native_mode.flags \|= DRM_MODE_FLAG_CSYNC;
		1154	if (misc & ATOM_INTERLACE)
		1155	lvds->native_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		1156	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1157	lvds->native_mode.flags \|= DRM_MODE_FLAG_DBLSCAN;
		1158
1268	serge	1159	/* set crtc values */
		1160	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1117	serge	1161
1268	serge	1162	lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
		1163
1117	serge	1164	encoder->native_mode = lvds->native_mode;
		1165	}
		1166	return lvds;
		1167	}
		1168
		1169	struct radeon_encoder_primary_dac *
		1170	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		1171	{
		1172	struct drm_device *dev = encoder->base.dev;
		1173	struct radeon_device *rdev = dev->dev_private;
		1174	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1175	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1176	uint16_t data_offset;
		1177	struct _COMPASSIONATE_DATA *dac_info;
		1178	uint8_t frev, crev;
		1179	uint8_t bg, dac;
		1180	struct radeon_encoder_primary_dac *p_dac = NULL;
		1181
		1182	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1183
		1184	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		1185
		1186	if (dac_info) {
		1187	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		1188
		1189	if (!p_dac)
		1190	return NULL;
		1191
		1192	bg = dac_info->ucDAC1_BG_Adjustment;
		1193	dac = dac_info->ucDAC1_DAC_Adjustment;
		1194	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		1195
		1196	}
		1197	return p_dac;
		1198	}
		1199
1179	serge	1200	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1268	serge	1201	struct drm_display_mode *mode)
1179	serge	1202	{
		1203	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1204	ATOM_ANALOG_TV_INFO *tv_info;
		1205	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		1206	ATOM_DTD_FORMAT *dtd_timings;
		1207	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1208	u8 frev, crev;
1268	serge	1209	u16 data_offset, misc;
1179	serge	1210
		1211	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
		1212
		1213	switch (crev) {
		1214	case 1:
		1215	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		1216	if (index > MAX_SUPPORTED_TV_TIMING)
		1217	return false;
		1218
1268	serge	1219	mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		1220	mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		1221	mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		1222	mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
		1223	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1179	serge	1224
1268	serge	1225	mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		1226	mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		1227	mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		1228	mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
		1229	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1179	serge	1230
1268	serge	1231	mode->flags = 0;
		1232	misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
		1233	if (misc & ATOM_VSYNC_POLARITY)
		1234	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1235	if (misc & ATOM_HSYNC_POLARITY)
		1236	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1237	if (misc & ATOM_COMPOSITESYNC)
		1238	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1239	if (misc & ATOM_INTERLACE)
		1240	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1241	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1242	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
1179	serge	1243
1268	serge	1244	mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1179	serge	1245
		1246	if (index == 1) {
		1247	/* PAL timings appear to have wrong values for totals */
1268	serge	1248	mode->crtc_htotal -= 1;
		1249	mode->crtc_vtotal -= 1;
1179	serge	1250	}
		1251	break;
		1252	case 2:
		1253	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
		1254	if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
		1255	return false;
		1256
		1257	dtd_timings = &tv_info_v1_2->aModeTimings[index];
1268	serge	1258	mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
		1259	le16_to_cpu(dtd_timings->usHBlanking_Time);
		1260	mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
		1261	mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
		1262	le16_to_cpu(dtd_timings->usHSyncOffset);
		1263	mode->crtc_hsync_end = mode->crtc_hsync_start +
		1264	le16_to_cpu(dtd_timings->usHSyncWidth);
1179	serge	1265
1268	serge	1266	mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
		1267	le16_to_cpu(dtd_timings->usVBlanking_Time);
		1268	mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
		1269	mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
		1270	le16_to_cpu(dtd_timings->usVSyncOffset);
		1271	mode->crtc_vsync_end = mode->crtc_vsync_start +
		1272	le16_to_cpu(dtd_timings->usVSyncWidth);
		1273
		1274	mode->flags = 0;
		1275	misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		1276	if (misc & ATOM_VSYNC_POLARITY)
		1277	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1278	if (misc & ATOM_HSYNC_POLARITY)
		1279	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1280	if (misc & ATOM_COMPOSITESYNC)
		1281	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1282	if (misc & ATOM_INTERLACE)
		1283	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1284	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1285	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
		1286
		1287	mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1179	serge	1288	break;
		1289	}
		1290	return true;
		1291	}
		1292
1404	serge	1293	enum radeon_tv_std
		1294	radeon_atombios_get_tv_info(struct radeon_device *rdev)
		1295	{
		1296	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1297	int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1298	uint16_t data_offset;
		1299	uint8_t frev, crev;
		1300	struct _ATOM_ANALOG_TV_INFO *tv_info;
		1301	enum radeon_tv_std tv_std = TV_STD_NTSC;
		1302
		1303	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1304
		1305	tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		1306
		1307	switch (tv_info->ucTV_BootUpDefaultStandard) {
		1308	case ATOM_TV_NTSC:
		1309	tv_std = TV_STD_NTSC;
		1310	DRM_INFO("Default TV standard: NTSC\n");
		1311	break;
		1312	case ATOM_TV_NTSCJ:
		1313	tv_std = TV_STD_NTSC_J;
		1314	DRM_INFO("Default TV standard: NTSC-J\n");
		1315	break;
		1316	case ATOM_TV_PAL:
		1317	tv_std = TV_STD_PAL;
		1318	DRM_INFO("Default TV standard: PAL\n");
		1319	break;
		1320	case ATOM_TV_PALM:
		1321	tv_std = TV_STD_PAL_M;
		1322	DRM_INFO("Default TV standard: PAL-M\n");
		1323	break;
		1324	case ATOM_TV_PALN:
		1325	tv_std = TV_STD_PAL_N;
		1326	DRM_INFO("Default TV standard: PAL-N\n");
		1327	break;
		1328	case ATOM_TV_PALCN:
		1329	tv_std = TV_STD_PAL_CN;
		1330	DRM_INFO("Default TV standard: PAL-CN\n");
		1331	break;
		1332	case ATOM_TV_PAL60:
		1333	tv_std = TV_STD_PAL_60;
		1334	DRM_INFO("Default TV standard: PAL-60\n");
		1335	break;
		1336	case ATOM_TV_SECAM:
		1337	tv_std = TV_STD_SECAM;
		1338	DRM_INFO("Default TV standard: SECAM\n");
		1339	break;
		1340	default:
		1341	tv_std = TV_STD_NTSC;
		1342	DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
		1343	break;
		1344	}
		1345	return tv_std;
		1346	}
		1347
1117	serge	1348	struct radeon_encoder_tv_dac *
		1349	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		1350	{
		1351	struct drm_device *dev = encoder->base.dev;
		1352	struct radeon_device *rdev = dev->dev_private;
		1353	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1354	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1355	uint16_t data_offset;
		1356	struct _COMPASSIONATE_DATA *dac_info;
		1357	uint8_t frev, crev;
		1358	uint8_t bg, dac;
		1359	struct radeon_encoder_tv_dac *tv_dac = NULL;
		1360
		1361	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1362
		1363	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		1364
		1365	if (dac_info) {
		1366	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1367
		1368	if (!tv_dac)
		1369	return NULL;
		1370
		1371	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		1372	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		1373	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1374
		1375	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		1376	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		1377	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1378
		1379	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		1380	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		1381	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		1382
1404	serge	1383	tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1117	serge	1384	}
		1385	return tv_dac;
		1386	}
		1387
		1388	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
		1389	{
		1390	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		1391	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
		1392
		1393	args.ucEnable = enable;
		1394
		1395	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1396	}
		1397
		1398	void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
		1399	{
		1400	ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
		1401	int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
		1402
		1403	args.ucEnable = enable;
		1404
		1405	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1406	}
		1407
1268	serge	1408	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
		1409	{
		1410	GET_ENGINE_CLOCK_PS_ALLOCATION args;
		1411	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
		1412
		1413	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1414	return args.ulReturnEngineClock;
		1415	}
		1416
		1417	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
		1418	{
		1419	GET_MEMORY_CLOCK_PS_ALLOCATION args;
		1420	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
		1421
		1422	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1423	return args.ulReturnMemoryClock;
		1424	}
		1425
1117	serge	1426	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		1427	uint32_t eng_clock)
		1428	{
		1429	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		1430	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		1431
		1432	args.ulTargetEngineClock = eng_clock; /* 10 khz */
		1433
		1434	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1435	}
		1436
		1437	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		1438	uint32_t mem_clock)
		1439	{
		1440	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		1441	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		1442
		1443	if (rdev->flags & RADEON_IS_IGP)
		1444	return;
		1445
		1446	args.ulTargetMemoryClock = mem_clock; /* 10 khz */
		1447
		1448	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1449	}
		1450
		1451	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		1452	{
		1453	struct radeon_device *rdev = dev->dev_private;
		1454	uint32_t bios_2_scratch, bios_6_scratch;
		1455
		1456	if (rdev->family >= CHIP_R600) {
1179	serge	1457	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	1458	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1459	} else {
1179	serge	1460	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	1461	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1462	}
		1463
		1464	/* let the bios control the backlight */
		1465	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		1466
		1467	/* tell the bios not to handle mode switching */
		1468	bios_6_scratch \|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH \| ATOM_S6_ACC_MODE);
		1469
		1470	if (rdev->family >= CHIP_R600) {
		1471	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1472	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1473	} else {
		1474	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1475	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1476	}
		1477
		1478	}
		1479
1179	serge	1480	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		1481	{
		1482	uint32_t scratch_reg;
		1483	int i;
		1484
		1485	if (rdev->family >= CHIP_R600)
		1486	scratch_reg = R600_BIOS_0_SCRATCH;
		1487	else
		1488	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1489
		1490	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1491	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		1492	}
		1493
		1494	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		1495	{
		1496	uint32_t scratch_reg;
		1497	int i;
		1498
		1499	if (rdev->family >= CHIP_R600)
		1500	scratch_reg = R600_BIOS_0_SCRATCH;
		1501	else
		1502	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1503
		1504	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1505	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		1506	}
		1507
1117	serge	1508	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		1509	{
		1510	struct drm_device *dev = encoder->dev;
		1511	struct radeon_device *rdev = dev->dev_private;
		1512	uint32_t bios_6_scratch;
		1513
		1514	if (rdev->family >= CHIP_R600)
		1515	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1516	else
		1517	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1518
		1519	if (lock)
		1520	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
		1521	else
		1522	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
		1523
		1524	if (rdev->family >= CHIP_R600)
		1525	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1526	else
		1527	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1528	}
		1529
		1530	/* at some point we may want to break this out into individual functions */
		1531	void
		1532	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		1533	struct drm_encoder *encoder,
		1534	bool connected)
		1535	{
		1536	struct drm_device *dev = connector->dev;
		1537	struct radeon_device *rdev = dev->dev_private;
		1538	struct radeon_connector *radeon_connector =
		1539	to_radeon_connector(connector);
		1540	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1541	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		1542
		1543	if (rdev->family >= CHIP_R600) {
		1544	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1545	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1546	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1547	} else {
		1548	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1549	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1550	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1551	}
		1552
		1553	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		1554	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		1555	if (connected) {
		1556	DRM_DEBUG("TV1 connected\n");
		1557	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		1558	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		1559	} else {
		1560	DRM_DEBUG("TV1 disconnected\n");
		1561	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		1562	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		1563	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		1564	}
		1565	}
		1566	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		1567	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		1568	if (connected) {
		1569	DRM_DEBUG("CV connected\n");
		1570	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		1571	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		1572	} else {
		1573	DRM_DEBUG("CV disconnected\n");
		1574	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		1575	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		1576	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		1577	}
		1578	}
		1579	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		1580	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		1581	if (connected) {
		1582	DRM_DEBUG("LCD1 connected\n");
		1583	bios_0_scratch \|= ATOM_S0_LCD1;
		1584	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		1585	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		1586	} else {
		1587	DRM_DEBUG("LCD1 disconnected\n");
		1588	bios_0_scratch &= ~ATOM_S0_LCD1;
		1589	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		1590	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		1591	}
		1592	}
		1593	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		1594	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		1595	if (connected) {
		1596	DRM_DEBUG("CRT1 connected\n");
		1597	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		1598	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		1599	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		1600	} else {
		1601	DRM_DEBUG("CRT1 disconnected\n");
		1602	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		1603	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		1604	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		1605	}
		1606	}
		1607	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		1608	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		1609	if (connected) {
		1610	DRM_DEBUG("CRT2 connected\n");
		1611	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		1612	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		1613	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		1614	} else {
		1615	DRM_DEBUG("CRT2 disconnected\n");
		1616	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		1617	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		1618	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		1619	}
		1620	}
		1621	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		1622	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		1623	if (connected) {
		1624	DRM_DEBUG("DFP1 connected\n");
		1625	bios_0_scratch \|= ATOM_S0_DFP1;
		1626	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		1627	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		1628	} else {
		1629	DRM_DEBUG("DFP1 disconnected\n");
		1630	bios_0_scratch &= ~ATOM_S0_DFP1;
		1631	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		1632	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		1633	}
		1634	}
		1635	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		1636	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		1637	if (connected) {
		1638	DRM_DEBUG("DFP2 connected\n");
		1639	bios_0_scratch \|= ATOM_S0_DFP2;
		1640	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		1641	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		1642	} else {
		1643	DRM_DEBUG("DFP2 disconnected\n");
		1644	bios_0_scratch &= ~ATOM_S0_DFP2;
		1645	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		1646	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		1647	}
		1648	}
		1649	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		1650	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		1651	if (connected) {
		1652	DRM_DEBUG("DFP3 connected\n");
		1653	bios_0_scratch \|= ATOM_S0_DFP3;
		1654	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		1655	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		1656	} else {
		1657	DRM_DEBUG("DFP3 disconnected\n");
		1658	bios_0_scratch &= ~ATOM_S0_DFP3;
		1659	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		1660	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		1661	}
		1662	}
		1663	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		1664	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		1665	if (connected) {
		1666	DRM_DEBUG("DFP4 connected\n");
		1667	bios_0_scratch \|= ATOM_S0_DFP4;
		1668	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		1669	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		1670	} else {
		1671	DRM_DEBUG("DFP4 disconnected\n");
		1672	bios_0_scratch &= ~ATOM_S0_DFP4;
		1673	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		1674	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		1675	}
		1676	}
		1677	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		1678	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		1679	if (connected) {
		1680	DRM_DEBUG("DFP5 connected\n");
		1681	bios_0_scratch \|= ATOM_S0_DFP5;
		1682	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		1683	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		1684	} else {
		1685	DRM_DEBUG("DFP5 disconnected\n");
		1686	bios_0_scratch &= ~ATOM_S0_DFP5;
		1687	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		1688	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		1689	}
		1690	}
		1691
		1692	if (rdev->family >= CHIP_R600) {
		1693	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		1694	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1695	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1696	} else {
		1697	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		1698	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1699	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1700	}
		1701	}
		1702
		1703	void
		1704	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		1705	{
		1706	struct drm_device *dev = encoder->dev;
		1707	struct radeon_device *rdev = dev->dev_private;
		1708	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1709	uint32_t bios_3_scratch;
		1710
		1711	if (rdev->family >= CHIP_R600)
		1712	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1713	else
		1714	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1715
		1716	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1717	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		1718	bios_3_scratch \|= (crtc << 18);
		1719	}
		1720	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1721	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		1722	bios_3_scratch \|= (crtc << 24);
		1723	}
		1724	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1725	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		1726	bios_3_scratch \|= (crtc << 16);
		1727	}
		1728	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1729	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		1730	bios_3_scratch \|= (crtc << 20);
		1731	}
		1732	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1733	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		1734	bios_3_scratch \|= (crtc << 17);
		1735	}
		1736	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1737	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		1738	bios_3_scratch \|= (crtc << 19);
		1739	}
		1740	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1741	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		1742	bios_3_scratch \|= (crtc << 23);
		1743	}
		1744	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1745	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		1746	bios_3_scratch \|= (crtc << 25);
		1747	}
		1748
		1749	if (rdev->family >= CHIP_R600)
		1750	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1751	else
		1752	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1753	}
		1754
		1755	void
		1756	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		1757	{
		1758	struct drm_device *dev = encoder->dev;
		1759	struct radeon_device *rdev = dev->dev_private;
		1760	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1761	uint32_t bios_2_scratch;
		1762
		1763	if (rdev->family >= CHIP_R600)
		1764	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		1765	else
		1766	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		1767
		1768	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1769	if (on)
		1770	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		1771	else
		1772	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		1773	}
		1774	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1775	if (on)
		1776	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		1777	else
		1778	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		1779	}
		1780	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1781	if (on)
		1782	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		1783	else
		1784	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		1785	}
		1786	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1787	if (on)
		1788	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		1789	else
		1790	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		1791	}
		1792	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1793	if (on)
		1794	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		1795	else
		1796	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		1797	}
		1798	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1799	if (on)
		1800	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		1801	else
		1802	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		1803	}
		1804	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1805	if (on)
		1806	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		1807	else
		1808	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		1809	}
		1810	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1811	if (on)
		1812	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		1813	else
		1814	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		1815	}
		1816	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		1817	if (on)
		1818	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		1819	else
		1820	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		1821	}
		1822	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		1823	if (on)
		1824	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		1825	else
		1826	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		1827	}
		1828
		1829	if (rdev->family >= CHIP_R600)
		1830	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1831	else
		1832	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1833	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 1428