WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1123	serge	26	#include "drmP.h"
1117	serge	27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
		35	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
		39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
		40	uint32_t supported_device);
		41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
1268	serge	49	bool linkb, uint32_t igp_lane_info,
1321	serge	50	uint16_t connector_object_id,
		51	struct radeon_hpd *hpd);
1117	serge	52
		53	/* from radeon_legacy_encoder.c */
		54	extern void
		55	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		56	uint32_t supported_device);
		57
		58	union atom_supported_devices {
		59	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		60	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		61	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		62	};
		63
1321	serge	64	static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
		65	uint8_t id)
1117	serge	66	{
		67	struct atom_context *ctx = rdev->mode_info.atom_context;
1321	serge	68	ATOM_GPIO_I2C_ASSIGMENT *gpio;
1117	serge	69	struct radeon_i2c_bus_rec i2c;
		70	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		71	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		72	uint16_t data_offset;
1321	serge	73	int i;
1117	serge	74
		75	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		76	i2c.valid = false;
		77
		78	atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
		79
		80	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		81
		82
1321	serge	83	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		84	gpio = &i2c_info->asGPIO_Info[i];
		85
		86	if (gpio->sucI2cId.ucAccess == id) {
		87	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		88	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		89	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		90	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		91	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		92	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		93	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		94	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		95	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		96	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		97	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		98	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		99	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		100	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		101	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		102	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		103
		104	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		105	i2c.hw_capable = true;
		106	else
		107	i2c.hw_capable = false;
		108
		109	if (gpio->sucI2cId.ucAccess == 0xa0)
		110	i2c.mm_i2c = true;
		111	else
		112	i2c.mm_i2c = false;
		113
		114	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		115
1117	serge	116	i2c.valid = true;
1321	serge	117	}
		118	}
1117	serge	119
		120	return i2c;
		121	}
		122
1321	serge	123	static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
		124	u8 id)
		125	{
		126	struct atom_context *ctx = rdev->mode_info.atom_context;
		127	struct radeon_gpio_rec gpio;
		128	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
		129	struct _ATOM_GPIO_PIN_LUT *gpio_info;
		130	ATOM_GPIO_PIN_ASSIGNMENT *pin;
		131	u16 data_offset, size;
		132	int i, num_indices;
		133
		134	memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
		135	gpio.valid = false;
		136
		137	atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
		138
		139	gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
		140
		141	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
		142
		143	for (i = 0; i < num_indices; i++) {
		144	pin = &gpio_info->asGPIO_Pin[i];
		145	if (id == pin->ucGPIO_ID) {
		146	gpio.id = pin->ucGPIO_ID;
		147	gpio.reg = pin->usGpioPin_AIndex * 4;
		148	gpio.mask = (1 << pin->ucGpioPinBitShift);
		149	gpio.valid = true;
		150	break;
		151	}
		152	}
		153
		154	return gpio;
		155	}
		156
		157	static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
		158	struct radeon_gpio_rec *gpio)
		159	{
		160	struct radeon_hpd hpd;
		161	hpd.gpio = *gpio;
		162	if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
		163	switch(gpio->mask) {
		164	case (1 << 0):
		165	hpd.hpd = RADEON_HPD_1;
		166	break;
		167	case (1 << 8):
		168	hpd.hpd = RADEON_HPD_2;
		169	break;
		170	case (1 << 16):
		171	hpd.hpd = RADEON_HPD_3;
		172	break;
		173	case (1 << 24):
		174	hpd.hpd = RADEON_HPD_4;
		175	break;
		176	case (1 << 26):
		177	hpd.hpd = RADEON_HPD_5;
		178	break;
		179	case (1 << 28):
		180	hpd.hpd = RADEON_HPD_6;
		181	break;
		182	default:
		183	hpd.hpd = RADEON_HPD_NONE;
		184	break;
		185	}
		186	} else
		187	hpd.hpd = RADEON_HPD_NONE;
		188	return hpd;
		189	}
		190
1117	serge	191	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		192	uint32_t supported_device,
		193	int *connector_type,
1179	serge	194	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	195	uint16_t *line_mux,
		196	struct radeon_hpd *hpd)
1117	serge	197	{
		198
		199	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		200	if ((dev->pdev->device == 0x791e) &&
		201	(dev->pdev->subsystem_vendor == 0x1043) &&
		202	(dev->pdev->subsystem_device == 0x826d)) {
		203	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		204	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		205	*connector_type = DRM_MODE_CONNECTOR_DVID;
		206	}
		207
		208	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		209	if ((dev->pdev->device == 0x7941) &&
		210	(dev->pdev->subsystem_vendor == 0x147b) &&
		211	(dev->pdev->subsystem_device == 0x2412)) {
		212	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		213	return false;
		214	}
		215
		216	/* Falcon NW laptop lists vga ddc line for LVDS */
		217	if ((dev->pdev->device == 0x5653) &&
		218	(dev->pdev->subsystem_vendor == 0x1462) &&
		219	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	220	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	221	i2c_bus->valid = false;
1179	serge	222	*line_mux = 53;
		223	}
1117	serge	224	}
		225
1321	serge	226	/* HIS X1300 is DVI+VGA, not DVI+DVI */
		227	if ((dev->pdev->device == 0x7146) &&
		228	(dev->pdev->subsystem_vendor == 0x17af) &&
		229	(dev->pdev->subsystem_device == 0x2058)) {
		230	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		231	return false;
		232	}
		233
		234	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
		235	if ((dev->pdev->device == 0x7142) &&
		236	(dev->pdev->subsystem_vendor == 0x1458) &&
		237	(dev->pdev->subsystem_device == 0x2134)) {
		238	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		239	return false;
		240	}
		241
		242
1117	serge	243	/* Funky macbooks */
		244	if ((dev->pdev->device == 0x71C5) &&
		245	(dev->pdev->subsystem_vendor == 0x106b) &&
		246	(dev->pdev->subsystem_device == 0x0080)) {
		247	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		248	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		249	return false;
		250	}
		251
		252	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		253	if ((dev->pdev->device == 0x9598) &&
		254	(dev->pdev->subsystem_vendor == 0x1043) &&
		255	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	256	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		257	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	258	}
		259	}
		260
1179	serge	261	/* ASUS HD 3450 board lists the DVI port as HDMI */
		262	if ((dev->pdev->device == 0x95C5) &&
		263	(dev->pdev->subsystem_vendor == 0x1043) &&
		264	(dev->pdev->subsystem_device == 0x01e2)) {
		265	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		266	*connector_type = DRM_MODE_CONNECTOR_DVII;
		267	}
		268	}
		269
		270	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		271	* HDMI + VGA reporting as HDMI
		272	*/
		273	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		274	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		275	*connector_type = DRM_MODE_CONNECTOR_VGA;
		276	*line_mux = 0;
		277	}
		278	}
		279
1321	serge	280	/* Acer laptop reports DVI-D as DVI-I */
		281	if ((dev->pdev->device == 0x95c4) &&
		282	(dev->pdev->subsystem_vendor == 0x1025) &&
		283	(dev->pdev->subsystem_device == 0x013c)) {
		284	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
		285	(supported_device == ATOM_DEVICE_DFP1_SUPPORT))
		286	*connector_type = DRM_MODE_CONNECTOR_DVID;
		287	}
		288
1117	serge	289	return true;
		290	}
		291
		292	const int supported_devices_connector_convert[] = {
		293	DRM_MODE_CONNECTOR_Unknown,
		294	DRM_MODE_CONNECTOR_VGA,
		295	DRM_MODE_CONNECTOR_DVII,
		296	DRM_MODE_CONNECTOR_DVID,
		297	DRM_MODE_CONNECTOR_DVIA,
		298	DRM_MODE_CONNECTOR_SVIDEO,
		299	DRM_MODE_CONNECTOR_Composite,
		300	DRM_MODE_CONNECTOR_LVDS,
		301	DRM_MODE_CONNECTOR_Unknown,
		302	DRM_MODE_CONNECTOR_Unknown,
		303	DRM_MODE_CONNECTOR_HDMIA,
		304	DRM_MODE_CONNECTOR_HDMIB,
		305	DRM_MODE_CONNECTOR_Unknown,
		306	DRM_MODE_CONNECTOR_Unknown,
		307	DRM_MODE_CONNECTOR_9PinDIN,
		308	DRM_MODE_CONNECTOR_DisplayPort
		309	};
		310
1268	serge	311	const uint16_t supported_devices_connector_object_id_convert[] = {
		312	CONNECTOR_OBJECT_ID_NONE,
		313	CONNECTOR_OBJECT_ID_VGA,
		314	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
		315	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
		316	CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
		317	CONNECTOR_OBJECT_ID_COMPOSITE,
		318	CONNECTOR_OBJECT_ID_SVIDEO,
		319	CONNECTOR_OBJECT_ID_LVDS,
		320	CONNECTOR_OBJECT_ID_9PIN_DIN,
		321	CONNECTOR_OBJECT_ID_9PIN_DIN,
		322	CONNECTOR_OBJECT_ID_DISPLAYPORT,
		323	CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
		324	CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
		325	CONNECTOR_OBJECT_ID_SVIDEO
		326	};
		327
1117	serge	328	const int object_connector_convert[] = {
		329	DRM_MODE_CONNECTOR_Unknown,
		330	DRM_MODE_CONNECTOR_DVII,
		331	DRM_MODE_CONNECTOR_DVII,
		332	DRM_MODE_CONNECTOR_DVID,
		333	DRM_MODE_CONNECTOR_DVID,
		334	DRM_MODE_CONNECTOR_VGA,
		335	DRM_MODE_CONNECTOR_Composite,
		336	DRM_MODE_CONNECTOR_SVIDEO,
		337	DRM_MODE_CONNECTOR_Unknown,
1179	serge	338	DRM_MODE_CONNECTOR_Unknown,
1117	serge	339	DRM_MODE_CONNECTOR_9PinDIN,
		340	DRM_MODE_CONNECTOR_Unknown,
		341	DRM_MODE_CONNECTOR_HDMIA,
		342	DRM_MODE_CONNECTOR_HDMIB,
		343	DRM_MODE_CONNECTOR_LVDS,
		344	DRM_MODE_CONNECTOR_9PinDIN,
		345	DRM_MODE_CONNECTOR_Unknown,
		346	DRM_MODE_CONNECTOR_Unknown,
		347	DRM_MODE_CONNECTOR_Unknown,
		348	DRM_MODE_CONNECTOR_DisplayPort
		349	};
		350
		351	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		352	{
		353	struct radeon_device *rdev = dev->dev_private;
		354	struct radeon_mode_info *mode_info = &rdev->mode_info;
		355	struct atom_context *ctx = mode_info->atom_context;
		356	int index = GetIndexIntoMasterTable(DATA, Object_Header);
1321	serge	357	u16 size, data_offset;
		358	u8 frev, crev;
1117	serge	359	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
		360	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		361	ATOM_OBJECT_HEADER *obj_header;
		362	int i, j, path_size, device_support;
		363	int connector_type;
1321	serge	364	u16 igp_lane_info, conn_id, connector_object_id;
1117	serge	365	bool linkb;
		366	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	367	struct radeon_gpio_rec gpio;
		368	struct radeon_hpd hpd;
1117	serge	369
		370	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		371
		372	if (data_offset == 0)
		373	return false;
		374
		375	if (crev < 2)
		376	return false;
		377
		378	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		379	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		380	(ctx->bios + data_offset +
		381	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		382	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		383	(ctx->bios + data_offset +
		384	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
		385	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		386
		387	path_size = 0;
		388	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		389	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		390	ATOM_DISPLAY_OBJECT_PATH *path;
		391	addr += path_size;
		392	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		393	path_size += le16_to_cpu(path->usSize);
		394	linkb = false;
		395	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		396	uint8_t con_obj_id, con_obj_num, con_obj_type;
		397
		398	con_obj_id =
		399	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		400	>> OBJECT_ID_SHIFT;
		401	con_obj_num =
		402	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		403	>> ENUM_ID_SHIFT;
		404	con_obj_type =
		405	(le16_to_cpu(path->usConnObjectId) &
		406	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		407
1221	serge	408	/* TODO CV support */
		409	if (le16_to_cpu(path->usDeviceTag) ==
		410	ATOM_DEVICE_CV_SUPPORT)
1117	serge	411	continue;
		412
1268	serge	413	/* IGP chips */
		414	if ((rdev->flags & RADEON_IS_IGP) &&
1117	serge	415	(con_obj_id ==
		416	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		417	uint16_t igp_offset = 0;
		418	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		419
		420	index =
		421	GetIndexIntoMasterTable(DATA,
		422	IntegratedSystemInfo);
		423
		424	atom_parse_data_header(ctx, index, &size, &frev,
		425	&crev, &igp_offset);
		426
		427	if (crev >= 2) {
		428	igp_obj =
		429	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		430	*) (ctx->bios + igp_offset);
		431
		432	if (igp_obj) {
		433	uint32_t slot_config, ct;
		434
		435	if (con_obj_num == 1)
		436	slot_config =
		437	igp_obj->
		438	ulDDISlot1Config;
		439	else
		440	slot_config =
		441	igp_obj->
		442	ulDDISlot2Config;
		443
		444	ct = (slot_config >> 16) & 0xff;
		445	connector_type =
		446	object_connector_convert
		447	[ct];
1268	serge	448	connector_object_id = ct;
1117	serge	449	igp_lane_info =
		450	slot_config & 0xffff;
		451	} else
		452	continue;
		453	} else
		454	continue;
		455	} else {
		456	igp_lane_info = 0;
		457	connector_type =
		458	object_connector_convert[con_obj_id];
1268	serge	459	connector_object_id = con_obj_id;
1117	serge	460	}
		461
		462	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		463	continue;
		464
		465	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
		466	j++) {
		467	uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
		468
		469	enc_obj_id =
		470	(le16_to_cpu(path->usGraphicObjIds[j]) &
		471	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		472	enc_obj_num =
		473	(le16_to_cpu(path->usGraphicObjIds[j]) &
		474	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		475	enc_obj_type =
		476	(le16_to_cpu(path->usGraphicObjIds[j]) &
		477	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		478
		479	/* FIXME: add support for router objects */
		480	if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		481	if (enc_obj_num == 2)
		482	linkb = true;
		483	else
		484	linkb = false;
		485
1123	serge	486	radeon_add_atom_encoder(dev,
		487	enc_obj_id,
		488	le16_to_cpu
		489	(path->
		490	usDeviceTag));
1117	serge	491
		492	}
		493	}
		494
1321	serge	495	/* look up gpio for ddc, hpd */
1117	serge	496	if ((le16_to_cpu(path->usDeviceTag) &
1321	serge	497	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) == 0) {
1117	serge	498	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		499	if (le16_to_cpu(path->usConnObjectId) ==
		500	le16_to_cpu(con_obj->asObjects[j].
		501	usObjectID)) {
		502	ATOM_COMMON_RECORD_HEADER
		503	*record =
		504	(ATOM_COMMON_RECORD_HEADER
		505	*)
		506	(ctx->bios + data_offset +
		507	le16_to_cpu(con_obj->
		508	asObjects[j].
		509	usRecordOffset));
		510	ATOM_I2C_RECORD *i2c_record;
1321	serge	511	ATOM_HPD_INT_RECORD *hpd_record;
		512	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
		513	hpd.hpd = RADEON_HPD_NONE;
1117	serge	514
		515	while (record->ucRecordType > 0
		516	&& record->
		517	ucRecordType <=
		518	ATOM_MAX_OBJECT_RECORD_NUMBER) {
1321	serge	519	switch (record->ucRecordType) {
1117	serge	520	case ATOM_I2C_RECORD_TYPE:
		521	i2c_record =
1321	serge	522	(ATOM_I2C_RECORD *)
		523	record;
		524	i2c_config =
		525	(ATOM_I2C_ID_CONFIG_ACCESS *)
		526	&i2c_record->sucI2cId;
		527	ddc_bus = radeon_lookup_i2c_gpio(rdev,
		528	i2c_config->
		529	ucAccess);
1117	serge	530	break;
1321	serge	531	case ATOM_HPD_INT_RECORD_TYPE:
		532	hpd_record =
		533	(ATOM_HPD_INT_RECORD *)
		534	record;
		535	gpio = radeon_lookup_gpio(rdev,
		536	hpd_record->ucHPDIntGPIOID);
		537	hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
		538	hpd.plugged_state = hpd_record->ucPlugged_PinState;
		539	break;
1117	serge	540	}
		541	record =
		542	(ATOM_COMMON_RECORD_HEADER
		543	) ((char )record
		544	+
		545	record->
		546	ucRecordSize);
		547	}
		548	break;
		549	}
		550	}
1321	serge	551	} else {
		552	hpd.hpd = RADEON_HPD_NONE;
1117	serge	553	ddc_bus.valid = false;
1321	serge	554	}
1117	serge	555
1179	serge	556	conn_id = le16_to_cpu(path->usConnObjectId);
		557
		558	if (!radeon_atom_apply_quirks
		559	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
1321	serge	560	&ddc_bus, &conn_id, &hpd))
1179	serge	561	continue;
		562
1123	serge	563	radeon_add_atom_connector(dev,
1179	serge	564	conn_id,
1123	serge	565	le16_to_cpu(path->
		566	usDeviceTag),
		567	connector_type, &ddc_bus,
1268	serge	568	linkb, igp_lane_info,
1321	serge	569	connector_object_id,
		570	&hpd);
1117	serge	571
		572	}
		573	}
		574
1123	serge	575	radeon_link_encoder_connector(dev);
1117	serge	576
		577	return true;
		578	}
		579
1268	serge	580	static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
		581	int connector_type,
		582	uint16_t devices)
		583	{
		584	struct radeon_device *rdev = dev->dev_private;
		585
		586	if (rdev->flags & RADEON_IS_IGP) {
		587	return supported_devices_connector_object_id_convert
		588	[connector_type];
		589	} else if (((connector_type == DRM_MODE_CONNECTOR_DVII) \|\|
		590	(connector_type == DRM_MODE_CONNECTOR_DVID)) &&
		591	(devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		592	struct radeon_mode_info *mode_info = &rdev->mode_info;
		593	struct atom_context *ctx = mode_info->atom_context;
		594	int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
		595	uint16_t size, data_offset;
		596	uint8_t frev, crev;
		597	ATOM_XTMDS_INFO *xtmds;
		598
		599	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		600	xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
		601
		602	if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
		603	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		604	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		605	else
		606	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		607	} else {
		608	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		609	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		610	else
		611	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		612	}
		613	} else {
		614	return supported_devices_connector_object_id_convert
		615	[connector_type];
		616	}
		617	}
		618
1117	serge	619	struct bios_connector {
		620	bool valid;
1179	serge	621	uint16_t line_mux;
1117	serge	622	uint16_t devices;
		623	int connector_type;
		624	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	625	struct radeon_hpd hpd;
1117	serge	626	};
		627
		628	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		629	drm_device
		630	*dev)
		631	{
		632	struct radeon_device *rdev = dev->dev_private;
		633	struct radeon_mode_info *mode_info = &rdev->mode_info;
		634	struct atom_context *ctx = mode_info->atom_context;
		635	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		636	uint16_t size, data_offset;
		637	uint8_t frev, crev;
		638	uint16_t device_support;
		639	uint8_t dac;
		640	union atom_supported_devices *supported_devices;
1321	serge	641	int i, j, max_device;
1117	serge	642	struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
		643
		644	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
1128	serge	645
1117	serge	646	supported_devices =
		647	(union atom_supported_devices *)(ctx->bios + data_offset);
		648
		649	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		650
1321	serge	651	if (frev > 1)
		652	max_device = ATOM_MAX_SUPPORTED_DEVICE;
		653	else
		654	max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
		655
		656	for (i = 0; i < max_device; i++) {
1117	serge	657	ATOM_CONNECTOR_INFO_I2C ci =
		658	supported_devices->info.asConnInfo[i];
		659
		660	bios_connectors[i].valid = false;
		661
		662	if (!(device_support & (1 << i))) {
		663	continue;
		664	}
		665
		666	if (i == ATOM_DEVICE_CV_INDEX) {
		667	DRM_DEBUG("Skipping Component Video\n");
		668	continue;
		669	}
		670
		671	bios_connectors[i].connector_type =
		672	supported_devices_connector_convert[ci.sucConnectorInfo.
		673	sbfAccess.
		674	bfConnectorType];
		675
		676	if (bios_connectors[i].connector_type ==
		677	DRM_MODE_CONNECTOR_Unknown)
		678	continue;
		679
		680	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		681
		682	bios_connectors[i].line_mux =
1321	serge	683	ci.sucI2cId.ucAccess;
1117	serge	684
		685	/* give tv unique connector ids */
		686	if (i == ATOM_DEVICE_TV1_INDEX) {
		687	bios_connectors[i].ddc_bus.valid = false;
		688	bios_connectors[i].line_mux = 50;
		689	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		690	bios_connectors[i].ddc_bus.valid = false;
		691	bios_connectors[i].line_mux = 51;
		692	} else if (i == ATOM_DEVICE_CV_INDEX) {
		693	bios_connectors[i].ddc_bus.valid = false;
		694	bios_connectors[i].line_mux = 52;
		695	} else
		696	bios_connectors[i].ddc_bus =
1321	serge	697	radeon_lookup_i2c_gpio(rdev,
1117	serge	698	bios_connectors[i].line_mux);
		699
1321	serge	700	if ((crev > 1) && (frev > 1)) {
		701	u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
		702	switch (isb) {
		703	case 0x4:
		704	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		705	break;
		706	case 0xa:
		707	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		708	break;
		709	default:
		710	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		711	break;
		712	}
		713	} else {
		714	if (i == ATOM_DEVICE_DFP1_INDEX)
		715	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		716	else if (i == ATOM_DEVICE_DFP2_INDEX)
		717	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		718	else
		719	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		720	}
		721
1117	serge	722	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		723	* shared with a DVI port, we'll pick up the DVI connector when we
		724	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		725	*/
		726	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		727	bios_connectors[i].connector_type =
		728	DRM_MODE_CONNECTOR_VGA;
		729
		730	if (!radeon_atom_apply_quirks
		731	(dev, (1 << i), &bios_connectors[i].connector_type,
1321	serge	732	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
		733	&bios_connectors[i].hpd))
1117	serge	734	continue;
		735
		736	bios_connectors[i].valid = true;
		737	bios_connectors[i].devices = (1 << i);
		738
1123	serge	739	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		740	radeon_add_atom_encoder(dev,
		741	radeon_get_encoder_id(dev,
		742	(1 << i),
		743	dac),
		744	(1 << i));
		745	else
		746	radeon_add_legacy_encoder(dev,
		747	radeon_get_encoder_id(dev,
		748	(1 <<
		749	i),
		750	dac),
		751	(1 << i));
1117	serge	752	}
		753
		754	/* combine shared connectors */
1321	serge	755	for (i = 0; i < max_device; i++) {
1117	serge	756	if (bios_connectors[i].valid) {
1321	serge	757	for (j = 0; j < max_device; j++) {
1117	serge	758	if (bios_connectors[j].valid && (i != j)) {
		759	if (bios_connectors[i].line_mux ==
		760	bios_connectors[j].line_mux) {
		761	if (((bios_connectors[i].
		762	devices &
		763	(ATOM_DEVICE_DFP_SUPPORT))
		764	&& (bios_connectors[j].
		765	devices &
		766	(ATOM_DEVICE_CRT_SUPPORT)))
		767	\|\|
		768	((bios_connectors[j].
		769	devices &
		770	(ATOM_DEVICE_DFP_SUPPORT))
		771	&& (bios_connectors[i].
		772	devices &
		773	(ATOM_DEVICE_CRT_SUPPORT)))) {
		774	bios_connectors[i].
		775	devices \|=
		776	bios_connectors[j].
		777	devices;
		778	bios_connectors[i].
		779	connector_type =
		780	DRM_MODE_CONNECTOR_DVII;
1321	serge	781	if (bios_connectors[j].devices &
		782	(ATOM_DEVICE_DFP_SUPPORT))
		783	bios_connectors[i].hpd =
		784	bios_connectors[j].hpd;
1117	serge	785	bios_connectors[j].
		786	valid = false;
		787	}
		788	}
		789	}
		790	}
		791	}
		792	}
		793
		794	/* add the connectors */
1321	serge	795	for (i = 0; i < max_device; i++) {
1268	serge	796	if (bios_connectors[i].valid) {
		797	uint16_t connector_object_id =
		798	atombios_get_connector_object_id(dev,
		799	bios_connectors[i].connector_type,
		800	bios_connectors[i].devices);
1123	serge	801	radeon_add_atom_connector(dev,
		802	bios_connectors[i].line_mux,
		803	bios_connectors[i].devices,
		804	bios_connectors[i].
		805	connector_type,
		806	&bios_connectors[i].ddc_bus,
1268	serge	807	false, 0,
1321	serge	808	connector_object_id,
		809	&bios_connectors[i].hpd);
1268	serge	810	}
1123	serge	811	}
1117	serge	812
1123	serge	813	radeon_link_encoder_connector(dev);
1128	serge	814
1117	serge	815	return true;
		816	}
		817
		818	union firmware_info {
		819	ATOM_FIRMWARE_INFO info;
		820	ATOM_FIRMWARE_INFO_V1_2 info_12;
		821	ATOM_FIRMWARE_INFO_V1_3 info_13;
		822	ATOM_FIRMWARE_INFO_V1_4 info_14;
		823	};
		824
		825	bool radeon_atom_get_clock_info(struct drm_device *dev)
		826	{
		827	struct radeon_device *rdev = dev->dev_private;
		828	struct radeon_mode_info *mode_info = &rdev->mode_info;
		829	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		830	union firmware_info *firmware_info;
		831	uint8_t frev, crev;
		832	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		833	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		834	struct radeon_pll *spll = &rdev->clock.spll;
		835	struct radeon_pll *mpll = &rdev->clock.mpll;
		836	uint16_t data_offset;
		837
		838	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		839	&crev, &data_offset);
		840
		841	firmware_info =
		842	(union firmware_info *)(mode_info->atom_context->bios +
		843	data_offset);
		844
		845	if (firmware_info) {
		846	/* pixel clocks */
		847	p1pll->reference_freq =
		848	le16_to_cpu(firmware_info->info.usReferenceClock);
		849	p1pll->reference_div = 0;
		850
1268	serge	851	if (crev < 2)
1117	serge	852	p1pll->pll_out_min =
		853	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1268	serge	854	else
		855	p1pll->pll_out_min =
		856	le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117	serge	857	p1pll->pll_out_max =
		858	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		859
		860	if (p1pll->pll_out_min == 0) {
		861	if (ASIC_IS_AVIVO(rdev))
		862	p1pll->pll_out_min = 64800;
		863	else
		864	p1pll->pll_out_min = 20000;
1268	serge	865	} else if (p1pll->pll_out_min > 64800) {
		866	/* Limiting the pll output range is a good thing generally as
		867	* it limits the number of possible pll combinations for a given
		868	* frequency presumably to the ones that work best on each card.
		869	* However, certain duallink DVI monitors seem to like
		870	* pll combinations that would be limited by this at least on
		871	* pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
		872	* family.
		873	*/
1321	serge	874	if (!radeon_new_pll)
1268	serge	875	p1pll->pll_out_min = 64800;
1117	serge	876	}
		877
		878	p1pll->pll_in_min =
		879	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		880	p1pll->pll_in_max =
		881	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		882
		883	p2pll = p1pll;
		884
		885	/* system clock */
		886	spll->reference_freq =
		887	le16_to_cpu(firmware_info->info.usReferenceClock);
		888	spll->reference_div = 0;
		889
		890	spll->pll_out_min =
		891	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		892	spll->pll_out_max =
		893	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		894
		895	/* ??? */
		896	if (spll->pll_out_min == 0) {
		897	if (ASIC_IS_AVIVO(rdev))
		898	spll->pll_out_min = 64800;
		899	else
		900	spll->pll_out_min = 20000;
		901	}
		902
		903	spll->pll_in_min =
		904	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		905	spll->pll_in_max =
		906	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		907
		908	/* memory clock */
		909	mpll->reference_freq =
		910	le16_to_cpu(firmware_info->info.usReferenceClock);
		911	mpll->reference_div = 0;
		912
		913	mpll->pll_out_min =
		914	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		915	mpll->pll_out_max =
		916	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		917
		918	/* ??? */
		919	if (mpll->pll_out_min == 0) {
		920	if (ASIC_IS_AVIVO(rdev))
		921	mpll->pll_out_min = 64800;
		922	else
		923	mpll->pll_out_min = 20000;
		924	}
		925
		926	mpll->pll_in_min =
		927	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		928	mpll->pll_in_max =
		929	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		930
		931	rdev->clock.default_sclk =
		932	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		933	rdev->clock.default_mclk =
		934	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		935
		936	return true;
		937	}
		938	return false;
		939	}
		940
1179	serge	941	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		942	struct radeon_encoder_int_tmds *tmds)
1117	serge	943	{
		944	struct drm_device *dev = encoder->base.dev;
		945	struct radeon_device *rdev = dev->dev_private;
		946	struct radeon_mode_info *mode_info = &rdev->mode_info;
		947	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		948	uint16_t data_offset;
		949	struct _ATOM_TMDS_INFO *tmds_info;
		950	uint8_t frev, crev;
		951	uint16_t maxfreq;
		952	int i;
		953
		954	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		955	&crev, &data_offset);
		956
		957	tmds_info =
		958	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		959	data_offset);
		960
		961	if (tmds_info) {
		962	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		963	for (i = 0; i < 4; i++) {
		964	tmds->tmds_pll[i].freq =
		965	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		966	tmds->tmds_pll[i].value =
		967	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		968	tmds->tmds_pll[i].value \|=
		969	(tmds_info->asMiscInfo[i].
		970	ucPLL_VCO_Gain & 0x3f) << 6;
		971	tmds->tmds_pll[i].value \|=
		972	(tmds_info->asMiscInfo[i].
		973	ucPLL_DutyCycle & 0xf) << 12;
		974	tmds->tmds_pll[i].value \|=
		975	(tmds_info->asMiscInfo[i].
		976	ucPLL_VoltageSwing & 0xf) << 16;
		977
		978	DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
		979	tmds->tmds_pll[i].freq,
		980	tmds->tmds_pll[i].value);
		981
		982	if (maxfreq == tmds->tmds_pll[i].freq) {
		983	tmds->tmds_pll[i].freq = 0xffffffff;
		984	break;
		985	}
		986	}
1179	serge	987	return true;
1117	serge	988	}
1179	serge	989	return false;
1117	serge	990	}
		991
1268	serge	992	static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
		993	radeon_encoder
		994	*encoder,
		995	int id)
		996	{
		997	struct drm_device *dev = encoder->base.dev;
		998	struct radeon_device *rdev = dev->dev_private;
		999	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1000	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
		1001	uint16_t data_offset;
		1002	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
		1003	uint8_t frev, crev;
		1004	struct radeon_atom_ss *ss = NULL;
1321	serge	1005	int i;
1268	serge	1006
		1007	if (id > ATOM_MAX_SS_ENTRY)
		1008	return NULL;
		1009
		1010	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1011	&crev, &data_offset);
		1012
		1013	ss_info =
		1014	(struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
		1015
		1016	if (ss_info) {
		1017	ss =
		1018	kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
		1019
		1020	if (!ss)
		1021	return NULL;
		1022
1321	serge	1023	for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
		1024	if (ss_info->asSS_Info[i].ucSS_Id == id) {
		1025	ss->percentage =
		1026	le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
		1027	ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
		1028	ss->step = ss_info->asSS_Info[i].ucSS_Step;
		1029	ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
		1030	ss->range = ss_info->asSS_Info[i].ucSS_Range;
		1031	ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1268	serge	1032	}
1321	serge	1033	}
		1034	}
1268	serge	1035	return ss;
		1036	}
		1037
1117	serge	1038	union lvds_info {
		1039	struct _ATOM_LVDS_INFO info;
		1040	struct _ATOM_LVDS_INFO_V12 info_12;
		1041	};
		1042
		1043	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		1044	radeon_encoder
		1045	*encoder)
		1046	{
		1047	struct drm_device *dev = encoder->base.dev;
		1048	struct radeon_device *rdev = dev->dev_private;
		1049	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1050	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1321	serge	1051	uint16_t data_offset, misc;
1117	serge	1052	union lvds_info *lvds_info;
		1053	uint8_t frev, crev;
		1054	struct radeon_encoder_atom_dig *lvds = NULL;
		1055
		1056	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1057	&crev, &data_offset);
		1058
		1059	lvds_info =
		1060	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		1061
		1062	if (lvds_info) {
		1063	lvds =
		1064	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1065
		1066	if (!lvds)
		1067	return NULL;
		1068
1268	serge	1069	lvds->native_mode.clock =
1117	serge	1070	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1268	serge	1071	lvds->native_mode.hdisplay =
1117	serge	1072	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1268	serge	1073	lvds->native_mode.vdisplay =
1117	serge	1074	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1268	serge	1075	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1117	serge	1076	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1268	serge	1077	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1117	serge	1078	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1268	serge	1079	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1117	serge	1080	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1268	serge	1081	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1117	serge	1082	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1268	serge	1083	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
		1084	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1085	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1117	serge	1086	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1087	lvds->panel_pwr_delay =
		1088	le16_to_cpu(lvds_info->info.usOffDelayInMs);
		1089	lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1321	serge	1090
		1091	misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
		1092	if (misc & ATOM_VSYNC_POLARITY)
		1093	lvds->native_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		1094	if (misc & ATOM_HSYNC_POLARITY)
		1095	lvds->native_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		1096	if (misc & ATOM_COMPOSITESYNC)
		1097	lvds->native_mode.flags \|= DRM_MODE_FLAG_CSYNC;
		1098	if (misc & ATOM_INTERLACE)
		1099	lvds->native_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		1100	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1101	lvds->native_mode.flags \|= DRM_MODE_FLAG_DBLSCAN;
		1102
1268	serge	1103	/* set crtc values */
		1104	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1117	serge	1105
1268	serge	1106	lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
		1107
1117	serge	1108	encoder->native_mode = lvds->native_mode;
		1109	}
		1110	return lvds;
		1111	}
		1112
		1113	struct radeon_encoder_primary_dac *
		1114	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		1115	{
		1116	struct drm_device *dev = encoder->base.dev;
		1117	struct radeon_device *rdev = dev->dev_private;
		1118	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1119	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1120	uint16_t data_offset;
		1121	struct _COMPASSIONATE_DATA *dac_info;
		1122	uint8_t frev, crev;
		1123	uint8_t bg, dac;
		1124	struct radeon_encoder_primary_dac *p_dac = NULL;
		1125
		1126	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1127
		1128	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		1129
		1130	if (dac_info) {
		1131	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		1132
		1133	if (!p_dac)
		1134	return NULL;
		1135
		1136	bg = dac_info->ucDAC1_BG_Adjustment;
		1137	dac = dac_info->ucDAC1_DAC_Adjustment;
		1138	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		1139
		1140	}
		1141	return p_dac;
		1142	}
		1143
1179	serge	1144	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1268	serge	1145	struct drm_display_mode *mode)
1179	serge	1146	{
		1147	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1148	ATOM_ANALOG_TV_INFO *tv_info;
		1149	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		1150	ATOM_DTD_FORMAT *dtd_timings;
		1151	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1152	u8 frev, crev;
1268	serge	1153	u16 data_offset, misc;
1179	serge	1154
		1155	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
		1156
		1157	switch (crev) {
		1158	case 1:
		1159	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		1160	if (index > MAX_SUPPORTED_TV_TIMING)
		1161	return false;
		1162
1268	serge	1163	mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		1164	mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		1165	mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		1166	mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
		1167	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1179	serge	1168
1268	serge	1169	mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		1170	mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		1171	mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		1172	mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
		1173	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1179	serge	1174
1268	serge	1175	mode->flags = 0;
		1176	misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
		1177	if (misc & ATOM_VSYNC_POLARITY)
		1178	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1179	if (misc & ATOM_HSYNC_POLARITY)
		1180	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1181	if (misc & ATOM_COMPOSITESYNC)
		1182	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1183	if (misc & ATOM_INTERLACE)
		1184	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1185	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1186	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
1179	serge	1187
1268	serge	1188	mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1179	serge	1189
		1190	if (index == 1) {
		1191	/* PAL timings appear to have wrong values for totals */
1268	serge	1192	mode->crtc_htotal -= 1;
		1193	mode->crtc_vtotal -= 1;
1179	serge	1194	}
		1195	break;
		1196	case 2:
		1197	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
		1198	if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
		1199	return false;
		1200
		1201	dtd_timings = &tv_info_v1_2->aModeTimings[index];
1268	serge	1202	mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
		1203	le16_to_cpu(dtd_timings->usHBlanking_Time);
		1204	mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
		1205	mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
		1206	le16_to_cpu(dtd_timings->usHSyncOffset);
		1207	mode->crtc_hsync_end = mode->crtc_hsync_start +
		1208	le16_to_cpu(dtd_timings->usHSyncWidth);
1179	serge	1209
1268	serge	1210	mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
		1211	le16_to_cpu(dtd_timings->usVBlanking_Time);
		1212	mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
		1213	mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
		1214	le16_to_cpu(dtd_timings->usVSyncOffset);
		1215	mode->crtc_vsync_end = mode->crtc_vsync_start +
		1216	le16_to_cpu(dtd_timings->usVSyncWidth);
		1217
		1218	mode->flags = 0;
		1219	misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		1220	if (misc & ATOM_VSYNC_POLARITY)
		1221	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1222	if (misc & ATOM_HSYNC_POLARITY)
		1223	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1224	if (misc & ATOM_COMPOSITESYNC)
		1225	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1226	if (misc & ATOM_INTERLACE)
		1227	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1228	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1229	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
		1230
		1231	mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1179	serge	1232	break;
		1233	}
		1234	return true;
		1235	}
		1236
1117	serge	1237	struct radeon_encoder_tv_dac *
		1238	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		1239	{
		1240	struct drm_device *dev = encoder->base.dev;
		1241	struct radeon_device *rdev = dev->dev_private;
		1242	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1243	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1244	uint16_t data_offset;
		1245	struct _COMPASSIONATE_DATA *dac_info;
		1246	uint8_t frev, crev;
		1247	uint8_t bg, dac;
		1248	struct radeon_encoder_tv_dac *tv_dac = NULL;
		1249
		1250	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1251
		1252	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		1253
		1254	if (dac_info) {
		1255	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1256
		1257	if (!tv_dac)
		1258	return NULL;
		1259
		1260	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		1261	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		1262	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1263
		1264	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		1265	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		1266	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1267
		1268	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		1269	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		1270	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		1271
		1272	}
		1273	return tv_dac;
		1274	}
		1275
		1276	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
		1277	{
		1278	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		1279	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
		1280
		1281	args.ucEnable = enable;
		1282
		1283	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1284	}
		1285
		1286	void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
		1287	{
		1288	ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
		1289	int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
		1290
		1291	args.ucEnable = enable;
		1292
		1293	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1294	}
		1295
1268	serge	1296	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
		1297	{
		1298	GET_ENGINE_CLOCK_PS_ALLOCATION args;
		1299	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
		1300
		1301	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1302	return args.ulReturnEngineClock;
		1303	}
		1304
		1305	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
		1306	{
		1307	GET_MEMORY_CLOCK_PS_ALLOCATION args;
		1308	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
		1309
		1310	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1311	return args.ulReturnMemoryClock;
		1312	}
		1313
1117	serge	1314	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		1315	uint32_t eng_clock)
		1316	{
		1317	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		1318	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		1319
		1320	args.ulTargetEngineClock = eng_clock; /* 10 khz */
		1321
		1322	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1323	}
		1324
		1325	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		1326	uint32_t mem_clock)
		1327	{
		1328	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		1329	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		1330
		1331	if (rdev->flags & RADEON_IS_IGP)
		1332	return;
		1333
		1334	args.ulTargetMemoryClock = mem_clock; /* 10 khz */
		1335
		1336	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1337	}
		1338
		1339	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		1340	{
		1341	struct radeon_device *rdev = dev->dev_private;
		1342	uint32_t bios_2_scratch, bios_6_scratch;
		1343
		1344	if (rdev->family >= CHIP_R600) {
1179	serge	1345	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	1346	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1347	} else {
1179	serge	1348	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	1349	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1350	}
		1351
		1352	/* let the bios control the backlight */
		1353	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		1354
		1355	/* tell the bios not to handle mode switching */
		1356	bios_6_scratch \|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH \| ATOM_S6_ACC_MODE);
		1357
		1358	if (rdev->family >= CHIP_R600) {
		1359	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1360	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1361	} else {
		1362	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1363	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1364	}
		1365
		1366	}
		1367
1179	serge	1368	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		1369	{
		1370	uint32_t scratch_reg;
		1371	int i;
		1372
		1373	if (rdev->family >= CHIP_R600)
		1374	scratch_reg = R600_BIOS_0_SCRATCH;
		1375	else
		1376	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1377
		1378	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1379	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		1380	}
		1381
		1382	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		1383	{
		1384	uint32_t scratch_reg;
		1385	int i;
		1386
		1387	if (rdev->family >= CHIP_R600)
		1388	scratch_reg = R600_BIOS_0_SCRATCH;
		1389	else
		1390	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1391
		1392	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1393	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		1394	}
		1395
1117	serge	1396	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		1397	{
		1398	struct drm_device *dev = encoder->dev;
		1399	struct radeon_device *rdev = dev->dev_private;
		1400	uint32_t bios_6_scratch;
		1401
		1402	if (rdev->family >= CHIP_R600)
		1403	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1404	else
		1405	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1406
		1407	if (lock)
		1408	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
		1409	else
		1410	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
		1411
		1412	if (rdev->family >= CHIP_R600)
		1413	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1414	else
		1415	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1416	}
		1417
		1418	/* at some point we may want to break this out into individual functions */
		1419	void
		1420	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		1421	struct drm_encoder *encoder,
		1422	bool connected)
		1423	{
		1424	struct drm_device *dev = connector->dev;
		1425	struct radeon_device *rdev = dev->dev_private;
		1426	struct radeon_connector *radeon_connector =
		1427	to_radeon_connector(connector);
		1428	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1429	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		1430
		1431	if (rdev->family >= CHIP_R600) {
		1432	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1433	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1434	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1435	} else {
		1436	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1437	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1438	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1439	}
		1440
		1441	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		1442	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		1443	if (connected) {
		1444	DRM_DEBUG("TV1 connected\n");
		1445	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		1446	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		1447	} else {
		1448	DRM_DEBUG("TV1 disconnected\n");
		1449	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		1450	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		1451	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		1452	}
		1453	}
		1454	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		1455	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		1456	if (connected) {
		1457	DRM_DEBUG("CV connected\n");
		1458	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		1459	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		1460	} else {
		1461	DRM_DEBUG("CV disconnected\n");
		1462	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		1463	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		1464	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		1465	}
		1466	}
		1467	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		1468	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		1469	if (connected) {
		1470	DRM_DEBUG("LCD1 connected\n");
		1471	bios_0_scratch \|= ATOM_S0_LCD1;
		1472	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		1473	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		1474	} else {
		1475	DRM_DEBUG("LCD1 disconnected\n");
		1476	bios_0_scratch &= ~ATOM_S0_LCD1;
		1477	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		1478	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		1479	}
		1480	}
		1481	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		1482	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		1483	if (connected) {
		1484	DRM_DEBUG("CRT1 connected\n");
		1485	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		1486	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		1487	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		1488	} else {
		1489	DRM_DEBUG("CRT1 disconnected\n");
		1490	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		1491	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		1492	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		1493	}
		1494	}
		1495	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		1496	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		1497	if (connected) {
		1498	DRM_DEBUG("CRT2 connected\n");
		1499	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		1500	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		1501	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		1502	} else {
		1503	DRM_DEBUG("CRT2 disconnected\n");
		1504	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		1505	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		1506	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		1507	}
		1508	}
		1509	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		1510	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		1511	if (connected) {
		1512	DRM_DEBUG("DFP1 connected\n");
		1513	bios_0_scratch \|= ATOM_S0_DFP1;
		1514	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		1515	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		1516	} else {
		1517	DRM_DEBUG("DFP1 disconnected\n");
		1518	bios_0_scratch &= ~ATOM_S0_DFP1;
		1519	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		1520	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		1521	}
		1522	}
		1523	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		1524	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		1525	if (connected) {
		1526	DRM_DEBUG("DFP2 connected\n");
		1527	bios_0_scratch \|= ATOM_S0_DFP2;
		1528	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		1529	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		1530	} else {
		1531	DRM_DEBUG("DFP2 disconnected\n");
		1532	bios_0_scratch &= ~ATOM_S0_DFP2;
		1533	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		1534	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		1535	}
		1536	}
		1537	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		1538	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		1539	if (connected) {
		1540	DRM_DEBUG("DFP3 connected\n");
		1541	bios_0_scratch \|= ATOM_S0_DFP3;
		1542	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		1543	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		1544	} else {
		1545	DRM_DEBUG("DFP3 disconnected\n");
		1546	bios_0_scratch &= ~ATOM_S0_DFP3;
		1547	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		1548	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		1549	}
		1550	}
		1551	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		1552	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		1553	if (connected) {
		1554	DRM_DEBUG("DFP4 connected\n");
		1555	bios_0_scratch \|= ATOM_S0_DFP4;
		1556	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		1557	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		1558	} else {
		1559	DRM_DEBUG("DFP4 disconnected\n");
		1560	bios_0_scratch &= ~ATOM_S0_DFP4;
		1561	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		1562	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		1563	}
		1564	}
		1565	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		1566	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		1567	if (connected) {
		1568	DRM_DEBUG("DFP5 connected\n");
		1569	bios_0_scratch \|= ATOM_S0_DFP5;
		1570	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		1571	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		1572	} else {
		1573	DRM_DEBUG("DFP5 disconnected\n");
		1574	bios_0_scratch &= ~ATOM_S0_DFP5;
		1575	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		1576	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		1577	}
		1578	}
		1579
		1580	if (rdev->family >= CHIP_R600) {
		1581	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		1582	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1583	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1584	} else {
		1585	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		1586	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1587	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1588	}
		1589	}
		1590
		1591	void
		1592	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		1593	{
		1594	struct drm_device *dev = encoder->dev;
		1595	struct radeon_device *rdev = dev->dev_private;
		1596	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1597	uint32_t bios_3_scratch;
		1598
		1599	if (rdev->family >= CHIP_R600)
		1600	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1601	else
		1602	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1603
		1604	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1605	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		1606	bios_3_scratch \|= (crtc << 18);
		1607	}
		1608	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1609	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		1610	bios_3_scratch \|= (crtc << 24);
		1611	}
		1612	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1613	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		1614	bios_3_scratch \|= (crtc << 16);
		1615	}
		1616	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1617	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		1618	bios_3_scratch \|= (crtc << 20);
		1619	}
		1620	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1621	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		1622	bios_3_scratch \|= (crtc << 17);
		1623	}
		1624	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1625	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		1626	bios_3_scratch \|= (crtc << 19);
		1627	}
		1628	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1629	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		1630	bios_3_scratch \|= (crtc << 23);
		1631	}
		1632	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1633	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		1634	bios_3_scratch \|= (crtc << 25);
		1635	}
		1636
		1637	if (rdev->family >= CHIP_R600)
		1638	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1639	else
		1640	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1641	}
		1642
		1643	void
		1644	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		1645	{
		1646	struct drm_device *dev = encoder->dev;
		1647	struct radeon_device *rdev = dev->dev_private;
		1648	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1649	uint32_t bios_2_scratch;
		1650
		1651	if (rdev->family >= CHIP_R600)
		1652	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		1653	else
		1654	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		1655
		1656	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1657	if (on)
		1658	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		1659	else
		1660	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		1661	}
		1662	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1663	if (on)
		1664	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		1665	else
		1666	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		1667	}
		1668	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1669	if (on)
		1670	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		1671	else
		1672	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		1673	}
		1674	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1675	if (on)
		1676	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		1677	else
		1678	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		1679	}
		1680	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1681	if (on)
		1682	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		1683	else
		1684	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		1685	}
		1686	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1687	if (on)
		1688	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		1689	else
		1690	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		1691	}
		1692	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1693	if (on)
		1694	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		1695	else
		1696	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		1697	}
		1698	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1699	if (on)
		1700	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		1701	else
		1702	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		1703	}
		1704	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		1705	if (on)
		1706	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		1707	else
		1708	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		1709	}
		1710	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		1711	if (on)
		1712	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		1713	else
		1714	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		1715	}
		1716
		1717	if (rdev->family >= CHIP_R600)
		1718	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1719	else
		1720	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1721	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 1321