WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1123	serge	26	#include "drmP.h"
1117	serge	27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
		35	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
		39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
		40	uint32_t supported_device);
		41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
		49	bool linkb, uint32_t igp_lane_info);
		50
		51	/* from radeon_legacy_encoder.c */
		52	extern void
		53	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		54	uint32_t supported_device);
		55
		56	union atom_supported_devices {
		57	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		58	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		59	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		60	};
		61
		62	static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
		63	*dev, uint8_t id)
		64	{
		65	struct radeon_device *rdev = dev->dev_private;
		66	struct atom_context *ctx = rdev->mode_info.atom_context;
		67	ATOM_GPIO_I2C_ASSIGMENT gpio;
		68	struct radeon_i2c_bus_rec i2c;
		69	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		70	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		71	uint16_t data_offset;
		72
		73	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		74	i2c.valid = false;
		75
		76	atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
		77
		78	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		79
		80	gpio = i2c_info->asGPIO_Info[id];
		81
		82	i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
		83	i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
		84	i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
		85	i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
		86	i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
		87	i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
		88	i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
		89	i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
		90	i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
		91	i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
		92	i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
		93	i2c.put_data_mask = (1 << gpio.ucDataEnShift);
		94	i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
		95	i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
		96	i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
		97	i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
		98	i2c.valid = true;
		99
		100	return i2c;
		101	}
		102
		103	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		104	uint32_t supported_device,
		105	int *connector_type,
1179	serge	106	struct radeon_i2c_bus_rec *i2c_bus,
		107	uint16_t *line_mux)
1117	serge	108	{
		109
		110	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		111	if ((dev->pdev->device == 0x791e) &&
		112	(dev->pdev->subsystem_vendor == 0x1043) &&
		113	(dev->pdev->subsystem_device == 0x826d)) {
		114	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		115	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		116	*connector_type = DRM_MODE_CONNECTOR_DVID;
		117	}
		118
		119	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		120	if ((dev->pdev->device == 0x7941) &&
		121	(dev->pdev->subsystem_vendor == 0x147b) &&
		122	(dev->pdev->subsystem_device == 0x2412)) {
		123	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		124	return false;
		125	}
		126
		127	/* Falcon NW laptop lists vga ddc line for LVDS */
		128	if ((dev->pdev->device == 0x5653) &&
		129	(dev->pdev->subsystem_vendor == 0x1462) &&
		130	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	131	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	132	i2c_bus->valid = false;
1179	serge	133	*line_mux = 53;
		134	}
1117	serge	135	}
		136
		137	/* Funky macbooks */
		138	if ((dev->pdev->device == 0x71C5) &&
		139	(dev->pdev->subsystem_vendor == 0x106b) &&
		140	(dev->pdev->subsystem_device == 0x0080)) {
		141	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		142	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		143	return false;
		144	}
		145
		146	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		147	if ((dev->pdev->device == 0x9598) &&
		148	(dev->pdev->subsystem_vendor == 0x1043) &&
		149	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	150	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		151	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	152	}
		153	}
		154
1179	serge	155	/* ASUS HD 3450 board lists the DVI port as HDMI */
		156	if ((dev->pdev->device == 0x95C5) &&
		157	(dev->pdev->subsystem_vendor == 0x1043) &&
		158	(dev->pdev->subsystem_device == 0x01e2)) {
		159	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		160	*connector_type = DRM_MODE_CONNECTOR_DVII;
		161	}
		162	}
		163
		164	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		165	* HDMI + VGA reporting as HDMI
		166	*/
		167	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		168	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		169	*connector_type = DRM_MODE_CONNECTOR_VGA;
		170	*line_mux = 0;
		171	}
		172	}
		173
1117	serge	174	return true;
		175	}
		176
		177	const int supported_devices_connector_convert[] = {
		178	DRM_MODE_CONNECTOR_Unknown,
		179	DRM_MODE_CONNECTOR_VGA,
		180	DRM_MODE_CONNECTOR_DVII,
		181	DRM_MODE_CONNECTOR_DVID,
		182	DRM_MODE_CONNECTOR_DVIA,
		183	DRM_MODE_CONNECTOR_SVIDEO,
		184	DRM_MODE_CONNECTOR_Composite,
		185	DRM_MODE_CONNECTOR_LVDS,
		186	DRM_MODE_CONNECTOR_Unknown,
		187	DRM_MODE_CONNECTOR_Unknown,
		188	DRM_MODE_CONNECTOR_HDMIA,
		189	DRM_MODE_CONNECTOR_HDMIB,
		190	DRM_MODE_CONNECTOR_Unknown,
		191	DRM_MODE_CONNECTOR_Unknown,
		192	DRM_MODE_CONNECTOR_9PinDIN,
		193	DRM_MODE_CONNECTOR_DisplayPort
		194	};
		195
		196	const int object_connector_convert[] = {
		197	DRM_MODE_CONNECTOR_Unknown,
		198	DRM_MODE_CONNECTOR_DVII,
		199	DRM_MODE_CONNECTOR_DVII,
		200	DRM_MODE_CONNECTOR_DVID,
		201	DRM_MODE_CONNECTOR_DVID,
		202	DRM_MODE_CONNECTOR_VGA,
		203	DRM_MODE_CONNECTOR_Composite,
		204	DRM_MODE_CONNECTOR_SVIDEO,
		205	DRM_MODE_CONNECTOR_Unknown,
1179	serge	206	DRM_MODE_CONNECTOR_Unknown,
1117	serge	207	DRM_MODE_CONNECTOR_9PinDIN,
		208	DRM_MODE_CONNECTOR_Unknown,
		209	DRM_MODE_CONNECTOR_HDMIA,
		210	DRM_MODE_CONNECTOR_HDMIB,
		211	DRM_MODE_CONNECTOR_LVDS,
		212	DRM_MODE_CONNECTOR_9PinDIN,
		213	DRM_MODE_CONNECTOR_Unknown,
		214	DRM_MODE_CONNECTOR_Unknown,
		215	DRM_MODE_CONNECTOR_Unknown,
		216	DRM_MODE_CONNECTOR_DisplayPort
		217	};
		218
		219	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		220	{
		221	struct radeon_device *rdev = dev->dev_private;
		222	struct radeon_mode_info *mode_info = &rdev->mode_info;
		223	struct atom_context *ctx = mode_info->atom_context;
		224	int index = GetIndexIntoMasterTable(DATA, Object_Header);
		225	uint16_t size, data_offset;
		226	uint8_t frev, crev, line_mux = 0;
		227	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
		228	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		229	ATOM_OBJECT_HEADER *obj_header;
		230	int i, j, path_size, device_support;
		231	int connector_type;
1179	serge	232	uint16_t igp_lane_info, conn_id;
1117	serge	233	bool linkb;
		234	struct radeon_i2c_bus_rec ddc_bus;
		235
		236	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		237
		238	if (data_offset == 0)
		239	return false;
		240
		241	if (crev < 2)
		242	return false;
		243
		244	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		245	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		246	(ctx->bios + data_offset +
		247	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		248	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		249	(ctx->bios + data_offset +
		250	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
		251	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		252
		253	path_size = 0;
		254	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		255	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		256	ATOM_DISPLAY_OBJECT_PATH *path;
		257	addr += path_size;
		258	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		259	path_size += le16_to_cpu(path->usSize);
		260	linkb = false;
		261
		262	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		263	uint8_t con_obj_id, con_obj_num, con_obj_type;
		264
		265	con_obj_id =
		266	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		267	>> OBJECT_ID_SHIFT;
		268	con_obj_num =
		269	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		270	>> ENUM_ID_SHIFT;
		271	con_obj_type =
		272	(le16_to_cpu(path->usConnObjectId) &
		273	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		274
		275	if ((le16_to_cpu(path->usDeviceTag) ==
		276	ATOM_DEVICE_TV1_SUPPORT)
		277	\|\| (le16_to_cpu(path->usDeviceTag) ==
		278	ATOM_DEVICE_TV2_SUPPORT)
		279	\|\| (le16_to_cpu(path->usDeviceTag) ==
		280	ATOM_DEVICE_CV_SUPPORT))
		281	continue;
		282
		283	if ((rdev->family == CHIP_RS780) &&
		284	(con_obj_id ==
		285	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		286	uint16_t igp_offset = 0;
		287	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		288
		289	index =
		290	GetIndexIntoMasterTable(DATA,
		291	IntegratedSystemInfo);
		292
		293	atom_parse_data_header(ctx, index, &size, &frev,
		294	&crev, &igp_offset);
		295
		296	if (crev >= 2) {
		297	igp_obj =
		298	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		299	*) (ctx->bios + igp_offset);
		300
		301	if (igp_obj) {
		302	uint32_t slot_config, ct;
		303
		304	if (con_obj_num == 1)
		305	slot_config =
		306	igp_obj->
		307	ulDDISlot1Config;
		308	else
		309	slot_config =
		310	igp_obj->
		311	ulDDISlot2Config;
		312
		313	ct = (slot_config >> 16) & 0xff;
		314	connector_type =
		315	object_connector_convert
		316	[ct];
		317	igp_lane_info =
		318	slot_config & 0xffff;
		319	} else
		320	continue;
		321	} else
		322	continue;
		323	} else {
		324	igp_lane_info = 0;
		325	connector_type =
		326	object_connector_convert[con_obj_id];
		327	}
		328
		329	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		330	continue;
		331
		332	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
		333	j++) {
		334	uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
		335
		336	enc_obj_id =
		337	(le16_to_cpu(path->usGraphicObjIds[j]) &
		338	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		339	enc_obj_num =
		340	(le16_to_cpu(path->usGraphicObjIds[j]) &
		341	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		342	enc_obj_type =
		343	(le16_to_cpu(path->usGraphicObjIds[j]) &
		344	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		345
		346	/* FIXME: add support for router objects */
		347	if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		348	if (enc_obj_num == 2)
		349	linkb = true;
		350	else
		351	linkb = false;
		352
1123	serge	353	radeon_add_atom_encoder(dev,
		354	enc_obj_id,
		355	le16_to_cpu
		356	(path->
		357	usDeviceTag));
1117	serge	358
		359	}
		360	}
		361
		362	/* look up gpio for ddc */
		363	if ((le16_to_cpu(path->usDeviceTag) &
		364	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		365	== 0) {
		366	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		367	if (le16_to_cpu(path->usConnObjectId) ==
		368	le16_to_cpu(con_obj->asObjects[j].
		369	usObjectID)) {
		370	ATOM_COMMON_RECORD_HEADER
		371	*record =
		372	(ATOM_COMMON_RECORD_HEADER
		373	*)
		374	(ctx->bios + data_offset +
		375	le16_to_cpu(con_obj->
		376	asObjects[j].
		377	usRecordOffset));
		378	ATOM_I2C_RECORD *i2c_record;
		379
		380	while (record->ucRecordType > 0
		381	&& record->
		382	ucRecordType <=
		383	ATOM_MAX_OBJECT_RECORD_NUMBER) {
		384	switch (record->
		385	ucRecordType) {
		386	case ATOM_I2C_RECORD_TYPE:
		387	i2c_record =
		388	(ATOM_I2C_RECORD
		389	*) record;
		390	line_mux =
		391	i2c_record->
		392	sucI2cId.
		393	bfI2C_LineMux;
		394	break;
		395	}
		396	record =
		397	(ATOM_COMMON_RECORD_HEADER
		398	) ((char )record
		399	+
		400	record->
		401	ucRecordSize);
		402	}
		403	break;
		404	}
		405	}
		406	} else
		407	line_mux = 0;
		408
		409	if ((le16_to_cpu(path->usDeviceTag) ==
		410	ATOM_DEVICE_TV1_SUPPORT)
		411	\|\| (le16_to_cpu(path->usDeviceTag) ==
		412	ATOM_DEVICE_TV2_SUPPORT)
		413	\|\| (le16_to_cpu(path->usDeviceTag) ==
		414	ATOM_DEVICE_CV_SUPPORT))
		415	ddc_bus.valid = false;
		416	else
		417	ddc_bus = radeon_lookup_gpio(dev, line_mux);
		418
1179	serge	419	conn_id = le16_to_cpu(path->usConnObjectId);
		420
		421	if (!radeon_atom_apply_quirks
		422	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
		423	&ddc_bus, &conn_id))
		424	continue;
		425
1123	serge	426	radeon_add_atom_connector(dev,
1179	serge	427	conn_id,
1123	serge	428	le16_to_cpu(path->
		429	usDeviceTag),
		430	connector_type, &ddc_bus,
		431	linkb, igp_lane_info);
1117	serge	432
		433	}
		434	}
		435
1123	serge	436	radeon_link_encoder_connector(dev);
1117	serge	437
		438	return true;
		439	}
		440
		441	struct bios_connector {
		442	bool valid;
1179	serge	443	uint16_t line_mux;
1117	serge	444	uint16_t devices;
		445	int connector_type;
		446	struct radeon_i2c_bus_rec ddc_bus;
		447	};
		448
		449	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		450	drm_device
		451	*dev)
		452	{
		453	struct radeon_device *rdev = dev->dev_private;
		454	struct radeon_mode_info *mode_info = &rdev->mode_info;
		455	struct atom_context *ctx = mode_info->atom_context;
		456	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		457	uint16_t size, data_offset;
		458	uint8_t frev, crev;
		459	uint16_t device_support;
		460	uint8_t dac;
		461	union atom_supported_devices *supported_devices;
		462	int i, j;
		463	struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
		464
		465	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
1128	serge	466
1117	serge	467	supported_devices =
		468	(union atom_supported_devices *)(ctx->bios + data_offset);
		469
		470	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		471
		472	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		473	ATOM_CONNECTOR_INFO_I2C ci =
		474	supported_devices->info.asConnInfo[i];
		475
		476	bios_connectors[i].valid = false;
		477
		478	if (!(device_support & (1 << i))) {
		479	continue;
		480	}
		481
		482	if (i == ATOM_DEVICE_CV_INDEX) {
		483	DRM_DEBUG("Skipping Component Video\n");
		484	continue;
		485	}
		486
		487	bios_connectors[i].connector_type =
		488	supported_devices_connector_convert[ci.sucConnectorInfo.
		489	sbfAccess.
		490	bfConnectorType];
		491
		492	if (bios_connectors[i].connector_type ==
		493	DRM_MODE_CONNECTOR_Unknown)
		494	continue;
		495
		496	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		497
		498	if ((rdev->family == CHIP_RS690) \|\|
		499	(rdev->family == CHIP_RS740)) {
		500	if ((i == ATOM_DEVICE_DFP2_INDEX)
		501	&& (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
		502	bios_connectors[i].line_mux =
		503	ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
		504	else if ((i == ATOM_DEVICE_DFP3_INDEX)
		505	&& (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
		506	bios_connectors[i].line_mux =
		507	ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
		508	else
		509	bios_connectors[i].line_mux =
		510	ci.sucI2cId.sbfAccess.bfI2C_LineMux;
		511	} else
		512	bios_connectors[i].line_mux =
		513	ci.sucI2cId.sbfAccess.bfI2C_LineMux;
		514
		515	/* give tv unique connector ids */
		516	if (i == ATOM_DEVICE_TV1_INDEX) {
		517	bios_connectors[i].ddc_bus.valid = false;
		518	bios_connectors[i].line_mux = 50;
		519	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		520	bios_connectors[i].ddc_bus.valid = false;
		521	bios_connectors[i].line_mux = 51;
		522	} else if (i == ATOM_DEVICE_CV_INDEX) {
		523	bios_connectors[i].ddc_bus.valid = false;
		524	bios_connectors[i].line_mux = 52;
		525	} else
		526	bios_connectors[i].ddc_bus =
		527	radeon_lookup_gpio(dev,
		528	bios_connectors[i].line_mux);
		529
		530	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		531	* shared with a DVI port, we'll pick up the DVI connector when we
		532	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		533	*/
		534	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		535	bios_connectors[i].connector_type =
		536	DRM_MODE_CONNECTOR_VGA;
		537
		538	if (!radeon_atom_apply_quirks
		539	(dev, (1 << i), &bios_connectors[i].connector_type,
1179	serge	540	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
1117	serge	541	continue;
		542
		543	bios_connectors[i].valid = true;
		544	bios_connectors[i].devices = (1 << i);
		545
1123	serge	546	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		547	radeon_add_atom_encoder(dev,
		548	radeon_get_encoder_id(dev,
		549	(1 << i),
		550	dac),
		551	(1 << i));
		552	else
		553	radeon_add_legacy_encoder(dev,
		554	radeon_get_encoder_id(dev,
		555	(1 <<
		556	i),
		557	dac),
		558	(1 << i));
1117	serge	559	}
		560
		561	/* combine shared connectors */
		562	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		563	if (bios_connectors[i].valid) {
		564	for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
		565	if (bios_connectors[j].valid && (i != j)) {
		566	if (bios_connectors[i].line_mux ==
		567	bios_connectors[j].line_mux) {
		568	if (((bios_connectors[i].
		569	devices &
		570	(ATOM_DEVICE_DFP_SUPPORT))
		571	&& (bios_connectors[j].
		572	devices &
		573	(ATOM_DEVICE_CRT_SUPPORT)))
		574	\|\|
		575	((bios_connectors[j].
		576	devices &
		577	(ATOM_DEVICE_DFP_SUPPORT))
		578	&& (bios_connectors[i].
		579	devices &
		580	(ATOM_DEVICE_CRT_SUPPORT)))) {
		581	bios_connectors[i].
		582	devices \|=
		583	bios_connectors[j].
		584	devices;
		585	bios_connectors[i].
		586	connector_type =
		587	DRM_MODE_CONNECTOR_DVII;
		588	bios_connectors[j].
		589	valid = false;
		590	}
		591	}
		592	}
		593	}
		594	}
		595	}
		596
		597	/* add the connectors */
1123	serge	598	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		599	if (bios_connectors[i].valid)
		600	radeon_add_atom_connector(dev,
		601	bios_connectors[i].line_mux,
		602	bios_connectors[i].devices,
		603	bios_connectors[i].
		604	connector_type,
		605	&bios_connectors[i].ddc_bus,
		606	false, 0);
		607	}
1117	serge	608
1123	serge	609	radeon_link_encoder_connector(dev);
1128	serge	610
1117	serge	611	return true;
		612	}
		613
		614	union firmware_info {
		615	ATOM_FIRMWARE_INFO info;
		616	ATOM_FIRMWARE_INFO_V1_2 info_12;
		617	ATOM_FIRMWARE_INFO_V1_3 info_13;
		618	ATOM_FIRMWARE_INFO_V1_4 info_14;
		619	};
		620
		621	bool radeon_atom_get_clock_info(struct drm_device *dev)
		622	{
		623	struct radeon_device *rdev = dev->dev_private;
		624	struct radeon_mode_info *mode_info = &rdev->mode_info;
		625	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		626	union firmware_info *firmware_info;
		627	uint8_t frev, crev;
		628	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		629	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		630	struct radeon_pll *spll = &rdev->clock.spll;
		631	struct radeon_pll *mpll = &rdev->clock.mpll;
		632	uint16_t data_offset;
		633
		634	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		635	&crev, &data_offset);
		636
		637	firmware_info =
		638	(union firmware_info *)(mode_info->atom_context->bios +
		639	data_offset);
		640
		641	if (firmware_info) {
		642	/* pixel clocks */
		643	p1pll->reference_freq =
		644	le16_to_cpu(firmware_info->info.usReferenceClock);
		645	p1pll->reference_div = 0;
		646
		647	p1pll->pll_out_min =
		648	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
		649	p1pll->pll_out_max =
		650	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		651
		652	if (p1pll->pll_out_min == 0) {
		653	if (ASIC_IS_AVIVO(rdev))
		654	p1pll->pll_out_min = 64800;
		655	else
		656	p1pll->pll_out_min = 20000;
		657	}
		658
		659	p1pll->pll_in_min =
		660	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		661	p1pll->pll_in_max =
		662	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		663
		664	p2pll = p1pll;
		665
		666	/* system clock */
		667	spll->reference_freq =
		668	le16_to_cpu(firmware_info->info.usReferenceClock);
		669	spll->reference_div = 0;
		670
		671	spll->pll_out_min =
		672	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		673	spll->pll_out_max =
		674	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		675
		676	/* ??? */
		677	if (spll->pll_out_min == 0) {
		678	if (ASIC_IS_AVIVO(rdev))
		679	spll->pll_out_min = 64800;
		680	else
		681	spll->pll_out_min = 20000;
		682	}
		683
		684	spll->pll_in_min =
		685	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		686	spll->pll_in_max =
		687	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		688
		689	/* memory clock */
		690	mpll->reference_freq =
		691	le16_to_cpu(firmware_info->info.usReferenceClock);
		692	mpll->reference_div = 0;
		693
		694	mpll->pll_out_min =
		695	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		696	mpll->pll_out_max =
		697	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		698
		699	/* ??? */
		700	if (mpll->pll_out_min == 0) {
		701	if (ASIC_IS_AVIVO(rdev))
		702	mpll->pll_out_min = 64800;
		703	else
		704	mpll->pll_out_min = 20000;
		705	}
		706
		707	mpll->pll_in_min =
		708	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		709	mpll->pll_in_max =
		710	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		711
		712	rdev->clock.default_sclk =
		713	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		714	rdev->clock.default_mclk =
		715	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		716
		717	return true;
		718	}
		719	return false;
		720	}
		721
1179	serge	722	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		723	struct radeon_encoder_int_tmds *tmds)
1117	serge	724	{
		725	struct drm_device *dev = encoder->base.dev;
		726	struct radeon_device *rdev = dev->dev_private;
		727	struct radeon_mode_info *mode_info = &rdev->mode_info;
		728	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		729	uint16_t data_offset;
		730	struct _ATOM_TMDS_INFO *tmds_info;
		731	uint8_t frev, crev;
		732	uint16_t maxfreq;
		733	int i;
		734
		735	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		736	&crev, &data_offset);
		737
		738	tmds_info =
		739	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		740	data_offset);
		741
		742	if (tmds_info) {
		743	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		744	for (i = 0; i < 4; i++) {
		745	tmds->tmds_pll[i].freq =
		746	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		747	tmds->tmds_pll[i].value =
		748	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		749	tmds->tmds_pll[i].value \|=
		750	(tmds_info->asMiscInfo[i].
		751	ucPLL_VCO_Gain & 0x3f) << 6;
		752	tmds->tmds_pll[i].value \|=
		753	(tmds_info->asMiscInfo[i].
		754	ucPLL_DutyCycle & 0xf) << 12;
		755	tmds->tmds_pll[i].value \|=
		756	(tmds_info->asMiscInfo[i].
		757	ucPLL_VoltageSwing & 0xf) << 16;
		758
		759	DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
		760	tmds->tmds_pll[i].freq,
		761	tmds->tmds_pll[i].value);
		762
		763	if (maxfreq == tmds->tmds_pll[i].freq) {
		764	tmds->tmds_pll[i].freq = 0xffffffff;
		765	break;
		766	}
		767	}
1179	serge	768	return true;
1117	serge	769	}
1179	serge	770	return false;
1117	serge	771	}
		772
		773	union lvds_info {
		774	struct _ATOM_LVDS_INFO info;
		775	struct _ATOM_LVDS_INFO_V12 info_12;
		776	};
		777
		778	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		779	radeon_encoder
		780	*encoder)
		781	{
		782	struct drm_device *dev = encoder->base.dev;
		783	struct radeon_device *rdev = dev->dev_private;
		784	struct radeon_mode_info *mode_info = &rdev->mode_info;
		785	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
		786	uint16_t data_offset;
		787	union lvds_info *lvds_info;
		788	uint8_t frev, crev;
		789	struct radeon_encoder_atom_dig *lvds = NULL;
		790
		791	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		792	&crev, &data_offset);
		793
		794	lvds_info =
		795	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		796
		797	if (lvds_info) {
		798	lvds =
		799	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		800
		801	if (!lvds)
		802	return NULL;
		803
		804	lvds->native_mode.dotclock =
		805	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
		806	lvds->native_mode.panel_xres =
		807	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
		808	lvds->native_mode.panel_yres =
		809	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
		810	lvds->native_mode.hblank =
		811	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
		812	lvds->native_mode.hoverplus =
		813	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
		814	lvds->native_mode.hsync_width =
		815	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
		816	lvds->native_mode.vblank =
		817	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
		818	lvds->native_mode.voverplus =
		819	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
		820	lvds->native_mode.vsync_width =
		821	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		822	lvds->panel_pwr_delay =
		823	le16_to_cpu(lvds_info->info.usOffDelayInMs);
		824	lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
		825
		826	encoder->native_mode = lvds->native_mode;
		827	}
		828	return lvds;
		829	}
		830
		831	struct radeon_encoder_primary_dac *
		832	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		833	{
		834	struct drm_device *dev = encoder->base.dev;
		835	struct radeon_device *rdev = dev->dev_private;
		836	struct radeon_mode_info *mode_info = &rdev->mode_info;
		837	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		838	uint16_t data_offset;
		839	struct _COMPASSIONATE_DATA *dac_info;
		840	uint8_t frev, crev;
		841	uint8_t bg, dac;
		842	struct radeon_encoder_primary_dac *p_dac = NULL;
		843
		844	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		845
		846	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		847
		848	if (dac_info) {
		849	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		850
		851	if (!p_dac)
		852	return NULL;
		853
		854	bg = dac_info->ucDAC1_BG_Adjustment;
		855	dac = dac_info->ucDAC1_DAC_Adjustment;
		856	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		857
		858	}
		859	return p_dac;
		860	}
		861
1179	serge	862	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
		863	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
		864	int32_t *pixel_clock)
		865	{
		866	struct radeon_mode_info *mode_info = &rdev->mode_info;
		867	ATOM_ANALOG_TV_INFO *tv_info;
		868	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		869	ATOM_DTD_FORMAT *dtd_timings;
		870	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		871	u8 frev, crev;
		872	uint16_t data_offset;
		873
		874	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
		875
		876	switch (crev) {
		877	case 1:
		878	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		879	if (index > MAX_SUPPORTED_TV_TIMING)
		880	return false;
		881
		882	crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		883	crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		884	crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		885	crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
		886
		887	crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		888	crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		889	crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		890	crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
		891
		892	crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
		893
		894	crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
		895	crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
		896	crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
		897	crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
		898	pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) 10;
		899
		900	if (index == 1) {
		901	/* PAL timings appear to have wrong values for totals */
		902	crtc_timing->usH_Total -= 1;
		903	crtc_timing->usV_Total -= 1;
		904	}
		905	break;
		906	case 2:
		907	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
		908	if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
		909	return false;
		910
		911	dtd_timings = &tv_info_v1_2->aModeTimings[index];
		912	crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
		913	crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
		914	crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
		915	crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
		916	crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
		917	crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
		918	crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
		919	crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
		920
		921	crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		922	pixel_clock = le16_to_cpu(dtd_timings->usPixClk) 10;
		923	break;
		924	}
		925	return true;
		926	}
		927
1117	serge	928	struct radeon_encoder_tv_dac *
		929	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		930	{
		931	struct drm_device *dev = encoder->base.dev;
		932	struct radeon_device *rdev = dev->dev_private;
		933	struct radeon_mode_info *mode_info = &rdev->mode_info;
		934	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		935	uint16_t data_offset;
		936	struct _COMPASSIONATE_DATA *dac_info;
		937	uint8_t frev, crev;
		938	uint8_t bg, dac;
		939	struct radeon_encoder_tv_dac *tv_dac = NULL;
		940
		941	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		942
		943	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		944
		945	if (dac_info) {
		946	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		947
		948	if (!tv_dac)
		949	return NULL;
		950
		951	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		952	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		953	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		954
		955	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		956	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		957	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		958
		959	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		960	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		961	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		962
		963	}
		964	return tv_dac;
		965	}
		966
		967	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
		968	{
		969	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		970	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
		971
		972	args.ucEnable = enable;
		973
		974	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		975	}
		976
		977	void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
		978	{
		979	ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
		980	int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
		981
		982	args.ucEnable = enable;
		983
		984	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		985	}
		986
		987	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		988	uint32_t eng_clock)
		989	{
		990	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		991	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		992
		993	args.ulTargetEngineClock = eng_clock; /* 10 khz */
		994
		995	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		996	}
		997
		998	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		999	uint32_t mem_clock)
		1000	{
		1001	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		1002	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		1003
		1004	if (rdev->flags & RADEON_IS_IGP)
		1005	return;
		1006
		1007	args.ulTargetMemoryClock = mem_clock; /* 10 khz */
		1008
		1009	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1010	}
		1011
		1012	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		1013	{
		1014	struct radeon_device *rdev = dev->dev_private;
		1015	uint32_t bios_2_scratch, bios_6_scratch;
		1016
		1017	if (rdev->family >= CHIP_R600) {
1179	serge	1018	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	1019	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1020	} else {
1179	serge	1021	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	1022	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1023	}
		1024
		1025	/* let the bios control the backlight */
		1026	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		1027
		1028	/* tell the bios not to handle mode switching */
		1029	bios_6_scratch \|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH \| ATOM_S6_ACC_MODE);
		1030
		1031	if (rdev->family >= CHIP_R600) {
		1032	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1033	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1034	} else {
		1035	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1036	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1037	}
		1038
		1039	}
		1040
1179	serge	1041	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		1042	{
		1043	uint32_t scratch_reg;
		1044	int i;
		1045
		1046	if (rdev->family >= CHIP_R600)
		1047	scratch_reg = R600_BIOS_0_SCRATCH;
		1048	else
		1049	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1050
		1051	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1052	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		1053	}
		1054
		1055	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		1056	{
		1057	uint32_t scratch_reg;
		1058	int i;
		1059
		1060	if (rdev->family >= CHIP_R600)
		1061	scratch_reg = R600_BIOS_0_SCRATCH;
		1062	else
		1063	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1064
		1065	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1066	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		1067	}
		1068
1117	serge	1069	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		1070	{
		1071	struct drm_device *dev = encoder->dev;
		1072	struct radeon_device *rdev = dev->dev_private;
		1073	uint32_t bios_6_scratch;
		1074
		1075	if (rdev->family >= CHIP_R600)
		1076	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1077	else
		1078	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1079
		1080	if (lock)
		1081	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
		1082	else
		1083	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
		1084
		1085	if (rdev->family >= CHIP_R600)
		1086	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1087	else
		1088	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1089	}
		1090
		1091	/* at some point we may want to break this out into individual functions */
		1092	void
		1093	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		1094	struct drm_encoder *encoder,
		1095	bool connected)
		1096	{
		1097	struct drm_device *dev = connector->dev;
		1098	struct radeon_device *rdev = dev->dev_private;
		1099	struct radeon_connector *radeon_connector =
		1100	to_radeon_connector(connector);
		1101	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1102	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		1103
		1104	if (rdev->family >= CHIP_R600) {
		1105	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1106	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1107	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1108	} else {
		1109	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1110	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1111	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1112	}
		1113
		1114	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		1115	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		1116	if (connected) {
		1117	DRM_DEBUG("TV1 connected\n");
		1118	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		1119	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		1120	} else {
		1121	DRM_DEBUG("TV1 disconnected\n");
		1122	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		1123	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		1124	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		1125	}
		1126	}
		1127	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		1128	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		1129	if (connected) {
		1130	DRM_DEBUG("CV connected\n");
		1131	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		1132	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		1133	} else {
		1134	DRM_DEBUG("CV disconnected\n");
		1135	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		1136	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		1137	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		1138	}
		1139	}
		1140	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		1141	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		1142	if (connected) {
		1143	DRM_DEBUG("LCD1 connected\n");
		1144	bios_0_scratch \|= ATOM_S0_LCD1;
		1145	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		1146	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		1147	} else {
		1148	DRM_DEBUG("LCD1 disconnected\n");
		1149	bios_0_scratch &= ~ATOM_S0_LCD1;
		1150	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		1151	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		1152	}
		1153	}
		1154	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		1155	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		1156	if (connected) {
		1157	DRM_DEBUG("CRT1 connected\n");
		1158	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		1159	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		1160	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		1161	} else {
		1162	DRM_DEBUG("CRT1 disconnected\n");
		1163	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		1164	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		1165	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		1166	}
		1167	}
		1168	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		1169	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		1170	if (connected) {
		1171	DRM_DEBUG("CRT2 connected\n");
		1172	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		1173	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		1174	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		1175	} else {
		1176	DRM_DEBUG("CRT2 disconnected\n");
		1177	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		1178	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		1179	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		1180	}
		1181	}
		1182	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		1183	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		1184	if (connected) {
		1185	DRM_DEBUG("DFP1 connected\n");
		1186	bios_0_scratch \|= ATOM_S0_DFP1;
		1187	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		1188	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		1189	} else {
		1190	DRM_DEBUG("DFP1 disconnected\n");
		1191	bios_0_scratch &= ~ATOM_S0_DFP1;
		1192	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		1193	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		1194	}
		1195	}
		1196	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		1197	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		1198	if (connected) {
		1199	DRM_DEBUG("DFP2 connected\n");
		1200	bios_0_scratch \|= ATOM_S0_DFP2;
		1201	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		1202	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		1203	} else {
		1204	DRM_DEBUG("DFP2 disconnected\n");
		1205	bios_0_scratch &= ~ATOM_S0_DFP2;
		1206	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		1207	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		1208	}
		1209	}
		1210	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		1211	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		1212	if (connected) {
		1213	DRM_DEBUG("DFP3 connected\n");
		1214	bios_0_scratch \|= ATOM_S0_DFP3;
		1215	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		1216	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		1217	} else {
		1218	DRM_DEBUG("DFP3 disconnected\n");
		1219	bios_0_scratch &= ~ATOM_S0_DFP3;
		1220	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		1221	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		1222	}
		1223	}
		1224	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		1225	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		1226	if (connected) {
		1227	DRM_DEBUG("DFP4 connected\n");
		1228	bios_0_scratch \|= ATOM_S0_DFP4;
		1229	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		1230	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		1231	} else {
		1232	DRM_DEBUG("DFP4 disconnected\n");
		1233	bios_0_scratch &= ~ATOM_S0_DFP4;
		1234	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		1235	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		1236	}
		1237	}
		1238	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		1239	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		1240	if (connected) {
		1241	DRM_DEBUG("DFP5 connected\n");
		1242	bios_0_scratch \|= ATOM_S0_DFP5;
		1243	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		1244	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		1245	} else {
		1246	DRM_DEBUG("DFP5 disconnected\n");
		1247	bios_0_scratch &= ~ATOM_S0_DFP5;
		1248	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		1249	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		1250	}
		1251	}
		1252
		1253	if (rdev->family >= CHIP_R600) {
		1254	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		1255	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1256	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1257	} else {
		1258	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		1259	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1260	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1261	}
		1262	}
		1263
		1264	void
		1265	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		1266	{
		1267	struct drm_device *dev = encoder->dev;
		1268	struct radeon_device *rdev = dev->dev_private;
		1269	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1270	uint32_t bios_3_scratch;
		1271
		1272	if (rdev->family >= CHIP_R600)
		1273	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1274	else
		1275	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1276
		1277	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1278	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		1279	bios_3_scratch \|= (crtc << 18);
		1280	}
		1281	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1282	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		1283	bios_3_scratch \|= (crtc << 24);
		1284	}
		1285	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1286	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		1287	bios_3_scratch \|= (crtc << 16);
		1288	}
		1289	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1290	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		1291	bios_3_scratch \|= (crtc << 20);
		1292	}
		1293	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1294	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		1295	bios_3_scratch \|= (crtc << 17);
		1296	}
		1297	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1298	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		1299	bios_3_scratch \|= (crtc << 19);
		1300	}
		1301	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1302	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		1303	bios_3_scratch \|= (crtc << 23);
		1304	}
		1305	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1306	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		1307	bios_3_scratch \|= (crtc << 25);
		1308	}
		1309
		1310	if (rdev->family >= CHIP_R600)
		1311	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1312	else
		1313	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1314	}
		1315
		1316	void
		1317	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		1318	{
		1319	struct drm_device *dev = encoder->dev;
		1320	struct radeon_device *rdev = dev->dev_private;
		1321	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1322	uint32_t bios_2_scratch;
		1323
		1324	if (rdev->family >= CHIP_R600)
		1325	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		1326	else
		1327	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		1328
		1329	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1330	if (on)
		1331	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		1332	else
		1333	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		1334	}
		1335	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1336	if (on)
		1337	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		1338	else
		1339	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		1340	}
		1341	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1342	if (on)
		1343	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		1344	else
		1345	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		1346	}
		1347	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1348	if (on)
		1349	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		1350	else
		1351	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		1352	}
		1353	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1354	if (on)
		1355	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		1356	else
		1357	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		1358	}
		1359	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1360	if (on)
		1361	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		1362	else
		1363	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		1364	}
		1365	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1366	if (on)
		1367	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		1368	else
		1369	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		1370	}
		1371	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1372	if (on)
		1373	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		1374	else
		1375	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		1376	}
		1377	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		1378	if (on)
		1379	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		1380	else
		1381	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		1382	}
		1383	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		1384	if (on)
		1385	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		1386	else
		1387	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		1388	}
		1389
		1390	if (rdev->family >= CHIP_R600)
		1391	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1392	else
		1393	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1394	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 1179