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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_ASIC_H__ |
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29 | #define __RADEON_ASIC_H__ |
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30 | |||
31 | /* |
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32 | * common functions |
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33 | */ |
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1268 | serge | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
1117 | serge | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
1403 | serge | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
1117 | serge | 37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
38 | |||
1268 | serge | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
1117 | serge | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
1117 | serge | 42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
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44 | |||
2997 | Serge | 45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
46 | u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); |
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47 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
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48 | u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); |
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49 | |||
50 | |||
1117 | serge | 51 | /* |
1430 | serge | 52 | * r100,rv100,rs100,rv200,rs200 |
1117 | serge | 53 | */ |
1963 | serge | 54 | struct r100_mc_save { |
55 | u32 GENMO_WT; |
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56 | u32 CRTC_EXT_CNTL; |
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57 | u32 CRTC_GEN_CNTL; |
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58 | u32 CRTC2_GEN_CNTL; |
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59 | u32 CUR_OFFSET; |
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60 | u32 CUR2_OFFSET; |
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61 | }; |
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62 | int r100_init(struct radeon_device *rdev); |
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63 | void r100_fini(struct radeon_device *rdev); |
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64 | int r100_suspend(struct radeon_device *rdev); |
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65 | int r100_resume(struct radeon_device *rdev); |
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1179 | serge | 66 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
2997 | Serge | 67 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
1963 | serge | 68 | int r100_asic_reset(struct radeon_device *rdev); |
1179 | serge | 69 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
1117 | serge | 70 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
71 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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2997 | Serge | 72 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
1117 | serge | 73 | int r100_irq_set(struct radeon_device *rdev); |
74 | int r100_irq_process(struct radeon_device *rdev); |
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1128 | serge | 75 | void r100_fence_ring_emit(struct radeon_device *rdev, |
76 | struct radeon_fence *fence); |
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2997 | Serge | 77 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
78 | struct radeon_ring *cp, |
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79 | struct radeon_semaphore *semaphore, |
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80 | bool emit_wait); |
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1128 | serge | 81 | int r100_cs_parse(struct radeon_cs_parser *p); |
1117 | serge | 82 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
83 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
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1128 | serge | 84 | int r100_copy_blit(struct radeon_device *rdev, |
85 | uint64_t src_offset, |
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86 | uint64_t dst_offset, |
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2997 | Serge | 87 | unsigned num_gpu_pages, |
88 | struct radeon_fence **fence); |
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1179 | serge | 89 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
90 | uint32_t tiling_flags, uint32_t pitch, |
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91 | uint32_t offset, uint32_t obj_size); |
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1963 | serge | 92 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
1179 | serge | 93 | void r100_bandwidth_update(struct radeon_device *rdev); |
94 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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2997 | Serge | 95 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1321 | serge | 96 | void r100_hpd_init(struct radeon_device *rdev); |
97 | void r100_hpd_fini(struct radeon_device *rdev); |
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98 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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99 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
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100 | enum radeon_hpd_id hpd); |
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1963 | serge | 101 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
102 | int r100_debugfs_cp_init(struct radeon_device *rdev); |
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103 | void r100_cp_disable(struct radeon_device *rdev); |
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104 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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105 | void r100_cp_fini(struct radeon_device *rdev); |
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106 | int r100_pci_gart_init(struct radeon_device *rdev); |
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107 | void r100_pci_gart_fini(struct radeon_device *rdev); |
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108 | int r100_pci_gart_enable(struct radeon_device *rdev); |
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109 | void r100_pci_gart_disable(struct radeon_device *rdev); |
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110 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
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111 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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2997 | Serge | 112 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1963 | serge | 113 | void r100_irq_disable(struct radeon_device *rdev); |
114 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
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115 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
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116 | void r100_vram_init_sizes(struct radeon_device *rdev); |
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117 | int r100_cp_reset(struct radeon_device *rdev); |
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118 | void r100_vga_render_disable(struct radeon_device *rdev); |
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119 | void r100_restore_sanity(struct radeon_device *rdev); |
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120 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
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121 | struct radeon_cs_packet *pkt, |
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122 | struct radeon_bo *robj); |
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123 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
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124 | struct radeon_cs_packet *pkt, |
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125 | const unsigned *auth, unsigned n, |
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126 | radeon_packet0_check_t check); |
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127 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
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128 | struct radeon_cs_packet *pkt, |
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129 | unsigned idx); |
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130 | void r100_enable_bm(struct radeon_device *rdev); |
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131 | void r100_set_common_regs(struct radeon_device *rdev); |
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132 | void r100_bm_disable(struct radeon_device *rdev); |
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133 | extern bool r100_gui_idle(struct radeon_device *rdev); |
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134 | extern void r100_pm_misc(struct radeon_device *rdev); |
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135 | extern void r100_pm_prepare(struct radeon_device *rdev); |
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136 | extern void r100_pm_finish(struct radeon_device *rdev); |
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137 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
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138 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); |
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139 | extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
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140 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
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141 | extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); |
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2997 | Serge | 142 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
143 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
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1117 | serge | 144 | |
1430 | serge | 145 | /* |
146 | * r200,rv250,rs300,rv280 |
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147 | */ |
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148 | extern int r200_copy_dma(struct radeon_device *rdev, |
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149 | uint64_t src_offset, |
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150 | uint64_t dst_offset, |
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2997 | Serge | 151 | unsigned num_gpu_pages, |
152 | struct radeon_fence **fence); |
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1963 | serge | 153 | void r200_set_safe_registers(struct radeon_device *rdev); |
1117 | serge | 154 | |
155 | /* |
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156 | * r300,r350,rv350,rv380 |
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157 | */ |
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1221 | serge | 158 | extern int r300_init(struct radeon_device *rdev); |
159 | extern void r300_fini(struct radeon_device *rdev); |
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160 | extern int r300_suspend(struct radeon_device *rdev); |
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161 | extern int r300_resume(struct radeon_device *rdev); |
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1963 | serge | 162 | extern int r300_asic_reset(struct radeon_device *rdev); |
2997 | Serge | 163 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
1221 | serge | 164 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
1128 | serge | 165 | struct radeon_fence *fence); |
1221 | serge | 166 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
167 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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168 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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169 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
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1430 | serge | 170 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
1963 | serge | 171 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
172 | extern void r300_mc_program(struct radeon_device *rdev); |
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173 | extern void r300_mc_init(struct radeon_device *rdev); |
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174 | extern void r300_clock_startup(struct radeon_device *rdev); |
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175 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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176 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
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177 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
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178 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
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179 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
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2997 | Serge | 180 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1430 | serge | 181 | |
1117 | serge | 182 | /* |
183 | * r420,r423,rv410 |
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184 | */ |
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1179 | serge | 185 | extern int r420_init(struct radeon_device *rdev); |
186 | extern void r420_fini(struct radeon_device *rdev); |
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187 | extern int r420_suspend(struct radeon_device *rdev); |
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188 | extern int r420_resume(struct radeon_device *rdev); |
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1963 | serge | 189 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
190 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
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191 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
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192 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
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193 | extern void r420_pipes_init(struct radeon_device *rdev); |
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1117 | serge | 194 | |
195 | /* |
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196 | * rs400,rs480 |
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197 | */ |
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1221 | serge | 198 | extern int rs400_init(struct radeon_device *rdev); |
199 | extern void rs400_fini(struct radeon_device *rdev); |
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200 | extern int rs400_suspend(struct radeon_device *rdev); |
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201 | extern int rs400_resume(struct radeon_device *rdev); |
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1117 | serge | 202 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
203 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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204 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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205 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1963 | serge | 206 | int rs400_gart_init(struct radeon_device *rdev); |
207 | int rs400_gart_enable(struct radeon_device *rdev); |
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208 | void rs400_gart_adjust_size(struct radeon_device *rdev); |
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209 | void rs400_gart_disable(struct radeon_device *rdev); |
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210 | void rs400_gart_fini(struct radeon_device *rdev); |
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2997 | Serge | 211 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 212 | |
213 | /* |
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214 | * rs600. |
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215 | */ |
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1963 | serge | 216 | extern int rs600_asic_reset(struct radeon_device *rdev); |
1221 | serge | 217 | extern int rs600_init(struct radeon_device *rdev); |
218 | extern void rs600_fini(struct radeon_device *rdev); |
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219 | extern int rs600_suspend(struct radeon_device *rdev); |
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220 | extern int rs600_resume(struct radeon_device *rdev); |
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1117 | serge | 221 | int rs600_irq_set(struct radeon_device *rdev); |
1179 | serge | 222 | int rs600_irq_process(struct radeon_device *rdev); |
1963 | serge | 223 | void rs600_irq_disable(struct radeon_device *rdev); |
1179 | serge | 224 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
1117 | serge | 225 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
226 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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227 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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228 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 229 | void rs600_bandwidth_update(struct radeon_device *rdev); |
1321 | serge | 230 | void rs600_hpd_init(struct radeon_device *rdev); |
231 | void rs600_hpd_fini(struct radeon_device *rdev); |
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232 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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233 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
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234 | enum radeon_hpd_id hpd); |
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1963 | serge | 235 | extern void rs600_pm_misc(struct radeon_device *rdev); |
236 | extern void rs600_pm_prepare(struct radeon_device *rdev); |
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237 | extern void rs600_pm_finish(struct radeon_device *rdev); |
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238 | extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
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239 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
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240 | extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); |
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241 | void rs600_set_safe_registers(struct radeon_device *rdev); |
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2997 | Serge | 242 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
243 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
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1321 | serge | 244 | |
1117 | serge | 245 | /* |
246 | * rs690,rs740 |
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247 | */ |
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1221 | serge | 248 | int rs690_init(struct radeon_device *rdev); |
249 | void rs690_fini(struct radeon_device *rdev); |
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250 | int rs690_resume(struct radeon_device *rdev); |
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251 | int rs690_suspend(struct radeon_device *rdev); |
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1117 | serge | 252 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
253 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 254 | void rs690_bandwidth_update(struct radeon_device *rdev); |
1963 | serge | 255 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
256 | struct drm_display_mode *mode1, |
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257 | struct drm_display_mode *mode2); |
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2997 | Serge | 258 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 259 | |
260 | /* |
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261 | * rv515 |
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262 | */ |
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1963 | serge | 263 | struct rv515_mc_save { |
264 | u32 vga_render_control; |
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265 | u32 vga_hdp_control; |
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3192 | Serge | 266 | bool crtc_enabled[2]; |
1963 | serge | 267 | }; |
2997 | Serge | 268 | |
1117 | serge | 269 | int rv515_init(struct radeon_device *rdev); |
1221 | serge | 270 | void rv515_fini(struct radeon_device *rdev); |
1117 | serge | 271 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
272 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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2997 | Serge | 273 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
1179 | serge | 274 | void rv515_bandwidth_update(struct radeon_device *rdev); |
1221 | serge | 275 | int rv515_resume(struct radeon_device *rdev); |
276 | int rv515_suspend(struct radeon_device *rdev); |
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1963 | serge | 277 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
278 | void rv515_vga_render_disable(struct radeon_device *rdev); |
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279 | void rv515_set_safe_registers(struct radeon_device *rdev); |
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280 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
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281 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
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282 | void rv515_clock_startup(struct radeon_device *rdev); |
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283 | void rv515_debugfs(struct radeon_device *rdev); |
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2997 | Serge | 284 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 285 | |
286 | /* |
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287 | * r520,rv530,rv560,rv570,r580 |
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288 | */ |
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1221 | serge | 289 | int r520_init(struct radeon_device *rdev); |
290 | int r520_resume(struct radeon_device *rdev); |
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2997 | Serge | 291 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
1117 | serge | 292 | |
293 | /* |
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1221 | serge | 294 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
1117 | serge | 295 | */ |
1179 | serge | 296 | int r600_init(struct radeon_device *rdev); |
297 | void r600_fini(struct radeon_device *rdev); |
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298 | int r600_suspend(struct radeon_device *rdev); |
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299 | int r600_resume(struct radeon_device *rdev); |
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300 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
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301 | int r600_wb_init(struct radeon_device *rdev); |
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302 | void r600_wb_fini(struct radeon_device *rdev); |
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303 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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1117 | serge | 304 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
305 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1233 | serge | 306 | int r600_cs_parse(struct radeon_cs_parser *p); |
3192 | Serge | 307 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
1233 | serge | 308 | void r600_fence_ring_emit(struct radeon_device *rdev, |
309 | struct radeon_fence *fence); |
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2997 | Serge | 310 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
311 | struct radeon_ring *cp, |
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312 | struct radeon_semaphore *semaphore, |
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313 | bool emit_wait); |
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3192 | Serge | 314 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
315 | struct radeon_fence *fence); |
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316 | void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
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317 | struct radeon_ring *ring, |
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318 | struct radeon_semaphore *semaphore, |
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319 | bool emit_wait); |
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320 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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321 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
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3764 | Serge | 322 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
1963 | serge | 323 | int r600_asic_reset(struct radeon_device *rdev); |
1233 | serge | 324 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
325 | uint32_t tiling_flags, uint32_t pitch, |
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326 | uint32_t offset, uint32_t obj_size); |
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1963 | serge | 327 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
2997 | Serge | 328 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
3192 | Serge | 329 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1233 | serge | 330 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
2997 | Serge | 331 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
3192 | Serge | 332 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
3764 | Serge | 333 | int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1233 | serge | 334 | int r600_copy_blit(struct radeon_device *rdev, |
335 | uint64_t src_offset, uint64_t dst_offset, |
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2997 | Serge | 336 | unsigned num_gpu_pages, struct radeon_fence **fence); |
3192 | Serge | 337 | int r600_copy_dma(struct radeon_device *rdev, |
338 | uint64_t src_offset, uint64_t dst_offset, |
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339 | unsigned num_gpu_pages, struct radeon_fence **fence); |
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1321 | serge | 340 | void r600_hpd_init(struct radeon_device *rdev); |
341 | void r600_hpd_fini(struct radeon_device *rdev); |
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342 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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343 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
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344 | enum radeon_hpd_id hpd); |
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1404 | serge | 345 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
1963 | serge | 346 | extern bool r600_gui_idle(struct radeon_device *rdev); |
347 | extern void r600_pm_misc(struct radeon_device *rdev); |
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348 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
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349 | extern void rs780_pm_init_profile(struct radeon_device *rdev); |
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3764 | Serge | 350 | extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
351 | extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1963 | serge | 352 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
353 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
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354 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); |
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355 | bool r600_card_posted(struct radeon_device *rdev); |
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356 | void r600_cp_stop(struct radeon_device *rdev); |
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357 | int r600_cp_start(struct radeon_device *rdev); |
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2997 | Serge | 358 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
1963 | serge | 359 | int r600_cp_resume(struct radeon_device *rdev); |
360 | void r600_cp_fini(struct radeon_device *rdev); |
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361 | int r600_count_pipe_bits(uint32_t val); |
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362 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
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363 | int r600_pcie_gart_init(struct radeon_device *rdev); |
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364 | void r600_scratch_init(struct radeon_device *rdev); |
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365 | int r600_blit_init(struct radeon_device *rdev); |
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366 | void r600_blit_fini(struct radeon_device *rdev); |
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367 | int r600_init_microcode(struct radeon_device *rdev); |
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368 | /* r600 irq */ |
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369 | int r600_irq_process(struct radeon_device *rdev); |
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370 | int r600_irq_init(struct radeon_device *rdev); |
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371 | void r600_irq_fini(struct radeon_device *rdev); |
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372 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
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373 | int r600_irq_set(struct radeon_device *rdev); |
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374 | void r600_irq_suspend(struct radeon_device *rdev); |
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375 | void r600_disable_interrupts(struct radeon_device *rdev); |
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376 | void r600_rlc_stop(struct radeon_device *rdev); |
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377 | /* r600 audio */ |
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378 | int r600_audio_init(struct radeon_device *rdev); |
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2997 | Serge | 379 | struct r600_audio r600_audio_status(struct radeon_device *rdev); |
1963 | serge | 380 | void r600_audio_fini(struct radeon_device *rdev); |
381 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
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382 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
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3764 | Serge | 383 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); |
384 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
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1963 | serge | 385 | /* r600 blit */ |
2997 | Serge | 386 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
387 | struct radeon_fence **fence, struct radeon_sa_bo **vb, |
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388 | struct radeon_semaphore **sem); |
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389 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
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390 | struct radeon_sa_bo *vb, struct radeon_semaphore *sem); |
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1963 | serge | 391 | void r600_kms_blit_copy(struct radeon_device *rdev, |
392 | u64 src_gpu_addr, u64 dst_gpu_addr, |
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2997 | Serge | 393 | unsigned num_gpu_pages, |
394 | struct radeon_sa_bo *vb); |
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395 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
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3764 | Serge | 396 | u32 r600_get_xclk(struct radeon_device *rdev); |
397 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); |
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1117 | serge | 398 | |
3764 | Serge | 399 | /* uvd */ |
400 | int r600_uvd_init(struct radeon_device *rdev); |
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401 | int r600_uvd_rbc_start(struct radeon_device *rdev); |
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402 | void r600_uvd_rbc_stop(struct radeon_device *rdev); |
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403 | int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
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404 | void r600_uvd_fence_emit(struct radeon_device *rdev, |
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405 | struct radeon_fence *fence); |
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406 | void r600_uvd_semaphore_emit(struct radeon_device *rdev, |
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407 | struct radeon_ring *ring, |
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408 | struct radeon_semaphore *semaphore, |
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409 | bool emit_wait); |
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410 | void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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411 | |||
1233 | serge | 412 | /* |
413 | * rv770,rv730,rv710,rv740 |
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414 | */ |
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415 | int rv770_init(struct radeon_device *rdev); |
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416 | void rv770_fini(struct radeon_device *rdev); |
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417 | int rv770_suspend(struct radeon_device *rdev); |
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418 | int rv770_resume(struct radeon_device *rdev); |
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1963 | serge | 419 | void rv770_pm_misc(struct radeon_device *rdev); |
420 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
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421 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
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422 | void r700_cp_stop(struct radeon_device *rdev); |
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423 | void r700_cp_fini(struct radeon_device *rdev); |
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3192 | Serge | 424 | int rv770_copy_dma(struct radeon_device *rdev, |
425 | uint64_t src_offset, uint64_t dst_offset, |
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426 | unsigned num_gpu_pages, |
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427 | struct radeon_fence **fence); |
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3764 | Serge | 428 | u32 rv770_get_xclk(struct radeon_device *rdev); |
429 | int rv770_uvd_resume(struct radeon_device *rdev); |
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430 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
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1233 | serge | 431 | |
1430 | serge | 432 | /* |
433 | * evergreen |
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434 | */ |
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1963 | serge | 435 | struct evergreen_mc_save { |
436 | u32 vga_render_control; |
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437 | u32 vga_hdp_control; |
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2997 | Serge | 438 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
1963 | serge | 439 | }; |
2997 | Serge | 440 | |
1963 | serge | 441 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1430 | serge | 442 | int evergreen_init(struct radeon_device *rdev); |
443 | void evergreen_fini(struct radeon_device *rdev); |
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444 | int evergreen_suspend(struct radeon_device *rdev); |
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445 | int evergreen_resume(struct radeon_device *rdev); |
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3764 | Serge | 446 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
447 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
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1963 | serge | 448 | int evergreen_asic_reset(struct radeon_device *rdev); |
1430 | serge | 449 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
1963 | serge | 450 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1430 | serge | 451 | void evergreen_hpd_init(struct radeon_device *rdev); |
452 | void evergreen_hpd_fini(struct radeon_device *rdev); |
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453 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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454 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, |
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455 | enum radeon_hpd_id hpd); |
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1963 | serge | 456 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
457 | int evergreen_irq_set(struct radeon_device *rdev); |
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458 | int evergreen_irq_process(struct radeon_device *rdev); |
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459 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
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3192 | Serge | 460 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
1963 | serge | 461 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
462 | extern void evergreen_pm_prepare(struct radeon_device *rdev); |
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463 | extern void evergreen_pm_finish(struct radeon_device *rdev); |
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2997 | Serge | 464 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
465 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
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3764 | Serge | 466 | int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
467 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
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1963 | serge | 468 | extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
469 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
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470 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); |
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2997 | Serge | 471 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
1963 | serge | 472 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
473 | int evergreen_blit_init(struct radeon_device *rdev); |
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2997 | Serge | 474 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
3192 | Serge | 475 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
476 | struct radeon_fence *fence); |
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477 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, |
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478 | struct radeon_ib *ib); |
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479 | int evergreen_copy_dma(struct radeon_device *rdev, |
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480 | uint64_t src_offset, uint64_t dst_offset, |
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481 | unsigned num_gpu_pages, |
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482 | struct radeon_fence **fence); |
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3764 | Serge | 483 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); |
484 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
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1430 | serge | 485 | |
1963 | serge | 486 | /* |
487 | * cayman |
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488 | */ |
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2997 | Serge | 489 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
490 | struct radeon_fence *fence); |
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3764 | Serge | 491 | void cayman_uvd_semaphore_emit(struct radeon_device *rdev, |
492 | struct radeon_ring *ring, |
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493 | struct radeon_semaphore *semaphore, |
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494 | bool emit_wait); |
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1963 | serge | 495 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
496 | int cayman_init(struct radeon_device *rdev); |
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497 | void cayman_fini(struct radeon_device *rdev); |
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498 | int cayman_suspend(struct radeon_device *rdev); |
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499 | int cayman_resume(struct radeon_device *rdev); |
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500 | int cayman_asic_reset(struct radeon_device *rdev); |
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2997 | Serge | 501 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
502 | int cayman_vm_init(struct radeon_device *rdev); |
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503 | void cayman_vm_fini(struct radeon_device *rdev); |
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504 | void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
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505 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
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3764 | Serge | 506 | void cayman_vm_set_page(struct radeon_device *rdev, |
507 | struct radeon_ib *ib, |
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508 | uint64_t pe, |
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2997 | Serge | 509 | uint64_t addr, unsigned count, |
510 | uint32_t incr, uint32_t flags); |
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511 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
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3192 | Serge | 512 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
513 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
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514 | struct radeon_ib *ib); |
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3764 | Serge | 515 | bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
3192 | Serge | 516 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
517 | void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
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1430 | serge | 518 | |
2997 | Serge | 519 | /* DCE6 - SI */ |
520 | void dce6_bandwidth_update(struct radeon_device *rdev); |
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521 | |||
522 | /* |
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523 | * si |
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524 | */ |
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525 | void si_fence_ring_emit(struct radeon_device *rdev, |
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526 | struct radeon_fence *fence); |
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527 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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528 | int si_init(struct radeon_device *rdev); |
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529 | void si_fini(struct radeon_device *rdev); |
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530 | int si_suspend(struct radeon_device *rdev); |
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531 | int si_resume(struct radeon_device *rdev); |
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3764 | Serge | 532 | bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
533 | bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
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2997 | Serge | 534 | int si_asic_reset(struct radeon_device *rdev); |
535 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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536 | int si_irq_set(struct radeon_device *rdev); |
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537 | int si_irq_process(struct radeon_device *rdev); |
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538 | int si_vm_init(struct radeon_device *rdev); |
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539 | void si_vm_fini(struct radeon_device *rdev); |
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3764 | Serge | 540 | void si_vm_set_page(struct radeon_device *rdev, |
541 | struct radeon_ib *ib, |
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542 | uint64_t pe, |
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2997 | Serge | 543 | uint64_t addr, unsigned count, |
544 | uint32_t incr, uint32_t flags); |
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545 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
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546 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
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3192 | Serge | 547 | int si_copy_dma(struct radeon_device *rdev, |
548 | uint64_t src_offset, uint64_t dst_offset, |
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549 | unsigned num_gpu_pages, |
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550 | struct radeon_fence **fence); |
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551 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
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3764 | Serge | 552 | u32 si_get_xclk(struct radeon_device *rdev); |
553 | uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); |
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554 | int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
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2997 | Serge | 555 | |
1117 | serge | 556 | #endif |