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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_ASIC_H__ |
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29 | #define __RADEON_ASIC_H__ |
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30 | |||
31 | /* |
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32 | * common functions |
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33 | */ |
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1268 | serge | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
1117 | serge | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
36 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
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37 | |||
1268 | serge | 38 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
1117 | serge | 39 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 40 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
1117 | serge | 41 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
42 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
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43 | |||
44 | /* |
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45 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
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46 | */ |
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1221 | serge | 47 | extern int r100_init(struct radeon_device *rdev); |
48 | extern void r100_fini(struct radeon_device *rdev); |
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49 | extern int r100_suspend(struct radeon_device *rdev); |
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50 | extern int r100_resume(struct radeon_device *rdev); |
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1117 | serge | 51 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
52 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 53 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
1117 | serge | 54 | int r100_gpu_reset(struct radeon_device *rdev); |
1179 | serge | 55 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
1117 | serge | 56 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
57 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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1179 | serge | 58 | void r100_cp_commit(struct radeon_device *rdev); |
1117 | serge | 59 | void r100_ring_start(struct radeon_device *rdev); |
60 | int r100_irq_set(struct radeon_device *rdev); |
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61 | int r100_irq_process(struct radeon_device *rdev); |
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1128 | serge | 62 | void r100_fence_ring_emit(struct radeon_device *rdev, |
63 | struct radeon_fence *fence); |
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64 | int r100_cs_parse(struct radeon_cs_parser *p); |
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1117 | serge | 65 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
66 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
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1128 | serge | 67 | int r100_copy_blit(struct radeon_device *rdev, |
68 | uint64_t src_offset, |
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69 | uint64_t dst_offset, |
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70 | unsigned num_pages, |
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71 | struct radeon_fence *fence); |
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1179 | serge | 72 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
73 | uint32_t tiling_flags, uint32_t pitch, |
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74 | uint32_t offset, uint32_t obj_size); |
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75 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
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76 | void r100_bandwidth_update(struct radeon_device *rdev); |
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77 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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78 | int r100_ring_test(struct radeon_device *rdev); |
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1117 | serge | 79 | |
80 | static struct radeon_asic r100_asic = { |
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81 | .init = &r100_init, |
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1221 | serge | 82 | // .fini = &r100_fini, |
83 | // .suspend = &r100_suspend, |
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84 | // .resume = &r100_resume, |
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85 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 86 | .gpu_reset = &r100_gpu_reset, |
87 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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88 | .gart_set_page = &r100_pci_gart_set_page, |
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1221 | serge | 89 | .cp_commit = &r100_cp_commit, |
90 | // .ring_start = &r100_ring_start, |
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91 | // .ring_test = &r100_ring_test, |
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92 | // .ring_ib_execute = &r100_ring_ib_execute, |
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93 | // .irq_set = &r100_irq_set, |
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94 | // .irq_process = &r100_irq_process, |
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95 | // .get_vblank_counter = &r100_get_vblank_counter, |
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96 | // .fence_ring_emit = &r100_fence_ring_emit, |
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97 | // .cs_parse = &r100_cs_parse, |
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98 | // .copy_blit = &r100_copy_blit, |
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99 | // .copy_dma = NULL, |
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100 | // .copy = &r100_copy_blit, |
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1268 | serge | 101 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
1221 | serge | 102 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
1268 | serge | 103 | .get_memory_clock = NULL, |
1221 | serge | 104 | .set_memory_clock = NULL, |
105 | .set_pcie_lanes = NULL, |
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106 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1179 | serge | 107 | .set_surface_reg = r100_set_surface_reg, |
108 | .clear_surface_reg = r100_clear_surface_reg, |
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109 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 110 | }; |
111 | |||
112 | |||
113 | /* |
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114 | * r300,r350,rv350,rv380 |
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115 | */ |
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1221 | serge | 116 | extern int r300_init(struct radeon_device *rdev); |
117 | extern void r300_fini(struct radeon_device *rdev); |
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118 | extern int r300_suspend(struct radeon_device *rdev); |
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119 | extern int r300_resume(struct radeon_device *rdev); |
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120 | extern int r300_gpu_reset(struct radeon_device *rdev); |
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121 | extern void r300_ring_start(struct radeon_device *rdev); |
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122 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
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1128 | serge | 123 | struct radeon_fence *fence); |
1221 | serge | 124 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
125 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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126 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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127 | extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
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128 | extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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129 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
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130 | extern int r300_copy_dma(struct radeon_device *rdev, |
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1128 | serge | 131 | uint64_t src_offset, |
132 | uint64_t dst_offset, |
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133 | unsigned num_pages, |
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134 | struct radeon_fence *fence); |
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1117 | serge | 135 | static struct radeon_asic r300_asic = { |
136 | .init = &r300_init, |
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1221 | serge | 137 | // .fini = &r300_fini, |
138 | // .suspend = &r300_suspend, |
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139 | // .resume = &r300_resume, |
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140 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 141 | .gpu_reset = &r300_gpu_reset, |
142 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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143 | .gart_set_page = &r100_pci_gart_set_page, |
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1221 | serge | 144 | // .cp_commit = &r100_cp_commit, |
145 | // .ring_start = &r300_ring_start, |
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146 | // .ring_test = &r100_ring_test, |
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147 | // .ring_ib_execute = &r100_ring_ib_execute, |
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148 | // .irq_set = &r100_irq_set, |
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149 | // .irq_process = &r100_irq_process, |
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150 | // .get_vblank_counter = &r100_get_vblank_counter, |
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151 | // .fence_ring_emit = &r300_fence_ring_emit, |
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152 | // .cs_parse = &r300_cs_parse, |
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153 | // .copy_blit = &r100_copy_blit, |
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154 | // .copy_dma = &r300_copy_dma, |
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155 | // .copy = &r100_copy_blit, |
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1268 | serge | 156 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
1221 | serge | 157 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
1268 | serge | 158 | .get_memory_clock = NULL, |
1221 | serge | 159 | .set_memory_clock = NULL, |
160 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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161 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1179 | serge | 162 | .set_surface_reg = r100_set_surface_reg, |
163 | .clear_surface_reg = r100_clear_surface_reg, |
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164 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 165 | }; |
166 | |||
167 | /* |
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168 | * r420,r423,rv410 |
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169 | */ |
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1179 | serge | 170 | extern int r420_init(struct radeon_device *rdev); |
171 | extern void r420_fini(struct radeon_device *rdev); |
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172 | extern int r420_suspend(struct radeon_device *rdev); |
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173 | extern int r420_resume(struct radeon_device *rdev); |
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1117 | serge | 174 | static struct radeon_asic r420_asic = { |
1179 | serge | 175 | .init = &r420_init, |
1221 | serge | 176 | // .fini = &r420_fini, |
177 | // .suspend = &r420_suspend, |
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178 | // .resume = &r420_resume, |
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179 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 180 | .gpu_reset = &r300_gpu_reset, |
181 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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182 | .gart_set_page = &rv370_pcie_gart_set_page, |
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1221 | serge | 183 | // .cp_commit = &r100_cp_commit, |
184 | // .ring_start = &r300_ring_start, |
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185 | // .ring_test = &r100_ring_test, |
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186 | // .ring_ib_execute = &r100_ring_ib_execute, |
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187 | // .irq_set = &r100_irq_set, |
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188 | // .irq_process = &r100_irq_process, |
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189 | // .get_vblank_counter = &r100_get_vblank_counter, |
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190 | // .fence_ring_emit = &r300_fence_ring_emit, |
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191 | // .cs_parse = &r300_cs_parse, |
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192 | // .copy_blit = &r100_copy_blit, |
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193 | // .copy_dma = &r300_copy_dma, |
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194 | // .copy = &r100_copy_blit, |
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1268 | serge | 195 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1221 | serge | 196 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 197 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1221 | serge | 198 | .set_memory_clock = &radeon_atom_set_memory_clock, |
199 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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200 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 201 | .set_surface_reg = r100_set_surface_reg, |
202 | .clear_surface_reg = r100_clear_surface_reg, |
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203 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 204 | }; |
205 | |||
206 | |||
207 | /* |
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208 | * rs400,rs480 |
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209 | */ |
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1221 | serge | 210 | extern int rs400_init(struct radeon_device *rdev); |
211 | extern void rs400_fini(struct radeon_device *rdev); |
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212 | extern int rs400_suspend(struct radeon_device *rdev); |
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213 | extern int rs400_resume(struct radeon_device *rdev); |
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1117 | serge | 214 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
215 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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216 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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217 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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218 | static struct radeon_asic rs400_asic = { |
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1221 | serge | 219 | .init = &rs400_init, |
220 | // .fini = &rs400_fini, |
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221 | // .suspend = &rs400_suspend, |
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222 | // .resume = &rs400_resume, |
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223 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 224 | .gpu_reset = &r300_gpu_reset, |
225 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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226 | .gart_set_page = &rs400_gart_set_page, |
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1221 | serge | 227 | // .cp_commit = &r100_cp_commit, |
228 | // .ring_start = &r300_ring_start, |
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229 | // .ring_test = &r100_ring_test, |
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230 | // .ring_ib_execute = &r100_ring_ib_execute, |
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231 | // .irq_set = &r100_irq_set, |
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232 | // .irq_process = &r100_irq_process, |
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233 | // .get_vblank_counter = &r100_get_vblank_counter, |
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234 | // .fence_ring_emit = &r300_fence_ring_emit, |
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235 | // .cs_parse = &r300_cs_parse, |
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236 | // .copy_blit = &r100_copy_blit, |
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237 | // .copy_dma = &r300_copy_dma, |
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238 | // .copy = &r100_copy_blit, |
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1268 | serge | 239 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
1221 | serge | 240 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
1268 | serge | 241 | .get_memory_clock = NULL, |
1221 | serge | 242 | .set_memory_clock = NULL, |
243 | .set_pcie_lanes = NULL, |
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244 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1179 | serge | 245 | .set_surface_reg = r100_set_surface_reg, |
246 | .clear_surface_reg = r100_clear_surface_reg, |
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247 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 248 | }; |
249 | |||
250 | |||
251 | /* |
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252 | * rs600. |
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253 | */ |
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1221 | serge | 254 | extern int rs600_init(struct radeon_device *rdev); |
255 | extern void rs600_fini(struct radeon_device *rdev); |
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256 | extern int rs600_suspend(struct radeon_device *rdev); |
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257 | extern int rs600_resume(struct radeon_device *rdev); |
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1117 | serge | 258 | int rs600_irq_set(struct radeon_device *rdev); |
1179 | serge | 259 | int rs600_irq_process(struct radeon_device *rdev); |
260 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
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1117 | serge | 261 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
262 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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263 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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264 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 265 | void rs600_bandwidth_update(struct radeon_device *rdev); |
1117 | serge | 266 | static struct radeon_asic rs600_asic = { |
1179 | serge | 267 | .init = &rs600_init, |
1221 | serge | 268 | // .fini = &rs600_fini, |
269 | // .suspend = &rs600_suspend, |
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270 | // .resume = &rs600_resume, |
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271 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 272 | .gpu_reset = &r300_gpu_reset, |
273 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
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274 | .gart_set_page = &rs600_gart_set_page, |
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1221 | serge | 275 | // .cp_commit = &r100_cp_commit, |
276 | // .ring_start = &r300_ring_start, |
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277 | // .ring_test = &r100_ring_test, |
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278 | // .ring_ib_execute = &r100_ring_ib_execute, |
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279 | // .irq_set = &rs600_irq_set, |
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280 | // .irq_process = &rs600_irq_process, |
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281 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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1117 | serge | 282 | // .fence_ring_emit = &r300_fence_ring_emit, |
283 | // .cs_parse = &r300_cs_parse, |
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284 | // .copy_blit = &r100_copy_blit, |
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285 | // .copy_dma = &r300_copy_dma, |
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286 | // .copy = &r100_copy_blit, |
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1268 | serge | 287 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1221 | serge | 288 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 289 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1221 | serge | 290 | .set_memory_clock = &radeon_atom_set_memory_clock, |
291 | .set_pcie_lanes = NULL, |
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292 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 293 | .bandwidth_update = &rs600_bandwidth_update, |
1117 | serge | 294 | }; |
295 | |||
296 | |||
297 | /* |
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298 | * rs690,rs740 |
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299 | */ |
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1221 | serge | 300 | int rs690_init(struct radeon_device *rdev); |
301 | void rs690_fini(struct radeon_device *rdev); |
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302 | int rs690_resume(struct radeon_device *rdev); |
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303 | int rs690_suspend(struct radeon_device *rdev); |
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1117 | serge | 304 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
305 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 306 | void rs690_bandwidth_update(struct radeon_device *rdev); |
1117 | serge | 307 | static struct radeon_asic rs690_asic = { |
1221 | serge | 308 | .init = &rs690_init, |
309 | // .fini = &rs690_fini, |
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310 | // .suspend = &rs690_suspend, |
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311 | // .resume = &rs690_resume, |
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312 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 313 | .gpu_reset = &r300_gpu_reset, |
314 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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315 | .gart_set_page = &rs400_gart_set_page, |
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1221 | serge | 316 | // .cp_commit = &r100_cp_commit, |
317 | // .ring_start = &r300_ring_start, |
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318 | // .ring_test = &r100_ring_test, |
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319 | // .ring_ib_execute = &r100_ring_ib_execute, |
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320 | // .irq_set = &rs600_irq_set, |
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321 | // .irq_process = &rs600_irq_process, |
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322 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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323 | // .fence_ring_emit = &r300_fence_ring_emit, |
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324 | // .cs_parse = &r300_cs_parse, |
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325 | // .copy_blit = &r100_copy_blit, |
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326 | // .copy_dma = &r300_copy_dma, |
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327 | // .copy = &r300_copy_dma, |
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1268 | serge | 328 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1221 | serge | 329 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 330 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1221 | serge | 331 | .set_memory_clock = &radeon_atom_set_memory_clock, |
332 | .set_pcie_lanes = NULL, |
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333 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 334 | .set_surface_reg = r100_set_surface_reg, |
335 | .clear_surface_reg = r100_clear_surface_reg, |
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336 | .bandwidth_update = &rs690_bandwidth_update, |
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1117 | serge | 337 | }; |
338 | |||
1179 | serge | 339 | |
1117 | serge | 340 | /* |
341 | * rv515 |
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342 | */ |
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343 | int rv515_init(struct radeon_device *rdev); |
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1221 | serge | 344 | void rv515_fini(struct radeon_device *rdev); |
1117 | serge | 345 | int rv515_gpu_reset(struct radeon_device *rdev); |
346 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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347 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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348 | void rv515_ring_start(struct radeon_device *rdev); |
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349 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
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350 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 351 | void rv515_bandwidth_update(struct radeon_device *rdev); |
1221 | serge | 352 | int rv515_resume(struct radeon_device *rdev); |
353 | int rv515_suspend(struct radeon_device *rdev); |
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1117 | serge | 354 | static struct radeon_asic rv515_asic = { |
355 | .init = &rv515_init, |
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1221 | serge | 356 | // .fini = &rv515_fini, |
357 | // .suspend = &rv515_suspend, |
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358 | // .resume = &rv515_resume, |
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359 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 360 | .gpu_reset = &rv515_gpu_reset, |
361 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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362 | .gart_set_page = &rv370_pcie_gart_set_page, |
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1221 | serge | 363 | // .cp_commit = &r100_cp_commit, |
364 | // .ring_start = &rv515_ring_start, |
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365 | // .ring_test = &r100_ring_test, |
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366 | // .ring_ib_execute = &r100_ring_ib_execute, |
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367 | // .irq_set = &rs600_irq_set, |
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368 | // .irq_process = &rs600_irq_process, |
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369 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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370 | // .fence_ring_emit = &r300_fence_ring_emit, |
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371 | // .cs_parse = &r300_cs_parse, |
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372 | // .copy_blit = &r100_copy_blit, |
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373 | // .copy_dma = &r300_copy_dma, |
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374 | // .copy = &r100_copy_blit, |
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1268 | serge | 375 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1221 | serge | 376 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 377 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1221 | serge | 378 | .set_memory_clock = &radeon_atom_set_memory_clock, |
379 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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380 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 381 | .set_surface_reg = r100_set_surface_reg, |
382 | .clear_surface_reg = r100_clear_surface_reg, |
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383 | .bandwidth_update = &rv515_bandwidth_update, |
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1117 | serge | 384 | }; |
385 | |||
386 | |||
387 | /* |
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388 | * r520,rv530,rv560,rv570,r580 |
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389 | */ |
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1221 | serge | 390 | int r520_init(struct radeon_device *rdev); |
391 | int r520_resume(struct radeon_device *rdev); |
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1117 | serge | 392 | static struct radeon_asic r520_asic = { |
1221 | serge | 393 | .init = &r520_init, |
394 | // .fini = &rv515_fini, |
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395 | // .suspend = &rv515_suspend, |
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396 | // .resume = &r520_resume, |
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397 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 398 | .gpu_reset = &rv515_gpu_reset, |
1119 | serge | 399 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
400 | .gart_set_page = &rv370_pcie_gart_set_page, |
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1221 | serge | 401 | // .cp_commit = &r100_cp_commit, |
402 | // .ring_start = &rv515_ring_start, |
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403 | // .ring_test = &r100_ring_test, |
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404 | // .ring_ib_execute = &r100_ring_ib_execute, |
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405 | // .irq_set = &rs600_irq_set, |
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406 | // .irq_process = &rs600_irq_process, |
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407 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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408 | // .fence_ring_emit = &r300_fence_ring_emit, |
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409 | // .cs_parse = &r300_cs_parse, |
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410 | // .copy_blit = &r100_copy_blit, |
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411 | // .copy_dma = &r300_copy_dma, |
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412 | // .copy = &r100_copy_blit, |
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1268 | serge | 413 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1221 | serge | 414 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 415 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1221 | serge | 416 | .set_memory_clock = &radeon_atom_set_memory_clock, |
417 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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418 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 419 | .set_surface_reg = r100_set_surface_reg, |
420 | .clear_surface_reg = r100_clear_surface_reg, |
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1221 | serge | 421 | .bandwidth_update = &rv515_bandwidth_update, |
1117 | serge | 422 | }; |
423 | |||
424 | /* |
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1221 | serge | 425 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
1117 | serge | 426 | */ |
1179 | serge | 427 | int r600_init(struct radeon_device *rdev); |
428 | void r600_fini(struct radeon_device *rdev); |
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429 | int r600_suspend(struct radeon_device *rdev); |
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430 | int r600_resume(struct radeon_device *rdev); |
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431 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
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432 | int r600_wb_init(struct radeon_device *rdev); |
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433 | void r600_wb_fini(struct radeon_device *rdev); |
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434 | void r600_cp_commit(struct radeon_device *rdev); |
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435 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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1117 | serge | 436 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
437 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1233 | serge | 438 | int r600_cs_parse(struct radeon_cs_parser *p); |
439 | void r600_fence_ring_emit(struct radeon_device *rdev, |
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440 | struct radeon_fence *fence); |
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441 | int r600_copy_dma(struct radeon_device *rdev, |
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442 | uint64_t src_offset, |
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443 | uint64_t dst_offset, |
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444 | unsigned num_pages, |
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445 | struct radeon_fence *fence); |
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446 | int r600_irq_process(struct radeon_device *rdev); |
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447 | int r600_irq_set(struct radeon_device *rdev); |
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448 | int r600_gpu_reset(struct radeon_device *rdev); |
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449 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
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450 | uint32_t tiling_flags, uint32_t pitch, |
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451 | uint32_t offset, uint32_t obj_size); |
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452 | int r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
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453 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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454 | int r600_ring_test(struct radeon_device *rdev); |
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455 | int r600_copy_blit(struct radeon_device *rdev, |
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456 | uint64_t src_offset, uint64_t dst_offset, |
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457 | unsigned num_pages, struct radeon_fence *fence); |
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1117 | serge | 458 | |
1233 | serge | 459 | static struct radeon_asic r600_asic = { |
460 | .init = &r600_init, |
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461 | // .fini = &r600_fini, |
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462 | // .suspend = &r600_suspend, |
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463 | // .resume = &r600_resume, |
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464 | // .cp_commit = &r600_cp_commit, |
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465 | .vga_set_state = &r600_vga_set_state, |
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466 | .gpu_reset = &r600_gpu_reset, |
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467 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
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468 | .gart_set_page = &rs600_gart_set_page, |
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469 | // .ring_test = &r600_ring_test, |
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470 | // .ring_ib_execute = &r600_ring_ib_execute, |
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471 | // .irq_set = &r600_irq_set, |
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472 | // .irq_process = &r600_irq_process, |
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473 | // .fence_ring_emit = &r600_fence_ring_emit, |
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474 | // .cs_parse = &r600_cs_parse, |
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475 | // .copy_blit = &r600_copy_blit, |
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476 | // .copy_dma = &r600_copy_blit, |
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477 | // .copy = &r600_copy_blit, |
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1268 | serge | 478 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1233 | serge | 479 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 480 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1233 | serge | 481 | .set_memory_clock = &radeon_atom_set_memory_clock, |
482 | .set_pcie_lanes = NULL, |
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483 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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484 | .set_surface_reg = r600_set_surface_reg, |
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485 | .clear_surface_reg = r600_clear_surface_reg, |
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486 | .bandwidth_update = &rv515_bandwidth_update, |
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487 | }; |
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488 | |||
489 | /* |
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490 | * rv770,rv730,rv710,rv740 |
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491 | */ |
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492 | int rv770_init(struct radeon_device *rdev); |
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493 | void rv770_fini(struct radeon_device *rdev); |
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494 | int rv770_suspend(struct radeon_device *rdev); |
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495 | int rv770_resume(struct radeon_device *rdev); |
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496 | int rv770_gpu_reset(struct radeon_device *rdev); |
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497 | |||
498 | static struct radeon_asic rv770_asic = { |
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499 | .init = &rv770_init, |
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500 | // .fini = &rv770_fini, |
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501 | // .suspend = &rv770_suspend, |
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502 | // .resume = &rv770_resume, |
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503 | // .cp_commit = &r600_cp_commit, |
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504 | .gpu_reset = &rv770_gpu_reset, |
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505 | .vga_set_state = &r600_vga_set_state, |
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506 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
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507 | .gart_set_page = &rs600_gart_set_page, |
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508 | // .ring_test = &r600_ring_test, |
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509 | // .ring_ib_execute = &r600_ring_ib_execute, |
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510 | // .irq_set = &r600_irq_set, |
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511 | // .irq_process = &r600_irq_process, |
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512 | // .fence_ring_emit = &r600_fence_ring_emit, |
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513 | // .cs_parse = &r600_cs_parse, |
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514 | // .copy_blit = &r600_copy_blit, |
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515 | // .copy_dma = &r600_copy_blit, |
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516 | // .copy = &r600_copy_blit, |
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1268 | serge | 517 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1233 | serge | 518 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1268 | serge | 519 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1233 | serge | 520 | .set_memory_clock = &radeon_atom_set_memory_clock, |
521 | .set_pcie_lanes = NULL, |
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522 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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523 | .set_surface_reg = r600_set_surface_reg, |
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524 | .clear_surface_reg = r600_clear_surface_reg, |
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525 | .bandwidth_update = &rv515_bandwidth_update, |
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526 | }; |
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527 | |||
1117 | serge | 528 | #endif |